RomanRom2/ossc
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247 Commits 8 Branches 38 Tags
8df33bb36443cee66d8d32bd5192ffe63df8c5ce
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2 Commits
Author SHA1 Message Date
marqs 85c295c5e2 make pll_reconfig more robust 2019-10-12 22:56:10 +03:00
marqs 9d496383c3 optimize clock network 
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
 2019-10-06 23:54:32 +03:00