add compatibility option for disabling HDMI PR2x

* fix compiler warnings
* fix Last Used initial input
* remove duplicate gtia_pal branch
* include hdmi_ar into saved profile

ip/pll_reconfig/inc/pll_reconfig_regs.h

@@ -36,7 +36,7 @@ typedef union {
 
 // char regs
 typedef struct {
-    char data[160];
+    alt_u32 data[5];
 } pll_config_data_regs;
 
 typedef struct {

ossc.qsf

@@ -163,8 +163,6 @@ set_location_assignment PIN_129 -to btn[1]
 set_location_assignment PIN_128 -to btn[0]
 
 
-
-
 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
 set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
@@ -220,20 +218,33 @@ set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_new.stp
 set_global_assignment -name FITTER_EFFORT "AUTO FIT"
 set_global_assignment -name SEED 1
 
-
-
-
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[2]
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[6]
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[6]
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[0]
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[4]
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[6]
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
-
-
-
-
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_HS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_VS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_DE
 
 
 set_global_assignment -name VERILOG_FILE rtl/videogen.v
@@ -259,4 +270,6 @@ set_global_assignment -name SEARCH_PATH software/sys_controller/mem_init/
 set_global_assignment -name SEARCH_PATH ip/ibex_qsys/rtl_extra
 set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"
 set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
+
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

ossc.sdc

@@ -43,10 +43,10 @@ foreach_in_collection c [get_clocks "pclk_tvp*"] {
     set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
 }
 
-# output delay constraints as documented in the IT6613 datasheet
-# -- increased IT_Tsu from 1.0 to 1.5 due to #52
-set IT_Tsu 1.5
-set IT_Th -0.5
+# output delay constraints based on params from IT6613 datasheet (S=1ns, H=0.5ns)
+# shifted aperture window due to issues #52 and #56
+set IT_Tsu 2.0
+set IT_Th -0.2
 set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
 foreach_in_collection c [get_clocks pclk_*_out] {
     set_output_delay -clock $c -min $IT_Th $critoutputs_hdmi -add

software/sys_controller/av_controller.c

@@ -87,7 +87,7 @@ alt_u8 profile_sel, profile_sel_menu, sd_profile_sel_menu, input_profiles[AV_LAS
 char row1[LCD_ROW_LEN+1], row2[LCD_ROW_LEN+1], menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1];
 
 extern alt_u8 menu_active;
-avinput_t target_input;
+avinput_t target_input, last_input;
 
 alt_u8 pcm1862_active;
 
@@ -1029,12 +1029,12 @@ void update_settings(int init_setup) {
         refresh_osd();
     }
     if (init_setup)
-        target_input = ts.def_input;
+        target_input = (ts.def_input == AV_LAST) ? last_input : ts.def_input;
 
     memcpy(&cs, &ts, sizeof(settings_t));
 }
 
-int main()
+int main(int argc, char **argv, char **envp)
 {
     ths_input_t target_ths = 0;
     pcm_input_t target_pcm = 0;
@@ -1223,6 +1223,7 @@ int main()
 
             cm.avinput = target_input;
             cm.sync_active = 0;
+            last_input = target_input;
             ths_source_sel(target_ths, (cm.cc.video_lpf > 1) ? (VIDEO_LPF_MAX-cm.cc.video_lpf) : THS_LPF_BYPASS);
             tvp_powerdown();
             DisableAudioOutput();
@@ -1258,7 +1259,7 @@ int main()
             cm.clkcnt = 0; //TODO: proper invalidate
         }
         if (tc.tx_mode != TX_DVI) {
-            if (tc.hdmi_itc != cm.cc.hdmi_itc || tc.hdmi_ar != cm.cc.hdmi_ar) {
+            if ((tc.hdmi_itc != cm.cc.hdmi_itc) || (tc.hdmi_ar != cm.cc.hdmi_ar)) {
                 //EnableAVIInfoFrame(FALSE, NULL);
                 printf("setting ITC to %d\nsetting Aspect-Ratio to %d\n", tc.hdmi_itc, tc.hdmi_ar);
                 HDMITX_SetAVIInfoFrame(vmode_out.vic, (tc.tx_mode == TX_HDMI_RGB) ? F_MODE_RGB444 : F_MODE_YUV444, tc.hdmi_ar, 0, tc.hdmi_itc, vm_conf.hdmitx_pixr_ifr);

software/sys_controller/ic_drivers/it6613/hdmitx.h

@@ -17,7 +17,7 @@
 
 
 #ifdef SUPPORT_SYNCEMBEDDED
-#pragma message("defined SUPPORT_SYNCEMBEDDED for Sync Embedded timing input or CCIR656 input.") 
+#pragma message("defined SUPPORT_SYNCEMBEDDED for Sync Embedded timing input or CCIR656 input.")
 #endif
 
 #ifndef _MCU_ // DSSSHA need large computation data rather than 8051 supported.
@@ -52,7 +52,6 @@
 //#define NULL 0
 
 //typedef unsigned char bool;
-typedef unsigned char  bool;
 #include "sysconfig.h"
 
 // Hardwired to CPU reset

software/sys_controller/inc/avconfig.h

@@ -107,6 +107,7 @@ typedef struct {
     alt_u8 fpga_pll_bw;
     alt_u8 panasonic_hack;
     alt_u8 o480p_pbox;
+    alt_u8 hdmi_pr2x_disable;
 
     /* Postprocessing settings */
     alt_u8 sl_mode;

software/sys_controller/inc/firmware.h

@@ -24,7 +24,7 @@
 #include "sysconfig.h"
 
 #define FW_VER_MAJOR            1
-#define FW_VER_MINOR            21
+#define FW_VER_MINOR            22
 
 #ifdef OSDLANG_JP
 #define FW_SUFFIX              "j"
@@ -61,7 +61,7 @@ typedef struct {
 } rem_update_dev;
 
 int fw_init_secondary();
-int fw_update();
+int fw_update(char *dirname, char *filename);
 void fw_update_commit(uint32_t* cluster_idx, uint32_t bytes_to_copy, uint16_t fs_csize, uint16_t fs_startsec, uint32_t flash_addr);
 
 #endif

software/sys_controller/src/firmware.c

@@ -271,6 +271,8 @@ void __attribute__((noinline, flatten, noreturn, __section__(".text_bram"))) fw_
     // flush command FIFO before FPGA reconfiguration start
     *(volatile uint32_t*)(INTEL_GENERIC_SERIAL_FLASH_INTERFACE_TOP_0_AVL_MEM_BASE);
 
+    rem_reconfig_dev.regs->image_addr[0] = flash_addr;
+    rem_reconfig_dev.regs->wdog_enable[0] = 0;
     rem_reconfig_dev.regs->reconfig_start = 1;
 
     while (1) {}

software/sys_controller/src/menu.c

@@ -247,6 +247,7 @@ MENU(menu_compatibility, P99_PROTECT({ \
     { "Full VSYNC bypas",                       OPT_AVCONFIG_SELECTION, { .sel = { &tc.full_vs_bypass,   OPT_WRAP,   SETTING_ITEM(off_on_desc) } } },
     { "Default HDMI VIC",                       OPT_AVCONFIG_NUMVALUE,  { .num = { &tc.default_vic,     OPT_NOWRAP, 0, HDMI_1080p50, value_disp } } },
     { "Panasonic hack",                        OPT_AVCONFIG_SELECTION, { .sel = { &tc.panasonic_hack,   OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
+    { "Disable PR2x",                          OPT_AVCONFIG_SELECTION, { .sel = { &tc.hdmi_pr2x_disable, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
 }))
 
 MENU(menu_audio, P99_PROTECT({ \
@@ -705,9 +706,6 @@ int load_lc_palette_set(char *dirname, char *filename) {
                 } else if (strncmp(tmpbuf, "maria_pal", 10) == 0) {
                     offset = offsetof(lc_palette_set, maria_pal)/4;
                     entries_remaining = 256;
-                } else if (strncmp(tmpbuf, "gtia_pal", 10) == 0) {
-                    offset = offsetof(lc_palette_set, gtia_pal)/4;
-                    entries_remaining = 128;
                 } else if (strncmp(tmpbuf, "sms_pal", 10) == 0) {
                     offset = offsetof(lc_palette_set, sms_pal)/4;
                     entries_remaining = 64;

software/sys_controller/src/userdata.c

@@ -50,6 +50,7 @@ extern uint8_t update_cur_vm;
 extern SD_DEV sdcard_dev;
 extern c_shmask_t c_shmask;
 extern c_lc_palette_set_t c_lc_palette_set;
+extern avinput_t last_input;
 
 char target_profile_name[USERDATA_NAME_LEN+1], cur_profile_name[USERDATA_NAME_LEN+1];
 
@@ -67,6 +68,7 @@ const ude_item_map ude_initcfg_items[] = {
     UDE_ITEM(10, 120, ts.osd_status_timeout),
     UDE_ITEM(11, 120, ts.osd_highlight_color),
     UDE_ITEM(12, 120, ts.phase_hotkey_enable),
+    UDE_ITEM(13, 122, last_input),
 };
 
 const ude_item_map ude_profile_items[] = {
@@ -140,6 +142,8 @@ const ude_item_map ude_profile_items[] = {
     // 65 reserved
     UDE_ITEM(66, 120, tc.panasonic_hack),
     UDE_ITEM(67, 120, tc.o480p_pbox),
+    UDE_ITEM(61, 122, tc.hdmi_ar),
+    UDE_ITEM(61, 122, tc.hdmi_pr2x_disable),
 };
 
 int write_userdata(uint8_t entry) {

software/sys_controller/src/video_modes.c

@@ -133,7 +133,7 @@ uint32_t calculate_pclk(uint32_t src_clk_hz, mode_data_t *vm_out, vm_proc_config
 
 int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm_proc_config_t *vm_conf)
 {
-    int i, diff_lines, diff_v_hz_x100, mindiff_id=0, mindiff_lines=1000, mindiff_v_hz_x100=10000, x_rpt_decr=0;
+    int i, diff_lines, diff_v_hz_x100, mindiff_id=0, mindiff_lines=1000, mindiff_v_hz_x100=10000, x_rpt_decr=0, skip_hv_mult=0;
     mode_data_t *mode_preset;
     mode_flags valid_lm[] = { (MODE_PT | (cc->pt_mode ? (MODE_L5_GEN_4_3<<(cc->pt_mode-1)) : 0)),
                               (MODE_L2 | (MODE_L2<<cc->l2_mode)),
@@ -154,7 +154,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
         switch (mode_preset->group) {
             case GROUP_384P:
                 //fixed Line2x/3x mode for 240x360p/400p
-                valid_lm[2] = MODE_L3_GEN_16_9;
+                valid_lm[2] = MODE_L3_GEN_16_9 | MODE_L3_GEN_4_3;
                 valid_lm[3] = MODE_L2_240x360;
                 valid_lm[4] = MODE_L3_240x360;
                 if ((!vm_in->timings.h_total) && (mode_preset->timings.v_total == 449)) {
@@ -281,7 +281,6 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
             while ((((vm_out->timings.v_hz_x100*vm_out->timings.v_total)/100)*vm_out->timings.h_total*(vm_conf->h_skip+1))>>vm_out->timings.interlaced < 25000000UL) {
                 vm_conf->x_rpt = vm_conf->h_skip = 2*(vm_conf->h_skip+1)-1;
             }
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
             break;
         case MODE_L2:
             // Upsample / pixel-repeat horizontal resolution of 384p/480p/960i modes
@@ -289,16 +288,15 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
                 if (upsample2x) {
                     vmode_hv_mult(vm_in, 2, 1);
                     vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
+                    skip_hv_mult = 1;
                 } else {
                     vm_conf->x_rpt = 1;
-                    vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
                 }
             } else {
                 if (cc->o480p_pbox) {
                     vm_conf->x_rpt = vm_conf->h_skip = 3;
                     x_rpt_decr += 1;
                 }
-                vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
             }
             break;
         case MODE_L3_GEN_16_9:
@@ -307,15 +305,22 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
                 if (upsample2x) {
                     vmode_hv_mult(vm_in, 2, 1);
                     vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
+                    skip_hv_mult = 1;
                 } else {
                     vm_conf->x_rpt = 1;
-                    vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
                 }
-            } else {
-                vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
+            } else if (cc->hdmi_pr2x_disable && ((mode_preset->group == GROUP_480P) || (mode_preset->group == GROUP_576P))) {
+                vmode_hv_mult(vm_in, 2, 1);
+                vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
+                skip_hv_mult = 1;
             }
             break;
         case MODE_L3_GEN_4_3:
+            // Upsample by 3x on GBI Line3x generic
+            if (mode_preset->group == GROUP_384P) {
+                vmode_hv_mult(vm_in, 3, 1);
+                vmode_hv_mult(vm_out, 3, 1);
+            }
             vm_conf->x_size = vm_out->timings.h_active-2*vm_in->mask.h;
             vm_out->timings.h_synclen /= 3;
             vm_out->timings.h_backporch /= 3;
@@ -323,6 +328,7 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
             vm_out->timings.h_total /= 3;
             vm_out->timings.h_total_adj = 0;
             vmode_hv_mult(vm_out, 4, VM_OUT_YMULT);
+            skip_hv_mult = 1;
             break;
         case MODE_L4_GEN_4_3:
             // Upsample / pixel-repeat horizontal resolution of 480i mode
@@ -330,17 +336,30 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
                 if (upsample2x) {
                     vmode_hv_mult(vm_in, 2, 1);
                     vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
+                    skip_hv_mult = 1;
                 } else {
                     vm_conf->x_rpt = 1;
-                    vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
                 }
-            } else {
-                vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
             }
             break;
         case MODE_L5_GEN_4_3:
+            if (cc->hdmi_pr2x_disable && mode_preset->group == GROUP_288P) {
+                vmode_hv_mult(vm_in, 2, 1);
+                vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
+                skip_hv_mult = 1;
+            }
+            break;
         case MODE_L6_GEN_4_3:
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
+            if (cc->hdmi_pr2x_disable) {
+                if (mode_preset->group == GROUP_288P) {
+                    // upsampled active would exceed 2048, must pixel-repeat
+                    vm_conf->x_rpt = 1;
+                } else {
+                    vmode_hv_mult(vm_in, 2, 1);
+                    vmode_hv_mult(vm_out, 2, VM_OUT_YMULT);
+                    skip_hv_mult = 1;
+                }
+            }
             break;
         case MODE_L2_512_COL:
         case MODE_L2_384_COL:
@@ -351,13 +370,13 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
             } else {
                 vm_conf->x_rpt = vm_conf->h_skip = 1;
             }
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
             break;
         case MODE_L3_512_COL:
         case MODE_L4_512_COL:
-        case MODE_L6_512_COL:
             vm_conf->x_rpt = vm_conf->h_skip = 1;
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
+            break;
+        case MODE_L6_512_COL:
+            vm_conf->x_rpt = vm_conf->h_skip = cc->hdmi_pr2x_disable ? 3 : 1;
             break;
         case MODE_L2_256_COL:
             if (cc->o480p_pbox) {
@@ -366,34 +385,35 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
             } else {
                 vm_conf->x_rpt = vm_conf->h_skip = 2;
             }
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
             break;
         case MODE_L3_384_COL:
         case MODE_L4_384_COL:
         case MODE_L5_512_COL:
+            vm_conf->x_rpt = vm_conf->h_skip = 2;
+            break;
         case MODE_L6_384_COL:
         case MODE_L6_320_COL:
-            vm_conf->x_rpt = vm_conf->h_skip = 2;
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
+            vm_conf->x_rpt = vm_conf->h_skip = cc->hdmi_pr2x_disable ? 5 : 2;
             break;
         case MODE_L3_240x360:
+            vm_conf->x_rpt = vm_conf->h_skip = 7;
+            break;
         case MODE_L3_320_COL:
         case MODE_L4_320_COL:
         case MODE_L5_384_COL:
-        case MODE_L6_256_COL:
             vm_conf->x_rpt = vm_conf->h_skip = 3;
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
+            break;
+        case MODE_L6_256_COL:
+            vm_conf->x_rpt = vm_conf->h_skip = cc->hdmi_pr2x_disable ? 7 : 3;
             break;
         case MODE_L2_240x360:
         case MODE_L3_256_COL:
         case MODE_L4_256_COL:
         case MODE_L5_320_COL:
             vm_conf->x_rpt = vm_conf->h_skip = 4;
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
             break;
         case MODE_L5_256_COL:
             vm_conf->x_rpt = vm_conf->h_skip = 5;
-            vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
             break;
         default:
             printf("WARNING: invalid mindiff_lm\n");
@@ -401,6 +421,9 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
             break;
     }
 
+    if (!skip_hv_mult)
+        vmode_hv_mult(vm_out, VM_OUT_XMULT, VM_OUT_YMULT);
+
     // Set clock multiplication factor
     if (mindiff_lm == MODE_L3_GEN_4_3)
         vm_conf->si_pclk_mult = 4;
@@ -410,11 +433,15 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
     // Reduce x_rpt for 1:1 PAR 256col mode
     if (mindiff_lm & (MODE_L2_256_COL|MODE_L4_256_COL|MODE_L5_256_COL))
         vm_conf->x_rpt -= cc->ar_256col;
-    else if (mindiff_lm & (MODE_L3_256_COL|MODE_L6_256_COL))
+    else if (mindiff_lm & MODE_L3_256_COL)
         vm_conf->x_rpt = cc->ar_256col ? 2 : 3;
+    else if (mindiff_lm & MODE_L6_256_COL)
+        vm_conf->x_rpt = cc->ar_256col ? (cc->hdmi_pr2x_disable+1)*3-1 : (cc->hdmi_pr2x_disable+1)*4-1;
 
-    if (mindiff_lm & (MODE_L3_320_COL|MODE_L2_240x360|MODE_L3_240x360))
+    if (mindiff_lm & (MODE_L3_320_COL|MODE_L2_240x360))
         x_rpt_decr += 1;
+    else if (mindiff_lm & (MODE_L3_240x360))
+        x_rpt_decr += 2;
 
     vm_conf->x_rpt -= x_rpt_decr;
 
@@ -424,9 +451,9 @@ int get_pure_lm_mode(avconfig_t *cc, mode_data_t *vm_in, mode_data_t *vm_out, vm
     }
 
     // Force TX pixel-repeat for high bandwidth modes
-    if (((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P)) ||
+    if (!cc->hdmi_pr2x_disable && (((mindiff_lm == MODE_L5_GEN_4_3) && (mode_preset->group == GROUP_288P)) ||
        ((mindiff_lm == MODE_L3_GEN_16_9) && ((mode_preset->group == GROUP_480P) || (mode_preset->group == GROUP_576P))) ||
-       (mindiff_lm == MODE_L3_240x360) || (mindiff_lm >= MODE_L6_GEN_4_3))
+       (mindiff_lm >= MODE_L6_GEN_4_3)))
         vm_conf->tx_pixelrep = 1;
 
     sniprintf(vm_out->name, 11, "%s x%u", vm_in->name, vm_conf->y_rpt+1);

software/sys_controller/src/video_modes_list.c

@@ -40,7 +40,7 @@ const mode_data_t video_modes_plm_default[] = {
     { "256x240LB",     HDMI_Unknown,     { 256,  240,   5000,   341, 0,  312,   39, 41,   25, 3,  0},  DEF_PHASE,  {{ 0,  0}},  VIDEO_SDTV,               GROUP_288P,   (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL | MODE_L6_256_COL),  },
     { "288p",          HDMI_288p50,      { 720,  288,   5008,   864, 0,  312,   69, 19,   63, 3,  0},  DEF_PHASE,  {{ 0,  0}},  VIDEO_SDTV,               GROUP_288P,   (MODE_PT | MODE_L2),                                                                        },
     /* 360p: GBI */
-    { "480x360",       HDMI_Unknown,     { 480,  360,   6000,   600, 0,  375,   63, 10,   38, 3,  0},  DEF_PHASE,  {{ 0,  0}},  VIDEO_EDTV,               GROUP_384P,   (MODE_PT | MODE_L2),                                                                        },
+    { "480x360",       HDMI_Unknown,     { 480,  360,   6000,   600, 0,  375,   63, 10,   38, 3,  0},  DEF_PHASE,  {{ 0,  0}},  VIDEO_EDTV,               GROUP_384P,   (MODE_PT | MODE_L2 | MODE_L3_GEN_4_3),                                                                        },
     { "240x360",       HDMI_Unknown,     { 240,  360,   6000,   300, 0,  375,   32, 10,   18, 3,  0},  DEF_PHASE,  {{ 0,  0}},  VIDEO_EDTV,               GROUP_384P,   (MODE_L2_240x360 | MODE_L3_240x360),                                                        },
     /* 384p: Sega Model 2 */
     { "384p",          HDMI_Unknown,     { 496,  384,   5500,   640, 0,  423,   50, 29,   62, 3,  0},  DEF_PHASE,  {{ 0,  0}},  VIDEO_EDTV,               GROUP_384P,   (MODE_PT | MODE_L2),                                                                        },