mirror of
https://github.com/marqs85/ossc
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227 lines
8.1 KiB
Systemverilog
227 lines
8.1 KiB
Systemverilog
//
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// Copyright (C) 2015-2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module sc_config_top(
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// common
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input clk_i,
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input rst_i,
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// avalon slave
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input [31:0] avalon_s_writedata,
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output reg [31:0] avalon_s_readdata,
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input [9:0] avalon_s_address,
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input [3:0] avalon_s_byteenable,
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input avalon_s_write,
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input avalon_s_read,
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input avalon_s_chipselect,
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output avalon_s_waitrequest_n,
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// SC interface
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input [31:0] fe_status_i,
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input [31:0] fe_status2_i,
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input [31:0] lt_status_i,
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output [31:0] hv_in_config_o,
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output [31:0] hv_in_config2_o,
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output [31:0] hv_in_config3_o,
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output [31:0] hv_out_config_o,
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output [31:0] hv_out_config2_o,
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output [31:0] hv_out_config3_o,
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output [31:0] xy_out_config_o,
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output [31:0] xy_out_config2_o,
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output [31:0] misc_config_o,
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output [31:0] sl_config_o,
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output [31:0] sl_config2_o,
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output [31:0] sl_config3_o,
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// Shadow mask read interface
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input vclk,
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input [3:0] shmask_xpos,
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input [3:0] shmask_ypos,
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output [10:0] shmask_data,
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// Lumacode interface
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input lumacode_clk_i,
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input [8:0] lumacode_addr_i,
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input lumacode_rden_i,
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output [31:0] lumacode_data_o
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);
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localparam FE_STATUS_REGNUM = 10'h0;
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localparam FE_STATUS2_REGNUM = 10'h1;
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localparam LT_STATUS_REGNUM = 10'h2;
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localparam HV_IN_CONFIG_REGNUM = 10'h3;
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localparam HV_IN_CONFIG2_REGNUM = 10'h4;
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localparam HV_IN_CONFIG3_REGNUM = 10'h5;
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localparam HV_OUT_CONFIG_REGNUM = 10'h6;
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localparam HV_OUT_CONFIG2_REGNUM = 10'h7;
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localparam HV_OUT_CONFIG3_REGNUM = 10'h8;
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localparam XY_OUT_CONFIG_REGNUM = 10'h9;
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localparam XY_OUT_CONFIG2_REGNUM = 10'ha;
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localparam MISC_CONFIG_REGNUM = 10'hb;
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localparam SL_CONFIG_REGNUM = 10'hc;
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localparam SL_CONFIG2_REGNUM = 10'hd;
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localparam SL_CONFIG3_REGNUM = 10'he;
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localparam SHMASK_DATA_OFFSET = 10'h100;
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localparam LUMACODE_RAM_OFFSET = 10'h200;
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reg [31:0] config_reg[HV_IN_CONFIG_REGNUM:SL_CONFIG3_REGNUM] /* synthesis ramstyle = "logic" */;
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assign avalon_s_waitrequest_n = 1'b1;
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// Shadow mask array
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altsyncram shmask_array_inst (
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.address_a (avalon_s_address[7:0]),
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.address_b ({shmask_ypos, shmask_xpos}),
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.clock0 (clk_i),
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.clock1 (vclk),
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.data_a (avalon_s_writedata[10:0]),
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.wren_a (avalon_s_chipselect && avalon_s_write && (avalon_s_address >= SHMASK_DATA_OFFSET) && (avalon_s_address < LUMACODE_RAM_OFFSET)),
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.q_b (shmask_data),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({11{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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shmask_array_inst.address_aclr_b = "NONE",
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shmask_array_inst.address_reg_b = "CLOCK1",
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shmask_array_inst.clock_enable_input_a = "BYPASS",
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shmask_array_inst.clock_enable_input_b = "BYPASS",
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shmask_array_inst.clock_enable_output_b = "BYPASS",
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shmask_array_inst.intended_device_family = "Cyclone IV E",
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shmask_array_inst.lpm_type = "altsyncram",
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shmask_array_inst.numwords_a = 256,
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shmask_array_inst.numwords_b = 256,
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shmask_array_inst.operation_mode = "DUAL_PORT",
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shmask_array_inst.outdata_aclr_b = "NONE",
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shmask_array_inst.outdata_reg_b = "CLOCK1",
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shmask_array_inst.power_up_uninitialized = "FALSE",
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shmask_array_inst.widthad_a = 8,
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shmask_array_inst.widthad_b = 8,
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shmask_array_inst.width_a = 11,
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shmask_array_inst.width_b = 11,
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shmask_array_inst.width_byteena_a = 1;
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// Lumacode palette RAM
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altsyncram lumacode_pal_ram (
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.address_a (avalon_s_address[8:0]),
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.address_b (lumacode_addr_i),
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.clock0 (clk_i),
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.clock1 (lumacode_clk_i),
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.data_a (avalon_s_writedata),
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.rden_b (lumacode_rden_i),
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.wren_a (avalon_s_chipselect && avalon_s_write && (avalon_s_address >= LUMACODE_RAM_OFFSET)),
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.q_b (lumacode_data_o),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({32{1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.wren_b (1'b0));
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defparam
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lumacode_pal_ram.address_aclr_b = "NONE",
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lumacode_pal_ram.address_reg_b = "CLOCK1",
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lumacode_pal_ram.clock_enable_input_a = "BYPASS",
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lumacode_pal_ram.clock_enable_input_b = "BYPASS",
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lumacode_pal_ram.clock_enable_output_b = "BYPASS",
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lumacode_pal_ram.intended_device_family = "Cyclone IV E",
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lumacode_pal_ram.lpm_type = "altsyncram",
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lumacode_pal_ram.numwords_a = 512,
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lumacode_pal_ram.numwords_b = 512,
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lumacode_pal_ram.operation_mode = "DUAL_PORT",
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lumacode_pal_ram.outdata_aclr_b = "NONE",
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lumacode_pal_ram.outdata_reg_b = "UNREGISTERED",
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lumacode_pal_ram.power_up_uninitialized = "FALSE",
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lumacode_pal_ram.rdcontrol_reg_b = "CLOCK1",
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lumacode_pal_ram.widthad_a = 9,
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lumacode_pal_ram.widthad_b = 9,
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lumacode_pal_ram.width_a = 32,
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lumacode_pal_ram.width_b = 32,
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lumacode_pal_ram.width_byteena_a = 1;
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genvar i;
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generate
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for (i=HV_IN_CONFIG_REGNUM; i <= SL_CONFIG3_REGNUM; i++) begin : gen_reg
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always @(posedge clk_i or posedge rst_i) begin
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if (rst_i) begin
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config_reg[i] <= 0;
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end else begin
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if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==i)) begin
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if (avalon_s_byteenable[3])
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config_reg[i][31:24] <= avalon_s_writedata[31:24];
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if (avalon_s_byteenable[2])
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config_reg[i][23:16] <= avalon_s_writedata[23:16];
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if (avalon_s_byteenable[1])
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config_reg[i][15:8] <= avalon_s_writedata[15:8];
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if (avalon_s_byteenable[0])
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config_reg[i][7:0] <= avalon_s_writedata[7:0];
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end
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end
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end
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end
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endgenerate
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// no readback for config regs -> unused bits optimized out
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always @(*) begin
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if (avalon_s_chipselect && avalon_s_read) begin
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case (avalon_s_address)
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FE_STATUS_REGNUM: avalon_s_readdata = fe_status_i;
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FE_STATUS2_REGNUM: avalon_s_readdata = fe_status2_i;
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LT_STATUS_REGNUM: avalon_s_readdata = lt_status_i;
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default: avalon_s_readdata = 32'h00000000;
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endcase
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end else begin
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avalon_s_readdata = 32'h00000000;
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end
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end
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assign hv_in_config_o = config_reg[HV_IN_CONFIG_REGNUM];
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assign hv_in_config2_o = config_reg[HV_IN_CONFIG2_REGNUM];
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assign hv_in_config3_o = config_reg[HV_IN_CONFIG3_REGNUM];
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assign hv_out_config_o = config_reg[HV_OUT_CONFIG_REGNUM];
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assign hv_out_config2_o = config_reg[HV_OUT_CONFIG2_REGNUM];
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assign hv_out_config3_o = config_reg[HV_OUT_CONFIG3_REGNUM];
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assign xy_out_config_o = config_reg[XY_OUT_CONFIG_REGNUM];
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assign xy_out_config2_o = config_reg[XY_OUT_CONFIG2_REGNUM];
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assign misc_config_o = config_reg[MISC_CONFIG_REGNUM];
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assign sl_config_o = config_reg[SL_CONFIG_REGNUM];
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assign sl_config2_o = config_reg[SL_CONFIG2_REGNUM];
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assign sl_config3_o = config_reg[SL_CONFIG3_REGNUM];
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endmodule
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