mirror of
https://github.com/marqs85/ossc
synced 2025-10-31 07:56:03 +03:00
a488422089
* Add initial input and SDTV sync glitch filter settings * Modify input initialization logic * Fix debug build warnings
85 lines
1.9 KiB
C
85 lines
1.9 KiB
C
#include <stdio.h>
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#include <unistd.h>
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#include "sysconfig.h"
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#include "system.h"
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#include "i2c_opencores.h"
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#include "it6613.h"
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volatile alt_u8 cur_bank;
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inline void select_bank_it(alt_u8 bank) {
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cur_bank = bank;
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I2C_start(I2CA_BASE, IT_BASE, 0);
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I2C_write(I2CA_BASE, IT_CURBANK, 0);
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I2C_write(I2CA_BASE, cur_bank, 1);
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}
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inline alt_u32 read_it(alt_u32 regaddr) {
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if ((regaddr > 0xFF) && (cur_bank == 0))
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select_bank_it(1);
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else if ((regaddr <= 0xFF) && (cur_bank == 1))
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select_bank_it(0);
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I2C_start(I2CA_BASE, IT_BASE, 0);
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I2C_write(I2CA_BASE, (regaddr & 0xFF), 1);
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I2C_start(I2CA_BASE, IT_BASE, 1);
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return I2C_read(I2CA_BASE,1);
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}
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inline void write_it(alt_u32 regaddr, alt_u8 data) {
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if ((regaddr > 0xFF) && (cur_bank == 0))
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select_bank_it(1);
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else if ((regaddr <= 0xFF) && (cur_bank == 1))
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select_bank_it(0);
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I2C_start(I2CA_BASE, IT_BASE, 0);
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I2C_write(I2CA_BASE, (regaddr & 0xFF), 0);
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I2C_write(I2CA_BASE, data, 1);
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}
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/*inline void reset_it() {
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usleep(100000);
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IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x00);
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usleep(100000);
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IOWR_ALTERA_AVALON_PIO_DATA(PIO_0_BASE, 0x01);
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usleep(100000);
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}*/
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int init_it() {
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alt_u32 vendor_id, device_id;
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alt_u32 i;
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cur_bank = 0;
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select_bank_it(cur_bank);
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vendor_id = read_it(IT_VENDORID);
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device_id = read_it(IT_DEVICEID);
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printf("VEN: 0x%.2lX, DEV: 0x%.2lX\n", vendor_id, device_id);
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if (!((vendor_id == IT6613_VENDORID) && (device_id == IT6613_DEVICEID)))
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return -1;
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write_it(REG_TX_SW_RST,B_REF_RST|B_VID_RST|B_AUD_RST|B_AREF_RST|B_HDCP_RST) ;
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usleep(1000);
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write_it(REG_TX_SW_RST,B_VID_RST|B_AUD_RST|B_AREF_RST|B_HDCP_RST) ;
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write_it(IT_DRIVECTRL, 0x10);
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write_it(IT_HDMIMODE, 0);
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for (i=0xC1; i<=0xD0; i++)
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write_it(i, 0);
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write_it(IT_OUTCOLOR, 0);
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// enable video
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//HDMITX_WriteI2C_Byte(REG_TX_SW_RST,B_VID_RST|B_AUD_RST|B_AREF_RST|B_HDCP_RST) ;
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write_it(REG_TX_SW_RST, B_AUD_RST|B_AREF_RST|B_HDCP_RST) ;
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usleep(1000);
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return 0;
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}
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