mirror of
https://github.com/marqs85/ossc
synced 2025-11-01 00:16:03 +03:00
106 lines
3.7 KiB
Tcl
106 lines
3.7 KiB
Tcl
#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module pulpino
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#
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set_module_property DESCRIPTION "HW CRC32"
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set_module_property NAME hw_crc32
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#set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "DSP"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME hw_crc32
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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set adv_dbg_if false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL CRC_Component
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE
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add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
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set_fileset_property SIM_VERILOG TOP_LEVEL CRC_Component
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add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE
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#
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# connection point clk_sink
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#
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add_interface clk_sink clock end
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set_interface_property clk_sink ENABLED true
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set_interface_property clk_sink EXPORT_OF ""
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set_interface_property clk_sink PORT_NAME_MAP ""
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set_interface_property clk_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clk_sink SVD_ADDRESS_GROUP ""
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add_interface_port clk_sink clk clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clk_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink reset reset Input 1
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#
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# connection point avalon_slave
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#
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add_interface avalon_slave avalon end
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set_interface_property avalon_slave addressUnits WORDS
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set_interface_property avalon_slave associatedClock clk_sink
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set_interface_property avalon_slave associatedReset reset_sink
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set_interface_property avalon_slave bitsPerSymbol 8
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set_interface_property avalon_slave burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave burstcountUnits WORDS
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set_interface_property avalon_slave explicitAddressSpan 0
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set_interface_property avalon_slave holdTime 0
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set_interface_property avalon_slave linewrapBursts false
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set_interface_property avalon_slave maximumPendingReadTransactions 0
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set_interface_property avalon_slave readLatency 1
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set_interface_property avalon_slave readWaitTime 1
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set_interface_property avalon_slave setupTime 0
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set_interface_property avalon_slave timingUnits Cycles
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set_interface_property avalon_slave writeWaitTime 0
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set_interface_property avalon_slave ENABLED true
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set_interface_property avalon_slave EXPORT_OF ""
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set_interface_property avalon_slave PORT_NAME_MAP ""
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set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave address address Input 3
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add_interface_port avalon_slave readdata readdata Output 32
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add_interface_port avalon_slave read read Input 1
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add_interface_port avalon_slave chipselect chipselect Input 1
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add_interface_port avalon_slave byteenable byteenable Input 4
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add_interface_port avalon_slave write write Input 1
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add_interface_port avalon_slave writedata writedata Input 32
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