mirror of
https://github.com/marqs85/ossc
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239 lines
8.9 KiB
Systemverilog
239 lines
8.9 KiB
Systemverilog
//
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// Copyright (C) 2019-2020 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module osd_generator_top (
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// common
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input clk_i,
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input rst_i,
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// avalon slave
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input [31:0] avalon_s_writedata,
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output [31:0] avalon_s_readdata,
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input [7:0] avalon_s_address,
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input [3:0] avalon_s_byteenable,
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input avalon_s_write,
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input avalon_s_read,
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input avalon_s_chipselect,
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output avalon_s_waitrequest_n,
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// OSD interface
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input vclk,
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input [10:0] xpos,
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input [10:0] ypos,
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output reg osd_enable,
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output reg [1:0] osd_color
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);
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localparam CHAR_ROWS = 30;
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localparam CHAR_COLS = 16;
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localparam CHAR_SECTIONS = 2;
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localparam CHAR_SEC_SEPARATOR = 2;
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localparam BG_BLACK = 2'h0;
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localparam BG_BLUE = 2'h1;
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localparam BG_YELLOW = 2'h2;
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localparam BG_WHITE = 2'h3;
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localparam OSD_CONFIG_REGNUM = 8'hf0;
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localparam OSD_ROW_LSEC_ENABLE_REGNUM = 8'hf1;
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localparam OSD_ROW_RSEC_ENABLE_REGNUM = 8'hf2;
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localparam OSD_ROW_COLOR_REGNUM = 8'hf3;
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reg [31:0] osd_config;
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reg [31:0] config_reg[OSD_ROW_LSEC_ENABLE_REGNUM:OSD_ROW_COLOR_REGNUM] /* synthesis ramstyle = "logic" */;
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reg [10:0] xpos_osd_area_scaled, xpos_text_scaled;
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reg [10:0] ypos_osd_area_scaled, ypos_text_scaled;
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reg [7:0] x_ptr[2:5], y_ptr[2:5] /* synthesis ramstyle = "logic" */;
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reg osd_text_act_pp[2:6], osd_act_pp[3:6];
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reg [14:0] to_ctr, to_ctr_ms;
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reg char_px;
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wire render_enable = osd_config[0];
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wire status_refresh = osd_config[1];
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wire menu_active = osd_config[2];
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wire [1:0] status_timeout = osd_config[4:3];
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wire [2:0] x_offset = osd_config[7:5];
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wire [2:0] y_offset = osd_config[10:8];
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wire [1:0] x_size = osd_config[12:11];
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wire [1:0] y_size = osd_config[14:13];
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wire [1:0] border_color = osd_config[16:15];
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wire [10:0] xpos_scaled_w = (xpos >> x_size)-({3'h0, x_offset} << 3);
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wire [10:0] ypos_scaled_w = (ypos >> y_size)-({3'h0, y_offset} << 3);
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wire [7:0] rom_rdaddr;
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wire [0:7] char_data[7:0];
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wire [4:0] char_row = (ypos_text_scaled >> 3);
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wire [5:0] char_col = (xpos_text_scaled >> 3) - (((xpos_text_scaled >> 3) >= CHAR_COLS) ? CHAR_SEC_SEPARATOR : 0);
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wire [9:0] char_idx = 32*char_row + char_col;
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assign avalon_s_waitrequest_n = 1'b1;
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char_array char_array_inst (
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.byteena_a(avalon_s_byteenable),
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.data(avalon_s_writedata),
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.rdaddress(char_idx),
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.rdclock(vclk),
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.wraddress(avalon_s_address),
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.wrclock(clk_i),
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.wren(avalon_s_chipselect && avalon_s_write && (avalon_s_address < CHAR_ROWS*CHAR_COLS*CHAR_SECTIONS)),
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.q(rom_rdaddr)
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);
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char_rom char_rom_inst (
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.clock(vclk),
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.address(rom_rdaddr),
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.q({char_data[7],char_data[6],char_data[5],char_data[4],char_data[3],char_data[2],char_data[1],char_data[0]})
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);
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// Pipeline structure
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// | 0 | 1 | 2 | 3 | 4 | 5 | 6 |
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// |----------|----------|---------|---------|---------|---------|--------|
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// > POS_TEXT | POS_AREA | | | | | |
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// > | PTR | PTR | PTR | PTR | | |
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// > | ENABLE | ENABLE | ENABLE | ENABLE | ENABLE | ENABLE |
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// > | INDEX | INDEX | | | | |
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// > | | | CHARROM | CHARROM | CHAR_PX | COLOR |
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integer idx, pp_idx;
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always @(posedge vclk) begin
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xpos_text_scaled <= xpos_scaled_w;
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ypos_text_scaled <= ypos_scaled_w;
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xpos_osd_area_scaled <= xpos_text_scaled + 3'h4;
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ypos_osd_area_scaled <= ypos_text_scaled + 3'h4;
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x_ptr[2] <= xpos_text_scaled[7:0];
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y_ptr[2] <= ypos_text_scaled[7:0];
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for(pp_idx = 3; pp_idx <= 5; pp_idx = pp_idx+1) begin
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x_ptr[pp_idx] <= x_ptr[pp_idx-1];
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y_ptr[pp_idx] <= y_ptr[pp_idx-1];
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end
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osd_text_act_pp[2] <= render_enable &
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(menu_active || (to_ctr_ms > 0)) &
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(((xpos_text_scaled < 8*CHAR_COLS) & config_reg[OSD_ROW_LSEC_ENABLE_REGNUM][ypos_text_scaled/8]) |
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((xpos_text_scaled >= 8*(CHAR_COLS+CHAR_SEC_SEPARATOR)) & (xpos_text_scaled < 8*(2*CHAR_COLS+CHAR_SEC_SEPARATOR)) & config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][ypos_text_scaled/8])) &
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(ypos_text_scaled < 8*CHAR_ROWS);
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for(pp_idx = 3; pp_idx <= 6; pp_idx = pp_idx+1) begin
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osd_text_act_pp[pp_idx] <= osd_text_act_pp[pp_idx-1];
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end
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osd_act_pp[3] <= render_enable &
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(menu_active || (to_ctr_ms > 0)) &
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(((xpos_osd_area_scaled/8 < (CHAR_COLS+1)) & config_reg[OSD_ROW_LSEC_ENABLE_REGNUM][(ypos_osd_area_scaled/8) ? ((ypos_osd_area_scaled/8)-1) : 0]) |
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((xpos_osd_area_scaled/8 >= (CHAR_COLS+1)) & (xpos_osd_area_scaled/8 < (2*CHAR_COLS+CHAR_SEC_SEPARATOR+1)) & (config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][(ypos_osd_area_scaled/8)-1] | config_reg[OSD_ROW_RSEC_ENABLE_REGNUM][ypos_osd_area_scaled/8]))) &
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(ypos_osd_area_scaled < 8*(CHAR_ROWS+1));
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for(pp_idx = 4; pp_idx <= 6; pp_idx = pp_idx+1) begin
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osd_act_pp[pp_idx] <= osd_act_pp[pp_idx-1];
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end
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char_px <= char_data[y_ptr[5]][x_ptr[5]];
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osd_enable <= osd_act_pp[6];
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if (osd_text_act_pp[6]) begin
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if (char_px) begin
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osd_color <= config_reg[OSD_ROW_COLOR_REGNUM][char_row] ? BG_YELLOW : BG_WHITE;
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end else begin
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osd_color <= BG_BLUE;
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end
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end else begin // border
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osd_color <= border_color;
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end
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end
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// OSD status timeout counters
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always @(posedge clk_i)
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begin
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if (status_refresh) begin
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to_ctr <= 15'd0;
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case (status_timeout)
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default: to_ctr_ms <= 2000; // 2s
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2'b01: to_ctr_ms <= 5000; // 5s
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2'b10: to_ctr_ms <= 10000; // 10s
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2'b11: to_ctr_ms <= 0; // off
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endcase
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end else begin
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if (to_ctr == 27000-1) begin
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to_ctr <= 0;
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if (to_ctr_ms != 15'h0)
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to_ctr_ms <= to_ctr_ms - 1'b1;
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end else begin
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to_ctr <= to_ctr + 1'b1;
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end
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end
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end
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// Avalon register interface
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always @(posedge clk_i or posedge rst_i) begin
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if (rst_i) begin
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osd_config <= 32'h0;
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end else begin
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if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==OSD_CONFIG_REGNUM)) begin
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if (avalon_s_byteenable[3])
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osd_config[31:24] <= avalon_s_writedata[31:24];
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if (avalon_s_byteenable[2])
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osd_config[23:16] <= avalon_s_writedata[23:16];
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if (avalon_s_byteenable[1])
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osd_config[15:8] <= avalon_s_writedata[15:8];
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if (avalon_s_byteenable[0])
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osd_config[7:0] <= avalon_s_writedata[7:0];
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end else begin
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osd_config[1] <= 1'b0; // reset timer refresh bit
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end
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end
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end
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genvar i;
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generate
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for (i=OSD_ROW_LSEC_ENABLE_REGNUM; i <= OSD_ROW_COLOR_REGNUM; i++) begin : gen_reg
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always @(posedge clk_i or posedge rst_i) begin
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if (rst_i) begin
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config_reg[i] <= 0;
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end else begin
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if (avalon_s_chipselect && avalon_s_write && (avalon_s_address==i)) begin
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if (avalon_s_byteenable[3])
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config_reg[i][31:24] <= avalon_s_writedata[31:24];
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if (avalon_s_byteenable[2])
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config_reg[i][23:16] <= avalon_s_writedata[23:16];
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if (avalon_s_byteenable[1])
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config_reg[i][15:8] <= avalon_s_writedata[15:8];
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if (avalon_s_byteenable[0])
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config_reg[i][7:0] <= avalon_s_writedata[7:0];
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end
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end
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end
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end
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endgenerate
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always @(*) begin
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if (avalon_s_chipselect && avalon_s_read) begin
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case (avalon_s_address)
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OSD_CONFIG_REGNUM: avalon_s_readdata = osd_config;
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OSD_ROW_LSEC_ENABLE_REGNUM: avalon_s_readdata = config_reg[OSD_ROW_LSEC_ENABLE_REGNUM];
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OSD_ROW_RSEC_ENABLE_REGNUM: avalon_s_readdata = config_reg[OSD_ROW_RSEC_ENABLE_REGNUM];
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OSD_ROW_COLOR_REGNUM: avalon_s_readdata = config_reg[OSD_ROW_COLOR_REGNUM];
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default: avalon_s_readdata = 32'h00000000;
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endcase
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end else begin
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avalon_s_readdata = 32'h00000000;
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end
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end
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endmodule
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