mirror of
https://github.com/marqs85/ossc
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117 lines
4.7 KiB
Verilog
117 lines
4.7 KiB
Verilog
// megafunction wizard: %LPM_MULT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: lpm_mult
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// ============================================================
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// File Name: lpm_mult_4_hybr_ref_pre.v
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// Megafunction Name(s):
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// lpm_mult
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//
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// Simulation Library Files(s):
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// lpm
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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// ************************************************************
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//Copyright (C) 2017 Intel Corporation. All rights reserved.
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//Your use of Intel Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Intel Program License
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//Subscription Agreement, the Intel Quartus Prime License Agreement,
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//the Intel FPGA IP License Agreement, or other applicable license
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//agreement, including, without limitation, that your use is for
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//the sole purpose of programming logic devices manufactured by
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//Intel and sold by Intel or its authorized distributors. Please
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//refer to the applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module lpm_mult_4_hybr_ref_pre (
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clock,
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dataa,
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datab,
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result);
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input clock;
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input [7:0] dataa;
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input [4:0] datab;
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output [8:0] result;
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wire [8:0] sub_wire0;
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wire [8:0] result = sub_wire0[8:0];
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lpm_mult lpm_mult_component (
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.clock (clock),
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.dataa (dataa),
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.datab (datab),
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.result (sub_wire0),
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.aclr (1'b0),
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.clken (1'b1),
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.sclr (1'b0),
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.sum (1'b0));
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defparam
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lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9",
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lpm_mult_component.lpm_pipeline = 1,
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lpm_mult_component.lpm_representation = "UNSIGNED",
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lpm_mult_component.lpm_type = "LPM_MULT",
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lpm_mult_component.lpm_widtha = 8,
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lpm_mult_component.lpm_widthb = 5,
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lpm_mult_component.lpm_widthp = 9;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "0"
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// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
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// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
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// Retrieval info: PRIVATE: Latency NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SignedMult NUMERIC "0"
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// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
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// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
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// Retrieval info: PRIVATE: WidthA NUMERIC "8"
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// Retrieval info: PRIVATE: WidthB NUMERIC "5"
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// Retrieval info: PRIVATE: WidthP NUMERIC "9"
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// Retrieval info: PRIVATE: aclr NUMERIC "0"
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// Retrieval info: PRIVATE: clken NUMERIC "0"
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// Retrieval info: PRIVATE: new_diagram STRING "1"
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// Retrieval info: PRIVATE: optimize NUMERIC "1"
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// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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// Retrieval info: CONSTANT: LPM_HINT STRING "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
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// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
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// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
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// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
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// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "5"
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// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "9"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
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// Retrieval info: USED_PORT: datab 0 0 5 0 INPUT NODEFVAL "datab[4..0]"
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// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
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// Retrieval info: CONNECT: @datab 0 0 5 0 datab 0 0 5 0
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// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mult_4_hybr_ref_pre_bb.v TRUE
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// Retrieval info: LIB_FILE: lpm
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