mirror of
https://github.com/marqs85/ossc
synced 2025-10-26 21:46:02 +03:00
454 lines
18 KiB
Tcl
454 lines
18 KiB
Tcl
# (C) 2001-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License Subscription
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# Agreement, Altera MegaCore Function License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# TCL File Generated by Component Editor 14.1
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# Fri May 09 18:08:10 MYT 2014
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# DO NOT MODIFY
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#
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# altera_epcq_controller_core "Altera EPCQ Serial Flash controller core" v14.1
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# Altera Coorperation 2014.05.23.15:01:29
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# This component is a serial flash controller which allows user to access Altera EPCQ devices
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#
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#
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# request TCL package from ACDS 14.1
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#
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package require -exact qsys 14.1
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#
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# module altera_epcq_controller
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#
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set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
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set_module_property NAME altera_epcq_controller_core
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set_module_property VERSION 16.1
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set_module_property INTERNAL true
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR "Altera Corporation"
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set_module_property DISPLAY_NAME "Altera EPCQ Serial Flash controller core"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property HIDE_FROM_QUARTUS true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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set_module_property VALIDATION_CALLBACK "validate"
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_arb
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
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add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv
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add_fileset SIM_VERILOG SIM_VERILOG "" ""
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set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_arb
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
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add_fileset_file altera_epcq_controller_arb.sv SYSTEM_VERILOG PATH altera_epcq_controller_arb.sv TOP_LEVEL_FILE
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add_fileset_file altera_epcq_controller.sv SYSTEM_VERILOG PATH altera_epcq_controller.sv
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#
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# add system info parameter
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add_parameter deviceFeaturesSystemInfo STRING "None"
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set_parameter_property deviceFeaturesSystemInfo system_info "DEVICE_FEATURES"
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set_parameter_property deviceFeaturesSystemInfo VISIBLE false
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#
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# parameters
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#
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add_parameter DEVICE_FAMILY STRING ""
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO "DEVICE_FAMILY"
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER true
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set_parameter_property DEVICE_FAMILY VISIBLE false
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add_parameter ADDR_WIDTH INTEGER 19
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set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
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set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
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set_parameter_property ADDR_WIDTH DERIVED true
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set_parameter_property ADDR_WIDTH TYPE INTEGER
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set_parameter_property ADDR_WIDTH VISIBLE false
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set_parameter_property ADDR_WIDTH UNITS None
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set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}
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set_parameter_property ADDR_WIDTH HDL_PARAMETER true
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add_parameter ASMI_ADDR_WIDTH INTEGER 24
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set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
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set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
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set_parameter_property ASMI_ADDR_WIDTH DERIVED true
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set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
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set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
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set_parameter_property ASMI_ADDR_WIDTH UNITS None
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set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}
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set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
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add_parameter ASI_WIDTH INTEGER 1
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set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
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set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
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set_parameter_property ASI_WIDTH DERIVED true
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set_parameter_property ASI_WIDTH TYPE INTEGER
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set_parameter_property ASI_WIDTH VISIBLE false
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set_parameter_property ASI_WIDTH UNITS None
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set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
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set_parameter_property ASI_WIDTH HDL_PARAMETER true
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add_parameter CS_WIDTH INTEGER 1
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set_parameter_property CS_WIDTH DEFAULT_VALUE 1
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set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
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set_parameter_property CS_WIDTH DERIVED true
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set_parameter_property CS_WIDTH TYPE INTEGER
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set_parameter_property CS_WIDTH VISIBLE false
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set_parameter_property CS_WIDTH UNITS None
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set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
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set_parameter_property CS_WIDTH HDL_PARAMETER true
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add_parameter CHIP_SELS INTEGER "1"
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set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
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set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
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set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
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set_parameter_property CHIP_SELS HDL_PARAMETER true
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set_parameter_property CHIP_SELS AFFECTS_GENERATION true
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add_parameter DDASI INTEGER "0"
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set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
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set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
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set_parameter_property DDASI AFFECTS_GENERATION true
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set_parameter_property DDASI VISIBLE false
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set_parameter_property DDASI DERIVED false
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add_parameter ENABLE_4BYTE_ADDR INTEGER "0"
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set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
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set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
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set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
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set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
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set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
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set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
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# SPI device selection
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add_parameter FLASH_TYPE STRING "EPCQ16"
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set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
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set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
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set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
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set_parameter_property FLASH_TYPE VISIBLE true
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set_parameter_property FLASH_TYPE DERIVED false
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add_parameter IO_MODE STRING "STANDARD"
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set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
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set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
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set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
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#
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# display items
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#
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock_sink
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset_n reset_n Input 1
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#
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# connection point avl_csr
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#
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add_interface avl_csr avalon end
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set_interface_property avl_csr addressUnits WORDS
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set_interface_property avl_csr associatedClock clock_sink
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set_interface_property avl_csr associatedReset reset
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set_interface_property avl_csr bitsPerSymbol 8
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set_interface_property avl_csr burstOnBurstBoundariesOnly false
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set_interface_property avl_csr burstcountUnits WORDS
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set_interface_property avl_csr explicitAddressSpan 0
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set_interface_property avl_csr holdTime 0
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set_interface_property avl_csr linewrapBursts false
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set_interface_property avl_csr maximumPendingReadTransactions 1
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set_interface_property avl_csr maximumPendingWriteTransactions 0
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set_interface_property avl_csr readLatency 0
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set_interface_property avl_csr readWaitTime 0
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set_interface_property avl_csr setupTime 0
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set_interface_property avl_csr timingUnits Cycles
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set_interface_property avl_csr writeWaitTime 0
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set_interface_property avl_csr ENABLED true
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set_interface_property avl_csr EXPORT_OF ""
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set_interface_property avl_csr PORT_NAME_MAP ""
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set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
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set_interface_property avl_csr SVD_ADDRESS_GROUP ""
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add_interface_port avl_csr avl_csr_read read Input 1
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add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
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add_interface_port avl_csr avl_csr_write write Input 1
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add_interface_port avl_csr avl_csr_addr address Input 3
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add_interface_port avl_csr avl_csr_wrdata writedata Input 32
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add_interface_port avl_csr avl_csr_rddata readdata Output 32
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add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
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#
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# connection point avl_mem
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#
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add_interface avl_mem avalon end
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set_interface_property avl_mem addressUnits WORDS
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set_interface_property avl_mem associatedClock clock_sink
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set_interface_property avl_mem associatedReset reset
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set_interface_property avl_mem bitsPerSymbol 8
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set_interface_property avl_mem burstOnBurstBoundariesOnly false
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set_interface_property avl_mem burstcountUnits WORDS
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set_interface_property avl_mem explicitAddressSpan 0
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set_interface_property avl_mem holdTime 0
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set_interface_property avl_mem linewrapBursts true
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set_interface_property avl_mem maximumPendingReadTransactions 1
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set_interface_property avl_mem maximumPendingWriteTransactions 0
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set_interface_property avl_mem constantBurstBehavior true
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set_interface_property avl_mem readLatency 0
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set_interface_property avl_mem readWaitTime 0
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set_interface_property avl_mem setupTime 0
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set_interface_property avl_mem timingUnits Cycles
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set_interface_property avl_mem writeWaitTime 0
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set_interface_property avl_mem ENABLED true
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set_interface_property avl_mem EXPORT_OF ""
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set_interface_property avl_mem PORT_NAME_MAP ""
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set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
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set_interface_property avl_mem SVD_ADDRESS_GROUP ""
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add_interface_port avl_mem avl_mem_write write Input 1
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add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
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add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
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add_interface_port avl_mem avl_mem_read read Input 1
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add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
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add_interface_port avl_mem avl_mem_wrdata writedata Input 32
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add_interface_port avl_mem avl_mem_rddata readdata Output 32
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add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
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add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
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#
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# connection point conduit_out
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#
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add_interface asmi_status_out conduit end
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add_interface_port asmi_status_out asmi_status_out conduit_status_out Input 8
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add_interface asmi_epcs_id conduit end
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add_interface_port asmi_epcs_id asmi_epcs_id conduit_epcs_id Input 8
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add_interface asmi_illegal_erase conduit end
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add_interface_port asmi_illegal_erase asmi_illegal_erase conduit_illegal_erase Input 1
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add_interface asmi_illegal_write conduit end
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add_interface_port asmi_illegal_write asmi_illegal_write conduit_illegal_write Input 1
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add_interface ddasi_dataoe conduit end
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add_interface_port ddasi_dataoe ddasi_dataoe conduit_ddasi_dataoe Input ASI_WIDTH
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add_interface ddasi_dclk conduit end
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add_interface_port ddasi_dclk ddasi_dclk conduit_ddasi_dclk Input 1
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add_interface ddasi_scein conduit end
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add_interface_port ddasi_scein ddasi_scein conduit_ddasi_scein Input CS_WIDTH
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add_interface ddasi_sdoin conduit end
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add_interface_port ddasi_sdoin ddasi_sdoin conduit_ddasi_sdoin Input ASI_WIDTH
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add_interface asmi_busy conduit end
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add_interface_port asmi_busy asmi_busy conduit_busy Input 1
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add_interface asmi_data_valid conduit end
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add_interface_port asmi_data_valid asmi_data_valid conduit_data_valid Input 1
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add_interface asmi_dataout conduit end
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add_interface_port asmi_dataout asmi_dataout conduit_dataout Input 8
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add_interface epcq_dataout conduit end
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add_interface_port epcq_dataout epcq_dataout conduit_epcq_dataout Input ASI_WIDTH
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add_interface ddasi_dataout conduit end
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add_interface_port ddasi_dataout ddasi_dataout conduit_ddasi_dataout Output ASI_WIDTH
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add_interface asmi_read_rdid conduit end
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add_interface_port asmi_read_rdid asmi_read_rdid conduit_read_rdid Output 1
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add_interface asmi_read_status conduit end
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add_interface_port asmi_read_status asmi_read_status conduit_read_status Output 1
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add_interface asmi_read_sid conduit end
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add_interface_port asmi_read_sid asmi_read_sid conduit_read_sid Output 1
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add_interface asmi_bulk_erase conduit end
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add_interface_port asmi_bulk_erase asmi_bulk_erase conduit_bulk_erase Output 1
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add_interface asmi_sector_erase conduit end
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add_interface_port asmi_sector_erase asmi_sector_erase conduit_sector_erase Output 1
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add_interface asmi_sector_protect conduit end
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add_interface_port asmi_sector_protect asmi_sector_protect conduit_sector_protect Output 1
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add_interface epcq_dclk conduit end
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add_interface_port epcq_dclk epcq_dclk conduit_epcq_dclk Output 1
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add_interface epcq_scein conduit end
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add_interface_port epcq_scein epcq_scein conduit_epcq_scein Output CS_WIDTH
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add_interface epcq_sdoin conduit end
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add_interface_port epcq_sdoin epcq_sdoin conduit_epcq_sdoin Output ASI_WIDTH
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add_interface epcq_dataoe conduit end
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add_interface_port epcq_dataoe epcq_dataoe conduit_epcq_dataoe Output ASI_WIDTH
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add_interface asmi_clkin conduit end
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add_interface_port asmi_clkin asmi_clkin conduit_clkin Output 1
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add_interface asmi_reset conduit end
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add_interface_port asmi_reset asmi_reset conduit_reset Output 1
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add_interface asmi_sce conduit end
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add_interface_port asmi_sce asmi_sce conduit_asmi_sce Output CS_WIDTH
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add_interface asmi_addr conduit end
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add_interface_port asmi_addr asmi_addr conduit_addr Output ASMI_ADDR_WIDTH
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add_interface asmi_datain conduit end
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add_interface_port asmi_datain asmi_datain conduit_datain Output 8
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add_interface asmi_fast_read conduit end
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add_interface_port asmi_fast_read asmi_fast_read conduit_fast_read Output 1
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add_interface asmi_rden conduit end
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add_interface_port asmi_rden asmi_rden conduit_rden Output 1
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add_interface asmi_shift_bytes conduit end
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add_interface_port asmi_shift_bytes asmi_shift_bytes conduit_shift_bytes Output 1
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add_interface asmi_wren conduit end
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add_interface_port asmi_wren asmi_wren conduit_wren Output 1
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add_interface asmi_write conduit end
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add_interface_port asmi_write asmi_write conduit_write Output 1
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add_interface asmi_rdid_out conduit end
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add_interface_port asmi_rdid_out asmi_rdid_out conduit_rdid_out Input 8
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add_interface asmi_en4b_addr conduit end
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add_interface_port asmi_en4b_addr asmi_en4b_addr conduit_en4b_addr Output 1
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#
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# connection point interrupt_sender
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#
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add_interface interrupt_sender interrupt end
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set_interface_property interrupt_sender associatedAddressablePoint avl_csr
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set_interface_property interrupt_sender associatedClock clock_sink
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set_interface_property interrupt_sender associatedReset reset
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set_interface_property interrupt_sender bridgedReceiverOffset ""
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set_interface_property interrupt_sender bridgesToReceiver ""
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set_interface_property interrupt_sender ENABLED true
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set_interface_property interrupt_sender EXPORT_OF ""
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set_interface_property interrupt_sender PORT_NAME_MAP ""
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set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
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add_interface_port interrupt_sender irq irq Output 1
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proc validate {} {
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set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
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"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
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set_parameter_property FLASH_TYPE "ALLOWED_RANGES" $all_supported_SPI_list
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set DEVICE_FAMILY [ get_parameter_value DEVICE_FAMILY ]
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set CHIP_SELS [ get_parameter_value CHIP_SELS]
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set temp_addr_width [ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
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set_parameter_value ENABLE_4BYTE_ADDR [ proc_get_derive_enable_2byte_addr [ get_parameter_value FLASH_TYPE ] ]
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if { [ get_parameter_value ENABLE_4BYTE_ADDR ] } {
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set_parameter_value ASMI_ADDR_WIDTH 32
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} else {
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set_parameter_value ASMI_ADDR_WIDTH 24
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}
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# check whether devices supporting multiple flash - only for Arria 10
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if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
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set is_multi_flash_support "true"
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if {$CHIP_SELS eq 3 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 2]}
|
|
if {$CHIP_SELS eq 2 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 1]}
|
|
if {$CHIP_SELS eq 1 } {set_parameter_value ADDR_WIDTH $temp_addr_width }
|
|
} else {
|
|
set is_multi_flash_support "false"
|
|
set_parameter_value ADDR_WIDTH $temp_addr_width
|
|
}
|
|
|
|
}
|
|
|
|
proc proc_get_derive_enable_2byte_addr {flash_type} {
|
|
if { [ string match "*256*" "$flash_type" ] || [ string match "*512*" "$flash_type" ] || [ string match "*1024*" "$flash_type" ]} {
|
|
return true
|
|
} else {
|
|
return false
|
|
}
|
|
}
|
|
|
|
proc proc_get_derive_addr_width {flash_type} {
|
|
switch $flash_type {
|
|
"EPCS16" - "EPCQ16" {
|
|
return 19
|
|
}
|
|
"EPCS64" - "EPCQ64" {
|
|
return 21
|
|
}
|
|
"EPCS128" - "EPCQ128" {
|
|
return 22
|
|
}
|
|
"EPCQ32" {
|
|
return 20
|
|
}
|
|
"EPCQ256" - "EPCQL256" {
|
|
return 23
|
|
}
|
|
"EPCQ512" - "EPCQL512" {
|
|
return 24
|
|
}
|
|
"EPCQL1024" {
|
|
return 25
|
|
}
|
|
default {
|
|
# Should never enter this function
|
|
send_message error "$flash_type is not a valid flash type"
|
|
}
|
|
|
|
}
|
|
}
|