RomanRom2/ossc
1
0 Fork 0
mirror of https://github.com/marqs85/ossc synced 2026-11-06 06:59:58 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity
Files
2995f437287228cd98f47cf73537aa73559a2459
ossc/software/sys_controller_bsp/drivers
T
History
marqs 9d496383c3 optimize clock network 
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
..
inc
optimize clock network
2019-10-06 23:54:32 +03:00
src
use symlinks for SW IP BSP files
2019-09-30 18:56:27 +03:00