mirror of
https://github.com/marqs85/ossc
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194 lines
6.9 KiB
Verilog
194 lines
6.9 KiB
Verilog
//
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// Copyright (C) 2015-2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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`include "lat_tester_includes.v"
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module videogen (
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input clk27,
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input reset_n,
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input lt_active,
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input [1:0] lt_mode,
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output [7:0] R_out,
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output [7:0] G_out,
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output [7:0] B_out,
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output reg HSYNC_out,
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output reg VSYNC_out,
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output PCLK_out,
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output reg ENABLE_out,
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input [1:0] pat_id,
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input [3:0] pat_speed,
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input interlace,
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input [8:0] H_BACKPORCH,
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input [7:0] H_SYNCLEN,
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input [10:0] H_ACTIVE,
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input [11:0] H_TOTAL,
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input [5:0] V_BACKPORCH,
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input [2:0] V_SYNCLEN,
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input [10:0] V_ACTIVE,
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input [10:0] V_TOTAL
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);
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parameter H_OVERSCAN = 10'd40; //at both sides
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parameter V_OVERSCAN = 10'd16; //top and bottom
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parameter H_AREA = 10'd640;
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parameter V_AREA = 10'd448;
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parameter H_GRADIENT = 10'd512;
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parameter V_GRADIENT = 10'd256;
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parameter V_GRAYRAMP = 10'd84;
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parameter H_BORDER = ((H_AREA-H_GRADIENT)>>1);
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parameter V_BORDER = ((V_AREA-V_GRADIENT)>>1);
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wire [9:0] X_START = H_BACKPORCH + H_SYNCLEN;
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wire [6:0] Y_START = V_BACKPORCH + V_SYNCLEN;
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//Counters
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reg [11:0] h_cnt;
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reg [10:0] v_cnt;
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reg [10:0] x_offset;
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reg [10:0] y_pos;
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reg fid, frame_id;
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assign PCLK_out = clk27;
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wire [11:0] x_pat = h_cnt-x_offset;
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//R, G and B should be 0 outside of active area
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assign R_out = ENABLE_out ? V_gen : 8'h00;
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assign G_out = ENABLE_out ? V_gen : 8'h00;
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assign B_out = ENABLE_out ? V_gen : 8'h00;
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reg [7:0] V_gen;
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//HSYNC gen (negative polarity)
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always @(posedge clk27 or negedge reset_n)
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begin
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if (!reset_n) begin
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h_cnt <= 0;
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HSYNC_out <= 0;
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end else begin
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//Hsync counter
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if (h_cnt < H_TOTAL-1)
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h_cnt <= h_cnt + 1'b1;
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else
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h_cnt <= 0;
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//Hsync signal
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HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
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end
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end
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//VSYNC gen (negative polarity)
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always @(posedge clk27 or negedge reset_n)
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begin
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if (!reset_n) begin
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v_cnt <= 0;
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y_pos <= 0;
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VSYNC_out <= 0;
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end else begin
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//Vsync counter
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if (!interlace) begin
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if (h_cnt == H_TOTAL-1) begin
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if (v_cnt < V_TOTAL-1) begin
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v_cnt <= v_cnt + 1'b1;
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if (v_cnt >= Y_START) begin
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if (pat_id == 2)
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y_pos <= y_pos + v_cnt[0];
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else
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y_pos <= y_pos + 1'b1;
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end
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end else begin
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v_cnt <= 0;
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x_offset <= (x_offset < H_ACTIVE) ? (x_offset + pat_speed + 1'b1) : 0;
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frame_id <= frame_id ^ 1;
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if (pat_id == 1)
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y_pos <= frame_id;
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else
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y_pos <= 0;
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end
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end
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//Vsync signal
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VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
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end else begin
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if ((fid==1'b0) && (v_cnt==(V_TOTAL>>1)) && (h_cnt==(H_TOTAL>>1)-1)) begin // odd field end
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v_cnt <= 11'h7ff;
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y_pos <= 1;
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fid <= fid ^ 1'b1;
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end else if (((fid==1'b1) && (v_cnt==(V_TOTAL>>1)-1) && (h_cnt == H_TOTAL-1))) begin // even field end
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v_cnt <= 0;
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y_pos <= 0;
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fid <= fid ^ 1'b1;
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end else if (h_cnt == H_TOTAL-1) begin
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v_cnt <= v_cnt + 1'b1;
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if (v_cnt >= Y_START)
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y_pos <= y_pos + 2;
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end
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//Vsync signal
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if (fid==1'b0)
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VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
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else
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VSYNC_out <= ((v_cnt+1'b1 < V_SYNCLEN) | ((v_cnt+1'b1==V_SYNCLEN) & (h_cnt < (H_TOTAL>>1)))) ? 1'b0 : 1'b1;
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end
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end
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end
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//Data and ENABLE gen
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always @(posedge clk27 or negedge reset_n)
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begin
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if (!reset_n) begin
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V_gen <= 8'h00;
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ENABLE_out <= 1'b0;
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end else begin
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if (lt_active) begin
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case (lt_mode)
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default: begin
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V_gen <= 8'h00;
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end
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`LT_POS_TOPLEFT: begin
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V_gen <= ((h_cnt < (X_START+(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt < (Y_START+(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
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end
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`LT_POS_CENTER: begin
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V_gen <= ((h_cnt >= (X_START+(H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (h_cnt < (X_START+(H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (v_cnt >= (Y_START+(V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (v_cnt < (Y_START+(V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00;
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end
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`LT_POS_BOTTOMRIGHT: begin
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V_gen <= ((h_cnt >= (X_START+H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt >= (Y_START+V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
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end
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endcase
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end else begin
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if (pat_id < 3) begin
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if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (y_pos < V_OVERSCAN) || (y_pos >= V_OVERSCAN+V_AREA))
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V_gen <= (h_cnt[0] ^ y_pos[0]) ? 8'hff : 8'h00;
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else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (y_pos < V_OVERSCAN+V_BORDER) || (y_pos >= V_OVERSCAN+V_AREA-V_BORDER))
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V_gen <= 8'h50;
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else if (y_pos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
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V_gen <= (((h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 4) << 3) + (h_cnt - (X_START+H_OVERSCAN+H_BORDER) >> 6);
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else
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V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
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end else begin
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V_gen <= ((h_cnt >= (X_START+x_offset)) && (h_cnt < (X_START+x_offset+(H_ACTIVE/(`LT_WIDTH_DIV)))) && (y_pos >= ((V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (y_pos < ((V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? {8{x_pat[3]^y_pos[3]}} : 8'h00;
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end
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end
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ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
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end
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end
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endmodule
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