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54 lines
2.1 KiB
Plaintext
54 lines
2.1 KiB
Plaintext
# memory.gdb - GDB memory region definitions
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#
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# Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
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# SOPC Builder design path: ../../sys.sopcinfo
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#
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# Generated: Sun Oct 16 12:18:06 EEST 2016
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# DO NOT MODIFY THIS FILE
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#
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# Changing this file will have subtle consequences
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# which will almost certainly lead to a nonfunctioning
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# system. If you do modify this file, be aware that your
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# changes will be overwritten and lost when this file
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# is generated again.
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#
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# DO NOT MODIFY THIS FILE
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# License Agreement
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#
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# Copyright (c) 2008
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# Altera Corporation, San Jose, California, USA.
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# All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a
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# copy of this software and associated documentation files (the "Software"),
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# to deal in the Software without restriction, including without limitation
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# the rights to use, copy, modify, merge, publish, distribute, sublicense,
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# and/or sell copies of the Software, and to permit persons to whom the
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# Software is furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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# DEALINGS IN THE SOFTWARE.
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#
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# This agreement shall be governed in all respects by the laws of the State
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# of California and by the laws of the United States of America.
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# Define memory regions for each memory connected to the CPU.
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# The cache attribute is specified which improves GDB performance
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# by allowing GDB to cache memory contents on the host.
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# epcq_controller_0_avl_mem
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memory 0x0 0x800000 cache
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# onchip_memory2_0
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memory 0x810000 0x81a000 cache
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