mirror of
https://github.com/marqs85/ossc
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301 lines
11 KiB
C
301 lines
11 KiB
C
#ifndef __NIOS2_H__
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#define __NIOS2_H__
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/******************************************************************************
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* *
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* License Agreement *
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* *
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* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
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* All rights reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included in *
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* all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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* This agreement shall be governed in all respects by the laws of the State *
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* of California and by the laws of the United States of America. *
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* *
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******************************************************************************/
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/*
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* This header provides processor specific macros for accessing the Nios2
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* control registers.
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*/
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#ifdef __cplusplus
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extern "C"
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{
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#endif /* __cplusplus */
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/*
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* Number of available IRQs in internal interrupt controller.
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*/
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#define NIOS2_NIRQ 32
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/*
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* Macros for accessing select Nios II general-purpose registers.
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*/
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/* ET (Exception Temporary) register */
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#define NIOS2_READ_ET(et) \
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do { __asm ("mov %0, et" : "=r" (et) ); } while (0)
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#define NIOS2_WRITE_ET(et) \
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do { __asm volatile ("mov et, %z0" : : "rM" (et)); } while (0)
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/* SP (Stack Pointer) register */
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#define NIOS2_READ_SP(sp) \
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do { __asm ("mov %0, sp" : "=r" (sp) ); } while (0)
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/*
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* Macros for useful processor instructions.
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*/
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#define NIOS2_BREAK() \
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do { __asm volatile ("break"); } while (0)
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#define NIOS2_REPORT_STACK_OVERFLOW() \
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do { __asm volatile("break 3"); } while (0)
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/*
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* Macros for accessing Nios II control registers.
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*/
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#define NIOS2_READ_STATUS(dest) \
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do { dest = __builtin_rdctl(0); } while (0)
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#define NIOS2_WRITE_STATUS(src) \
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do { __builtin_wrctl(0, src); } while (0)
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#define NIOS2_READ_ESTATUS(dest) \
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do { dest = __builtin_rdctl(1); } while (0)
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#define NIOS2_READ_BSTATUS(dest) \
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do { dest = __builtin_rdctl(2); } while (0)
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#define NIOS2_READ_IENABLE(dest) \
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do { dest = __builtin_rdctl(3); } while (0)
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#define NIOS2_WRITE_IENABLE(src) \
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do { __builtin_wrctl(3, src); } while (0)
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#define NIOS2_READ_IPENDING(dest) \
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do { dest = __builtin_rdctl(4); } while (0)
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#define NIOS2_READ_CPUID(dest) \
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do { dest = __builtin_rdctl(5); } while (0)
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#define NIOS2_READ_EXCEPTION(dest) \
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do { dest = __builtin_rdctl(7); } while (0)
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#define NIOS2_READ_PTEADDR(dest) \
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do { dest = __builtin_rdctl(8); } while (0)
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#define NIOS2_WRITE_PTEADDR(src) \
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do { __builtin_wrctl(8, src); } while (0)
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#define NIOS2_READ_TLBACC(dest) \
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do { dest = __builtin_rdctl(9); } while (0)
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#define NIOS2_WRITE_TLBACC(src) \
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do { __builtin_wrctl(9, src); } while (0)
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#define NIOS2_READ_TLBMISC(dest) \
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do { dest = __builtin_rdctl(10); } while (0)
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#define NIOS2_WRITE_TLBMISC(src) \
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do { __builtin_wrctl(10, src); } while (0)
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#define NIOS2_READ_ECCINJ(dest) \
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do { dest = __builtin_rdctl(11); } while (0)
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#define NIOS2_WRITE_ECCINJ(src) \
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do { __builtin_wrctl(11, src); } while (0)
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#define NIOS2_READ_BADADDR(dest) \
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do { dest = __builtin_rdctl(12); } while (0)
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#define NIOS2_WRITE_CONFIG(src) \
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do { __builtin_wrctl(13, src); } while (0)
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#define NIOS2_READ_CONFIG(dest) \
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do { dest = __builtin_rdctl(13); } while (0)
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#define NIOS2_WRITE_MPUBASE(src) \
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do { __builtin_wrctl(14, src); } while (0)
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#define NIOS2_READ_MPUBASE(dest) \
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do { dest = __builtin_rdctl(14); } while (0)
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#define NIOS2_WRITE_MPUACC(src) \
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do { __builtin_wrctl(15, src); } while (0)
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#define NIOS2_READ_MPUACC(dest) \
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do { dest = __builtin_rdctl(15); } while (0)
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/*
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* Nios II control registers that are always present
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*/
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#define NIOS2_STATUS status
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#define NIOS2_ESTATUS estatus
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#define NIOS2_BSTATUS bstatus
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#define NIOS2_IENABLE ienable
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#define NIOS2_IPENDING ipending
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#define NIOS2_CPUID cpuid
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/*
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* Bit masks & offsets for Nios II control registers.
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* The presence and size of a field is sometimes dependent on the Nios II
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* configuration. Bit masks for every possible field and the maximum size of
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* that field are defined.
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*
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* All bit-masks are expressed relative to the position
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* of the data with a register. To read data that is LSB-
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* aligned, the register read data should be masked, then
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* right-shifted by the designated "OFST" macro value. The
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* opposite should be used for register writes when starting
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* with LSB-aligned data.
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*/
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/* STATUS, ESTATUS, BSTATUS, and SSTATUS registers */
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#define NIOS2_STATUS_PIE_MSK (0x00000001)
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#define NIOS2_STATUS_PIE_OFST (0)
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#define NIOS2_STATUS_U_MSK (0x00000002)
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#define NIOS2_STATUS_U_OFST (1)
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#define NIOS2_STATUS_EH_MSK (0x00000004)
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#define NIOS2_STATUS_EH_OFST (2)
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#define NIOS2_STATUS_IH_MSK (0x00000008)
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#define NIOS2_STATUS_IH_OFST (3)
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#define NIOS2_STATUS_IL_MSK (0x000003f0)
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#define NIOS2_STATUS_IL_OFST (4)
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#define NIOS2_STATUS_CRS_MSK (0x0000fc00)
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#define NIOS2_STATUS_CRS_OFST (10)
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#define NIOS2_STATUS_PRS_MSK (0x003f0000)
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#define NIOS2_STATUS_PRS_OFST (16)
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#define NIOS2_STATUS_NMI_MSK (0x00400000)
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#define NIOS2_STATUS_NMI_OFST (22)
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#define NIOS2_STATUS_RSIE_MSK (0x00800000)
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#define NIOS2_STATUS_RSIE_OFST (23)
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#define NIOS2_STATUS_SRS_MSK (0x80000000)
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#define NIOS2_STATUS_SRS_OFST (31)
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/* EXCEPTION register */
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#define NIOS2_EXCEPTION_REG_CAUSE_MASK (0x0000007c)
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#define NIOS2_EXCEPTION_REG_CAUSE_OFST (2)
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#define NIOS2_EXCEPTION_REG_ECCFTL_MASK (0x80000000)
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#define NIOS2_EXCEPTION_REG_ECCFTL_OFST (31)
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/* PTEADDR (Page Table Entry Address) register */
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#define NIOS2_PTEADDR_REG_VPN_OFST 2
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#define NIOS2_PTEADDR_REG_VPN_MASK 0x3ffffc
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#define NIOS2_PTEADDR_REG_PTBASE_OFST 22
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#define NIOS2_PTEADDR_REG_PTBASE_MASK 0xffc00000
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/* TLBACC (TLB Access) register */
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#define NIOS2_TLBACC_REG_PFN_OFST 0
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#define NIOS2_TLBACC_REG_PFN_MASK 0xfffff
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#define NIOS2_TLBACC_REG_G_OFST 20
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#define NIOS2_TLBACC_REG_G_MASK 0x100000
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#define NIOS2_TLBACC_REG_X_OFST 21
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#define NIOS2_TLBACC_REG_X_MASK 0x200000
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#define NIOS2_TLBACC_REG_W_OFST 22
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#define NIOS2_TLBACC_REG_W_MASK 0x400000
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#define NIOS2_TLBACC_REG_R_OFST 23
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#define NIOS2_TLBACC_REG_R_MASK 0x800000
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#define NIOS2_TLBACC_REG_C_OFST 24
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#define NIOS2_TLBACC_REG_C_MASK 0x1000000
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#define NIOS2_TLBACC_REG_IG_OFST 25
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#define NIOS2_TLBACC_REG_IG_MASK 0xfe000000
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/* TLBMISC (TLB Miscellaneous) register */
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#define NIOS2_TLBMISC_REG_D_OFST 0
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#define NIOS2_TLBMISC_REG_D_MASK 0x1
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#define NIOS2_TLBMISC_REG_PERM_OFST 1
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#define NIOS2_TLBMISC_REG_PERM_MASK 0x2
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#define NIOS2_TLBMISC_REG_BAD_OFST 2
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#define NIOS2_TLBMISC_REG_BAD_MASK 0x4
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#define NIOS2_TLBMISC_REG_DBL_OFST 3
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#define NIOS2_TLBMISC_REG_DBL_MASK 0x8
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#define NIOS2_TLBMISC_REG_PID_OFST 4
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#define NIOS2_TLBMISC_REG_PID_MASK 0x3fff0
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#define NIOS2_TLBMISC_REG_WE_OFST 18
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#define NIOS2_TLBMISC_REG_WE_MASK 0x40000
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#define NIOS2_TLBMISC_REG_RD_OFST 19
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#define NIOS2_TLBMISC_REG_RD_MASK 0x80000
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#define NIOS2_TLBMISC_REG_WAY_OFST 20
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#define NIOS2_TLBMISC_REG_WAY_MASK 0xf00000
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#define NIOS2_TLBMISC_REG_EE_OFST 24
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#define NIOS2_TLBMISC_REG_EE_MASK 0x1000000
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/* ECCINJ (ECC Inject) register */
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#define NIOS2_ECCINJ_REG_RF_OFST 0
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#define NIOS2_ECCINJ_REG_RF_MASK 0x3
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#define NIOS2_ECCINJ_REG_ICTAG_OFST 2
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#define NIOS2_ECCINJ_REG_ICTAG_MASK 0xc
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#define NIOS2_ECCINJ_REG_ICDAT_OFST 4
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#define NIOS2_ECCINJ_REG_ICDAT_MASK 0x30
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#define NIOS2_ECCINJ_REG_DCTAG_OFST 6
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#define NIOS2_ECCINJ_REG_DCTAG_MASK 0xc0
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#define NIOS2_ECCINJ_REG_DCDAT_OFST 8
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#define NIOS2_ECCINJ_REG_DCDAT_MASK 0x300
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#define NIOS2_ECCINJ_REG_TLB_OFST 10
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#define NIOS2_ECCINJ_REG_TLB_MASK 0xc00
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#define NIOS2_ECCINJ_REG_DTCM0_OFST 12
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#define NIOS2_ECCINJ_REG_DTCM0_MASK 0x3000
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#define NIOS2_ECCINJ_REG_DTCM1_OFST 14
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#define NIOS2_ECCINJ_REG_DTCM1_MASK 0xc000
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#define NIOS2_ECCINJ_REG_DTCM2_OFST 16
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#define NIOS2_ECCINJ_REG_DTCM2_MASK 0x30000
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#define NIOS2_ECCINJ_REG_DTCM3_OFST 18
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#define NIOS2_ECCINJ_REG_DTCM3_MASK 0xc0000
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/* CONFIG register */
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#define NIOS2_CONFIG_REG_PE_MASK (0x00000001)
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#define NIOS2_CONFIG_REG_PE_OFST (0)
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#define NIOS2_CONFIG_REG_ANI_MASK (0x00000002)
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#define NIOS2_CONFIG_REG_ANI_OFST (1)
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#define NIOS2_CONFIG_REG_ECCEN_MASK (0x00000004)
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#define NIOS2_CONFIG_REG_ECCEN_OFST (2)
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#define NIOS2_CONFIG_REG_ECCEXC_MASK (0x00000008)
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#define NIOS2_CONFIG_REG_ECCEXC_OFST (3)
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/* MPUBASE (MPU Base Address) Register */
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#define NIOS2_MPUBASE_D_MASK (0x00000001)
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#define NIOS2_MPUBASE_D_OFST (0)
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#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e)
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#define NIOS2_MPUBASE_INDEX_OFST (1)
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#define NIOS2_MPUBASE_BASE_ADDR_MASK (0xffffffc0)
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#define NIOS2_MPUBASE_BASE_ADDR_OFST (6)
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/* MPUACC (MPU Access) Register */
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#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0)
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#define NIOS2_MPUACC_LIMIT_OFST (6)
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#define NIOS2_MPUACC_MASK_MASK (0xffffffc0)
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#define NIOS2_MPUACC_MASK_OFST (6)
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#define NIOS2_MPUACC_C_MASK (0x00000020)
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#define NIOS2_MPUACC_C_OFST (5)
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#define NIOS2_MPUACC_PERM_MASK (0x0000001c)
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#define NIOS2_MPUACC_PERM_OFST (2)
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#define NIOS2_MPUACC_RD_MASK (0x00000002)
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#define NIOS2_MPUACC_RD_OFST (1)
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#define NIOS2_MPUACC_WR_MASK (0x00000001)
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#define NIOS2_MPUACC_WR_OFST (0)
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __NIOS2_H__ */
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