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https://github.com/marqs85/ossc
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55 lines
3.4 KiB
C
55 lines
3.4 KiB
C
/******************************************************************************
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* *
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* License Agreement *
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* *
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* Copyright (c) 2003,2007 Altera Corporation, San Jose, California, USA. *
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* All rights reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included in *
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* all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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* This agreement shall be governed in all respects by the laws of the State *
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* of California and by the laws of the United States of America. *
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* *
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******************************************************************************/
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#include "sys/alt_warning.h"
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#include "sys/alt_cache.h"
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#include "system.h"
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/*
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* Convert a pointer to a block of cached memory into a block of uncached memory.
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* Return a pointer that should be used to access the uncached memory.
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*
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* This routine was created for Nios II Gen1 cores which allow mixing cacheable and
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* uncachable data in the same data cache line. So, they could take any memory region
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* and make it uncached. However, Nios II Gen2 cores don't support mixing cacheable
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* and uncachable data in the same data cache line so require the memory region to
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* be aligned to a cache line boundary and must be an integer number of cache line
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* bytes in size. So, software on a Nios II Gen2 core shouldn't really be using this
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* function so it fails with a link error.
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*/
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volatile void*
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alt_remap_uncached(void* ptr, alt_u32 len)
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{
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/* Generate a link time error, should this function ever be called. */
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ALT_LINK_ERROR("alt_remap_uncached() is not available because Nios II Gen2 cores with data caches don't support mixing cacheable and uncacheable data on the same line.");
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return NULL;
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}
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