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	 f502b2e46c
			
		
	
	
		f502b2e46c
		
	
	
	
	
		
			
			- Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources
		
			
				
	
	
		
			350 lines
		
	
	
		
			16 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			350 lines
		
	
	
		
			16 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| // megafunction wizard: %ALTPLL%
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| // GENERATION: STANDARD
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| // VERSION: WM1.0
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| // MODULE: altpll 
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| 
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| // ============================================================
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| // File Name: pll_3x.v
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| // Megafunction Name(s):
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| // 			altpll
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| //
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| // Simulation Library Files(s):
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| // 			altera_mf
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| // ============================================================
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| // ************************************************************
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| // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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| //
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| // 15.1.0 Build 185 10/21/2015 SJ Lite Edition
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| // ************************************************************
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| 
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| 
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| //Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
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| //Your use of Altera Corporation's design tools, logic functions 
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| //and other software and tools, and its AMPP partner logic 
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| //functions, and any output files from any of the foregoing 
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| //(including device programming or simulation files), and any 
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| //associated documentation or information are expressly subject 
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| //to the terms and conditions of the Altera Program License 
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| //Subscription Agreement, the Altera Quartus Prime License Agreement,
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| //the Altera MegaCore Function License Agreement, or other 
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| //applicable license agreement, including, without limitation, 
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| //that your use is for the sole purpose of programming logic 
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| //devices manufactured by Altera and sold by Altera or its 
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| //authorized distributors.  Please refer to the applicable 
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| //agreement for further details.
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| 
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| 
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| // synopsys translate_off
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| `timescale 1 ps / 1 ps
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| // synopsys translate_on
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| module pll_3x (
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| 	areset,
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| 	inclk0,
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| 	c0,
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| 	c1,
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| 	locked);
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| 
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| 	input	  areset;
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| 	input	  inclk0;
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| 	output	  c0;
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| 	output	  c1;
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| 	output	  locked;
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| `ifndef ALTERA_RESERVED_QIS
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| // synopsys translate_off
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| `endif
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| 	tri0	  areset;
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| `ifndef ALTERA_RESERVED_QIS
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| // synopsys translate_on
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| `endif
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| 
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| 	wire [4:0] sub_wire0;
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| 	wire  sub_wire3;
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| 	wire [0:0] sub_wire6 = 1'h0;
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| 	wire [1:1] sub_wire2 = sub_wire0[1:1];
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| 	wire [0:0] sub_wire1 = sub_wire0[0:0];
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| 	wire  c0 = sub_wire1;
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| 	wire  c1 = sub_wire2;
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| 	wire  locked = sub_wire3;
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| 	wire  sub_wire4 = inclk0;
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| 	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
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| 
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| 	altpll	altpll_component (
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| 				.areset (areset),
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| 				.inclk (sub_wire5),
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| 				.clk (sub_wire0),
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| 				.locked (sub_wire3),
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| 				.activeclock (),
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| 				.clkbad (),
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| 				.clkena ({6{1'b1}}),
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| 				.clkloss (),
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| 				.clkswitch (1'b0),
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| 				.configupdate (1'b0),
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| 				.enable0 (),
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| 				.enable1 (),
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| 				.extclk (),
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| 				.extclkena ({4{1'b1}}),
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| 				.fbin (1'b1),
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| 				.fbmimicbidir (),
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| 				.fbout (),
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| 				.fref (),
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| 				.icdrclk (),
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| 				.pfdena (1'b1),
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| 				.phasecounterselect ({4{1'b1}}),
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| 				.phasedone (),
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| 				.phasestep (1'b1),
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| 				.phaseupdown (1'b1),
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| 				.pllena (1'b1),
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| 				.scanaclr (1'b0),
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| 				.scanclk (1'b0),
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| 				.scanclkena (1'b1),
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| 				.scandata (1'b0),
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| 				.scandataout (),
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| 				.scandone (),
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| 				.scanread (1'b0),
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| 				.scanwrite (1'b0),
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| 				.sclkout0 (),
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| 				.sclkout1 (),
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| 				.vcooverrange (),
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| 				.vcounderrange ());
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| 	defparam
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| 		altpll_component.bandwidth_type = "HIGH",
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| 		altpll_component.clk0_divide_by = 1,
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| 		altpll_component.clk0_duty_cycle = 50,
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| 		altpll_component.clk0_multiply_by = 3,
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| 		altpll_component.clk0_phase_shift = "0",
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| 		altpll_component.clk1_divide_by = 1,
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| 		altpll_component.clk1_duty_cycle = 50,
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| 		altpll_component.clk1_multiply_by = 4,
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| 		altpll_component.clk1_phase_shift = "0",
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| 		altpll_component.compensate_clock = "CLK0",
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| 		altpll_component.inclk0_input_frequency = 37037,
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| 		altpll_component.intended_device_family = "Cyclone IV E",
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| 		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_3x",
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| 		altpll_component.lpm_type = "altpll",
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| 		altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
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| 		altpll_component.pll_type = "AUTO",
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| 		altpll_component.port_activeclock = "PORT_UNUSED",
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| 		altpll_component.port_areset = "PORT_USED",
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| 		altpll_component.port_clkbad0 = "PORT_UNUSED",
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| 		altpll_component.port_clkbad1 = "PORT_UNUSED",
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| 		altpll_component.port_clkloss = "PORT_UNUSED",
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| 		altpll_component.port_clkswitch = "PORT_UNUSED",
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| 		altpll_component.port_configupdate = "PORT_UNUSED",
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| 		altpll_component.port_fbin = "PORT_UNUSED",
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| 		altpll_component.port_inclk0 = "PORT_USED",
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| 		altpll_component.port_inclk1 = "PORT_UNUSED",
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| 		altpll_component.port_locked = "PORT_USED",
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| 		altpll_component.port_pfdena = "PORT_UNUSED",
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| 		altpll_component.port_phasecounterselect = "PORT_UNUSED",
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| 		altpll_component.port_phasedone = "PORT_UNUSED",
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| 		altpll_component.port_phasestep = "PORT_UNUSED",
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| 		altpll_component.port_phaseupdown = "PORT_UNUSED",
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| 		altpll_component.port_pllena = "PORT_UNUSED",
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| 		altpll_component.port_scanaclr = "PORT_UNUSED",
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| 		altpll_component.port_scanclk = "PORT_UNUSED",
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| 		altpll_component.port_scanclkena = "PORT_UNUSED",
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| 		altpll_component.port_scandata = "PORT_UNUSED",
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| 		altpll_component.port_scandataout = "PORT_UNUSED",
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| 		altpll_component.port_scandone = "PORT_UNUSED",
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| 		altpll_component.port_scanread = "PORT_UNUSED",
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| 		altpll_component.port_scanwrite = "PORT_UNUSED",
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| 		altpll_component.port_clk0 = "PORT_USED",
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| 		altpll_component.port_clk1 = "PORT_USED",
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| 		altpll_component.port_clk2 = "PORT_UNUSED",
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| 		altpll_component.port_clk3 = "PORT_UNUSED",
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| 		altpll_component.port_clk4 = "PORT_UNUSED",
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| 		altpll_component.port_clk5 = "PORT_UNUSED",
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| 		altpll_component.port_clkena0 = "PORT_UNUSED",
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| 		altpll_component.port_clkena1 = "PORT_UNUSED",
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| 		altpll_component.port_clkena2 = "PORT_UNUSED",
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| 		altpll_component.port_clkena3 = "PORT_UNUSED",
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| 		altpll_component.port_clkena4 = "PORT_UNUSED",
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| 		altpll_component.port_clkena5 = "PORT_UNUSED",
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| 		altpll_component.port_extclk0 = "PORT_UNUSED",
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| 		altpll_component.port_extclk1 = "PORT_UNUSED",
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| 		altpll_component.port_extclk2 = "PORT_UNUSED",
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| 		altpll_component.port_extclk3 = "PORT_UNUSED",
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| 		altpll_component.self_reset_on_loss_lock = "OFF",
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| 		altpll_component.width_clock = 5;
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| 
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| 
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| endmodule
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| 
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| // ============================================================
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| // CNX file retrieval info
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| // ============================================================
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| // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
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| // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
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| // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
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| // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
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| // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "High"
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| // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0"
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| // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1"
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| // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
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| // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
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| // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
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| // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
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| // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
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| // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
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| // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
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| // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
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| // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
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| // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
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| // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
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| // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
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| // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
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| // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "81.000000"
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| // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "108.000000"
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| // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
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| // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
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| // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
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| // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
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| // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
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| // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
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| // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
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| // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
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| // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
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| // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
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| // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
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| // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
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| // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
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| // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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| // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
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| // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
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| // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
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| // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
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| // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
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| // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
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| // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
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| // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
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| // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
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| // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
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| // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "3"
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| // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
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| // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
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| // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
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| // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
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| // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
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| // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
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| // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
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| // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
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| // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
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| // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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| // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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| // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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| // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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| // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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| // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
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| // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
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| // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
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| // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
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| // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
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| // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
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| // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
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| // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
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| // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
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| // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
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| // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
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| // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_2x.mif"
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| // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
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| // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
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| // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
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| // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
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| // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
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| // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
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| // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
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| // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
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| // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
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| // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
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| // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
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| // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
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| // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
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| // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
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| // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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| // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
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| // Retrieval info: PRIVATE: USE_CLK1 STRING "1"
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| // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
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| // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
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| // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
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| // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
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| // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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| // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "HIGH"
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| // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
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| // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
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| // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
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| // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
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| // Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
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| // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
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| // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
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| // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
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| // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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| // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
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| // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
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| // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
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| // Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
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| // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
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| // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
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| // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
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| // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
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| // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
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| // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
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| // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
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| // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
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| // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
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| // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
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| // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
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| // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
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| // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
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| // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
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| // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
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| // Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
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| // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
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| // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
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| // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
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| // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
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| // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
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| // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.v TRUE
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| // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.ppf TRUE
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| // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.inc FALSE
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| // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.cmp FALSE
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| // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x.bsf FALSE
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| // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_inst.v FALSE
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| // Retrieval info: GEN_FILE: TYPE_NORMAL pll_3x_bb.v FALSE
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| // Retrieval info: LIB_FILE: altera_mf
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| // Retrieval info: CBX_MODULE_PREFIX: ON
 |