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	 209130b167
			
		
	
	
		209130b167
		
	
	
	
	
		
			
			- integrate mask and border generation more deeply into the post processing chain - delay RLPF by one PP stage (reduce logic length after large mux) - synthesise a registers after several adder logics
		
			
				
	
	
		
			155 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			155 lines
		
	
	
		
			5.2 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| //
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| // Copyright (C) 2015-2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
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| //
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| // This file is part of Open Source Scan Converter project.
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| //
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| // This program is free software: you can redistribute it and/or modify
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| // it under the terms of the GNU General Public License as published by
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| // the Free Software Foundation, either version 3 of the License, or
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| // (at your option) any later version.
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| //
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| // This program is distributed in the hope that it will be useful,
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| // but WITHOUT ANY WARRANTY; without even the implied warranty of
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| // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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| // GNU General Public License for more details.
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| //
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| // You should have received a copy of the GNU General Public License
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| // along with this program.  If not, see <http://www.gnu.org/licenses/>.
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| //
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| 
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| `include "lat_tester_includes.v"
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| 
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| module videogen (
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|     input clk27,
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|     input reset_n,
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|     input lt_active,
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|     input [1:0] lt_mode,
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|     output [7:0] R_out,
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|     output [7:0] G_out,
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|     output [7:0] B_out,
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|     output reg HSYNC_out,
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|     output reg VSYNC_out,
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|     output PCLK_out,
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|     output reg ENABLE_out
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| );
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| 
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| //Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
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| parameter   H_SYNCLEN       =   10'd62;
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| parameter   H_BACKPORCH     =   10'd60;
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| parameter   H_ACTIVE        =   10'd720;
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| parameter   H_FRONTPORCH    =   10'd16;
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| parameter   H_TOTAL         =   10'd858;
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| 
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| parameter   V_SYNCLEN       =   10'd6;
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| parameter   V_BACKPORCH     =   10'd30;
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| parameter   V_ACTIVE        =   10'd480;
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| parameter   V_FRONTPORCH    =   10'd9;
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| parameter   V_TOTAL         =   10'd525;
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| 
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| parameter   H_OVERSCAN      =   10'd40; //at both sides
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| parameter   V_OVERSCAN      =   10'd16; //top and bottom
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| parameter   H_AREA          =   10'd640;
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| parameter   V_AREA          =   10'd448;
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| parameter   H_GRADIENT      =   10'd512;
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| parameter   V_GRADIENT      =   10'd256;
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| parameter   V_GRAYRAMP      =   10'd84;
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| parameter   H_BORDER        =   ((H_AREA-H_GRADIENT)>>1);
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| parameter   V_BORDER        =   ((V_AREA-V_GRADIENT)>>1);
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| 
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| parameter   X_START     =   H_SYNCLEN + H_BACKPORCH;
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| parameter   Y_START     =   V_SYNCLEN + V_BACKPORCH;
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| 
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| //Counters
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| reg [9:0] h_cnt; //max. 1024
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| reg [9:0] v_cnt; //max. 1024
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| 
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| reg [9:0] xpos;
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| reg [9:0] ypos;
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| 
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| assign PCLK_out = clk27;
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| 
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| //R, G and B should be 0 outside of active area
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| assign R_out = ENABLE_out ? V_gen : 8'h00;
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| assign G_out = ENABLE_out ? V_gen : 8'h00;
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| assign B_out = ENABLE_out ? V_gen : 8'h00;
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| 
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| reg [7:0] V_gen;
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| 
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| 
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| //HSYNC gen (negative polarity)
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| always @(posedge clk27 or negedge reset_n)
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| begin
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|     if (!reset_n) begin
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|         h_cnt <= 0;
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|         HSYNC_out <= 0;
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|     end else begin
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|         //Hsync counter
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|         if (h_cnt < H_TOTAL-1)
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|             h_cnt <= h_cnt + 1'b1;
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|         else
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|             h_cnt <= 0;
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| 
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|         //Hsync signal
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|         HSYNC_out <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
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|     end
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| end
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| 
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| //VSYNC gen (negative polarity)
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| always @(posedge clk27 or negedge reset_n)
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| begin
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|     if (!reset_n) begin
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|         v_cnt <= 0;
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|         VSYNC_out <= 0;
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|     end else begin
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|         //Vsync counter
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|         if (h_cnt == H_TOTAL-1) begin
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|             if (v_cnt < V_TOTAL-1)
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|                 v_cnt <= v_cnt + 1'b1;
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|             else
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|                 v_cnt <= 0;
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|         end
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| 
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|         //Vsync signal
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|         VSYNC_out <= (v_cnt < V_SYNCLEN) ? 1'b0 : 1'b1;
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|     end
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| end
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| 
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| //Data and ENABLE gen
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| always @(posedge clk27 or negedge reset_n)
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| begin
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|     if (!reset_n) begin
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|         V_gen <= 8'h00;
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|         ENABLE_out <= 1'b0;
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|     end else begin
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|         if (lt_active) begin
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|             case (lt_mode)
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|                 default: begin
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|                     V_gen <= 8'h00;
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|                 end
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|                 `LT_POS_TOPLEFT: begin
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|                     V_gen <= ((h_cnt < (X_START+(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt < (Y_START+(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
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|                 end
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|                 `LT_POS_CENTER: begin
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|                     V_gen <= ((h_cnt >= (X_START+(H_ACTIVE/2)-(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (h_cnt < (X_START+(H_ACTIVE/2)+(H_ACTIVE/(`LT_WIDTH_DIV*2)))) && (v_cnt >= (Y_START+(V_ACTIVE/2)-(V_ACTIVE/(`LT_HEIGHT_DIV*2)))) && (v_cnt < (Y_START+(V_ACTIVE/2)+(V_ACTIVE/(`LT_HEIGHT_DIV*2))))) ? 8'hff : 8'h00;
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|                 end
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|                 `LT_POS_BOTTOMRIGHT: begin
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|                     V_gen <= ((h_cnt >= (X_START+H_ACTIVE-(H_ACTIVE/`LT_WIDTH_DIV))) && (v_cnt >= (Y_START+V_ACTIVE-(V_ACTIVE/`LT_HEIGHT_DIV)))) ? 8'hff : 8'h00;
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|                 end
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|             endcase
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|         end else begin
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|             if ((h_cnt < X_START+H_OVERSCAN) || (h_cnt >= X_START+H_OVERSCAN+H_AREA) || (v_cnt < Y_START+V_OVERSCAN) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA))
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|                 V_gen <= (h_cnt[0] ^ v_cnt[0]) ? 8'hff : 8'h00;
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|             else if ((h_cnt < X_START+H_OVERSCAN+H_BORDER) || (h_cnt >= X_START+H_OVERSCAN+H_AREA-H_BORDER) || (v_cnt < Y_START+V_OVERSCAN+V_BORDER) || (v_cnt >= Y_START+V_OVERSCAN+V_AREA-V_BORDER))
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|                 V_gen <= 8'h50;
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|             else if (v_cnt >= Y_START+V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
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|                 V_gen <= (((h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 4) << 3) + (h_cnt - (X_START+H_OVERSCAN+H_BORDER) >> 6);
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|             else
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|                 V_gen <= (h_cnt - (X_START+H_OVERSCAN+H_BORDER)) >> 1;
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|         end
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| 
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|         ENABLE_out <= (h_cnt >= X_START && h_cnt < X_START + H_ACTIVE && v_cnt >= Y_START && v_cnt < Y_START + V_ACTIVE);
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|     end
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| end
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| 
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| endmodule
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