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			66 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			66 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| //
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| // Copyright (C) 2015-2023  Markus Hiienkari <mhiienka@niksula.hut.fi>
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| //
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| // This file is part of Open Source Scan Converter project.
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| //
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| // This program is free software: you can redistribute it and/or modify
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| // it under the terms of the GNU General Public License as published by
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| // the Free Software Foundation, either version 3 of the License, or
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| // (at your option) any later version.
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| //
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| // This program is distributed in the hope that it will be useful,
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| // but WITHOUT ANY WARRANTY; without even the implied warranty of
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| // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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| // GNU General Public License for more details.
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| //
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| // You should have received a copy of the GNU General Public License
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| // along with this program.  If not, see <http://www.gnu.org/licenses/>.
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| //
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| 
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| module videogen (
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|     input pclk,
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|     input [11:0] xpos,
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|     input [10:0] ypos,
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|     output reg [7:0] R_out,
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|     output reg [7:0] G_out,
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|     output reg [7:0] B_out
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| );
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| 
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| //Parameters for 720x480@59.94Hz (858px x 525lines, pclk 27MHz -> 59.94Hz)
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| parameter   H_SYNCLEN       =   10'd62;
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| parameter   H_BACKPORCH     =   10'd60;
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| parameter   H_ACTIVE        =   10'd720;
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| parameter   H_FRONTPORCH    =   10'd16;
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| parameter   H_TOTAL         =   10'd858;
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| 
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| parameter   V_SYNCLEN       =   10'd6;
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| parameter   V_BACKPORCH     =   10'd30;
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| parameter   V_ACTIVE        =   10'd480;
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| parameter   V_FRONTPORCH    =   10'd9;
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| parameter   V_TOTAL         =   10'd525;
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| 
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| parameter   H_OVERSCAN      =   10'd40; //at both sides
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| parameter   V_OVERSCAN      =   10'd16; //top and bottom
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| parameter   H_AREA          =   10'd640;
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| parameter   V_AREA          =   10'd448;
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| parameter   H_GRADIENT      =   10'd512;
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| parameter   V_GRADIENT      =   10'd256;
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| parameter   V_GRAYRAMP      =   10'd84;
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| parameter   H_BORDER        =   ((H_AREA-H_GRADIENT)>>1);
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| parameter   V_BORDER        =   ((V_AREA-V_GRADIENT)>>1);
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| 
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| // Pattern gen
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| always @(posedge pclk)
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| begin
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|     if ((xpos < H_OVERSCAN) || (xpos >= H_OVERSCAN+H_AREA) || (ypos < V_OVERSCAN) || (ypos >= V_OVERSCAN+V_AREA))
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|         {R_out, G_out, B_out} <= {3{(xpos[0] ^ ypos[0]) ? 8'hff : 8'h00}};
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|     else if ((xpos < H_OVERSCAN+H_BORDER) || (xpos >= H_OVERSCAN+H_AREA-H_BORDER) || (ypos < V_OVERSCAN+V_BORDER) || (ypos >= V_OVERSCAN+V_AREA-V_BORDER))
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|         {R_out, G_out, B_out} <= {3{8'h50}};
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|     else if (ypos >= V_OVERSCAN+V_BORDER+V_GRADIENT-V_GRAYRAMP)
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|         {R_out, G_out, B_out} <= {3{8'((((xpos - (H_OVERSCAN+H_BORDER)) >> 4) << 3) + (xpos - (H_OVERSCAN+H_BORDER) >> 6))}};
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|     else
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|         {R_out, G_out, B_out} <= {3{8'((xpos - (H_OVERSCAN+H_BORDER)) >> 1)}};
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| end
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| 
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| endmodule
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