mirror of
https://github.com/marqs85/ossc
synced 2025-10-28 14:36:04 +03:00
160 lines
5.7 KiB
Tcl
160 lines
5.7 KiB
Tcl
#
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# request TCL package from ACDS 16.1
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#
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package require -exact qsys 16.1
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#
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# module
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#
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set_module_property DESCRIPTION "OSD generator"
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set_module_property NAME osd_generator
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#set_module_property VERSION 18.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Processors and Peripherals"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME osd_generator
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# parameters
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#
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#add_parameter USE_MEMORY_BLOCKS INTEGER 1
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#set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks for character array"
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#set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean
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#set_parameter_property USE_MEMORY_BLOCKS UNITS None
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#set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL osd_generator_top
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
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add_fileset SIM_VERILOG SIM_VERILOG "" ""
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false
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set_fileset_property SIM_VERILOG TOP_LEVEL osd_generator_top
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add_fileset_file osd_generator_top.sv VERILOG PATH osd_generator_top.sv
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#
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# parameters
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#
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#
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# display items
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#
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk_i clk Input 1
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#
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# connection point reset_sink
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#
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock_sink
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_i reset Input 1
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#
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# connection point avalon_s
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#
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add_interface avalon_s avalon end
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set_interface_property avalon_s addressUnits WORDS
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set_interface_property avalon_s associatedClock clock_sink
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set_interface_property avalon_s associatedReset reset_sink
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set_interface_property avalon_s bitsPerSymbol 8
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set_interface_property avalon_s burstOnBurstBoundariesOnly false
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set_interface_property avalon_s burstcountUnits WORDS
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set_interface_property avalon_s explicitAddressSpan 0
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set_interface_property avalon_s holdTime 0
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set_interface_property avalon_s linewrapBursts false
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set_interface_property avalon_s maximumPendingReadTransactions 0
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set_interface_property avalon_s maximumPendingWriteTransactions 0
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set_interface_property avalon_s readLatency 0
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set_interface_property avalon_s readWaitTime 1
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set_interface_property avalon_s setupTime 0
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set_interface_property avalon_s timingUnits Cycles
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set_interface_property avalon_s writeWaitTime 0
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set_interface_property avalon_s ENABLED true
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set_interface_property avalon_s EXPORT_OF ""
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set_interface_property avalon_s PORT_NAME_MAP ""
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set_interface_property avalon_s CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_s SVD_ADDRESS_GROUP ""
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add_interface_port avalon_s avalon_s_address address Input 8
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add_interface_port avalon_s avalon_s_writedata writedata Input 32
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add_interface_port avalon_s avalon_s_readdata readdata Output 32
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add_interface_port avalon_s avalon_s_byteenable byteenable Input 4
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add_interface_port avalon_s avalon_s_write write Input 1
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add_interface_port avalon_s avalon_s_read read Input 1
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add_interface_port avalon_s avalon_s_chipselect chipselect Input 1
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add_interface_port avalon_s avalon_s_waitrequest_n waitrequest_n Output 1
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set_interface_assignment avalon_s embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_s embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_s embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_s embeddedsw.configuration.isPrintableDevice 0
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#
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# connection point bus
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#
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#add_sv_interface bus osd_if
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# Setting the parameter property to add SV interface parameters
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#set_parameter_property my_interface_parameter SV_INTERFACE_PARAMETER bus
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# Setting the port properties to add them to SV interface port set_port_property clk SV_INTERFACE_PORT bus #set_port_property p1 SV_INTERFACE_PORT bus
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#set_port_property p2 SV_INTERFACE_PORT bus
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#set_port_property p1 SV_INTERFACE_SIGNAL bus
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#set_port_property p2 SV_INTERFACE_SIGNAL bus
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#Adding the SV Interface File
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#add_fileset_file osd_if.sv SYSTEM_VERILOG PATH osd_if.sv SYSTEMVERILOG_INTERFACE
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#
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# connection point osd_if
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#
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add_interface osd_if conduit end
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set_interface_property osd_if associatedClock ""
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set_interface_property osd_if associatedReset ""
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set_interface_property osd_if ENABLED true
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set_interface_property osd_if EXPORT_OF ""
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set_interface_property osd_if PORT_NAME_MAP ""
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set_interface_property osd_if CMSIS_SVD_VARIABLES ""
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set_interface_property osd_if SVD_ADDRESS_GROUP ""
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add_interface_port osd_if vclk vclk Input 1
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add_interface_port osd_if xpos xpos Input 11
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add_interface_port osd_if ypos ypos Input 11
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add_interface_port osd_if osd_enable osd_enable Output 1
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add_interface_port osd_if osd_color osd_color Output 2
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