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			76 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			76 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| //
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| // Copyright (C) 2017  Markus Hiienkari <mhiienka@niksula.hut.fi>
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| //
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| // This file is part of Open Source Scan Converter project.
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| //
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| // This program is free software: you can redistribute it and/or modify
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| // it under the terms of the GNU General Public License as published by
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| // the Free Software Foundation, either version 3 of the License, or
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| // (at your option) any later version.
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| //
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| // This program is distributed in the hope that it will be useful,
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| // but WITHOUT ANY WARRANTY; without even the implied warranty of
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| // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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| // GNU General Public License for more details.
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| //
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| // You should have received a copy of the GNU General Public License
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| // along with this program.  If not, see <http://www.gnu.org/licenses/>.
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| //
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| 
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| #ifndef PCM1862_REGS_H_
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| #define PCM1862_REGS_H_
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| 
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| #define PCM1862_BASE (0x94>>1)
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| 
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| #define PCM1862_PAGESEL         0x00
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| 
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| /* Page 0 registers */
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| 
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| #define PCM1862_PGA1L           0x01
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| #define PCM1862_PGA1R           0x02
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| #define PCM1862_PGA2L           0x03
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| #define PCM1862_PGA2R           0x04
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| #define PCM1862_PGACONFIG       0x05
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| #define PCM1862_ADC1L           0x06
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| #define PCM1862_ADC1R           0x07
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| #define PCM1862_ADC2L           0x08
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| #define PCM1862_ADC2R           0x09
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| #define PCM1862_ADC2CONFIG      0x0A
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| #define PCM1862_PCMFMT          0x0B
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| #define PCM1862_TDMFMT          0x0C
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| #define PCM1862_TXTDM_OFFSET    0x0D
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| #define PCM1862_RXTDM_OFFSET    0x0E
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| #define PCM1862_DPGA1_GAIN_L    0x0F
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| 
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| #define PCM1862_DPGA1_GAIN_R    0x16
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| #define PCM1862_DPGA2_GAIN_L    0x17
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| #define PCM1862_DPGA2_GAIN_R    0x18
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| #define PCM1862_DPGA_CONFIG     0x19
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| #define PCM1862_DMIC_CONFIG     0x1A
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| #define PCM1862_DIN_RESAMPLE    0x1B
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| 
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| #define PCM1862_CLKCONFIG       0x20
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| #define PCM1862_DSP1_CLKDIV     0x21
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| #define PCM1862_DSP2_CLKDIV     0x22
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| #define PCM1862_ADC_CLKDIV      0x23
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| 
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| #define PCM1862_PLLCONFIG       0x28
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| 
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| #define PCM1862_PWR_CTRL        0x70
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| #define PCM1862_DSP_CTRL        0x71
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| 
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| 
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| /* Page 1 registers */
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| 
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| #define PCM1862_DSP2_CFG        0x01
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| #define PCM1862_DSP2_ADDR       0x02
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| #define PCM1862_DSP2_WDATA0     0x04
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| #define PCM1862_DSP2_WDATA1     0x05
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| #define PCM1862_DSP2_WDATA2     0x06
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| #define PCM1862_DSP2_RDATA0     0x08
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| #define PCM1862_DSP2_RDATA1     0x09
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| #define PCM1862_DSP2_RDATA2     0x0A
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| 
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| 
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| #endif /* PCM1862_REGS_H_ */
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