RomanRom2/ossc
1
0
Fork 0
mirror of https://github.com/marqs85/ossc synced 2025-10-26 05:26:02 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity
9d496383c3
ossc/ip/pll_reconfig
History
marqs 9d496383c3 optimize clock network 
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
..
inc optimize clock network 2019-10-06 23:54:32 +03:00
pll_reconfig_hw.tcl optimize clock network 2019-10-06 23:54:32 +03:00
pll_reconfig_sw.tcl optimize clock network 2019-10-06 23:54:32 +03:00
pll_reconfig_top.sv optimize clock network 2019-10-06 23:54:32 +03:00