marqs 9d496383c3 optimize clock network ...

* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl

2019-10-06 23:54:32 +03:00

..

char_array.qip

osd_generator: add M9K support to allow larger character array

2019-10-05 11:33:59 +03:00

char_array.v

osd_generator: add M9K support to allow larger character array

2019-10-05 11:33:59 +03:00

char_rom.qip

first OSD implementation

2019-10-03 02:03:43 +03:00

char_rom.v

first OSD implementation

2019-10-03 02:03:43 +03:00

ir_rcv.v

Improve IR receiver tolerance

2017-01-28 03:37:29 +02:00

lat_tester_includes.v

Scanline updates and fixes

2019-03-23 00:09:46 +02:00

lat_tester.v

Update latency tester

2017-10-28 12:10:54 +03:00

linebuf.qip

update to Quartus 17.1

2017-12-07 21:35:08 +02:00

linebuf.v

update to Quartus 17.1

2017-12-07 21:35:08 +02:00

lpm_mult_4_hybr_ref_pre.qip

add missing IP files

2018-03-06 09:36:38 +01:00

lpm_mult_4_hybr_ref_pre.v

add missing IP files

2018-03-06 09:36:38 +01:00

lpm_mult_4_hybr_ref.qip

various post processing pipeline updates:

2018-03-06 09:36:21 +01:00

lpm_mult_4_hybr_ref.v

finer granulated steps for hybrid sl settings

2018-03-07 10:21:18 +01:00

lpm_mult_4_sl.qip

add missing IP files

2018-03-06 09:33:28 +01:00

lpm_mult_4_sl.v

SL Multiplication:

2018-03-06 09:34:12 +01:00

ossc.v

optimize clock network

2019-10-06 23:54:32 +03:00

pll_2x.ppf

optimize clock network

2019-10-06 23:54:32 +03:00

pll_2x.qip

optimize clock network

2019-10-06 23:54:32 +03:00

pll_2x.v

optimize clock network

2019-10-06 23:54:32 +03:00

pll_config_2x_5x_data.mif

optimize clock network

2019-10-06 23:54:32 +03:00

pll_config_3x_4x_data.mif

optimize clock network

2019-10-06 23:54:32 +03:00

scanconverter.v

optimize clock network

2019-10-06 23:54:32 +03:00

timescale.v

Initial public release (FW 0.64)

2016-02-23 01:03:50 +02:00

videogen.v

optimize clock network

2019-10-06 23:54:32 +03:00