marqs 9d496383c3 optimize clock network ...

* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl

2019-10-06 23:54:32 +03:00

..

epcq_controller_0.hex

Initial public release (FW 0.64)

2016-02-23 01:03:50 +02:00

meminit.qip

Initial public release (FW 0.64)

2016-02-23 01:03:50 +02:00

meminit.spd

Initial public release (FW 0.64)

2016-02-23 01:03:50 +02:00

sys_onchip_memory2_0.hex

optimize clock network

2019-10-06 23:54:32 +03:00