mirror of
https://github.com/marqs85/ossc
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231 lines
9.7 KiB
Systemverilog
231 lines
9.7 KiB
Systemverilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// (C) 2001-2014 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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`timescale 1ps / 1ps
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module altera_epcq_controller_arb #(
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parameter CS_WIDTH = 1,
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parameter ENABLE_4BYTE_ADDR = 1,
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parameter ADDR_WIDTH = 22,
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parameter ASI_WIDTH = 1,
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parameter DEVICE_FAMILY = "CYCLONE V",
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parameter ASMI_ADDR_WIDTH = 22,
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parameter CHIP_SELS = 1
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)(
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input wire clk,
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input wire reset_n,
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// ports to access csr
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input wire avl_csr_write,
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input wire avl_csr_read,
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input wire [2:0] avl_csr_addr,
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input wire [31:0] avl_csr_wrdata,
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output reg [31:0] avl_csr_rddata,
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output reg avl_csr_rddata_valid,
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output reg avl_csr_waitrequest,
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// ports to access memory
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input wire avl_mem_write,
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input wire avl_mem_read,
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input wire [ADDR_WIDTH-1:0] avl_mem_addr,
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input wire [31:0] avl_mem_wrdata,
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input wire [3:0] avl_mem_byteenable,
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input wire [6:0] avl_mem_burstcount,
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output wire [31:0] avl_mem_rddata,
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output reg avl_mem_rddata_valid,
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output reg avl_mem_waitrequest,
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// interrupt signal
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output reg irq,
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// Disable dedicated active serial interface
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input wire [ASI_WIDTH-1:0] epcq_dataout,
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output reg epcq_dclk,
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output reg [CS_WIDTH-1:0] epcq_scein,
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output reg [ASI_WIDTH-1:0] epcq_sdoin,
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output reg [ASI_WIDTH-1:0] epcq_dataoe,
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// ASMI PARALLEL interface
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input wire [ASI_WIDTH-1:0] ddasi_dataoe,
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output reg [ASI_WIDTH-1:0] ddasi_dataout,
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input wire ddasi_dclk,
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input wire [CS_WIDTH-1:0] ddasi_scein,
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input reg [ASI_WIDTH-1:0] ddasi_sdoin,
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input wire asmi_busy,
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input wire asmi_data_valid,
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input wire [7:0] asmi_dataout,
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output reg asmi_clkin,
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output reg asmi_reset,
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output reg [CS_WIDTH-1:0] asmi_sce,
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output reg [ASMI_ADDR_WIDTH-1:0] asmi_addr,
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output reg [7:0] asmi_datain,
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output reg asmi_fast_read,
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output wire asmi_rden,
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output reg asmi_shift_bytes,
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output reg asmi_en4b_addr,
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output wire asmi_wren,
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output reg asmi_write,
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input wire asmi_illegal_erase,
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input wire asmi_illegal_write,
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input wire [7:0] asmi_rdid_out,
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input wire [7:0] asmi_status_out,
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input wire [7:0] asmi_epcs_id,
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output reg asmi_read_rdid,
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output reg asmi_read_status,
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output reg asmi_read_sid,
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output reg asmi_bulk_erase,
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output reg asmi_sector_erase,
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output reg asmi_sector_protect
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);
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reg temp_mem_write, temp_mem_read, mem_write, mem_read, back_pressured_ctrl;
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reg [ADDR_WIDTH-1:0] temp_mem_addr, mem_addr;
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reg [31:0] temp_mem_wrdata, mem_wrdata;
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reg [3:0] temp_mem_byteenable, mem_byteenable;
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reg [6:0] temp_mem_burstcount, mem_burstcount;
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wire back_pressured, temp_csr_waitrequest, temp_mem_waitrequest;
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//-------------------- Arbitration logic between avalon csr and mem interface -----------
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always @(posedge clk or negedge reset_n) begin
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if (~reset_n) begin
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back_pressured_ctrl <= 1'b0;
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end
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else if (back_pressured) begin
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back_pressured_ctrl <= 1'b1;
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end
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else if (~temp_csr_waitrequest) begin
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back_pressured_ctrl <= 1'b0;
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end
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end
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always @(posedge clk or negedge reset_n) begin
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if (~reset_n) begin
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mem_write <= 1'b0;
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mem_read <= 1'b0;
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mem_addr <= {ADDR_WIDTH{1'b0}};
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mem_wrdata <= {32{1'b0}};
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mem_byteenable <= {4{1'b0}};
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mem_burstcount <= {7{1'b0}};
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end
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else if ((avl_csr_write || avl_csr_read) && ~avl_csr_waitrequest && (avl_mem_write || avl_mem_read) && ~avl_mem_waitrequest) begin
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// to back pressure master
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mem_write <= avl_mem_write;
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mem_read <= avl_mem_read;
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mem_addr <= avl_mem_addr;
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mem_wrdata <= avl_mem_wrdata;
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mem_byteenable <= avl_mem_byteenable;
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mem_burstcount <= avl_mem_burstcount;
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end
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end
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assign back_pressured = ((avl_csr_write || avl_csr_read) && ~temp_csr_waitrequest && (avl_mem_write || avl_mem_read)) ? 1'b1 : 1'b0; // to back pressure controller
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assign avl_csr_waitrequest = (~avl_csr_write && ~avl_csr_read && back_pressured_ctrl) ? 1'b1 : temp_csr_waitrequest;
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assign avl_mem_waitrequest = (back_pressured_ctrl) ? 1'b1 : temp_mem_waitrequest;
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assign temp_mem_write = (back_pressured) ? 1'b0 :
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(back_pressured_ctrl) ? mem_write : avl_mem_write;
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assign temp_mem_read = (back_pressured) ? 1'b0 :
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(back_pressured_ctrl) ? mem_read : avl_mem_read;
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assign temp_mem_addr = (back_pressured) ? {ADDR_WIDTH{1'b0}} :
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(back_pressured_ctrl) ? mem_addr : avl_mem_addr;
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assign temp_mem_wrdata = (back_pressured) ? {32{1'b0}} :
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(back_pressured_ctrl) ? mem_wrdata : avl_mem_wrdata;
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assign temp_mem_byteenable = (back_pressured) ? {4{1'b0}} :
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(back_pressured_ctrl) ? mem_byteenable : avl_mem_byteenable;
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assign temp_mem_burstcount = (back_pressured) ? {7{1'b0}} :
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(back_pressured_ctrl) ? mem_burstcount : avl_mem_burstcount;
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//---------------------------------------------------------------------------------------//
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altera_epcq_controller #(
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.CS_WIDTH (CS_WIDTH),
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.DEVICE_FAMILY (DEVICE_FAMILY),
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.ADDR_WIDTH (ADDR_WIDTH),
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.ASMI_ADDR_WIDTH (ASMI_ADDR_WIDTH),
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.ASI_WIDTH (ASI_WIDTH),
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.CHIP_SELS (CHIP_SELS),
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.ENABLE_4BYTE_ADDR (ENABLE_4BYTE_ADDR)
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) controller (
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.clk (clk),
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.reset_n (reset_n),
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.avl_csr_read (avl_csr_read),
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.avl_csr_waitrequest (temp_csr_waitrequest),
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.avl_csr_write (avl_csr_write),
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.avl_csr_addr (avl_csr_addr),
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.avl_csr_wrdata (avl_csr_wrdata),
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.avl_csr_rddata (avl_csr_rddata),
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.avl_csr_rddata_valid (avl_csr_rddata_valid),
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.avl_mem_write (temp_mem_write),
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.avl_mem_burstcount (temp_mem_burstcount),
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.avl_mem_waitrequest (temp_mem_waitrequest),
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.avl_mem_read (temp_mem_read),
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.avl_mem_addr (temp_mem_addr),
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.avl_mem_wrdata (temp_mem_wrdata),
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.avl_mem_byteenable (temp_mem_byteenable),
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.avl_mem_rddata (avl_mem_rddata),
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.avl_mem_rddata_valid (avl_mem_rddata_valid),
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.asmi_status_out (asmi_status_out),
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.asmi_epcs_id (asmi_epcs_id),
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.asmi_illegal_erase (asmi_illegal_erase),
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.asmi_illegal_write (asmi_illegal_write),
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.ddasi_dataoe (ddasi_dataoe),
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.ddasi_dclk (ddasi_dclk),
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.ddasi_scein (ddasi_scein),
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.ddasi_sdoin (ddasi_sdoin),
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.asmi_busy (asmi_busy),
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.asmi_data_valid (asmi_data_valid),
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.asmi_dataout (asmi_dataout),
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.epcq_dataout (epcq_dataout),
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.ddasi_dataout (ddasi_dataout),
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.asmi_read_rdid (asmi_read_rdid),
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.asmi_read_status (asmi_read_status),
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.asmi_read_sid (asmi_read_sid),
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.asmi_bulk_erase (asmi_bulk_erase),
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.asmi_sector_erase (asmi_sector_erase),
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.asmi_sector_protect (asmi_sector_protect),
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.epcq_dclk (epcq_dclk),
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.epcq_scein (epcq_scein),
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.epcq_sdoin (epcq_sdoin),
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.epcq_dataoe (epcq_dataoe),
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.asmi_clkin (asmi_clkin),
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.asmi_reset (asmi_reset),
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.asmi_sce (asmi_sce),
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.asmi_addr (asmi_addr),
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.asmi_datain (asmi_datain),
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.asmi_fast_read (asmi_fast_read),
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.asmi_rden (asmi_rden),
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.asmi_shift_bytes (asmi_shift_bytes),
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.asmi_wren (asmi_wren),
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.asmi_write (asmi_write),
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.asmi_rdid_out (asmi_rdid_out),
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.asmi_en4b_addr (asmi_en4b_addr),
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.irq (irq)
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);
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endmodule
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