mirror of
https://github.com/marqs85/ossc
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67 lines
3.2 KiB
Verilog
67 lines
3.2 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE rev.B2 compliant I2C Master controller defines ////
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//// ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $
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//
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// $Date: 2001/11/05 11:59:25 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: i2c_master_defines.v,v $
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// Revision 1.3 2001/11/05 11:59:25 rherveille
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// Fixed wb_ack_o generation bug.
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// Fixed bug in the byte_controller statemachine.
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// Added headers.
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//
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// I2C registers wishbone addresses
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// bitcontroller states
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`define I2C_CMD_NOP 6'b000000
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`define I2C_CMD_START 6'b000001
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`define I2C_CMD_STOP 6'b000010
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`define I2C_CMD_WRITE 6'b000100
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`define I2C_CMD_READ 6'b001000
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`define SPI_CMD_WRITE 6'b010000
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`define SPI_CMD_READ 6'b100000
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