marqs 9d496383c3 optimize clock network ...

* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl

2019-10-06 23:54:32 +03:00

..

sys_controller

optimize clock network

2019-10-06 23:54:32 +03:00

sys_controller_bsp

optimize clock network

2019-10-06 23:54:32 +03:00

ossc_sw.project

switch to RV32E

2018-10-30 01:31:40 +02:00