mirror of
https://github.com/marqs85/ossc
synced 2025-10-26 21:46:02 +03:00
117 lines
4.5 KiB
Tcl
117 lines
4.5 KiB
Tcl
# TCL File Generated by Component Editor 15.1
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# Tue Dec 22 18:46:40 EET 2015
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# DO NOT MODIFY
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#
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# nios2_hw_crc32 "nios2_hw_crc32" v1.0
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# 2015.12.22.18:46:40
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#
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#
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#
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# request TCL package from ACDS 15.1
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#
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package require -exact qsys 15.1
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#
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# module nios2_hw_crc32
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#
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set_module_property DESCRIPTION ""
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set_module_property NAME nios2_hw_crc32
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set_module_property VERSION 17.1
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Custom Instruction Modules"
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME nios2_hw_crc32
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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#
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# file sets
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#
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL CRC_Custom_Instruction
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file CRC_Component.v VERILOG PATH hdl/CRC_Component.v
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add_fileset_file CRC_Custom_Instruction.v VERILOG PATH hdl/CRC_Custom_Instruction.v TOP_LEVEL_FILE
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#
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# parameters
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#
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add_parameter crc_width INTEGER 32
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set_parameter_property crc_width DEFAULT_VALUE 32
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set_parameter_property crc_width DISPLAY_NAME crc_width
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set_parameter_property crc_width TYPE INTEGER
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set_parameter_property crc_width UNITS None
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set_parameter_property crc_width HDL_PARAMETER true
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add_parameter polynomial_inital STD_LOGIC_VECTOR 4294967295
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set_parameter_property polynomial_inital DEFAULT_VALUE 4294967295
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set_parameter_property polynomial_inital DISPLAY_NAME polynomial_inital
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set_parameter_property polynomial_inital TYPE STD_LOGIC_VECTOR
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set_parameter_property polynomial_inital UNITS None
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set_parameter_property polynomial_inital ALLOWED_RANGES 0:17179869183
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set_parameter_property polynomial_inital HDL_PARAMETER true
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add_parameter polynomial STD_LOGIC_VECTOR 79764919
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set_parameter_property polynomial DEFAULT_VALUE 79764919
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set_parameter_property polynomial DISPLAY_NAME polynomial
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set_parameter_property polynomial TYPE STD_LOGIC_VECTOR
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set_parameter_property polynomial UNITS None
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set_parameter_property polynomial ALLOWED_RANGES 0:17179869183
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set_parameter_property polynomial HDL_PARAMETER true
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add_parameter reflected_input INTEGER 1
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set_parameter_property reflected_input DEFAULT_VALUE 1
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set_parameter_property reflected_input DISPLAY_NAME reflected_input
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set_parameter_property reflected_input TYPE INTEGER
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set_parameter_property reflected_input UNITS None
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set_parameter_property reflected_input HDL_PARAMETER true
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add_parameter reflected_output INTEGER 1
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set_parameter_property reflected_output DEFAULT_VALUE 1
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set_parameter_property reflected_output DISPLAY_NAME reflected_output
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set_parameter_property reflected_output TYPE INTEGER
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set_parameter_property reflected_output UNITS None
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set_parameter_property reflected_output HDL_PARAMETER true
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add_parameter xor_output STD_LOGIC_VECTOR 4294967295
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set_parameter_property xor_output DEFAULT_VALUE 4294967295
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set_parameter_property xor_output DISPLAY_NAME xor_output
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set_parameter_property xor_output TYPE STD_LOGIC_VECTOR
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set_parameter_property xor_output UNITS None
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set_parameter_property xor_output ALLOWED_RANGES 0:17179869183
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set_parameter_property xor_output HDL_PARAMETER true
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#
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# display items
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#
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#
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# connection point nios_custom_instruction_slave
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#
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add_interface nios_custom_instruction_slave nios_custom_instruction end
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set_interface_property nios_custom_instruction_slave clockCycle 0
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set_interface_property nios_custom_instruction_slave operands 1
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set_interface_property nios_custom_instruction_slave ENABLED true
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set_interface_property nios_custom_instruction_slave EXPORT_OF ""
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set_interface_property nios_custom_instruction_slave PORT_NAME_MAP ""
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set_interface_property nios_custom_instruction_slave CMSIS_SVD_VARIABLES ""
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set_interface_property nios_custom_instruction_slave SVD_ADDRESS_GROUP ""
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add_interface_port nios_custom_instruction_slave clk clk Input 1
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add_interface_port nios_custom_instruction_slave clk_en clk_en Input 1
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add_interface_port nios_custom_instruction_slave dataa dataa Input 32
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add_interface_port nios_custom_instruction_slave done done Output 1
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add_interface_port nios_custom_instruction_slave n n Input 3
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add_interface_port nios_custom_instruction_slave reset reset Input 1
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add_interface_port nios_custom_instruction_slave result result Output 32
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add_interface_port nios_custom_instruction_slave start start Input 1
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