marqs 9d496383c3 optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl		2019-10-06 23:54:32 +03:00
..
drivers	optimize clock network	2019-10-06 23:54:32 +03:00
HAL	clean up and update README	2018-10-08 00:37:42 +03:00
alt_sys_init.c	integrate zero-riscy	2018-10-06 13:19:12 +03:00
create-this-bsp	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00
libhal_bsp.a	optimize clock network	2019-10-06 23:54:32 +03:00
linker.h	integrate zero-riscy	2018-10-06 13:19:12 +03:00
linker.x	integrate zero-riscy	2018-10-06 13:19:12 +03:00
Makefile	switch to RV32E	2018-10-30 01:31:40 +02:00
mem_init.mk	integrate zero-riscy	2018-10-06 13:19:12 +03:00
memory.gdb	integrate zero-riscy	2018-10-06 13:19:12 +03:00
public.mk	switch to RV32E	2018-10-30 01:31:40 +02:00
settings.bsp	integrate zero-riscy	2018-10-06 13:19:12 +03:00
system.h	optimize clock network	2019-10-06 23:54:32 +03:00