mirror of
https://github.com/marqs85/ossc
synced 2025-10-31 16:06:02 +03:00
328 lines
9.4 KiB
Verilog
328 lines
9.4 KiB
Verilog
//
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// Copyright (C) 2015-2018 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//`define DEBUG
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`define VIDEOGEN
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`define PO_RESET_WIDTH 27 //1us
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module ossc (
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input clk27,
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input ir_rx,
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inout scl,
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inout sda,
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input [1:0] btn,
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input [7:0] R_in,
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input [7:0] G_in,
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input [7:0] B_in,
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input FID_in,
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input VSYNC_in,
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input HSYNC_in,
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input PCLK_in,
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output [7:0] HDMI_TX_RD,
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output [7:0] HDMI_TX_GD,
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output [7:0] HDMI_TX_BD,
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output HDMI_TX_DE,
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output HDMI_TX_HS,
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output HDMI_TX_VS,
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output HDMI_TX_PCLK,
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input HDMI_TX_INT_N,
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input HDMI_TX_MODE,
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output hw_reset_n,
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output LED_G,
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output LED_R,
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output LCD_RS,
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output LCD_CS_N,
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output LCD_BL,
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output SD_CLK,
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inout SD_CMD,
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inout [3:0] SD_DAT
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);
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wire [15:0] sys_ctrl;
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wire h_unstable;
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wire [1:0] pclk_lock;
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wire [1:0] pll_lock_lost;
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wire [31:0] h_info, h_info2, v_info, extra_info;
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wire [10:0] vmax, vmax_tvp;
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wire [1:0] fpga_vsyncgen;
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wire ilace_flag;
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wire [19:0] pcnt_frame;
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wire [15:0] ir_code;
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wire [7:0] ir_code_cnt;
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wire [7:0] R_out, G_out, B_out;
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wire HSYNC_out;
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wire VSYNC_out;
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wire PCLK_out;
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wire DE_out;
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wire [7:0] R_out_videogen, G_out_videogen, B_out_videogen;
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wire HSYNC_out_videogen;
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wire VSYNC_out_videogen;
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wire PCLK_out_videogen;
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wire DE_out_videogen;
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reg [7:0] po_reset_ctr = 0;
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reg po_reset_n = 1'b0;
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wire jtagm_reset_req;
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wire sys_reset_n = (po_reset_n & ~jtagm_reset_req);
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reg [7:0] R_in_L, G_in_L, B_in_L;
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reg HSYNC_in_L, VSYNC_in_L, FID_in_L;
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reg [1:0] btn_L, btn_LL;
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reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL, HDMI_TX_MODE_L, HDMI_TX_MODE_LL;
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wire lt_active = sys_ctrl[15];
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wire lt_armed = sys_ctrl[14];
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wire [1:0] lt_mode = sys_ctrl[13:12];
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wire [1:0] lt_mode_synced;
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wire [15:0] lt_lat_result;
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wire [11:0] lt_stb_result;
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wire lt_finished;
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wire remote_event = sys_ctrl[8];
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reg remove_event_prev;
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reg [14:0] to_ctr, to_ctr_ms;
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wire lcd_bl_timeout;
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// Latch inputs from TVP7002 (synchronized to PCLK_in)
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always @(posedge PCLK_in or negedge hw_reset_n)
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begin
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if (!hw_reset_n) begin
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R_in_L <= 8'h00;
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G_in_L <= 8'h00;
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B_in_L <= 8'h00;
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HSYNC_in_L <= 1'b0;
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VSYNC_in_L <= 1'b0;
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FID_in_L <= 1'b0;
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end else begin
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R_in_L <= R_in;
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G_in_L <= G_in;
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B_in_L <= B_in;
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HSYNC_in_L <= HSYNC_in;
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VSYNC_in_L <= VSYNC_in;
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FID_in_L <= FID_in;
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end
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end
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// Insert synchronizers to async inputs (synchronize to CPU clock)
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always @(posedge clk27 or negedge po_reset_n)
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begin
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if (!po_reset_n) begin
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btn_L <= 2'b00;
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btn_LL <= 2'b00;
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ir_rx_L <= 1'b0;
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ir_rx_LL <= 1'b0;
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HDMI_TX_INT_N_L <= 1'b0;
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HDMI_TX_INT_N_LL <= 1'b0;
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HDMI_TX_MODE_L <= 1'b0;
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HDMI_TX_MODE_LL <= 1'b0;
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end else begin
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btn_L <= btn;
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btn_LL <= btn_L;
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ir_rx_L <= ir_rx;
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ir_rx_LL <= ir_rx_L;
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HDMI_TX_INT_N_L <= HDMI_TX_INT_N;
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HDMI_TX_INT_N_LL <= HDMI_TX_INT_N_L;
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HDMI_TX_MODE_L <= HDMI_TX_MODE;
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HDMI_TX_MODE_LL <= HDMI_TX_MODE_L;
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end
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end
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// Power-on reset pulse generation (not strictly necessary)
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always @(posedge clk27)
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begin
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if (po_reset_ctr == `PO_RESET_WIDTH)
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po_reset_n <= 1'b1;
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else
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po_reset_ctr <= po_reset_ctr + 1'b1;
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end
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assign hw_reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
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`ifdef DEBUG
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assign LED_R = HSYNC_in_L;
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assign LED_G = VSYNC_in_L;
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`else
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assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 2'h0)|h_unstable);
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assign LED_G = (ir_code == 0);
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`endif
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assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
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assign LCD_CS_N = sys_ctrl[6];
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assign LCD_RS = sys_ctrl[5];
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wire lcd_bl_on = sys_ctrl[4]; //hw_reset_n in v1.2 PCB
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wire [1:0] lcd_bl_time = sys_ctrl[3:2];
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assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
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`ifdef VIDEOGEN
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wire videogen_sel;
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assign videogen_sel = ~sys_ctrl[1];
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assign HDMI_TX_RD = videogen_sel ? R_out_videogen : R_out;
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assign HDMI_TX_GD = videogen_sel ? G_out_videogen : G_out;
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assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
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assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
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assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
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assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
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assign HDMI_TX_DE = videogen_sel ? DE_out_videogen : DE_out;
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`else
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wire videogen_sel;
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assign videogen_sel = 1'b0;
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assign HDMI_TX_RD = R_out;
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assign HDMI_TX_GD = G_out;
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assign HDMI_TX_BD = B_out;
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assign HDMI_TX_HS = HSYNC_out;
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assign HDMI_TX_VS = VSYNC_out;
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assign HDMI_TX_PCLK = PCLK_out;
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assign HDMI_TX_DE = DE_out;
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`endif
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// LCD backlight timeout counters
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always @(posedge clk27)
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begin
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if (remote_event != remove_event_prev) begin
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to_ctr <= 15'd0;
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to_ctr_ms <= 15'd0;
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end else begin
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if (to_ctr == 27000-1) begin
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to_ctr <= 0;
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if (to_ctr_ms < 15'h7fff)
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to_ctr_ms <= to_ctr_ms + 1'b1;
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end else begin
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to_ctr <= to_ctr + 1'b1;
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end
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end
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case (lcd_bl_time)
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default: lcd_bl_timeout <= 0; //off
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2'b01: lcd_bl_timeout <= (to_ctr_ms >= 3000); //3s
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2'b10: lcd_bl_timeout <= (to_ctr_ms >= 10000); //10s
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2'b11: lcd_bl_timeout <= (to_ctr_ms >= 30000); //30s
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endcase
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remove_event_prev <= remote_event;
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end
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sys sys_inst(
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.clk_clk (clk27),
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.reset_reset_n (sys_reset_n),
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.pulpino_0_config_testmode_i (1'b0),
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.pulpino_0_config_fetch_enable_i (1'b1),
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.pulpino_0_config_clock_gating_i (1'b0),
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.pulpino_0_config_boot_addr_i (32'h00010000),
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.master_0_master_reset_reset (jtagm_reset_req),
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.i2c_opencores_0_export_scl_pad_io (scl),
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.i2c_opencores_0_export_sda_pad_io (sda),
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.i2c_opencores_0_export_spi_miso_pad_i (1'b0),
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.i2c_opencores_1_export_scl_pad_io (SD_CLK),
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.i2c_opencores_1_export_sda_pad_io (SD_CMD),
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.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
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.pio_0_sys_ctrl_out_export (sys_ctrl),
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.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE_LL, btn_LL, ir_code}),
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.pio_2_status_in_export ({VSYNC_out, 2'b00, vmax_tvp, fpga_vsyncgen, 4'h0, ilace_flag, vmax}),
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.pio_3_h_info_out_export (h_info),
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.pio_4_h_info2_out_export (h_info2),
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.pio_5_v_info_out_export (v_info),
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.pio_6_extra_info_out_export (extra_info),
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.pio_7_lt_results_in_export ({lt_finished, 3'h0, lt_stb_result, lt_lat_result}),
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.pio_8_pcnt_vhz_in_export ({12'h000, pcnt_frame})
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);
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scanconverter scanconverter_inst (
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.reset_n (hw_reset_n),
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.PCLK_in (PCLK_in),
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.clk27 (clk27),
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.HSYNC_in (HSYNC_in_L),
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.VSYNC_in (VSYNC_in_L),
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.FID_in (FID_in_L),
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.R_in (R_in_L),
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.G_in (G_in_L),
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.B_in (B_in_L),
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.h_info (h_info),
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.h_info2 (h_info2),
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.v_info (v_info),
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.extra_info (extra_info),
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.R_out (R_out),
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.G_out (G_out),
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.B_out (B_out),
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.HSYNC_out (HSYNC_out),
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.VSYNC_out (VSYNC_out),
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.PCLK_out (PCLK_out),
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.DE_out (DE_out),
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.h_unstable (h_unstable),
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.fpga_vsyncgen (fpga_vsyncgen),
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.pclk_lock (pclk_lock),
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.pll_lock_lost (pll_lock_lost),
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.vmax (vmax),
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.vmax_tvp (vmax_tvp),
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.pcnt_frame (pcnt_frame),
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.ilace_flag (ilace_flag),
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.lt_active (lt_active),
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.lt_mode (lt_mode_synced)
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);
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ir_rcv ir0 (
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.clk27 (clk27),
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.reset_n (po_reset_n),
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.ir_rx (ir_rx_LL),
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.ir_code (ir_code),
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.ir_code_ack (),
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.ir_code_cnt (ir_code_cnt)
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);
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lat_tester lt0 (
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.clk27 (clk27),
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.pclk (HDMI_TX_PCLK),
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.active (lt_active),
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.armed (lt_armed),
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.sensor (btn_LL[1]),
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.trigger (HDMI_TX_DE & HDMI_TX_GD[0]),
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.VSYNC_in (HDMI_TX_VS),
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.mode_in (lt_mode),
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.mode_synced (lt_mode_synced),
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.lat_result (lt_lat_result),
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.stb_result (lt_stb_result),
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.finished (lt_finished)
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);
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`ifdef VIDEOGEN
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videogen vg0 (
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.clk27 (clk27),
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.reset_n (po_reset_n & videogen_sel),
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.lt_active (lt_active),
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.lt_mode (lt_mode_synced),
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.R_out (R_out_videogen),
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.G_out (G_out_videogen),
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.B_out (B_out_videogen),
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.HSYNC_out (HSYNC_out_videogen),
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.VSYNC_out (VSYNC_out_videogen),
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.PCLK_out (PCLK_out_videogen),
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.ENABLE_out (DE_out_videogen)
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);
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`endif
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endmodule
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