RomanRom2/ossc
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mirror of https://github.com/marqs85/ossc synced 2026-10-30 19:57:20 +03:00
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c8b542b91750030e4a6fd1c72560fd622ab07971
ossc/software/sys_controller/mem_init
T
History
marqs c8b542b917 * 480p/576p line2x 
* 480i/576i passthrough
* alternating scanlines for interlaced material
2016-07-09 23:12:35 +03:00
..
epcq_controller_0.hex
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
meminit.qip
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
meminit.spd
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
sys_onchip_memory2_0.hex
* 480p/576p line2x
2016-07-09 23:12:35 +03:00