mirror of
https://github.com/marqs85/ossc
synced 2025-10-31 16:06:02 +03:00
262 lines
12 KiB
Plaintext
262 lines
12 KiB
Plaintext
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 64-Bit
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# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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# Date created = 17:27:03 May 17, 2014
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# ossc_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE15E22C8
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set_global_assignment -name TOP_LEVEL_ENTITY ossc
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION "24.1std.0 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_location_assignment PIN_25 -to clk27
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set_location_assignment PIN_99 -to hw_reset_n
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set_location_assignment PIN_23 -to ir_rx
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set_location_assignment PIN_126 -to cfg[1]
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set_location_assignment PIN_127 -to cfg[0]
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#============================================================
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# TVP7002
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#============================================================
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set_location_assignment PIN_52 -to TVP_R_i[0]
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set_location_assignment PIN_53 -to TVP_R_i[1]
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set_location_assignment PIN_54 -to TVP_R_i[2]
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set_location_assignment PIN_55 -to TVP_R_i[3]
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set_location_assignment PIN_58 -to TVP_R_i[4]
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set_location_assignment PIN_59 -to TVP_R_i[5]
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set_location_assignment PIN_60 -to TVP_R_i[6]
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set_location_assignment PIN_61 -to TVP_R_i[7]
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set_location_assignment PIN_88 -to TVP_B_i[7]
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set_location_assignment PIN_87 -to TVP_B_i[6]
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set_location_assignment PIN_86 -to TVP_B_i[5]
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set_location_assignment PIN_85 -to TVP_B_i[4]
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set_location_assignment PIN_83 -to TVP_B_i[3]
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set_location_assignment PIN_80 -to TVP_B_i[2]
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set_location_assignment PIN_77 -to TVP_B_i[1]
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set_location_assignment PIN_89 -to TVP_PCLK_i
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set_location_assignment PIN_76 -to TVP_B_i[0]
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set_location_assignment PIN_90 -to TVP_HS_i
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set_location_assignment PIN_91 -to TVP_VSYNC_i
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set_location_assignment PIN_98 -to TVP_SOG_i
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set_location_assignment PIN_72 -to TVP_G_i[7]
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set_location_assignment PIN_71 -to TVP_G_i[6]
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set_location_assignment PIN_69 -to TVP_G_i[5]
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set_location_assignment PIN_68 -to TVP_G_i[4]
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set_location_assignment PIN_67 -to TVP_G_i[3]
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set_location_assignment PIN_66 -to TVP_G_i[2]
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set_location_assignment PIN_65 -to TVP_G_i[1]
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set_location_assignment PIN_64 -to TVP_G_i[0]
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#============================================================
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# HDMITX
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#============================================================
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set_location_assignment PIN_113 -to HDMI_TX_PCLK
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set_location_assignment PIN_111 -to HDMI_TX_BD[3]
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set_location_assignment PIN_112 -to HDMI_TX_BD[4]
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set_location_assignment PIN_110 -to HDMI_TX_BD[2]
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set_location_assignment PIN_106 -to HDMI_TX_BD[1]
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set_location_assignment PIN_105 -to HDMI_TX_BD[0]
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set_location_assignment PIN_104 -to HDMI_TX_DE
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set_location_assignment PIN_103 -to HDMI_TX_HS
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set_location_assignment PIN_101 -to HDMI_TX_VS
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set_location_assignment PIN_114 -to HDMI_TX_BD[5]
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set_location_assignment PIN_115 -to HDMI_TX_BD[6]
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set_location_assignment PIN_119 -to HDMI_TX_BD[7]
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set_location_assignment PIN_120 -to HDMI_TX_GD[0]
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set_location_assignment PIN_121 -to HDMI_TX_GD[1]
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set_location_assignment PIN_125 -to HDMI_TX_GD[2]
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set_location_assignment PIN_132 -to HDMI_TX_GD[3]
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set_location_assignment PIN_133 -to HDMI_TX_GD[4]
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set_location_assignment PIN_134 -to HDMI_TX_GD[5]
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set_location_assignment PIN_135 -to HDMI_TX_GD[6]
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set_location_assignment PIN_136 -to HDMI_TX_GD[7]
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set_location_assignment PIN_137 -to HDMI_TX_RD[0]
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set_location_assignment PIN_141 -to HDMI_TX_RD[1]
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set_location_assignment PIN_142 -to HDMI_TX_RD[2]
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set_location_assignment PIN_143 -to HDMI_TX_RD[3]
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set_location_assignment PIN_144 -to HDMI_TX_RD[4]
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set_location_assignment PIN_7 -to HDMI_TX_RD[5]
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set_location_assignment PIN_10 -to HDMI_TX_RD[6]
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set_location_assignment PIN_11 -to HDMI_TX_RD[7]
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set_location_assignment PIN_100 -to HDMI_TX_INT_N
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#============================================================
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# SD card
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#============================================================
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set_location_assignment PIN_32 -to SD_CLK
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set_location_assignment PIN_31 -to SD_CMD
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set_location_assignment PIN_33 -to SD_DAT[0]
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set_location_assignment PIN_39 -to SD_DAT[1]
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set_location_assignment PIN_28 -to SD_DAT[2]
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set_location_assignment PIN_30 -to SD_DAT[3]
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#============================================================
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# Leds
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#============================================================
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set_location_assignment PIN_44 -to LED_G
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set_location_assignment PIN_46 -to LED_R
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#============================================================
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# I2C
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#============================================================
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set_location_assignment PIN_49 -to sda
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set_location_assignment PIN_50 -to scl
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#============================================================
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# Char LCD
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#============================================================
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set_location_assignment PIN_42 -to LCD_RS
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set_location_assignment PIN_43 -to LCD_CS_N
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set_location_assignment PIN_51 -to LCD_BL
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#============================================================
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# Buttons
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#============================================================
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set_location_assignment PIN_129 -to btn[1]
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set_location_assignment PIN_128 -to btn[0]
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
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set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
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set_global_assignment -name INI_VARS "FIOMGR_ENABLE_SPI_TIMING=ON"
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set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
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set_global_assignment -name OPTIMIZATION_MODE BALANCED
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set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
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set_global_assignment -name ENABLE_OCT_DONE OFF
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name GENERATE_RBF_FILE ON
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set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
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set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 50%
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#set_location_assignment PLL_4 -to "scanconverter:scanconverter_inst|pll_3x:pll_linetriple|altpll:altpll_component|pll_3x_altpll:auto_generated|pll1"
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#set_location_assignment PLL_3 -to "scanconverter:scanconverter_inst|pll_3x_lowfreq:pll_linetriple_lowfreq|altpll:altpll_component|pll_3x_lowfreq_altpll:auto_generated|pll1"
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#set_location_assignment PLL_1 -to "scanconverter:scanconverter_inst|pll_2x:pll_linedouble|altpll:altpll_component|pll_2x_altpll:auto_generated|pll1"
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set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1
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set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_new.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 1
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[0]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[3]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_BD[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_GD[7]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[1]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[5]
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set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to HDMI_TX_RD[7]
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set_global_assignment -name VERILOG_FILE rtl/videogen.v
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set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v
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set_global_assignment -name VERILOG_FILE rtl/ossc.v
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set_global_assignment -name VERILOG_FILE rtl/scanconverter.v
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set_global_assignment -name VERILOG_FILE rtl/linebuf_top.v
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set_global_assignment -name VERILOG_FILE rtl/tvp7002_frontend.v
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set_global_assignment -name VERILOG_FILE rtl/lat_tester.v
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set_global_assignment -name QIP_FILE sys/synthesis/sys.qip
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set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip
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set_global_assignment -name QIP_FILE rtl/linebuf.qip
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set_global_assignment -name QIP_FILE rtl/char_rom.qip
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set_global_assignment -name QIP_FILE rtl/pll_2x.qip
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set_global_assignment -name QIP_FILE rtl/lpm_mult_8x5_9.qip
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set_global_assignment -name QIP_FILE rtl/lpm_mult_sl.qip
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set_global_assignment -name SDC_FILE ossc.sdc
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set_global_assignment -name CDF_FILE output_files/Chain1.cdf
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set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name QIP_FILE rtl/char_array.qip
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set_global_assignment -name SEARCH_PATH rtl
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set_global_assignment -name SEARCH_PATH software/sys_controller/mem_init/
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set_global_assignment -name SEARCH_PATH ip/ibex_qsys/rtl_extra
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set_global_assignment -name VERILOG_MACRO "SYNTHESIS=<None>"
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set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |