mirror of
https://github.com/marqs85/ossc
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92 lines
3.1 KiB
C
92 lines
3.1 KiB
C
// Copyright 2017 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the “License”); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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/**
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* @file
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* @brief Register mapping for PULPino peripherals.
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*
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* Contains event register mappings for the PULPino SOC as
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* well as some general definitions for the overall system.
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*
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* @author Florian Zaruba
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*
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* @version 1.0
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*
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* @date 2/10/2015
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*
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*/
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#ifndef PULPINO_H
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#define PULPINO_H
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#define PULPINO_BASE_ADDR 0x10000000
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/** SOC PERIPHERALS */
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#define SOC_PERIPHERALS_BASE_ADDR ( PULPINO_BASE_ADDR + 0xA100000 )
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#define UART_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x0000 )
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#define GPIO_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x1000 )
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#define SPI_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x2000 )
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#define TIMER_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x3000 )
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#define EVENT_UNIT_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x4000 )
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#define I2C_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x5000 )
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#define FLL_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x6000 )
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#define SOC_CTRL_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x7000 )
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/** STDOUT */
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#define STDOUT_BASE_ADDR ( SOC_PERIPHERALS_BASE_ADDR + 0x10000 )
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#define FPUTCHAR_BASE_ADDR ( STDOUT_BASE_ADDR + 0x1000 )
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#define FILE_CMD_BASE_ADDR ( STDOUT_BASE_ADDR + 0x2000 )
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#define STREAM_BASE_ADDR ( STDOUT_BASE_ADDR + 0x3000 )
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/** Instruction RAM */
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#define INSTR_RAM_BASE_ADDR ( 0x00 )
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#define INSTR_RAM_START_ADDR ( 0x80 )
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/** ROM */
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#define ROM_BASE_ADDR ( 0x10000 )
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/** Data RAM */
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#define DATA_RAM_BASE_ADDR ( 0x00100000 )
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/** Registers and pointers */
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#define REGP(x) ((volatile unsigned int*)(x))
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#define REG(x) (*((volatile unsigned int*)(x)))
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#define REGP_8(x) (((volatile uint8_t*)(x)))
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/* pointer to mem of apb pulpino unit - PointerSocCtrl */
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#define __PSC__(a) *(unsigned volatile int*) (SOC_CTRL_BASE_ADDR + a)
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/** Peripheral Clock gating */
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#define CGREG __PSC__(0x04)
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/** Clock gate SPI */
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#define CGSPI 0x00
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/** Clock gate UART */
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#define CGUART 0x01
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/** Clock gate GPIO */
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#define CGGPIO 0x02
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/** Clock gate SPI Master */
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#define CGGSPIM 0x03
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/** Clock gate Timer */
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#define CGTIM 0x04
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/** Clock gate Event Unit */
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#define CGEVENT 0x05
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/** Clock gate I2C */
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#define CGGI2C 0x06
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/** Clock gate FLL */
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#define CGFLL 0x07
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/** Boot address register */
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#define BOOTREG __PSC__(0x08)
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#define RES_STATUS __PSC__(0x14)
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#endif
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