mirror of
https://github.com/marqs85/ossc_pcb
synced 2025-04-18 11:02:40 +03:00
update to Kicad 7 and restore RoHS and WEEE logos
This commit is contained in:
marqs
parent
c716680f89
commit
7b8cfe3acf
3902
fpga.kicad_sch
3902
fpga.kicad_sch
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@ -1,12 +1,12 @@
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G01*
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@ -1,12 +1,12 @@
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|
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|
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@ -1,12 +1,12 @@
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||||
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@ -1,12 +1,12 @@
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M48
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; DRILL file {KiCad 6.0.11+dfsg-1} date 2023-06-05T20:18:09 EEST
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FMAT,2
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3826
hdmitx.kicad_sch
3826
hdmitx.kicad_sch
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Load Diff
12828
ossc_board.kicad_pcb
12828
ossc_board.kicad_pcb
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Load Diff
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{
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"board": {
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"courtyards_overlap": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_type_mismatch": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"invalid_outline": "warning",
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"isolated_copper": "warning",
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"item_on_disabled_layer": "error",
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"padstack": "error",
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@ -97,7 +109,6 @@
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"unconnected_items": "error",
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},
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@ -107,18 +118,63 @@
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||||
"min_through_hole_diameter": 0.32999999999999996,
|
||||
"min_track_width": 0.16,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.6859999999999999,
|
||||
"solder_mask_to_copper_clearance": 0.0,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"teardrop_options": [
|
||||
{
|
||||
"td_allow_use_two_tracks": true,
|
||||
"td_curve_segcount": 5,
|
||||
"td_on_pad_in_zone": false,
|
||||
"td_onpadsmd": true,
|
||||
"td_onroundshapesonly": false,
|
||||
"td_ontrackend": false,
|
||||
"td_onviapad": true
|
||||
}
|
||||
],
|
||||
"teardrop_parameters": [
|
||||
{
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_round_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_rect_shape",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
},
|
||||
{
|
||||
"td_curve_segcount": 0,
|
||||
"td_height_ratio": 1.0,
|
||||
"td_length_ratio": 0.5,
|
||||
"td_maxheight": 2.0,
|
||||
"td_maxlen": 1.0,
|
||||
"td_target_name": "td_track_end",
|
||||
"td_width_to_size_filter_ratio": 0.9
|
||||
}
|
||||
],
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.2,
|
||||
@ -140,7 +196,8 @@
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
"layer_presets": [],
|
||||
"viewports": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
@ -324,18 +381,23 @@
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"conflicting_netclasses": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"endpoint_off_grid": "warning",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"missing_bidi_pin": "warning",
|
||||
"missing_input_pin": "warning",
|
||||
"missing_power_pin": "error",
|
||||
"missing_unit": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
@ -345,6 +407,7 @@
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"simulation_model_issue": "ignore",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
@ -362,7 +425,7 @@
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"bus_width": 12,
|
||||
"clearance": 0.16,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
@ -376,10 +439,10 @@
|
||||
"track_width": 0.22,
|
||||
"via_diameter": 0.686,
|
||||
"via_drill": 0.33,
|
||||
"wire_width": 6.0
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"bus_width": 12,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
@ -388,27 +451,15 @@
|
||||
"microvia_diameter": 0.508,
|
||||
"microvia_drill": 0.127,
|
||||
"name": "75ohm_vid",
|
||||
"nets": [
|
||||
"/tvp_board1/RGB1_B",
|
||||
"/tvp_board1/RGB1_G",
|
||||
"/tvp_board1/RGB1_R",
|
||||
"/tvp_board1/RGB1_S",
|
||||
"/tvp_board1/RGB2_B",
|
||||
"/tvp_board1/RGB2_G",
|
||||
"/tvp_board1/RGB2_R",
|
||||
"/tvp_board1/RGB3_B",
|
||||
"/tvp_board1/RGB3_G",
|
||||
"/tvp_board1/RGB3_R"
|
||||
],
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.64,
|
||||
"via_diameter": 0.686,
|
||||
"via_drill": 0.35,
|
||||
"wire_width": 6.0
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"bus_width": 12,
|
||||
"clearance": 0.16,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
@ -417,18 +468,15 @@
|
||||
"microvia_diameter": 0.508,
|
||||
"microvia_drill": 0.127,
|
||||
"name": "FAT_power",
|
||||
"nets": [
|
||||
"Net-(F1-Pad1)"
|
||||
],
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 1.0,
|
||||
"via_diameter": 1.5,
|
||||
"via_drill": 1.1,
|
||||
"wire_width": 6.0
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"bus_width": 12,
|
||||
"clearance": 0.16,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
@ -437,25 +485,15 @@
|
||||
"microvia_diameter": 0.508,
|
||||
"microvia_drill": 0.127,
|
||||
"name": "Power",
|
||||
"nets": [
|
||||
"/fpga1/VCCA",
|
||||
"/fpga1/VCCD_PLL",
|
||||
"/fpga1/VCCINT",
|
||||
"/hdmitx1/AVCC1V8",
|
||||
"/hdmitx1/DVDD1V8",
|
||||
"/tvp_board1/AVDD",
|
||||
"/tvp_board1/DVDD",
|
||||
"GND"
|
||||
],
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.686,
|
||||
"via_drill": 0.35,
|
||||
"wire_width": 6.0
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"bus_width": 12,
|
||||
"clearance": 0.16,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
@ -464,48 +502,209 @@
|
||||
"microvia_diameter": 0.508,
|
||||
"microvia_drill": 0.127,
|
||||
"name": "digi_hs",
|
||||
"nets": [
|
||||
"/fpga1/ASDO",
|
||||
"/fpga1/DATA0",
|
||||
"/fpga1/DCLK",
|
||||
"/fpga1/HDMITX_HSYNC",
|
||||
"/fpga1/HDMITX_INT_N",
|
||||
"/fpga1/HDMITX_PCLK",
|
||||
"/fpga1/HDMITX_R0",
|
||||
"/fpga1/HDMITX_R1",
|
||||
"/fpga1/HDMITX_R2",
|
||||
"/fpga1/HDMITX_R3",
|
||||
"/fpga1/HDMITX_R4",
|
||||
"/fpga1/HDMITX_R5",
|
||||
"/fpga1/HDMITX_R6",
|
||||
"/fpga1/HDMITX_R7",
|
||||
"/fpga1/HDMITX_VSYNC",
|
||||
"/fpga1/IR_RX",
|
||||
"/fpga1/SCL",
|
||||
"/fpga1/SDA",
|
||||
"/fpga1/nCSO",
|
||||
"/hdmitx1/TMDS_CLK+",
|
||||
"/hdmitx1/TMDS_CLK-",
|
||||
"/hdmitx1/TMDS_D0+",
|
||||
"/hdmitx1/TMDS_D0-",
|
||||
"/hdmitx1/TMDS_D1+",
|
||||
"/hdmitx1/TMDS_D1-",
|
||||
"/hdmitx1/TMDS_D2+",
|
||||
"/hdmitx1/TMDS_D2-",
|
||||
"/tvp_board1/PCLK"
|
||||
],
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.18,
|
||||
"via_diameter": 0.686,
|
||||
"via_drill": 0.33,
|
||||
"wire_width": 6.0
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
"version": 3
|
||||
},
|
||||
"net_colors": null
|
||||
"net_colors": null,
|
||||
"netclass_assignments": null,
|
||||
"netclass_patterns": [
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB1_B"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB1_G"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB1_R"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB1_S"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB2_B"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB2_G"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB2_R"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB3_B"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB3_G"
|
||||
},
|
||||
{
|
||||
"netclass": "75ohm_vid",
|
||||
"pattern": "/tvp_board1/RGB3_R"
|
||||
},
|
||||
{
|
||||
"netclass": "FAT_power",
|
||||
"pattern": "Net-(F1-Pad1)"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "/fpga1/VCCA"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "/fpga1/VCCD_PLL"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "/fpga1/VCCINT"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "/hdmitx1/AVCC1V8"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "/hdmitx1/DVDD1V8"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "/tvp_board1/AVDD"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "/tvp_board1/DVDD"
|
||||
},
|
||||
{
|
||||
"netclass": "Power",
|
||||
"pattern": "GND"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/ASDO"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/DATA0"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/DCLK"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_HSYNC"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_INT_N"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_PCLK"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R0"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R1"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R2"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R3"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R4"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R5"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R6"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_R7"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/HDMITX_VSYNC"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/IR_RX"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/SCL"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/SDA"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/fpga1/nCSO"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_CLK+"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_CLK-"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_D0+"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_D0-"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_D1+"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_D1-"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_D2+"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/hdmitx1/TMDS_D2-"
|
||||
},
|
||||
{
|
||||
"netclass": "digi_hs",
|
||||
"pattern": "/tvp_board1/PCLK"
|
||||
}
|
||||
]
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
@ -521,6 +720,8 @@
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"dashed_lines_dash_length_ratio": 12.0,
|
||||
"dashed_lines_gap_length_ratio": 3.0,
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 60.0,
|
||||
"field_names": [],
|
||||
@ -552,7 +753,11 @@
|
||||
"page_layout_descr_file": "ossc_board.kicad_wks",
|
||||
"plot_directory": "doc/",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_current_sheet_as_root": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"spice_model_current_sheet_as_root": true,
|
||||
"spice_save_all_currents": false,
|
||||
"spice_save_all_voltages": false,
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
|
||||
1930
ossc_board.kicad_sch
1930
ossc_board.kicad_sch
File diff suppressed because it is too large
Load Diff
6197
tvp_board.kicad_sch
6197
tvp_board.kicad_sch
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user