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output line + (at 15.24 -129.54 180) + (length 3.81) + (name "PETn7" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "A48" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + (pin power_in line + (at 15.24 -132.08 180) + (length 3.81) + (name "GND" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "A49" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + (embedded_fonts no) + ) +) diff --git a/Library/PCIexpress.kicad_sym b/Library/PCIexpress.kicad_sym index 4f11ae3..779c2a2 100644 --- a/Library/PCIexpress.kicad_sym +++ b/Library/PCIexpress.kicad_sym @@ -1,1681 +1,26946 @@ -(kicad_symbol_lib (version 20211014) (generator kicad_symbol_editor) - (symbol "PCIexpress_bracket" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) - (property "Reference" "J" (id 0) (at 0 0 0) - (effects (font (size 1.27 1.27))) - ) - (property "Value" "PCIexpress_bracket" (id 1) (at 0 0 0) - (effects (font (size 1.27 1.27))) - ) - (property "Footprint" "" (id 2) (at 0 0 0) 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"F.Cu") + (uuid "f28777f6-8773-4981-8549-f601df33b8a7") + ) + (pad "32" connect rect + (at 1.5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "444c9c13-16b5-4ccd-9ee4-e9c9dc60ac71") + ) + (pad "33" connect rect + (at 1.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "02a93394-a9cc-49be-9f42-8076ec4c15f6") + ) + (pad "34" connect rect + (at 1 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "6bf64faf-eb45-4407-9665-fcfc2c51ce71") + ) + (pad "35" connect rect + (at 0.75 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "d1b6c7db-5061-41ea-be98-b2acdd54895f") + ) + (pad "36" connect rect + (at 0.5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "6fd7a7ff-2817-4f26-96a3-b34553a11f72") + ) + (pad "37" connect rect + (at 0.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "c0e43607-94f8-496b-acdd-5f1261bbef75") + ) + (pad "38" connect rect + (at 0 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "d038712e-1cb1-4579-a428-72b9632d1724") + ) + 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0.35 2.2) + (layers "B.Cu") + (uuid "72767cf5-5bef-4551-81b6-5e1b0a100e2e") + ) + (pad "47" connect rect + (at -2.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "87ce3df8-c567-4963-99e5-a5fb4228b918") + ) + (pad "48" connect rect + (at -2.5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "ccb9321a-a9d5-4c50-9dfe-aa8984736e30") + ) + (pad "49" connect rect + (at -2.75 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "a77f0c5c-f780-42c0-9f30-2ec609724ac3") + ) + (pad "50" connect rect + (at -3 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "4b1949eb-32cf-4864-a6df-5e147b0e825e") + ) + (pad "51" connect rect + (at -3.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "aea5f8db-3d7c-43cc-afc0-4d2b72483424") + ) + (pad "52" connect rect + (at -3.5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "9d2dd827-0497-4320-96e3-476c99a6c63b") + ) + (pad "53" connect rect + (at -3.75 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "6cc90286-dbd1-4a79-bb36-383fb71ab547") + ) + (pad "54" connect rect + (at -4 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "dca8c69b-0ebe-4726-a60f-29d5e32c3fbb") + ) + (pad "55" connect rect + (at -4.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "533f07d0-724f-4bc5-a378-3a05451b7ae4") + ) + (pad "56" connect rect + (at -4.5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "30fd98f9-0cfd-4e4c-8cce-6ece9c46c99c") + ) + (pad "57" connect rect + (at -4.75 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "6f2ada47-1cc8-4836-83c9-c4649a1c89a5") + ) + (pad "58" connect rect + (at -5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "14cbeec0-3020-42d1-be12-fb85df50f50e") + ) + (pad "59" connect rect + (at -5.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "cbe873bf-d11c-4792-b0bd-a6d507780af0") + ) + (pad "60" connect rect + (at -5.5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "f2e08787-2ab6-4fd7-8913-d3197583f780") + ) + (pad "61" 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(layers "B.Cu") + (uuid "14de7a5a-588b-41fc-80c2-92c8d927295b") + ) + (pad "69" connect rect + (at -7.75 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "99701112-b2a5-4f95-8556-198358f00cdb") + ) + (pad "70" connect rect + (at -8 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "c3ef7a3e-8238-438e-bf3e-1d012e57f5df") + ) + (pad "71" connect rect + (at -8.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "e3e7b4c2-36bc-42a0-b859-52669aef63f3") + ) + (pad "72" connect rect + (at -8.5 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "332fbe63-eaf0-4a3e-8edc-9813e23824ca") + ) + (pad "73" connect rect + (at -8.75 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "c06572c1-d764-4172-b897-7d0b4b14fdd5") + ) + (pad "74" connect rect + (at -9 -0.29 180) + (size 0.35 2.2) + (layers "B.Cu") + (uuid "424d8695-af46-4f73-b82c-12353796f215") + ) + (pad "75" connect rect + (at -9.25 -0.04 180) + (size 0.35 1.7) + (layers "F.Cu") + (uuid "7ae3fec0-d8d7-46f7-8952-778afd51c0fc") + ) + (zone + (net 0) + (net_name "") + (layer "F.Cu") + (uuid "87e697a5-1f05-4587-bd13-db6526ec55c7") + (name "Front Component Keepout") + (hatch full 0.5) + (connect_pads + (clearance 0) + ) + (min_thickness 0.25) + (filled_areas_thickness no) + (keepout + (tracks allowed) + (vias allowed) + (pads allowed) + (copperpour allowed) + (footprints not_allowed) + ) + (placement + (enabled no) + (sheetname "") + ) + (fill + (thermal_gap 0.5) + (thermal_bridge_width 0.5) + ) + (polygon + (pts + (xy 15 -2.89) (xy 15 1.11) (xy -15 1.11) (xy -15 -2.89) + ) + ) + ) + (zone + (net 0) + (net_name "") + (layer "B.Cu") + (uuid "ace17c97-ffe4-4c62-add0-b497c1831dfe") + (name "Rear Component Keepout") + (hatch full 0.5) + (connect_pads + (clearance 0) + ) + (min_thickness 0.25) + (filled_areas_thickness no) + (keepout + (tracks allowed) + (vias allowed) + (pads allowed) + (copperpour allowed) + (footprints not_allowed) + ) + (placement + (enabled no) + (sheetname "") + ) + (fill + (thermal_gap 0.5) + (thermal_bridge_width 0.5) + ) + (polygon + (pts + (xy 15 1.11) (xy 15 -4.09) (xy -15 -4.09) (xy -15 1.11) + ) + ) + ) + (embedded_fonts no) +) diff --git a/Library/PCIexpress.pretty/PCIexpress_bracket_adapter.kicad_mod b/Library/PCIexpress.pretty/PCIexpress_bracket_adapter.kicad_mod index e98c44a..ae4c9f6 100644 --- a/Library/PCIexpress.pretty/PCIexpress_bracket_adapter.kicad_mod +++ b/Library/PCIexpress.pretty/PCIexpress_bracket_adapter.kicad_mod @@ -1,37 +1,285 @@ -(module PCIexpress_bracket_adapter (layer F.Cu) (tedit 5D338897) - (descr "PCIexpress low profile to full height bracket") - (tags "PCIexpress bracket") - (attr virtual) - (fp_text reference REF** (at 0 -19.75) (layer F.SilkS) hide - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value PCIexpress_bracket_adapter (at 0 -23) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -46.18 -104.86) (end -46.18 10.09) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.48188 15.140707) (end -46.62188 15.140707) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -104.86) (end -47.04 10.09) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -47.04 -104.86) (end -46.18 -104.86) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -104.86) (end -58.47 -104.86) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -105.72) (end -58.47 -105.72) (layer Dwgs.User) (width 0.12)) - (fp_line (start -58.47 -104.86) (end -58.47 -105.72) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -13.325) (end -46.18 -13.325) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.47 -12.055) (end -34.47 -6.645) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -12.055) (end -34.47 -12.055) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -6.645) (end -35.74 -5.375) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -5.375) (end -46.18 -5.375) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 10.09) (end -47.48188 15.140707) (layer Dwgs.User) (width 0.12)) - (fp_line (start -46.18 10.09) (end -46.62188 15.140707) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -9.35) (end -36.05 -9.35) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -63.25) (end -36.05 -63.25) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.47 -65.955) (end -34.47 -60.545) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -67.225) (end -46.18 -67.225) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -59.275) (end -46.18 -59.275) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -65.955) (end -34.47 -65.955) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -60.545) (end -35.74 -59.275) (angle -90) (layer Dwgs.User) (width 0.12)) - (model ${KIPRJMOD}/../Library/PCIexpress.3dshapes/PCIexpress_bracket_adapter.step - (offset (xyz -46.18 104.86 15.86)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 90)) - ) +(footprint "PCIexpress_bracket_adapter" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "PCIexpress low profile to full height bracket") + (tags "PCIexpress bracket") + (property "Reference" "REF**" + (at 0 -19.75 0) + (layer "F.SilkS") + (hide yes) + (uuid "31458a61-3722-446e-85bf-17d19c6e8ea1") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "PCIexpress_bracket_adapter" + (at 0 -23 0) + (layer "F.Fab") + (uuid "7e233eb9-703a-42cd-9962-7043b6205852") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2e4530d2-5770-4e9b-8ec8-1afe329c0b4b") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "2c9de6dd-b38c-479f-bbd3-5e6c5d4fabef") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr exclude_from_pos_files exclude_from_bom) + (fp_line + (start -58.47 -104.86) + (end -58.47 -105.72) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "da7e1332-c019-4d1f-bf87-ee2d140f8911") + ) + (fp_line + (start -47.48188 15.140707) + (end -46.62188 15.140707) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "b0eb32a1-99b1-4f51-9767-355c9140cd36") + ) + (fp_line + (start -47.04 -105.72) + (end -58.47 -105.72) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "8f880efe-b03d-4f6b-aff4-a359f1246d64") + ) + (fp_line + (start -47.04 -104.86) + (end -58.47 -104.86) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "87f7e419-4920-4b51-bc4c-00f91eaf37c5") + ) + (fp_line + (start -47.04 -104.86) + (end -47.04 10.09) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "cbd6a3e2-575a-4cf6-938e-9128c000a11c") + ) + (fp_line + (start -47.04 10.09) + (end -47.48188 15.140707) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "cf916f4a-4699-4d88-a28c-de90e330358c") + ) + (fp_line + (start -46.18 -104.86) + (end -46.18 10.09) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "1ea8ebb1-e061-44db-913b-490a74fd91c5") + ) + (fp_line + (start -46.18 10.09) + (end -46.62188 15.140707) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "c7228e82-636a-4be7-b873-7568e34848f7") + ) + (fp_line + (start -35.74 -67.225) + (end -46.18 -67.225) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "19137eb3-be77-46ca-bb10-3339192b1d4f") + ) + (fp_line + (start -35.74 -59.275) + (end -46.18 -59.275) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "b8d18ec0-3dab-4e3c-89a6-eb53274ecd2e") + ) + (fp_line + (start -35.74 -13.325) + (end -46.18 -13.325) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "b8c8d947-a25b-4a31-a496-266fba6c5cb1") + ) + (fp_line + (start -35.74 -5.375) + (end -46.18 -5.375) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "cf92fe0e-57e8-4633-8211-7902a7999eb1") + ) + (fp_line + (start -34.47 -65.955) + (end -34.47 -60.545) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "df7f2366-036b-4c09-be2f-c16ef24079ab") + ) + (fp_line + (start -34.47 -12.055) + (end -34.47 -6.645) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "ab59a3cf-0fcd-4559-bd7a-b8f8d930f4bf") + ) + (fp_arc + (start -47.04 -105.72) + (mid -46.431888 -105.468112) + (end -46.18 -104.86) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "ec2d102c-b08d-4e88-8d1f-6ae94e273d33") + ) + (fp_arc + (start -35.74 -67.225) + (mid -34.841974 -66.853026) + (end -34.47 -65.955) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "8b7fa6cf-4be3-4d68-a4c2-c70408eca79f") + ) + (fp_arc + (start -35.74 -13.325) + (mid -34.841974 -12.953026) + (end -34.47 -12.055) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "b7033e53-24c6-46b2-a1fe-5f8471c175e1") + ) + (fp_arc + (start -34.47 -60.545) + (mid -34.841974 -59.646974) + (end -35.74 -59.275) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "9f804d22-50a5-4704-92d6-df48866b19d1") + ) + (fp_arc + (start -34.47 -6.645) + (mid -34.841974 -5.746974) + (end -35.74 -5.375) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "1c662fd7-80e4-4e9d-928c-e3dc4aa5ca17") + ) + (fp_circle + (center -37.65 -63.25) + (end -36.05 -63.25) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "Dwgs.User") + (uuid "38cc6800-a59e-415f-a806-49e5695ca876") + ) + (fp_circle + (center -37.65 -9.35) + (end -36.05 -9.35) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "Dwgs.User") + (uuid "44aee13e-a72c-4fe6-9777-e4fae1bd4367") + ) + (embedded_fonts no) + (model "C:/Users/Tony/Documents/Github/PCIexpress-KiCad/Library/PCIexpress.3dshapes/PCIexpress_bracket_adapter.step" + (offset + (xyz -46.18 104.86 15.86) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 90) + ) + ) ) diff --git a/Library/PCIexpress.pretty/PCIexpress_bracket_full.kicad_mod b/Library/PCIexpress.pretty/PCIexpress_bracket_full.kicad_mod index 195175d..84ff182 100644 --- a/Library/PCIexpress.pretty/PCIexpress_bracket_full.kicad_mod +++ b/Library/PCIexpress.pretty/PCIexpress_bracket_full.kicad_mod @@ -1,37 +1,285 @@ -(module PCIexpress_bracket_full (layer F.Cu) (tedit 5D33889E) - (descr "PCIexpress full height bracket") - (tags "PCIexpress bracket") - (attr virtual) - (fp_text reference REF** (at 0 -19.75) (layer F.SilkS) hide - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value PCIexpress_bracket_full (at 0 -23) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -46.18 -104.86) (end -46.18 10.09) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.48188 15.140707) (end -46.62188 15.140707) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -104.86) (end -47.04 10.09) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -47.04 -104.86) (end -46.18 -104.86) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -104.86) (end -58.47 -104.86) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -105.72) (end -58.47 -105.72) (layer Dwgs.User) (width 0.12)) - (fp_line (start -58.47 -104.86) (end -58.47 -105.72) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.47 -97.455) (end -34.47 -92.045) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -97.455) (end -34.47 -97.455) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -92.045) (end -35.74 -90.775) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -98.725) (end -46.18 -98.725) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -90.775) (end -46.18 -90.775) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -13.325) (end -46.18 -13.325) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.47 -12.055) (end -34.47 -6.645) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -12.055) (end -34.47 -12.055) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -35.74 -6.645) (end -35.74 -5.375) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -35.74 -5.375) (end -46.18 -5.375) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 10.09) (end -47.48188 15.140707) (layer Dwgs.User) (width 0.12)) - (fp_line (start -46.18 10.09) (end -46.62188 15.140707) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -94.75) (end -36.05 -94.75) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -9.35) (end -36.05 -9.35) (layer Dwgs.User) (width 0.12)) - (model ${KIPRJMOD}/../Library/PCIexpress.3dshapes/PCIexpress_bracket_full.step - (offset (xyz -46.18 104.86 15.86)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 90)) - ) +(footprint "PCIexpress_bracket_full" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "PCIexpress full height bracket") + (tags "PCIexpress bracket") + (property "Reference" "REF**" + (at 0 -19.75 0) + (layer "F.SilkS") + (hide yes) + (uuid "2056425e-dafd-44c3-b3a9-9251605ef4bc") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "PCIexpress_bracket_full" + (at 0 -23 0) + (layer "F.Fab") + (uuid "9111e0f5-fc7d-43bd-8827-7ab49f317b1f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "064d7f64-ab2f-4b33-9825-679bc9032b70") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "22cf2487-5503-4076-bbc8-ca45a08b4e6a") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr exclude_from_pos_files exclude_from_bom) + (fp_line + (start -58.47 -104.86) + (end -58.47 -105.72) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "57b1fd35-d4d0-47c2-b16e-3bc8de2e9d32") + ) + (fp_line + (start -47.48188 15.140707) + (end -46.62188 15.140707) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "30feeb62-c08b-424d-a35f-252d28e162ae") + ) + (fp_line + (start -47.04 -105.72) + (end -58.47 -105.72) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "019fdbe7-f28e-4d20-af70-c49616153088") + ) + (fp_line + (start -47.04 -104.86) + (end -58.47 -104.86) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "67da6aa2-e737-4fe2-a5ec-a8cceb2a6a10") + ) + (fp_line + (start -47.04 -104.86) + (end -47.04 10.09) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "3bbb2ea0-679b-468e-8ab8-3e4fea91e5e5") + ) + (fp_line + (start -47.04 10.09) + (end -47.48188 15.140707) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "ecdf934c-1921-438a-b307-cce5b73191f7") + ) + (fp_line + (start -46.18 -104.86) + (end -46.18 10.09) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "d5f10967-213f-48c5-b1de-34b08ded6d9b") + ) + (fp_line + (start -46.18 10.09) + (end -46.62188 15.140707) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "362211fe-70e8-4342-8bde-c594a7f23c81") + ) + (fp_line + (start -35.74 -98.725) + (end -46.18 -98.725) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "ad270d1e-a7bf-4efb-beb3-795c615ee731") + ) + (fp_line + (start -35.74 -90.775) + (end -46.18 -90.775) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "e4dd8040-e194-40e4-bdf8-a971d3455c6b") + ) + (fp_line + (start -35.74 -13.325) + (end -46.18 -13.325) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "35828afa-78ea-4415-85ff-00a11b265c59") + ) + (fp_line + (start -35.74 -5.375) + (end -46.18 -5.375) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "aa9211b9-1049-410b-b26c-a0cfa66daa54") + ) + (fp_line + (start -34.47 -97.455) + (end -34.47 -92.045) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "a2622f43-4d51-4537-a9d5-b43b09e0d8fa") + ) + (fp_line + (start -34.47 -12.055) + (end -34.47 -6.645) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "d9658bf4-4167-43d2-ad73-25625d564e93") + ) + (fp_arc + (start -47.04 -105.72) + (mid -46.431888 -105.468112) + (end -46.18 -104.86) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "07899c81-fe7f-432a-9db6-4997085d0eb1") + ) + (fp_arc + (start -35.74 -98.725) + (mid -34.841974 -98.353026) + (end -34.47 -97.455) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "3230441f-30de-4154-bba4-7962a1fcc9c3") + ) + (fp_arc + (start -35.74 -13.325) + (mid -34.841974 -12.953026) + (end -34.47 -12.055) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "a3278e9d-9ac9-4ddc-b151-8aa58af21dd6") + ) + (fp_arc + (start -34.47 -92.045) + (mid -34.841974 -91.146974) + (end -35.74 -90.775) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "3803a18f-7a2b-4836-aacf-16d046d22ead") + ) + (fp_arc + (start -34.47 -6.645) + (mid -34.841974 -5.746974) + (end -35.74 -5.375) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "0f8937c1-aa4c-42d2-aaa8-8fb4f6a8af02") + ) + (fp_circle + (center -37.65 -94.75) + (end -36.05 -94.75) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "Dwgs.User") + (uuid "9e0892b8-9071-4ecf-8534-181114ff5cc1") + ) + (fp_circle + (center -37.65 -9.35) + (end -36.05 -9.35) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "Dwgs.User") + (uuid "e000a995-a564-4056-89f8-b41da4068073") + ) + (embedded_fonts no) + (model "C:/Users/Tony/Documents/Github/PCIexpress-KiCad/Library/PCIexpress.3dshapes/PCIexpress_bracket_full.step" + (offset + (xyz -46.18 104.86 15.86) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 90) + ) + ) ) diff --git a/Library/PCIexpress.pretty/PCIexpress_bracket_low.kicad_mod b/Library/PCIexpress.pretty/PCIexpress_bracket_low.kicad_mod index a784eb2..2dd0ae5 100644 --- a/Library/PCIexpress.pretty/PCIexpress_bracket_low.kicad_mod +++ b/Library/PCIexpress.pretty/PCIexpress_bracket_low.kicad_mod @@ -1,38 +1,296 @@ -(module PCIexpress_bracket_low (layer F.Cu) (tedit 5D3388A6) - (descr "PCIexpress low profile bracket") - (tags "PCIexpress bracket") - (attr virtual) - (fp_text reference REF** (at 0 -19.75) (layer F.SilkS) hide - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value PCIexpress_bracket_low (at 0 -23) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_circle (center -37.65 -9.35) (end -36.05 -9.35) (layer Dwgs.User) (width 0.12)) - (fp_line (start -46.18 -68.11) (end -46.18 6.059293) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.48188 11.11) (end -46.62188 11.11) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -68.09) (end -47.04 6.059293) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -47.04 -68.11) (end -46.18 -68.11) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -68.09) (end -58.88 -68.09) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 -68.97) (end -58.88 -68.97) (layer Dwgs.User) (width 0.12)) - (fp_line (start -58.88 -68.11) (end -58.88 -68.97) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.01 -13.325) (end -46.18 -13.325) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.74 -12.055) (end -32.74 -6.645) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -34.01 -12.055) (end -32.74 -12.055) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -34.01 -6.645) (end -34.01 -5.375) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.01 -5.375) (end -46.18 -5.375) (layer Dwgs.User) (width 0.12)) - (fp_line (start -47.04 6.059293) (end -47.48188 11.11) (layer Dwgs.User) (width 0.12)) - (fp_line (start -46.18 6.059293) (end -46.62188 11.11) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -9.35) (end -36.05 -9.35) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -63.25) (end -36.05 -63.25) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.01 -59.275) (end -46.18 -59.275) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -34.01 -60.545) (end -34.01 -59.275) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -34.01 -65.955) (end -32.74 -65.955) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.74 -65.955) (end -32.74 -60.545) (layer Dwgs.User) (width 0.12)) - (fp_line (start -34.01 -67.225) (end -46.18 -67.225) (layer Dwgs.User) (width 0.12)) - (model ${KIPRJMOD}/../Library/PCIexpress.3dshapes/PCIexpress_bracket_low.step - (offset (xyz -46.18 68.09999999999999 15.86)) - (scale (xyz 1 1 1)) - (rotate (xyz 0 0 90)) - ) +(footprint "PCIexpress_bracket_low" + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (layer "F.Cu") + (descr "PCIexpress low profile bracket") + (tags "PCIexpress bracket") + (property "Reference" "REF**" + (at 0 -19.75 0) + (layer "F.SilkS") + (hide yes) + (uuid "48edd9c0-d9e5-494d-83c5-2c0a3f81cdbe") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "PCIexpress_bracket_low" + (at 0 -23 0) + (layer "F.Fab") + (uuid "ebdb2bf3-f0e0-4009-a59d-cff1774788cd") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "728e27a8-30c8-4e61-ba91-d85394eba23f") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (layer "F.Fab") + (hide yes) + (uuid "655b3b5b-4abb-4a0c-887e-3ec83b1412cf") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr exclude_from_pos_files exclude_from_bom) + (fp_line + (start -58.88 -68.11) + (end -58.88 -68.97) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "de2fa78a-03f4-4dc6-8b78-46080e0f3c3b") + ) + (fp_line + (start -47.48188 11.11) + (end -46.62188 11.11) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "e156fb6f-73e1-4ca9-9a5e-c5ef7c75b229") + ) + (fp_line + (start -47.04 -68.97) + (end -58.88 -68.97) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "758ccd0b-3f77-41e9-b6c7-3dd411652d4a") + ) + (fp_line + (start -47.04 -68.09) + (end -58.88 -68.09) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "9563c82a-9199-401b-96c9-18cbab1517bf") + ) + (fp_line + (start -47.04 -68.09) + (end -47.04 6.059293) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "b5732888-8455-4b8c-bebc-4d8544a6019b") + ) + (fp_line + (start -47.04 6.059293) + (end -47.48188 11.11) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "7274b9bc-9219-4b68-81c5-2cc342587a79") + ) + (fp_line + (start -46.18 -68.11) + (end -46.18 6.059293) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "e4d89fd5-776a-4497-bbeb-622b727e500f") + ) + (fp_line + (start -46.18 6.059293) + (end -46.62188 11.11) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "90e124d5-4491-4e26-866f-903a87368124") + ) + (fp_line + (start -34.01 -67.225) + (end -46.18 -67.225) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "cfc76a8a-f3ec-4544-a02e-97b9f4958122") + ) + (fp_line + (start -34.01 -59.275) + (end -46.18 -59.275) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "cad6bd33-c53c-4a9e-9f51-887849f2e069") + ) + (fp_line + (start -34.01 -13.325) + (end -46.18 -13.325) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "4186c9a3-99cd-460a-b982-81f6e9562e26") + ) + (fp_line + (start -34.01 -5.375) + (end -46.18 -5.375) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "9bc0bf88-b68d-4ca3-8403-60d1235bff89") + ) + (fp_line + (start -32.74 -65.955) + (end -32.74 -60.545) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "7fa61338-8cce-4554-b6ce-3704aad099af") + ) + (fp_line + (start -32.74 -12.055) + (end -32.74 -6.645) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "953eae69-cba2-4f21-82d3-b4f7b21ab379") + ) + (fp_arc + (start -47.04 -68.97) + (mid -46.431888 -68.718112) + (end -46.18 -68.11) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "d76b7827-da3b-4c08-9a2d-d2d5d3fe6c01") + ) + (fp_arc + (start -34.01 -67.225) + (mid -33.111974 -66.853026) + (end -32.74 -65.955) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "24456d2f-bf66-479e-9b2f-ba803c6110fb") + ) + (fp_arc + (start -34.01 -13.325) + (mid -33.111974 -12.953026) + (end -32.74 -12.055) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "b390c2b4-321d-4a32-8885-2373be8a8059") + ) + (fp_arc + (start -32.74 -60.545) + (mid -33.111974 -59.646974) + (end -34.01 -59.275) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "389c3bb0-dc57-4817-a5da-a04fbcf2cf03") + ) + (fp_arc + (start -32.74 -6.645) + (mid -33.111974 -5.746974) + (end -34.01 -5.375) + (stroke + (width 0.12) + (type solid) + ) + (layer "Dwgs.User") + (uuid "2ed5501d-16b5-4a33-991b-f598f07f99c9") + ) + (fp_circle + (center -37.65 -63.25) + (end -36.05 -63.25) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "Dwgs.User") + (uuid "5fadfe68-524c-462e-9c1c-9a5d566b2549") + ) + (fp_circle + (center -37.65 -9.35) + (end -36.05 -9.35) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "Dwgs.User") + (uuid "2b5301c7-b065-4519-ba61-83dd000eb83e") + ) + (fp_circle + (center -37.65 -9.35) + (end -36.05 -9.35) + (stroke + (width 0.12) + (type solid) + ) + (fill no) + (layer "Dwgs.User") + (uuid "66b0226c-860c-4487-b1d6-a8314ea2ccd0") + ) + (embedded_fonts no) + (model "C:/Users/Tony/Documents/Github/PCIexpress-KiCad/Library/PCIexpress.3dshapes/PCIexpress_bracket_low.step" + (offset + (xyz -46.18 68.1 15.86) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 90) + ) + ) ) diff --git a/Library/PCIexpress.pretty/PCIexpress_x1.kicad_mod b/Library/PCIexpress.pretty/PCIexpress_x1.kicad_mod index a5c7307..6cd4019 100644 --- a/Library/PCIexpress.pretty/PCIexpress_x1.kicad_mod +++ b/Library/PCIexpress.pretty/PCIexpress_x1.kicad_mod @@ -1,156 +1,1112 @@ -(module PCIexpress_x1 (layer F.Cu) (tedit 5D338A37) - (descr "PCIexpress x1 footprint") - (tags PCIexpress) - (attr virtual) - (fp_text reference REF** (at 0 -19.75) (layer F.SilkS) hide - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value BUS_PCIexpress_x1 (at 0 -23) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_circle (center 261.77 -106.13) (end 263.37 -106.13) (layer Dwgs.User) (width 0.12)) - (fp_circle (center 261.77 -16.6) (end 263.37 -16.6) (layer Dwgs.User) (width 0.12)) - (fp_line (start 261.77 -99.7) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -99.7) (end 261.77 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -22.9) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -13.75) (end 256.65 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -13.75) (end 256.65 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -108.15) (end 256.65 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -108.15) (end 256.65 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 108 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 107 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -10) (end 107.5 -15) (layer Cmts.User) (width 0.12)) - (fp_text user "Keep out components and traces component side" (at 107.75 -9 180) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 110.3 -16.1) (end 110.3 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 105.05 -16.1) (end 110.3 -16.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 105.05 -14.1) (end 105.05 -16.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 96.9 -14.1) (end 105.05 -14.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 96.9 -14.1) (end 96.9 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_text user "Max component height: solder side 2,67mm component side 14,49mm" (at 40 -44.25) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Keep out components and traces solder side" (at -42.25 -77.5 180) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -40.07 -13.75) (end -40.07 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at 120 -87.75 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 117.42 -108.15) (end 117.42 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -110.15) (end -32.45 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -89.7) (end -32.45 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -67.9) (end 121.5 -67.9) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at 121.893243 -40.134926 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user "Keep out components and traces solder side" (at -44.75 -36 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -44.15 -58.5) (end -44.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 121.5 -67.9) (end 121.5 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 92 -108.15) (end 117.42 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 92 -110.15) (end 92 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 20.15 -13.75) (end 121.5 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -110.15) (end 92 -110.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -58.5) (end -32.45 -67.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -58.5) (end -32.45 -58.5) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at -21.75 -12) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 20.15 -12.75) (end 20.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -13.75) (end -45.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -10.925) (end -0.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_text user "Full length max" (at 269 -74 90) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_line (start 266.85 -111.15) (end 266.8527 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -111.15) (end 266.85 -111.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5027 -12.75) (end 266.8527 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -94.75) (end -36.05 -94.75) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -63.25) (end -36.05 -63.25) (layer Dwgs.User) (width 0.12)) - (fp_poly (pts (xy -11.8 -4.5) (xy -11.8 -8) (xy -3.8 -8) (xy -3.8 -4.5)) (layer B.Mask) (width 0)) - (fp_poly (pts (xy -11.8 -4.5) (xy -11.8 -8) (xy -3.8 -8) (xy -3.8 -4.5)) (layer F.Mask) (width 0)) - (fp_text user "Keep Out Cu" (at -7.75 -3.5) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -11.8 -8) (end -3.8 -8) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -9.35) (end -36.05 -9.35) (layer Dwgs.User) (width 0.12)) - (fp_text user "Half length max" (at 124.5 -72.25 90) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Full height max" (at 36.75 -108.25) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Low profile max height" (at 39.25 -71) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_line (start -45.15 -68.9) (end 122.5 -68.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -111.15) (end -45.15 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -111.15) (end 122.5 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -111.15) (end 122.5 -111.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 20.15 -12.75) (end 122.5027 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -4.5) (end -45.15 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -4.5) (end -30.15 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -12.75) (end -11.8 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -11.8 -4.5) (end -11.8 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -3.8 -4.5) (end -3.8 -10.925) (layer Dwgs.User) (width 0.12)) - (fp_line (start -11.8 -4.5) (end -3.8 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -1.975 -10.925) (end -0.15 -10.925) (angle -180) (layer Dwgs.User) (width 0.12)) - (fp_poly (pts (xy -0.25 -5.5) (xy 20.25 -5.5) (xy 20.25 0) (xy -0.25 0)) (layer B.Mask) (width 0.2)) - (fp_poly (pts (xy -0.25 -5.5) (xy 20.25 -5.5) (xy 20.25 0) (xy -0.25 0)) (layer F.Mask) (width 0.2)) - (fp_line (start 20.15 -0.5) (end 19.65 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -0.5) (end 0.35 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 20.15 -0.5) (end 20.15 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -0.5) (end -0.15 -10.925) (layer Dwgs.User) (width 0.12)) - (fp_line (start 13.45 0) (end 19.65 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 12.95 -0.5) (end 13.45 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 11.05 -0.5) (end 10.55 0) (layer Dwgs.User) (width 0.12)) - (fp_arc (start 12 -7.45) (end 11.05 -7.45) (angle 180) (layer Dwgs.User) (width 0.12)) - (fp_line (start 12.95 -7.45) (end 12.95 -0.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 11.05 -7.45) (end 11.05 -0.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 0.35 0) (end 10.55 0) (layer Dwgs.User) (width 0.12)) - (fp_text user %R (at 0 -17.5) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user "Keep out components and traces both sides" (at 264.25 -65.25 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad A13 connect rect (at 14.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A12 connect rect (at 13.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A18 connect rect (at 19.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A17 connect rect (at 18.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A16 connect rect (at 17.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A15 connect rect (at 16.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A14 connect rect (at 15.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A11 connect rect (at 10.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A10 connect rect (at 9.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A9 connect rect (at 8.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A8 connect rect (at 7.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A7 connect rect (at 6.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A6 connect rect (at 5.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A5 connect rect (at 4.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A4 connect rect (at 3.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A3 connect rect (at 2.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A2 connect rect (at 1.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A1 connect rect (at 0.5 -4) (size 0.7 3.2) (layers B.Cu)) - (pad B13 connect rect (at 14.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B12 connect rect (at 13.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B18 connect rect (at 19.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B17 connect rect (at 18.5 -4) (size 0.7 3.2) (layers F.Cu)) - (pad B16 connect rect (at 17.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B15 connect rect (at 16.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B14 connect rect (at 15.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B11 connect rect (at 10.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B10 connect rect (at 9.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B9 connect rect (at 8.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B8 connect rect (at 7.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B7 connect rect (at 6.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B6 connect rect (at 5.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B5 connect rect (at 4.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B4 connect rect (at 3.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B3 connect rect (at 2.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B2 connect rect (at 1.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B1 connect rect (at 0.5 -3.5) (size 0.7 4.2) (layers F.Cu)) +(footprint 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4.2) + (layers "B.Cu") + (uuid "3c533737-a990-4c95-b075-8725a9121f4a") + ) + (pad "A4" connect rect + (at 3.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "b6fcb8be-972c-4028-adba-7b6b4428a8a5") + ) + (pad "A5" connect rect + (at 4.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "369bda9d-286d-441b-b640-e4e429036278") + ) + (pad "A6" connect rect + (at 5.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "d29925ba-5929-4c70-94e1-cbbe6d45e7d9") + ) + (pad "A7" connect rect + (at 6.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "11839aa1-9b29-46b3-a2c5-3116ad2b97f8") + ) + (pad "A8" connect rect + (at 7.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "a1417a63-1b0d-41fc-bdd5-1be33f2f50a2") + ) + (pad "A9" connect rect + (at 8.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "ececbcdb-21fa-403c-8751-253773e4ea0f") + ) + (pad "A10" connect rect + (at 9.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "2bfc2fb8-7e63-4b61-b39f-84a6bcf5fe2b") + ) + (pad "A11" connect rect + (at 10.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "7816f038-713b-466e-a8d3-648f0e3b04d1") + ) + (pad "A12" connect rect + (at 13.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "04335a8e-af94-4c34-b215-50cbb6640639") + ) + (pad "A13" connect rect + (at 14.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "b6b30c38-41f0-4d9e-a5a6-8ae9841bfdfa") + ) + (pad "A14" connect rect + (at 15.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "16b88451-7b47-4f9f-8886-89c24730d460") + ) + (pad "A15" connect rect + (at 16.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "486d1e7d-382e-4303-b5ea-f0cbf448080d") + ) + (pad "A16" connect rect + (at 17.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "b1d2dec6-61cf-45f8-9c8a-02670a6606fc") + ) + (pad "A17" connect rect + (at 18.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "5f102948-167b-4467-b98c-7b7974c04d13") + ) + (pad "A18" connect rect + (at 19.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "82c2de97-c774-4438-888f-6e8a027f105f") + ) + (pad "B1" connect rect + (at 0.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "da1c78cc-4ee0-444c-883e-e992e12e2258") + ) + (pad "B2" connect rect + (at 1.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "5ca3805e-c14f-440d-87fd-59f0cf5be12a") + ) + (pad "B3" connect rect + (at 2.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "c053d74f-224b-4d01-b1dc-f8cc9f14c6e6") + ) + (pad "B4" connect rect + (at 3.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "72f6f222-e6f6-484f-899c-10feebd8cf06") + ) + (pad "B5" connect rect + (at 4.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "ad21847c-d49d-4985-8e8e-866e53067a10") + ) + (pad "B6" connect rect + (at 5.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "4b268490-6a80-4ad7-a97a-7eb79439264c") + ) + (pad "B7" connect rect + (at 6.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "6f05b943-26ce-4346-b1e7-7ccda2f8422c") + ) + (pad "B8" connect rect + (at 7.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "236b80ad-e393-4232-a3f8-5b6ed147c11b") + ) + (pad "B9" connect rect + (at 8.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "e3998ae2-95f1-4284-bf2d-888821002ec9") + ) + (pad "B10" connect rect + (at 9.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "4f19c9aa-d403-4f7e-9195-1275dd52db01") + ) + (pad "B11" connect rect + (at 10.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "e813cdc9-f0d3-4907-94ed-2715df45e901") + ) + (pad "B12" connect rect + (at 13.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "ff32cd45-c88a-4084-8bfd-c7b7df3aace9") + ) + (pad "B13" connect rect + (at 14.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "c1ce4934-c612-43ec-a8be-089deebd1025") + ) + (pad "B14" connect rect + (at 15.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "e936117c-df44-48e1-b31c-903f154440be") + ) + (pad "B15" connect rect + (at 16.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "30f77f19-96c1-4941-a343-d854f1e6fe11") + ) + (pad "B16" connect rect + (at 17.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "837d499a-7de6-4798-ae67-920ba5cb94ce") + ) + (pad "B17" connect rect + (at 18.5 -4) + (size 0.7 3.2) + (layers "F.Cu") + (uuid "84781cc7-9e11-46c7-a9bd-8bc5c638ab24") + ) + (pad "B18" connect rect + (at 19.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "f0283e48-55cb-43a1-abc4-fd5fb44f5ef6") + ) + (embedded_fonts no) ) diff --git a/Library/PCIexpress.pretty/PCIexpress_x16.kicad_mod b/Library/PCIexpress.pretty/PCIexpress_x16.kicad_mod index 3bbd936..f95e648 100644 --- a/Library/PCIexpress.pretty/PCIexpress_x16.kicad_mod +++ b/Library/PCIexpress.pretty/PCIexpress_x16.kicad_mod @@ -1,302 +1,2028 @@ -(module PCIexpress_x16 (layer F.Cu) (tedit 5D338A18) - (descr "PCIexpress x16 footprint") - (tags PCIexpress) - (attr virtual) - (fp_text reference REF** (at 0 -19.75) (layer F.SilkS) hide - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value BUS_PCIexpress_x16 (at 0 -23) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_circle (center 261.77 -106.13) (end 263.37 -106.13) (layer Dwgs.User) (width 0.12)) - (fp_circle (center 261.77 -16.6) (end 263.37 -16.6) (layer Dwgs.User) (width 0.12)) - (fp_line (start 261.77 -99.7) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -99.7) (end 261.77 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -22.9) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -13.75) (end 256.65 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -13.75) (end 256.65 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -108.15) (end 256.65 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -108.15) (end 256.65 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 108 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 107 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -10) (end 107.5 -15) (layer Cmts.User) (width 0.12)) - (fp_text user "Keep out components and traces component side" (at 126 -9 180) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 110.3 -16.1) (end 110.3 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 105.05 -16.1) (end 110.3 -16.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 105.05 -14.1) (end 105.05 -16.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 96.9 -14.1) (end 105.05 -14.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 96.9 -14.1) (end 96.9 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_text user "Max component height: solder side 2,67mm component side 14,49mm" (at 40 -44.25) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Keep out components and traces solder side" (at -42.25 -77.5 180) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -40.07 -13.75) (end -40.07 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at 120 -87.75 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 117.42 -108.15) (end 117.42 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -110.15) (end -32.45 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -89.7) (end -32.45 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -67.9) (end 121.5 -67.9) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at 121.893243 -40.134926 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user "Keep out components and traces solder side" (at -44.75 -36 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -44.15 -58.5) (end -44.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 121.5 -67.9) (end 121.5 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 92 -108.15) (end 117.42 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 92 -110.15) (end 92 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 84.15 -13.75) (end 121.5 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -110.15) (end 92 -110.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -58.5) (end -32.45 -67.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -58.5) (end -32.45 -58.5) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at -21.75 -12) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 84.15 -12.75) (end 84.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -13.75) (end -45.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -10.925) (end -0.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_text user "Full length max" (at 269 -74 90) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_line (start 266.85 -111.15) (end 266.8527 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -111.15) (end 266.85 -111.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5027 -12.75) (end 266.8527 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -94.75) (end -36.05 -94.75) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -63.25) (end -36.05 -63.25) (layer Dwgs.User) (width 0.12)) - (fp_poly (pts (xy -11.8 -4.5) (xy -11.8 -8) (xy -3.8 -8) (xy -3.8 -4.5)) (layer B.Mask) (width 0)) - (fp_poly (pts (xy -11.8 -4.5) (xy -11.8 -8) (xy -3.8 -8) (xy -3.8 -4.5)) (layer F.Mask) (width 0)) - (fp_text user "Keep Out Cu" (at -7.75 -3.5) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -11.8 -8) (end -3.8 -8) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -9.35) (end -36.05 -9.35) (layer Dwgs.User) (width 0.12)) - (fp_text user "Half length max" (at 124.5 -72.25 90) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Full height max" (at 36.75 -108.25) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Low profile max height" (at 39.25 -71) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_line (start -45.15 -68.9) (end 122.5 -68.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -111.15) (end -45.15 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -111.15) (end 122.5 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -111.15) (end 122.5 -111.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 84.15 -12.75) (end 122.5027 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -4.5) (end -45.15 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -4.5) (end -30.15 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -12.75) (end -11.8 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -11.8 -4.5) (end -11.8 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -3.8 -4.5) (end -3.8 -10.925) (layer Dwgs.User) (width 0.12)) - (fp_line (start -11.8 -4.5) (end -3.8 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -1.975 -10.925) (end -0.15 -10.925) (angle -180) (layer Dwgs.User) (width 0.12)) - (fp_poly (pts (xy -0.25 -5.5) (xy 84.25 -5.5) (xy 84.25 0) (xy -0.25 0)) (layer B.Mask) (width 0.2)) - (fp_poly (pts (xy -0.25 -5.5) (xy 84.25 -5.5) (xy 84.25 0) (xy -0.25 0)) (layer F.Mask) (width 0.2)) - (fp_line (start 84.15 -0.5) (end 83.65 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -0.5) (end 0.35 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 84.15 -0.5) (end 84.15 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -0.5) (end -0.15 -10.925) (layer Dwgs.User) (width 0.12)) - (fp_line (start 13.45 0) (end 83.65 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 12.95 -0.5) (end 13.45 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 11.05 -0.5) (end 10.55 0) (layer Dwgs.User) (width 0.12)) - (fp_arc (start 12 -7.45) (end 11.05 -7.45) (angle 180) (layer Dwgs.User) (width 0.12)) - (fp_line (start 12.95 -7.45) (end 12.95 -0.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 11.05 -7.45) (end 11.05 -0.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 0.35 0) (end 10.55 0) (layer Dwgs.User) (width 0.12)) - (fp_text user %R (at 0 -17.5) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user "Keep out components and traces both sides" (at 264.25 -65.25 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 87.4 -2.95) (end 98.2 -2.95) (layer Dwgs.User) (width 0.12)) - (fp_line (start 86.9 -3.45) (end 86.9 -7.95) (layer Dwgs.User) (width 0.12)) - (fp_arc (start 85.525 -7.95) (end 86.9 -7.95) (angle -180) (layer Dwgs.User) (width 0.12)) - (fp_line (start 86.9 -3.45) (end 87.4 -2.95) (layer Dwgs.User) (width 0.12)) - (fp_line (start 99.6 -5.5) (end 99.6 -7.95) (layer Dwgs.User) (width 0.12)) - (fp_line (start 95.9 -7.95) (end 86.9 -7.95) (layer Dwgs.User) (width 0.12)) - (fp_arc (start 95.9 -9.7) (end 94.15 -9.7) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start 95.9 -7.95) (end 99.6 -7.95) (layer Dwgs.User) (width 0.12)) - (fp_arc (start 95.9 -11) (end 95.9 -12.75) (angle -90) (layer Dwgs.User) (width 0.12)) - (fp_line (start 94.15 -11) (end 94.15 -9.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 98.2 -2.95) (end 99.6 -5.5) (layer Dwgs.User) (width 0.12)) - (fp_poly (pts (xy 86.9 -7.95) (xy 99.6 -7.95) (xy 99.6 -5.5) (xy 98.2 -2.95) - (xy 87.4 -2.95) (xy 86.9 -3.45)) (layer F.Mask) (width 0)) - (fp_poly (pts (xy 86.9 -7.95) (xy 99.6 -7.95) (xy 99.6 -5.5) (xy 98.2 -2.95) - (xy 87.4 -2.95) (xy 86.9 -3.45)) (layer B.Mask) (width 0)) - (fp_text user "Keep Out Cu" (at 93 -1.75) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad A13 connect rect (at 14.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A12 connect rect (at 13.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A18 connect rect (at 19.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A17 connect rect (at 18.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A16 connect rect (at 17.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A15 connect rect (at 16.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A14 connect rect (at 15.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A11 connect rect (at 10.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A10 connect rect (at 9.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A9 connect rect (at 8.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A8 connect rect (at 7.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A7 connect rect (at 6.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A6 connect rect (at 5.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A5 connect rect (at 4.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A4 connect rect (at 3.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A3 connect rect (at 2.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A2 connect rect (at 1.5 -3.5) (size 0.7 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0.7 4.2) + (layers "F.Cu") + (uuid "497aad7a-489d-4303-87e5-62487840fa72") + ) + (pad "B3" connect rect + (at 2.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "7cdb9715-ccf0-41f4-9f8d-cb43414e1b4e") + ) + (pad "B4" connect rect + (at 3.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "836e7a0f-66ad-4f31-befa-36dbf4928123") + ) + (pad "B5" connect rect + (at 4.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "81054821-e98a-4483-8d32-d7110ce1121d") + ) + (pad "B6" connect rect + (at 5.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "03047a15-9e1a-49da-8484-0fd4df4937f0") + ) + (pad "B7" connect rect + (at 6.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "9d16951b-bbf8-4bc1-885a-97a14250f8d0") + ) + (pad "B8" connect rect + (at 7.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "b2465146-1892-4783-b1fc-ef52e1a0f7e4") + ) + (pad "B9" connect rect + (at 8.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "76f0ad96-f619-4d64-8294-05d339948188") + ) + (pad "B10" connect rect + (at 9.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "3c256d06-91fe-43c5-aa2d-f5f4c7fda8f2") + ) + (pad "B11" connect rect + (at 10.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "1abd81aa-e981-458f-8937-15c8108f1a72") + ) + (pad "B12" connect rect + (at 13.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "3da93693-08da-4143-8b6b-7bb1256046d3") + ) + (pad "B13" connect rect + (at 14.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "9f65e947-ffe7-4b41-9f06-e8115497363b") + ) + (pad "B14" connect rect + (at 15.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "01b8ae1f-cfa6-4e71-b21a-d8767f896722") + ) + (pad "B15" connect rect + (at 16.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "0ad00b73-c8f5-41cb-ba3e-16120858a046") + ) + (pad "B16" connect rect + (at 17.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "86790576-5c4b-4e36-9338-6869e41392f2") + ) + (pad "B17" connect rect + (at 18.5 -4) + (size 0.7 3.2) + (layers "F.Cu") + (uuid "4fefb8fb-dc5f-49ce-9d26-a161fe31fdc1") + ) + (pad "B18" connect rect + (at 19.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "700a6991-7b54-4038-ba76-fa4be4bf7656") + ) + (pad "B19" connect rect + (at 20.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "846e1a2c-1d8d-402b-9c63-f21f9cb505c7") + ) + (pad "B20" connect rect + (at 21.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "d34163ec-64d0-40a3-ad1c-0a85596cf7c3") + ) + (pad "B21" connect rect + (at 22.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "cc17b8e8-b63c-4177-9608-b909eff9ee1b") + ) + (pad "B22" connect rect + (at 23.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "40223316-600b-4b6b-8ce8-76e0e0238f31") + ) + (embedded_fonts no) +) diff --git a/Library/PCIexpress.pretty/PCIexpress_x4.kicad_mod b/Library/PCIexpress.pretty/PCIexpress_x4.kicad_mod index 80aa690..b40cc9f 100644 --- a/Library/PCIexpress.pretty/PCIexpress_x4.kicad_mod +++ b/Library/PCIexpress.pretty/PCIexpress_x4.kicad_mod @@ -1,184 +1,1280 @@ -(module PCIexpress_x4 (layer F.Cu) (tedit 5D338A2E) - (descr "PCIexpress x4 footprint") - (tags PCIexpress) - (attr virtual) - (fp_text reference REF** (at 0 -19.75) (layer F.SilkS) hide - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value BUS_PCIexpress_x4 (at 0 -23) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_circle (center 261.77 -106.13) (end 263.37 -106.13) (layer Dwgs.User) (width 0.12)) - (fp_circle (center 261.77 -16.6) (end 263.37 -16.6) (layer Dwgs.User) (width 0.12)) - (fp_line (start 261.77 -99.7) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -99.7) (end 261.77 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -22.9) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -13.75) (end 256.65 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -13.75) (end 256.65 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -108.15) (end 256.65 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -108.15) (end 256.65 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 108 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 107 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -10) (end 107.5 -15) (layer Cmts.User) (width 0.12)) - (fp_text user "Keep out components and traces component side" (at 107.75 -9 180) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 110.3 -16.1) (end 110.3 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 105.05 -16.1) (end 110.3 -16.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 105.05 -14.1) (end 105.05 -16.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 96.9 -14.1) (end 105.05 -14.1) (layer Dwgs.User) (width 0.12)) - (fp_line (start 96.9 -14.1) (end 96.9 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_text user "Max component height: solder side 2,67mm component side 14,49mm" (at 40 -44.25) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Keep out components and traces solder side" (at -42.25 -77.5 180) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -40.07 -13.75) (end -40.07 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at 120 -87.75 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 117.42 -108.15) (end 117.42 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -110.15) (end -32.45 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -89.7) (end -32.45 -89.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -67.9) (end 121.5 -67.9) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at 121.893243 -40.134926 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user "Keep out components and traces solder side" (at -44.75 -36 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -44.15 -58.5) (end -44.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 121.5 -67.9) (end 121.5 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 92 -108.15) (end 117.42 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 92 -110.15) (end 92 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 34.15 -13.75) (end 121.5 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -110.15) (end 92 -110.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start -32.45 -58.5) (end -32.45 -67.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -58.5) (end -32.45 -58.5) (layer Dwgs.User) (width 0.12)) - (fp_text user "Keep out components and traces both sides" (at -21.75 -12) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start 34.15 -12.75) (end 34.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -13.75) (end -45.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -10.925) (end -0.15 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_text user "Full length max" (at 269 -74 90) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_line (start 266.85 -111.15) (end 266.8527 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -111.15) (end 266.85 -111.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5027 -12.75) (end 266.8527 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -94.75) (end -36.05 -94.75) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -63.25) (end -36.05 -63.25) (layer Dwgs.User) (width 0.12)) - (fp_poly (pts (xy -11.8 -4.5) (xy -11.8 -8) (xy -3.8 -8) (xy -3.8 -4.5)) (layer B.Mask) (width 0)) - (fp_poly (pts (xy -11.8 -4.5) (xy -11.8 -8) (xy -3.8 -8) (xy -3.8 -4.5)) (layer F.Mask) (width 0)) - (fp_text user "Keep Out Cu" (at -7.75 -3.5) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_line (start -11.8 -8) (end -3.8 -8) (layer Dwgs.User) (width 0.12)) - (fp_circle (center -37.65 -9.35) (end -36.05 -9.35) (layer Dwgs.User) (width 0.12)) - (fp_text user "Half length max" (at 124.5 -72.25 90) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Full height max" (at 36.75 -108.25) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_text user "Low profile max height" (at 39.25 -71) (layer Cmts.User) - (effects (font (size 2 2) (thickness 0.25))) - ) - (fp_line (start -45.15 -68.9) (end 122.5 -68.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -111.15) (end -45.15 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -111.15) (end 122.5 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -45.15 -111.15) (end 122.5 -111.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 34.15 -12.75) (end 122.5027 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -4.5) (end -45.15 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -4.5) (end -30.15 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -30.15 -12.75) (end -11.8 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -11.8 -4.5) (end -11.8 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -3.8 -4.5) (end -3.8 -10.925) (layer Dwgs.User) (width 0.12)) - (fp_line (start -11.8 -4.5) (end -3.8 -4.5) (layer Dwgs.User) (width 0.12)) - (fp_arc (start -1.975 -10.925) (end -0.15 -10.925) (angle -180) (layer Dwgs.User) (width 0.12)) - (fp_poly (pts (xy -0.25 -5.5) (xy 34.25 -5.5) (xy 34.25 0) (xy -0.25 0)) (layer B.Mask) (width 0.2)) - (fp_poly (pts (xy -0.25 -5.5) (xy 34.25 -5.5) (xy 34.25 0) (xy -0.25 0)) (layer F.Mask) (width 0.2)) - (fp_line (start 34.15 -0.5) (end 33.65 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -0.5) (end 0.35 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 34.15 -0.5) (end 34.15 -12.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start -0.15 -0.5) (end -0.15 -10.925) (layer Dwgs.User) (width 0.12)) - (fp_line (start 13.45 0) (end 33.65 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 12.95 -0.5) (end 13.45 0) (layer Dwgs.User) (width 0.12)) - (fp_line (start 11.05 -0.5) (end 10.55 0) (layer Dwgs.User) (width 0.12)) - (fp_arc (start 12 -7.45) (end 11.05 -7.45) (angle 180) (layer Dwgs.User) (width 0.12)) - (fp_line (start 12.95 -7.45) (end 12.95 -0.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 11.05 -7.45) (end 11.05 -0.5) (layer Dwgs.User) (width 0.12)) - (fp_line (start 0.35 0) (end 10.55 0) (layer Dwgs.User) (width 0.12)) - (fp_text user %R (at 0 -17.5) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text user "Keep out components and traces both sides" (at 264.25 -65.25 90) (layer Cmts.User) - (effects (font (size 1 1) (thickness 0.15))) - ) - (pad A13 connect rect (at 14.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A12 connect rect (at 13.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A18 connect rect (at 19.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A17 connect rect (at 18.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A16 connect rect (at 17.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A15 connect rect (at 16.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A14 connect rect (at 15.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A11 connect rect (at 10.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A10 connect rect (at 9.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A9 connect rect (at 8.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A8 connect rect (at 7.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A7 connect rect (at 6.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A6 connect rect (at 5.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A5 connect rect (at 4.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A4 connect rect (at 3.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A3 connect rect (at 2.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A2 connect rect (at 1.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A1 connect rect (at 0.5 -4) (size 0.7 3.2) (layers B.Cu)) - (pad B13 connect rect (at 14.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B12 connect rect (at 13.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B18 connect rect (at 19.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B17 connect rect (at 18.5 -4) (size 0.7 3.2) (layers F.Cu)) - (pad B16 connect rect (at 17.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B15 connect rect (at 16.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B14 connect rect (at 15.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B11 connect rect (at 10.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B10 connect rect (at 9.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B9 connect rect (at 8.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B8 connect rect (at 7.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B7 connect rect (at 6.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B6 connect rect (at 5.5 -3.5) (size 0.7 4.2) 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28.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B28 connect rect (at 29.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B29 connect rect (at 30.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B30 connect rect (at 31.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad B31 connect rect (at 32.5 -4) (size 0.7 3.2) (layers F.Cu)) - (pad B32 connect rect (at 33.5 -3.5) (size 0.7 4.2) (layers F.Cu)) - (pad A20 connect rect (at 21.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A21 connect rect (at 22.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A22 connect rect (at 23.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A23 connect rect (at 24.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A24 connect rect (at 25.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A25 connect rect (at 26.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A26 connect rect (at 27.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A27 connect rect (at 28.5 -3.5) (size 0.7 4.2) (layers B.Cu)) - (pad A28 connect rect (at 29.5 -3.5) (size 0.7 4.2) (layers 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"27506987-2256-4cc9-9e4c-f82aa036fd9f") + (effects + (font + (size 2 2) + (thickness 0.25) + ) + ) + ) + (fp_text user "Half length max" + (at 124.5 -72.25 90) + (layer "Cmts.User") + (uuid "323c109b-bbe4-4c33-aa22-a347610dfb6d") + (effects + (font + (size 2 2) + (thickness 0.25) + ) + ) + ) + (fp_text user "Keep out components and traces both sides" + (at 120 -87.75 90) + (layer "Cmts.User") + (uuid "5492c2cc-09ff-429d-aeca-bba43f74d883") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (fp_text user "Keep out components and traces component side" + (at 107.75 -9 180) + (layer "Cmts.User") + (uuid "78ae2933-08f5-492f-a80b-2260e2429abb") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (fp_text user "Keep out components and traces solder side" + (at -42.25 -77.5 180) + (layer "Cmts.User") + (uuid "8198c7dd-90b6-4b6b-8646-1b5e7b8dc182") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (fp_text user "Keep out components and traces both sides" + (at -21.75 -12 0) + (layer "Cmts.User") + (uuid "a495a114-10da-4486-bb70-7e374e5f4a37") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (fp_text user "Max component height: solder side 2,67mm component side 14,49mm" + (at 40 -44.25 0) + (layer "Cmts.User") + (uuid "cc1ae88a-cb9f-4883-9893-13d424009e03") + (effects + (font + (size 2 2) + (thickness 0.25) + ) + ) + ) + (fp_text user "Keep out components and traces both sides" + (at 121.893243 -40.134926 90) + (layer "Cmts.User") + (uuid "d00349a8-7d96-4b85-a99c-0e69f1f18304") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (fp_text user "Keep out components and traces solder side" + (at -44.75 -36 90) + (layer "Cmts.User") + (uuid "e4cdaebd-bc65-475d-ba13-9dfb8e839fcd") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (fp_text user "${REFERENCE}" + (at 0 -17.5 0) + (layer "F.Fab") + (uuid "711f3f2a-b55d-4dc1-b7fe-3ecd57d5c906") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "A1" connect rect + (at 0.5 -4) + (size 0.7 3.2) + (layers "B.Cu") + (uuid "7d216b98-6a15-4b80-ac97-fcb8330dfbea") + ) + (pad "A2" connect rect + (at 1.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "1825f83b-6d20-4c5d-b30c-4369b7cea88b") + ) + (pad "A3" connect rect + (at 2.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "ea3544bd-a1df-4269-9ee5-bb4a7dac3d9a") + ) + (pad "A4" connect rect + (at 3.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "f1616f46-b7b1-42bb-a0df-0553ccc0e61d") + ) + (pad "A5" connect rect + (at 4.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "65aef076-367e-4011-9abf-dde199fe96fe") + ) + (pad "A6" connect rect + (at 5.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "7898aedc-218e-41c6-b3f4-9eed5e16ac97") + ) + (pad "A7" connect rect + (at 6.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid "da59bac3-f829-4ef9-a481-ab41da87c064") + ) + (pad "A8" connect rect + (at 7.5 -3.5) + (size 0.7 4.2) + (layers "B.Cu") + (uuid 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+ (layers "F.Cu") + (uuid "72d35d22-e91b-4809-a258-65a3c0b57efd") + ) + (pad "B8" connect rect + (at 7.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "b0217738-5b76-492a-a8b4-74774dac3f85") + ) + (pad "B9" connect rect + (at 8.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "4b152ef7-3b31-40cf-acbb-a91dd208d7a5") + ) + (pad "B10" connect rect + (at 9.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "921ac966-4ae8-4ae0-b9d6-ae5daa32fba3") + ) + (pad "B11" connect rect + (at 10.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "18d00af1-b4ff-4412-ae39-1456753d8889") + ) + (pad "B12" connect rect + (at 13.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "eb7ded37-4de1-4804-8262-944fd67cbec8") + ) + (pad "B13" connect rect + (at 14.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "af5e0c07-6d9a-4a46-ade6-804d556d9b38") + ) + (pad "B14" connect rect + (at 15.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "4092cae2-102c-4654-822e-e22cd46bdc59") + ) + (pad "B15" connect rect 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"1794ade9-8d9a-4d6b-b5c9-6cacd7b4be3c") + ) + (pad "B23" connect rect + (at 24.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "420e6316-d13b-48dd-883e-4a4a6820541e") + ) + (pad "B24" connect rect + (at 25.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "a8408970-bf12-4da5-9b93-5d451eeac841") + ) + (pad "B25" connect rect + (at 26.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "7c441e20-abdc-430b-a81c-358c559de7ac") + ) + (pad "B26" connect rect + (at 27.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "b6c0135c-827e-429e-8b1d-22aaca5ae24c") + ) + (pad "B27" connect rect + (at 28.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "0c9e51b7-15d6-4277-b485-c2b02356666d") + ) + (pad "B28" connect rect + (at 29.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "be344b6f-3151-4a00-a2e5-609359ee2101") + ) + (pad "B29" connect rect + (at 30.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "138737b0-a642-439e-ab7d-dc8225e46661") + ) + (pad "B30" connect rect + (at 31.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "d2f2e7f5-fdb2-46b4-8bfc-4b4def5a0829") + ) + (pad "B31" connect rect + (at 32.5 -4) + (size 0.7 3.2) + (layers "F.Cu") + (uuid "b302b296-4f9d-4db6-86ef-1c32b61a8ca9") + ) + (pad "B32" connect rect + (at 33.5 -3.5) + (size 0.7 4.2) + (layers "F.Cu") + (uuid "6af66af4-b7e1-43f1-8463-902b9646f268") + ) + (embedded_fonts no) ) diff --git a/Library/PCIexpress.pretty/PCIexpress_x8.kicad_mod b/Library/PCIexpress.pretty/PCIexpress_x8.kicad_mod index fb07d91..e4a302b 100644 --- a/Library/PCIexpress.pretty/PCIexpress_x8.kicad_mod +++ b/Library/PCIexpress.pretty/PCIexpress_x8.kicad_mod @@ -1,218 +1,1484 @@ -(module PCIexpress_x8 (layer F.Cu) (tedit 5D338A24) - (descr "PCIexpress x8 footprint") - (tags PCIexpress) - (attr virtual) - (fp_text reference REF** (at 0 -19.75) (layer F.SilkS) hide - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_text value BUS_PCIexpress_x8 (at 0 -23) (layer F.Fab) - (effects (font (size 1 1) (thickness 0.15))) - ) - (fp_circle (center 261.77 -106.13) (end 263.37 -106.13) (layer Dwgs.User) (width 0.12)) - (fp_circle (center 261.77 -16.6) (end 263.37 -16.6) (layer Dwgs.User) (width 0.12)) - (fp_line (start 261.77 -99.7) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -99.7) (end 261.77 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -22.9) (end 261.77 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -13.75) (end 256.65 -22.9) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -13.75) (end 256.65 -13.75) (layer Dwgs.User) (width 0.12)) - (fp_line (start 256.65 -108.15) (end 256.65 -99.7) (layer Dwgs.User) (width 0.12)) - (fp_line (start 122.5 -108.15) (end 256.65 -108.15) (layer Dwgs.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 108 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -15) (end 107 -14.5) (layer Cmts.User) (width 0.12)) - (fp_line (start 107.5 -10) (end 107.5 -15) (layer Cmts.User) (width 0.12)) - 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This is a KiCad 5 template - diff --git a/PCIexpress_x8_low/sym-lib-table b/PCIexpress_x8_low/sym-lib-table deleted file mode 100644 index 0f91e04..0000000 --- a/PCIexpress_x8_low/sym-lib-table +++ /dev/null @@ -1,3 +0,0 @@ -(sym_lib_table - (lib (name "PCIexpress")(type "KiCad")(uri "${KIPRJMOD}/../Library/PCIexpress.kicad_sym")(options "")(descr "")) -) diff --git a/PCIexpress_x8_low/term.kicad_sch b/PCIexpress_x8_low/term.kicad_sch deleted file mode 100644 index 6c4a783..0000000 --- a/PCIexpress_x8_low/term.kicad_sch +++ /dev/null @@ -1,220 +0,0 @@ -(kicad_sch (version 20211123) (generator eeschema) - - (uuid 138accee-b1f8-4d40-885b-a4c421af0b5f) - - (paper "A4") - - (title_block - (title "PCIexpress_x8_low") - (company "Author: Luca Anastasio") - ) - - (lib_symbols - (symbol "Device:R" (pin_numbers hide) (pin_names (offset 0)) (in_bom yes) (on_board yes) - (property "Reference" "R" (id 0) (at 2.032 0 90) - (effects (font (size 1.27 1.27))) - ) - (property "Value" "R" (id 1) (at 0 0 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1.27)))) - ) - ) - ) - (symbol "power:GND" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes) - (property "Reference" "#PWR" (id 0) (at 0 -6.35 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Value" "GND" (id 1) (at 0 -3.81 0) - (effects (font (size 1.27 1.27))) - ) - (property "Footprint" "" (id 2) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "" (id 3) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "ki_keywords" "global power" (id 4) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "ki_description" "Power symbol creates a global label with name \"GND\" , ground" (id 5) (at 0 0 0) - (effects (font (size 1.27 1.27)) hide) - ) - (symbol "GND_0_1" - (polyline - (pts - (xy 0 0) - (xy 0 -1.27) - (xy 1.27 -1.27) - (xy 0 -2.54) - (xy -1.27 -1.27) - (xy 0 -1.27) - ) - (stroke (width 0) (type default) (color 0 0 0 0)) - (fill (type none)) - ) - ) - (symbol "GND_1_1" - (pin power_in line (at 0 0 270) (length 0) hide - (name "GND" (effects (font (size 1.27 1.27)))) - (number "1" (effects (font (size 1.27 1.27)))) - ) - ) - ) - ) - - (junction (at 120.65 90.17) (diameter 0) (color 0 0 0 0) - (uuid a75797dc-33f8-44bd-ab50-2d7dad538a4c) - ) - (junction (at 146.05 90.17) (diameter 0) (color 0 0 0 0) - (uuid d989d5ba-dd83-475d-8326-0c1d9f0e6170) - ) - - (wire (pts (xy 120.65 100.33) (xy 120.65 102.87)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid 06e13852-0801-4278-a8e1-39b67ac03067) - ) - (wire (pts (xy 146.05 90.17) (xy 148.59 90.17)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid 73521490-6bc8-4a54-bf62-022d98a6797b) - ) - (wire (pts (xy 146.05 100.33) (xy 146.05 102.87)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid 7c77275f-fcd6-4b03-9f73-e2cc435c04a2) - ) - (wire (pts (xy 120.65 90.17) (xy 123.19 90.17)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid b27aeb11-0710-46a4-9b58-da66826cc23c) - ) - (wire (pts (xy 146.05 92.71) (xy 146.05 90.17)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid b9d80a62-33c5-4c0f-8c85-a2e2778b852c) - ) - (wire (pts (xy 120.65 92.71) (xy 120.65 90.17)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid ccc9129d-7d58-4b08-9c83-dc8bb223c3b0) - ) - (wire (pts (xy 118.11 90.17) (xy 120.65 90.17)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid e28bd26d-0269-450a-a75a-925607c0334a) - ) - (wire (pts (xy 143.51 90.17) (xy 146.05 90.17)) - (stroke (width 0) (type default) (color 0 0 0 0)) - (uuid f984b941-ac1b-4786-ac7e-5a3f8d530bf0) - ) - - (hierarchical_label "OUT-" (shape output) (at 118.11 90.17 180) - (effects (font (size 1.27 1.27)) (justify right)) - (uuid 560c5408-35da-4f17-ad93-ebff4545c710) - ) - (hierarchical_label "OUT+" (shape output) (at 143.51 90.17 180) - (effects (font (size 1.27 1.27)) (justify right)) - (uuid 595c76c5-b9dd-4911-8646-86cb029a2ea8) - ) - (hierarchical_label "IN-" (shape input) (at 123.19 90.17 0) - (effects (font (size 1.27 1.27)) (justify left)) - (uuid 8e56861f-3e22-4790-90a2-8f08f13ad3b3) - ) - (hierarchical_label "IN+" (shape input) (at 148.59 90.17 0) - (effects (font (size 1.27 1.27)) (justify left)) - (uuid 9478b91d-f06c-46c4-826a-83065824199c) - ) - - (symbol (lib_id "Device:R") (at 120.65 96.52 0) (unit 1) - (in_bom yes) (on_board yes) - (uuid 00000000-0000-0000-0000-00005d52dcbc) - (property "Reference" "R1" (id 0) (at 122.428 95.3516 0) - (effects (font (size 1.27 1.27)) (justify left)) - ) - (property "Value" "" (id 1) (at 122.428 97.663 0) - (effects (font (size 1.27 1.27)) (justify left)) - ) - (property "Footprint" "" (id 2) (at 118.872 96.52 90) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "~" (id 3) (at 120.65 96.52 0) - (effects (font (size 1.27 1.27)) hide) - ) - (pin "1" (uuid 92e685dc-6258-40e8-88b3-b39b5d4e3eaa)) - (pin "2" (uuid 41226e20-4e27-4e1b-8ecc-a5c74eb10528)) - ) - - (symbol (lib_id "Device:R") (at 146.05 96.52 0) (unit 1) - (in_bom yes) (on_board yes) - (uuid 00000000-0000-0000-0000-00005d52e298) - (property "Reference" "R2" (id 0) (at 147.828 95.3516 0) - (effects (font (size 1.27 1.27)) (justify left)) - ) - (property "Value" "" (id 1) (at 147.828 97.663 0) - (effects (font (size 1.27 1.27)) (justify left)) - ) - (property "Footprint" "" (id 2) (at 144.272 96.52 90) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "~" (id 3) (at 146.05 96.52 0) - (effects (font (size 1.27 1.27)) hide) - ) - (pin "1" (uuid b7bb03c1-865f-4526-9489-aa0f7043a7e0)) - (pin "2" (uuid d5ee8607-b6f8-4805-857f-f8e7188c8825)) - ) - - (symbol (lib_id "power:GND") (at 120.65 102.87 0) (unit 1) - (in_bom yes) (on_board yes) - (uuid 00000000-0000-0000-0000-00005d52e619) - (property "Reference" "#PWR0109" (id 0) (at 120.65 109.22 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Value" "" (id 1) (at 120.777 107.2642 0)) - (property "Footprint" "" (id 2) (at 120.65 102.87 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "" (id 3) (at 120.65 102.87 0) - (effects (font (size 1.27 1.27)) hide) - ) - (pin "1" (uuid 7d7f3204-832e-42d0-ba6c-9e9dd86cee80)) - ) - - (symbol (lib_id "power:GND") (at 146.05 102.87 0) (unit 1) - (in_bom yes) (on_board yes) - (uuid 00000000-0000-0000-0000-00005d52ec15) - (property "Reference" "#PWR0110" (id 0) (at 146.05 109.22 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Value" "" (id 1) (at 146.177 107.2642 0)) - (property "Footprint" "" (id 2) (at 146.05 102.87 0) - (effects (font (size 1.27 1.27)) hide) - ) - (property "Datasheet" "" (id 3) (at 146.05 102.87 0) - (effects (font (size 1.27 1.27)) hide) - ) - (pin "1" (uuid 17867cc3-9e6c-4166-9af7-20ba90430fea)) - ) -) diff --git a/README.md b/README.md index 77d2237..25cf3f1 100644 --- a/README.md +++ b/README.md @@ -1,27 +1,65 @@ # PCIexpress-KiCad PCI Expressâ„¢ libraries and templates for KiCad -Made using guidelines from PCI Expressâ„¢ Card Electromechanical Specification Rev. 1.2 +Made using guidelines from PCI Expressâ„¢ Card Electromechanical Specification Rev. 4.0 Version 0.9 and PCI Expressâ„¢ M.2 Specification Revision 1.0 -Updated for KiCad 6 +Updated for KiCad 9.0.1 ![](example.jpg) ### Contents **Templates:** +* M.2 A Key 22/30mm width, 30/42/60/80/110mm length +* M.2 B Key 22/30mm width, 30/42/60/80/110mm length +* M.2 M Key 22/30mm width, 30/42/60/80/110mm length +* M.2 E Key 22/30mm width, 30/42/60/80/110mm length +* M.2 A+E Key 22/30mm width, 30/42/60/80/110mm length +* M.2 B+M Key 22/30mm width, 30/42/60/80/110mm length * x1 cards: full size, half length, low profile +* x2 cards: full size, half length, low profile * x4 cards: full size, half length, low profile * x8 cards: full size, half length, low profile * x16 cards: full size, half length, low profile **Symbols:** +* A Key M.2 +* B Key M.2 +* C Key M.2 +* D Key M.2 +* E Key M.2 +* F Key M.2 +* G Key M.2 +* H Key M.2 +* J Key M.2 +* K Key M.2 +* L Key M.2 +* M Key M.2 +* A+E Key M.2 +* B+M Key M.2 * x1 +* x2 * x4 * x8 * x16 * Bracket **Footprints:** +* A Key M.2 with multiple card outlines +* B Key M.2 with multiple card outlines +* C Key M.2 with multiple card outlines +* D Key M.2 with multiple card outlines +* E Key M.2 with multiple card outlines +* F Key M.2 with multiple card outlines +* G Key M.2 with multiple card outlines +* H Key M.2 with multiple card outlines +* J Key M.2 with multiple card outlines +* K Key M.2 with multiple card outlines +* L Key M.2 with multiple card outlines +* M Key M.2 with multiple card outlines +* A+E Key M.2 with multiple card outlines +* B+M Key M.2 with multiple card outlines +* M.2 Mounting Pad * x1 with multiple card outlines +* x2 with multiple card outlines * x4 with multiple card outlines * x8 with multiple card outlines * x16 with multiple card outlines @@ -29,6 +67,11 @@ Updated for KiCad 6 * Low profile bracket (with 3D model) * Low profile to full height adapter bracker (with 3D model) +**Notes:** +* Transmit and Recieve pairs on M.2 Symbols are from the perspective of module not the host. +* Transmit and Recieve pairs on PCIe symbols are from the perspective of module not the host. +* Triple check the pinout on your specific M.2 socket to ensure correct wiring. + ### License This documentation describes Open Hardware and is licensed under the CERN OHL v.1.2. diff --git a/PCIexpress_x16_full/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 22110/.gitignore similarity index 100% rename from PCIexpress_x16_full/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 22110/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 22110/M.2 A Key 22110.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 22110/M.2 A Key 22110.kicad_pcb new file mode 100644 index 0000000..8d88fc8 --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 22110/M.2 A Key 22110.kicad_pcb @@ -0,0 +1,3121 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "GND") + (net 2 "/M.2 A Key/PET1P") + (net 3 "/M.2 A Key/PET1N") + (net 4 "/M.2 A Key/PET0P") + (net 5 "/M.2 A Key/PET0N") + (net 6 "/PET1+") + (net 7 "/PET0-") + (net 8 "/PET0+") + (net 9 "/PET1-") + (net 10 "+3.3V") + (net 11 "/USB_D+") + (net 12 "/USB_D-") + (net 13 "/LED#1") + (net 14 "/LED#2") + (net 15 "/DP_MLDIR") + (net 16 "/DP_ML3-") + (net 17 "/DP_AUX-") + (net 18 "/DP_ML3+") + (net 19 "/DP_AUX+") + (net 20 "/DP_ML2-") + (net 21 "/DP_ML1-") + (net 22 "/DP_ML2+") + (net 23 "/DP_ML1+") + (net 24 "/DP_HPD") + (net 25 "/DP_ML0-") + (net 26 "/DP_ML0+") + (net 27 "/PER0-") + (net 28 "/PER0+") + (net 29 "unconnected-(J1-Vender_Defined-Pad38)") + (net 30 "unconnected-(J1-Vender_Defined-Pad40)") + (net 31 "unconnected-(J1-Vender_Defined-Pad42)") + (net 32 "unconnected-(J1-COEX3-Pad44)") + (net 33 "unconnected-(J1-COEX2-Pad46)") + (net 34 "/REFCLK0+") + (net 35 "unconnected-(J1-COEX1-Pad48)") + (net 36 "/REFCLK0-") + (net 37 "/SUSCLK") + (net 38 "/PERST0#") + (net 39 "/CLKREQ0#") + (net 40 "/W_DISABLE2#") + (net 41 "/PEWAKE0#") + (net 42 "/W_DISABLE1#") + (net 43 "/I2C_DATA") + (net 44 "/PER1+") + (net 45 "/I2C_CLK") + (net 46 "/PER1-") + (net 47 "/ALERT#") + (net 48 "unconnected-(J1-RESERVED-Pad64)") + (net 49 "/PERST1#") + (net 50 "/CLKREQ1#") + (net 51 "/PEWAKE1#") + (net 52 "/REFCLK1+") + (net 53 "/REFCLK1-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "3d356e6e-51c5-4742-891a-2e269df22017") + (at 107.914916 154.544 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C3" + (at 0 -1.05 90) + (layer "F.SilkS") + (uuid "5e53516f-5683-42e8-a93e-27cf8114c5c3") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "dd879e30-f5c1-466f-a74f-2b99e469b3c1") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "5ef3b102-4d7e-4294-b6be-f90f6cb37642") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "39accfe4-c7ba-4f5c-8d91-2dafb7fa5f28") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr smd) + (fp_line + (start 0.7 -0.35) + (end 0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "5d2b262e-2426-4b6d-9731-ade33616d51f") + ) + (fp_line + (start -0.7 -0.35) + (end 0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "59b7d5ea-2b0c-4a46-b322-9f2297f3d403") + ) + (fp_line + (start 0.7 0.35) + (end -0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "3c9e4837-75ba-42fa-aec2-10e399cd58c6") + ) + (fp_line + (start -0.7 0.35) + (end -0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "e29ceda9-b845-45c6-9d7e-83463301ac57") + ) + (fp_line + (start 0.3 -0.15) + (end 0.3 0.15) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "7055e1a1-0a29-492a-a919-84f2ad53d4e5") + ) + (fp_line + (start -0.3 -0.15) + (end 0.3 -0.15) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "5f041ca2-fddf-4b28-966c-8159bf85de00") + ) + (fp_line + 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This is a KiCad 9 template + diff --git a/PCIexpress_x16_half/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 2230/.gitignore similarity index 100% rename from PCIexpress_x16_half/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 2230/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 2230/M.2 A Key 2230.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 2230/M.2 A Key 2230.kicad_pcb new file mode 100644 index 0000000..1a4ceec --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 2230/M.2 A Key 2230.kicad_pcb @@ -0,0 +1,3138 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) 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This is a KiCad 9 template + diff --git a/PCIexpress_x16_low/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 2242/.gitignore similarity index 100% rename from PCIexpress_x16_low/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 2242/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 2242/M.2 A Key 2242.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 2242/M.2 A Key 2242.kicad_pcb new file mode 100644 index 0000000..698b4ed --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 2242/M.2 A Key 2242.kicad_pcb @@ -0,0 +1,3135 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + 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This is a KiCad 9 template + diff --git a/PCIexpress_x1_full/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 2260/.gitignore similarity index 100% rename from PCIexpress_x1_full/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 2260/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 2260/M.2 A Key 2260.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 2260/M.2 A Key 2260.kicad_pcb new file mode 100644 index 0000000..656f378 --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 2260/M.2 A Key 2260.kicad_pcb @@ -0,0 +1,3123 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + 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This is a KiCad 9 template + diff --git a/PCIexpress_x1_half/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 2280/.gitignore similarity index 100% rename from PCIexpress_x1_half/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 2280/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 2280/M.2 A Key 2280.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 2280/M.2 A Key 2280.kicad_pcb new file mode 100644 index 0000000..411d702 --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 2280/M.2 A Key 2280.kicad_pcb @@ -0,0 +1,3121 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + 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This is a KiCad 9 template + diff --git a/PCIexpress_x1_low/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 30110/.gitignore similarity index 100% rename from PCIexpress_x1_low/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 30110/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 30110/M.2 A Key 30110.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 30110/M.2 A Key 30110.kicad_pcb new file mode 100644 index 0000000..89a934f --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 30110/M.2 A Key 30110.kicad_pcb @@ -0,0 +1,3140 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" 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This is a KiCad 9 template + diff --git a/PCIexpress_x4_full/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 3030/.gitignore similarity index 100% rename from PCIexpress_x4_full/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 3030/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 3030/M.2 A Key 3030.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 3030/M.2 A Key 3030.kicad_pcb new file mode 100644 index 0000000..dcfbc09 --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 3030/M.2 A Key 3030.kicad_pcb @@ -0,0 +1,3137 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + 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This is a KiCad 9 template + diff --git a/PCIexpress_x4_half/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 3042/.gitignore similarity index 100% rename from PCIexpress_x4_half/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 3042/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 3042/M.2 A Key 3042.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 3042/M.2 A Key 3042.kicad_pcb new file mode 100644 index 0000000..2e90364 --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 3042/M.2 A Key 3042.kicad_pcb @@ -0,0 +1,3140 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + 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This is a KiCad 9 template + diff --git a/PCIexpress_x4_low/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 3060/.gitignore similarity index 100% rename from PCIexpress_x4_low/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 3060/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 3060/M.2 A Key 3060.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 3060/M.2 A Key 3060.kicad_pcb new file mode 100644 index 0000000..8d6196b --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 3060/M.2 A Key 3060.kicad_pcb @@ -0,0 +1,3140 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + 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This is a KiCad 9 template + diff --git a/PCIexpress_x8_full/.gitignore b/Templates/M.2 A Key Templates/M.2 A Key 3080/.gitignore similarity index 100% rename from PCIexpress_x8_full/.gitignore rename to Templates/M.2 A Key Templates/M.2 A Key 3080/.gitignore diff --git a/Templates/M.2 A Key Templates/M.2 A Key 3080/M.2 A Key 3080.kicad_pcb b/Templates/M.2 A Key Templates/M.2 A Key 3080/M.2 A Key 3080.kicad_pcb new file mode 100644 index 0000000..3cb1b83 --- /dev/null +++ b/Templates/M.2 A Key Templates/M.2 A Key 3080/M.2 A Key 3080.kicad_pcb @@ -0,0 +1,3140 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + 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This is a KiCad 9 template + diff --git a/PCIexpress_x8_half/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 22110/.gitignore similarity index 100% rename from PCIexpress_x8_half/.gitignore rename to Templates/M.2 A+E Key Templates/M.2 A+E Key 22110/.gitignore diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 22110/M.2 A+E Key 22110.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 22110/M.2 A+E Key 22110.kicad_pcb new file mode 100644 index 0000000..1f3548a --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 22110/M.2 A+E Key 22110.kicad_pcb @@ -0,0 +1,2996 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 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This is a KiCad 9 template + diff --git a/PCIexpress_x8_low/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/.gitignore similarity index 100% rename from PCIexpress_x8_low/.gitignore rename to Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/.gitignore diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/M.2 A+E Key 2230.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/M.2 A+E Key 2230.kicad_pcb new file mode 100644 index 0000000..015a563 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/M.2 A+E Key 2230.kicad_pcb @@ -0,0 +1,3019 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" 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"/00f9635e-3855-4d25-80f9-9972c6f60abd/f5aa2f3a-f830-4baa-850a-767a8008e5b7/4085d364-ba96-420e-b5a6-dae580e8c21f" + (reference "C2") + (unit 1) + ) + (path "/00f9635e-3855-4d25-80f9-9972c6f60abd/f5aa2f3a-f830-4baa-850a-767a8008e5b7/d91fb369-9227-4ab0-aedf-b8e91770cbc3" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/meta/info.html b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/meta/info.html new file mode 100644 index 0000000..2e8a657 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2230/meta/info.html @@ -0,0 +1,3 @@ +M.2 A+E Key 2230 +

This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2242/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2242/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2242/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2242/M.2 A+E Key 2242.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2242/M.2 A+E Key 2242.kicad_pcb new file mode 100644 index 0000000..cf58240 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2242/M.2 A+E Key 2242.kicad_pcb @@ -0,0 +1,2996 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2260/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2260/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2260/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2260/M.2 A+E Key 2260.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2260/M.2 A+E Key 2260.kicad_pcb new file mode 100644 index 0000000..fac3d86 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2260/M.2 A+E Key 2260.kicad_pcb @@ -0,0 +1,2996 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" 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This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2280/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2280/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2280/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 2280/M.2 A+E Key 2280.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2280/M.2 A+E Key 2280.kicad_pcb new file mode 100644 index 0000000..94f33ab --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 2280/M.2 A+E Key 2280.kicad_pcb @@ -0,0 +1,2996 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 30110/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 30110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 30110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 30110/M.2 A+E Key 30110.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 30110/M.2 A+E Key 30110.kicad_pcb new file mode 100644 index 0000000..fc283d0 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 30110/M.2 A+E Key 30110.kicad_pcb @@ -0,0 +1,3023 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "GND") + (net 2 "/M.2 A+E Key/PET1P") + (net 3 "/M.2 A+E Key/PET0N") + (net 4 "/M.2 A+E Key/PET1N") + (net 5 "/M.2 A+E Key/PET0P") + (net 6 "/PET0-") + (net 7 "+3.3V") + (net 8 "/USB_D+") + (net 9 "/USB_D-") + (net 10 "/LED#1") + (net 11 "/LED#2") + (net 12 "unconnected-(J1-NC-Pad17)") + (net 13 "unconnected-(J1-NC-Pad19)") + (net 14 "unconnected-(J1-NC-Pad20)") + (net 15 "unconnected-(J1-NC-Pad21)") + (net 16 "unconnected-(J1-NC-Pad22)") + (net 17 "unconnected-(J1-NC-Pad23)") + (net 18 "unconnected-(J1-NC-Pad32)") + (net 19 "unconnected-(J1-NC-Pad34)") + (net 20 "/PER0-") + (net 21 "unconnected-(J1-NC-Pad36)") + (net 22 "/PER0+") + (net 23 "unconnected-(J1-Vender_Defined-Pad38)") + (net 24 "unconnected-(J1-Vender_Defined-Pad40)") + (net 25 "unconnected-(J1-Vender_Defined-Pad42)") + (net 26 "unconnected-(J1-COEX3-Pad44)") + (net 27 "unconnected-(J1-COEX2-Pad46)") + (net 28 "/REFCLK0+") + (net 29 "unconnected-(J1-COEX1-Pad48)") + (net 30 "/REFCLK0-") + (net 31 "/SUSCLK") + (net 32 "/PERST0#") + (net 33 "/CLKREQ0#") + (net 34 "/W_DISABLE2#") + (net 35 "/PEWAKE#") + (net 36 "/W_DISABLE1#") + (net 37 "/I2C_DATA") + (net 38 "/PER1+") + (net 39 "/I2C_CLK") + (net 40 "/PER1-") + (net 41 "/ALERT#") + (net 42 "unconnected-(J1-RESERVED-Pad64)") + (net 43 "/PERST1#") + (net 44 "/CLKREQ1#") + (net 45 "/PEWAKE1#") + (net 46 "/REFCLK1+") + (net 47 "/REFCLK1-") + (net 48 "/PET0+") + (net 49 "/PET1-") + (net 50 "/PET1+") + (footprint "PCIexpress:M.2 A+E Key Connector" + (layer "F.Cu") + (uuid "0d9482f6-1ccf-4c99-8426-0b486b637b8e") + (at 109.01 159.54) + (property "Reference" "J1" + (at 0 -5.08 0) + (unlocked yes) + (layer "F.Fab") + (uuid "213f8908-5004-4788-b245-62043f74a253") + (effects + (font + (size 1 1) + (thickness 0.1) + ) + ) + ) + (property "Value" "~" + (at 0 5 0) + (unlocked yes) + (layer "F.Fab") + (uuid "1f68a088-d276-494a-a2c9-65fe0544c0d6") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "b8fa8b9b-9731-4236-85d1-902359fd7d6d") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Description" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "3900cc5a-d1b8-44fb-9655-1ac266343a7f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) 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This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3030/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3030/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3030/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3030/M.2 A+E Key 3030.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3030/M.2 A+E Key 3030.kicad_pcb new file mode 100644 index 0000000..26ff524 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3030/M.2 A+E Key 3030.kicad_pcb @@ -0,0 +1,3023 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" 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This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3042/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3042/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3042/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3042/M.2 A+E Key 3042.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3042/M.2 A+E Key 3042.kicad_pcb new file mode 100644 index 0000000..e8dadb8 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3042/M.2 A+E Key 3042.kicad_pcb @@ -0,0 +1,3023 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3060/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3060/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3060/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3060/M.2 A+E Key 3060.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3060/M.2 A+E Key 3060.kicad_pcb new file mode 100644 index 0000000..6e37eb6 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3060/M.2 A+E Key 3060.kicad_pcb @@ -0,0 +1,3023 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" 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This is a KiCad 9 template + diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/.gitignore b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/M.2 A+E Key 3080.kicad_pcb b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/M.2 A+E Key 3080.kicad_pcb new file mode 100644 index 0000000..4f16d8f --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/M.2 A+E Key 3080.kicad_pcb @@ -0,0 +1,3023 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" 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"/5fe856aa-e488-4d77-b69a-5a4a48502cc8/3cfcf2f6-95cb-4bd5-be38-9f012bbbcb18/4085d364-ba96-420e-b5a6-dae580e8c21f" + (reference "C2") + (unit 1) + ) + (path "/5fe856aa-e488-4d77-b69a-5a4a48502cc8/3cfcf2f6-95cb-4bd5-be38-9f012bbbcb18/d91fb369-9227-4ab0-aedf-b8e91770cbc3" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/meta/info.html b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/meta/info.html new file mode 100644 index 0000000..04a0577 --- /dev/null +++ b/Templates/M.2 A+E Key Templates/M.2 A+E Key 3080/meta/info.html @@ -0,0 +1,3 @@ +M.2 A+E Key 3080 +

This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 22110/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 22110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 22110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 22110/M.2 B Key 22110.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 22110/M.2 B Key 22110.kicad_pcb new file mode 100644 index 0000000..cd02429 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 22110/M.2 B Key 22110.kicad_pcb @@ -0,0 +1,2975 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref 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"/DPR") + (net 17 "/GPIO_7") + (net 18 "/GPIO_11") + (net 19 "/GPIO_10") + (net 20 "/GPIO_8") + (net 21 "/UIM-RESET") + (net 22 "/UIM-CLK") + (net 23 "/UIM-DATA") + (net 24 "/PER1-") + (net 25 "/UIM-PWR") + (net 26 "/PER1+") + (net 27 "/DEVSLP") + (net 28 "/GPIO_0") + (net 29 "/GPIO_1") + (net 30 "/GPIO_2") + (net 31 "/GPIO_3") + (net 32 "/PER0-") + (net 33 "/GPIO_4") + (net 34 "/PER0+") + (net 35 "/PERST#") + (net 36 "/CLKREQ#") + (net 37 "/REFCLK-") + (net 38 "/PEWAKE#") + (net 39 "/REFCLK+") + (net 40 "unconnected-(J1-NC-Pad56)") + (net 41 "unconnected-(J1-NC-Pad58)") + (net 42 "/ANTCTL0") + (net 43 "unconnected-(J1-COEX3-Pad60)") + (net 44 "/ANTCTL1") + (net 45 "unconnected-(J1-COEX2-Pad62)") + (net 46 "/ANTCTL2") + (net 47 "unconnected-(J1-COEX1-Pad64)") + (net 48 "/ANTCTL3") + (net 49 "/SIM_DETECT") + (net 50 "/RESET#") + (net 51 "/SUSCLK") + (net 52 "/CONFIG_1") + (net 53 "/CONFIG_2") + (net 54 "/PET0+") + (net 55 "/PET1+") + (net 56 "/PET1-") + (net 57 "/PET0-") + (footprint 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22110/meta/info.html @@ -0,0 +1,3 @@ +M.2 B Key 22110 +

This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2230/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 2230/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2230/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2230/M.2 B Key 2230.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 2230/M.2 B Key 2230.kicad_pcb new file mode 100644 index 0000000..5273e6c --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2230/M.2 B Key 2230.kicad_pcb @@ -0,0 +1,3000 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B key/PET0N") + (net 2 "/PET0-") + (net 3 "/M.2 B key/PET0P") + (net 4 "/PET0+") + (net 5 "/M.2 B key/PET1N") + (net 6 "/PET1-") + (net 7 "/M.2 B key/PET1P") + (net 8 "/PET1+") + (net 9 "GND") + (net 10 "/UIM-DATA") + (net 11 "/GPIO_4") + (net 12 "/W_DISABLE1#") + (net 13 "+3.3V") + (net 14 "/DEVSLP") + (net 15 "/DPR") + (net 16 "/GPIO_8") + (net 17 "/CONFIG_1") + (net 18 "/SIM_DETECT") + (net 19 "/UIM-PWR") + (net 20 "unconnected-(J1-COEX3-Pad60)") + (net 21 "/REFCLK-") + (net 22 "/RESET#") + (net 23 "/PER0-") + (net 24 "/GPIO_7") + (net 25 "/ANTCTL1") + (net 26 "/GPIO_0") + (net 27 "/GPIO_5") + (net 28 "/SUSCLK") + (net 29 "/GPIO_6") + (net 30 "/PERST#") + (net 31 "/UIM-CLK") + (net 32 "/GPIO_1") + (net 33 "/GPIO_10") + (net 34 "/ANTCTL0") + (net 35 "unconnected-(J1-COEX2-Pad62)") + (net 36 "/GPIO_2") + (net 37 "/CONFIG_3") + (net 38 "/PEWAKE#") + (net 39 "/CONFIG_0") + (net 40 "/GPIO_11") + (net 41 "/ANTCTL2") + (net 42 "unconnected-(J1-NC-Pad56)") + (net 43 "/USB_D-") + (net 44 "unconnected-(J1-COEX1-Pad64)") + (net 45 "/UIM-RESET") + (net 46 "/CONFIG_2") + (net 47 "/PER0+") + (net 48 "/CLKREQ#") + (net 49 "/ANTCTL3") + (net 50 "/FULL_CARD_PWR_OFF#") + (net 51 "/GPIO_9{slash}LED#1") + (net 52 "unconnected-(J1-NC-Pad58)") + (net 53 "/USB_D+") + (net 54 "/GPIO_3") + (net 55 "/REFCLK+") + (net 56 "/PER1-") + (net 57 "/PER1+") + (footprint "Athena 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This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2242/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 2242/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2242/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2242/M.2 B Key 2242.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 2242/M.2 B Key 2242.kicad_pcb new file mode 100644 index 0000000..f9dde6c --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2242/M.2 B Key 2242.kicad_pcb @@ -0,0 +1,2977 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B key/PET0N") + (net 2 "/M.2 B key/PET0P") + (net 3 "/M.2 B key/PET1P") + (net 4 "/M.2 B key/PET1N") + (net 5 "GND") + (net 6 "/CONFIG_3") + (net 7 "+3.3V") + (net 8 "/FULL_CARD_PWR_OFF#") + (net 9 "/USB_D+") + (net 10 "/W_DISABLE1#") + (net 11 "/USB_D-") + (net 12 "/GPIO_9{slash}LED#1") + (net 13 "/GPIO_5") + (net 14 "/CONFIG_0") + (net 15 "/GPIO_6") + (net 16 "/DPR") + (net 17 "/GPIO_7") + (net 18 "/GPIO_11") + (net 19 "/GPIO_10") + (net 20 "/GPIO_8") + (net 21 "/UIM-RESET") + (net 22 "/UIM-CLK") + (net 23 "/UIM-DATA") + (net 24 "/PER1-") + (net 25 "/UIM-PWR") + (net 26 "/PER1+") + (net 27 "/DEVSLP") + (net 28 "/GPIO_0") + (net 29 "/GPIO_1") + (net 30 "/GPIO_2") + (net 31 "/GPIO_3") + (net 32 "/PER0-") + (net 33 "/GPIO_4") + (net 34 "/PER0+") + (net 35 "/PERST#") + (net 36 "/CLKREQ#") + (net 37 "/REFCLK-") + (net 38 "/PEWAKE#") + (net 39 "/REFCLK+") + (net 40 "unconnected-(J1-NC-Pad56)") + (net 41 "unconnected-(J1-NC-Pad58)") + (net 42 "/ANTCTL0") + (net 43 "unconnected-(J1-COEX3-Pad60)") + (net 44 "/ANTCTL1") + (net 45 "unconnected-(J1-COEX2-Pad62)") + (net 46 "/ANTCTL2") + (net 47 "unconnected-(J1-COEX1-Pad64)") + (net 48 "/ANTCTL3") + (net 49 "/SIM_DETECT") + (net 50 "/RESET#") + (net 51 "/SUSCLK") + (net 52 "/CONFIG_1") + (net 53 "/CONFIG_2") + (net 54 "/PET0+") + (net 55 "/PET1+") + (net 56 "/PET1-") + (net 57 "/PET0-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "1e3fdea4-2e3e-4b78-b7d2-3aa76f6a2868") + (at 111.61 152.8 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C3" + (at 0 0.75 90) + (layer "F.SilkS") + (uuid "547e88c6-b6e6-4dd0-8132-66c33259d9d4") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "09710524-9bc7-49d3-878d-bbf413d31d01") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "7d4285e9-d878-4ef2-a06f-cee3ad8c6d02") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid 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This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2260/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 2260/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2260/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2260/M.2 B Key 2260.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 2260/M.2 B Key 2260.kicad_pcb new file mode 100644 index 0000000..cf87420 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2260/M.2 B Key 2260.kicad_pcb @@ -0,0 +1,2975 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This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2280/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 2280/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2280/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 2280/M.2 B Key 2280.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 2280/M.2 B Key 2280.kicad_pcb new file mode 100644 index 0000000..bb7eeab --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 2280/M.2 B Key 2280.kicad_pcb @@ -0,0 +1,2975 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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+ (net 17 "/GPIO_7") + (net 18 "/GPIO_11") + (net 19 "/GPIO_10") + (net 20 "/GPIO_8") + (net 21 "/UIM-RESET") + (net 22 "/UIM-CLK") + (net 23 "/UIM-DATA") + (net 24 "/PER1-") + (net 25 "/UIM-PWR") + (net 26 "/PER1+") + (net 27 "/DEVSLP") + (net 28 "/GPIO_0") + (net 29 "/GPIO_1") + (net 30 "/GPIO_2") + (net 31 "/GPIO_3") + (net 32 "/PER0-") + (net 33 "/GPIO_4") + (net 34 "/PER0+") + (net 35 "/PERST#") + (net 36 "/CLKREQ#") + (net 37 "/REFCLK-") + (net 38 "/PEWAKE#") + (net 39 "/REFCLK+") + (net 40 "unconnected-(J1-NC-Pad56)") + (net 41 "unconnected-(J1-NC-Pad58)") + (net 42 "/ANTCTL0") + (net 43 "unconnected-(J1-COEX3-Pad60)") + (net 44 "/ANTCTL1") + (net 45 "unconnected-(J1-COEX2-Pad62)") + (net 46 "/ANTCTL2") + (net 47 "unconnected-(J1-COEX1-Pad64)") + (net 48 "/ANTCTL3") + (net 49 "/SIM_DETECT") + (net 50 "/RESET#") + (net 51 "/SUSCLK") + (net 52 "/CONFIG_1") + (net 53 "/CONFIG_2") + (net 54 "/PET0+") + (net 55 "/PET1+") + (net 56 "/PET1-") + (net 57 "/PET0-") + (footprint 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This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 30110/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 30110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 30110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 30110/M.2 B key 30110.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 30110/M.2 B key 30110.kicad_pcb new file mode 100644 index 0000000..a69dd88 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 30110/M.2 B key 30110.kicad_pcb @@ -0,0 +1,2999 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B key/PET1N") + (net 2 "/M.2 B key/PET1P") + (net 3 "/M.2 B key/PET0P") + (net 4 "/M.2 B key/PET0N") + (net 5 "/PET1-") + (net 6 "/PET0-") + (net 7 "/CONFIG_3") + (net 8 "+3.3V") + (net 9 "GND") + (net 10 "/FULL_CARD_PWR_OFF#") + (net 11 "/USB_D+") + (net 12 "/W_DISABLE1#") + (net 13 "/USB_D-") + (net 14 "/GPIO_9{slash}LED#1") + (net 15 "/GPIO_5") + (net 16 "/CONFIG_0") + (net 17 "/GPIO_6") + (net 18 "/DPR") + (net 19 "/GPIO_7") + (net 20 "/GPIO_11") + (net 21 "/GPIO_10") + (net 22 "/GPIO_8") + (net 23 "/UIM-RESET") + (net 24 "/UIM-CLK") + (net 25 "/UIM-DATA") + (net 26 "/PER1-") + (net 27 "/UIM-PWR") + (net 28 "/PER1+") + (net 29 "/DEVSLP") + (net 30 "/GPIO_0") + (net 31 "/GPIO_1") + (net 32 "/GPIO_2") + (net 33 "/GPIO_3") + (net 34 "/PER0-") + (net 35 "/GPIO_4") + (net 36 "/PER0+") + (net 37 "/PERST#") + (net 38 "/CLKREQ#") + (net 39 "/REFCLK-") + (net 40 "/PEWAKE#") + (net 41 "/REFCLK+") + (net 42 "unconnected-(J1-NC-Pad56)") + (net 43 "unconnected-(J1-NC-Pad58)") + (net 44 "/ANTCTL0") + (net 45 "unconnected-(J1-COEX3-Pad60)") + (net 46 "/ANTCTL1") + (net 47 "unconnected-(J1-COEX2-Pad62)") + (net 48 "/ANTCTL2") + (net 49 "unconnected-(J1-COEX1-Pad64)") + (net 50 "/ANTCTL3") + (net 51 "/SIM_DETECT") + (net 52 "/RESET#") + (net 53 "/SUSCLK") + (net 54 "/CONFIG_1") + (net 55 "/CONFIG_2") + (net 56 "/PET0+") + (net 57 "/PET1+") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "00eec7ae-e629-46e2-8812-8774baccd223") + (at 110.41 153.47 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C4" + (at 0 -0.72 90) + (layer "F.SilkS") + (uuid "aeef58e6-53ed-4809-9b2c-f3958a71c8fc") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "2a42951d-a1e7-45d8-a9c0-088eeec9f7f8") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "92513790-6830-451b-a966-07721cc352bb") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide 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"7d63355c-7474-456e-8e25-72f0b0e3255b") + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (instances + (project "M.2 B key 30110" + (path "/214bfc41-24f4-4af9-b8d5-f53b552105c4" + (page "2") + ) + ) + ) + ) + (sheet_instances + (path "/" + (page "1") + ) + ) + (embedded_fonts no) +) diff --git a/Templates/M.2 B Key Templates/M.2 B Key 30110/M.2 B key.kicad_sch b/Templates/M.2 B Key Templates/M.2 B Key 30110/M.2 B key.kicad_sch new file mode 100644 index 0000000..a91e734 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 30110/M.2 B key.kicad_sch @@ -0,0 +1,3999 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "82704d6d-46d4-44c4-9e05-97698149e6dd") + (paper "A4") + (lib_symbols + (symbol "Mechanical:MountingHole_Pad" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 1.016) + (hide yes) + ) + (exclude_from_sim no) + (in_bom no) + (on_board yes) + (property "Reference" "H" + (at 0 6.35 0) + (effects + (font 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "b570131d-ec55-4d89-a1d2-af1f40dec2ae") + ) + (pin "1" + (uuid "2c371b40-4158-41bc-b2c3-3815e64cc625") + ) + (instances + (project "M.2 B key 30110" + (path "/214bfc41-24f4-4af9-b8d5-f53b552105c4/a97a1c5a-89b8-4965-a918-3f182150b9ea/27d77bf0-8499-4672-87f1-05095c3d0a68" + (reference "C4") + (unit 1) + ) + (path "/214bfc41-24f4-4af9-b8d5-f53b552105c4/a97a1c5a-89b8-4965-a918-3f182150b9ea/2cd6dc77-f114-44b1-9704-d60d213c1d42" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 B Key Templates/M.2 B Key 30110/meta/info.html b/Templates/M.2 B Key Templates/M.2 B Key 30110/meta/info.html new file mode 100644 index 0000000..777a435 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 30110/meta/info.html @@ -0,0 +1,3 @@ +M.2 B Key 30110 +

This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3030/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 3030/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3030/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3030/M.2 B Key 3030.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 3030/M.2 B Key 3030.kicad_pcb new file mode 100644 index 0000000..bae6275 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3030/M.2 B Key 3030.kicad_pcb @@ -0,0 +1,2961 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B key/PET0N") + (net 2 "/M.2 B key/PET0P") + (net 3 "/M.2 B key/PET1P") + (net 4 "/M.2 B key/PET1N") + (net 5 "GND") + (net 6 "/CONFIG_3") + (net 7 "+3.3V") + (net 8 "/FULL_CARD_PWR_OFF#") + (net 9 "/USB_D+") + (net 10 "/W_DISABLE1#") + (net 11 "/USB_D-") + (net 12 "/GPIO_9{slash}LED#1") + (net 13 "/GPIO_5") + (net 14 "/CONFIG_0") + (net 15 "/GPIO_6") + (net 16 "/DPR") + (net 17 "/GPIO_7") + (net 18 "/GPIO_11") + (net 19 "/GPIO_10") + (net 20 "/GPIO_8") + (net 21 "/UIM-RESET") + (net 22 "/UIM-CLK") + (net 23 "/UIM-DATA") + (net 24 "/PER1-") + (net 25 "/UIM-PWR") + (net 26 "/PER1+") + (net 27 "/DEVSLP") + (net 28 "/GPIO_0") + (net 29 "/GPIO_1") + (net 30 "/GPIO_2") + (net 31 "/GPIO_3") + (net 32 "/PER0-") + (net 33 "/GPIO_4") + (net 34 "/PER0+") + (net 35 "/PERST#") + (net 36 "/CLKREQ#") + (net 37 "/REFCLK-") + (net 38 "/PEWAKE#") + (net 39 "/REFCLK+") + (net 40 "unconnected-(J1-NC-Pad56)") + (net 41 "unconnected-(J1-NC-Pad58)") + (net 42 "/ANTCTL0") + (net 43 "unconnected-(J1-COEX3-Pad60)") + (net 44 "/ANTCTL1") + (net 45 "unconnected-(J1-COEX2-Pad62)") + (net 46 "/ANTCTL2") + (net 47 "unconnected-(J1-COEX1-Pad64)") + (net 48 "/ANTCTL3") + (net 49 "/SIM_DETECT") + (net 50 "/RESET#") + (net 51 "/SUSCLK") + (net 52 "/CONFIG_1") + (net 53 "/CONFIG_2") + (net 54 "/PET0+") + (net 55 "/PET1+") + (net 56 "/PET1-") + (net 57 "/PET0-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "0d079970-0806-4cc7-a7ad-ec83bb19f056") + (at 108.36 153.24 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C1" + (at 0 0.73 270) + (layer "F.SilkS") + (uuid "32829e15-e0eb-496a-b416-6586949d9cb3") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid 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This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3042/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 3042/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3042/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3042/M.2 B key 3042.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 3042/M.2 B key 3042.kicad_pcb new file mode 100644 index 0000000..cf9aae2 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3042/M.2 B key 3042.kicad_pcb @@ -0,0 +1,3001 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B key/PET1N") + (net 2 "/M.2 B key/PET1P") + (net 3 "/M.2 B key/PET0P") + (net 4 "/M.2 B key/PET0N") + (net 5 "/PET1-") + (net 6 "/PET0-") + (net 7 "/CONFIG_3") + (net 8 "+3.3V") + (net 9 "GND") + (net 10 "/FULL_CARD_PWR_OFF#") + (net 11 "/USB_D+") + (net 12 "/W_DISABLE1#") + (net 13 "/USB_D-") + (net 14 "/GPIO_9{slash}LED#1") + (net 15 "/GPIO_5") + (net 16 "/CONFIG_0") + (net 17 "/GPIO_6") + (net 18 "/DPR") + (net 19 "/GPIO_7") + (net 20 "/GPIO_11") + (net 21 "/GPIO_10") + (net 22 "/GPIO_8") + (net 23 "/UIM-RESET") + (net 24 "/UIM-CLK") + (net 25 "/UIM-DATA") + (net 26 "/PER1-") + (net 27 "/UIM-PWR") + (net 28 "/PER1+") + (net 29 "/DEVSLP") + (net 30 "/GPIO_0") + (net 31 "/GPIO_1") + (net 32 "/GPIO_2") + (net 33 "/GPIO_3") + (net 34 "/PER0-") + (net 35 "/GPIO_4") + (net 36 "/PER0+") + (net 37 "/PERST#") + (net 38 "/CLKREQ#") + (net 39 "/REFCLK-") + (net 40 "/PEWAKE#") + (net 41 "/REFCLK+") + (net 42 "unconnected-(J1-NC-Pad56)") + (net 43 "unconnected-(J1-NC-Pad58)") + (net 44 "/ANTCTL0") + (net 45 "unconnected-(J1-COEX3-Pad60)") + (net 46 "/ANTCTL1") + (net 47 "unconnected-(J1-COEX2-Pad62)") + (net 48 "/ANTCTL2") + (net 49 "unconnected-(J1-COEX1-Pad64)") + (net 50 "/ANTCTL3") + (net 51 "/SIM_DETECT") + (net 52 "/RESET#") + (net 53 "/SUSCLK") + (net 54 "/CONFIG_1") + (net 55 "/CONFIG_2") + (net 56 "/PET0+") + (net 57 "/PET1+") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "0c643610-2eb1-4c9f-a494-16a6ec64b0b6") + (at 108.16 154.72 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C2" + (at 0 -0.73 90) + (layer "F.SilkS") + (uuid "eb1b7d02-7678-410e-8726-4eef9ea83be5") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "b7e5cbae-a64e-463c-8778-0131878eb128") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "bd87f155-c4bc-4712-980d-61ef33f1c6c1") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide 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This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3060/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 3060/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3060/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3060/M.2 B Key 3060.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 3060/M.2 B Key 3060.kicad_pcb new file mode 100644 index 0000000..9080e9b --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3060/M.2 B Key 3060.kicad_pcb @@ -0,0 +1,3001 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B key/PET1N") + (net 2 "/M.2 B key/PET1P") + (net 3 "/M.2 B key/PET0P") + (net 4 "/M.2 B key/PET0N") + (net 5 "/PET1-") + (net 6 "/PET0-") + (net 7 "/CONFIG_3") + (net 8 "+3.3V") + (net 9 "GND") + (net 10 "/FULL_CARD_PWR_OFF#") + (net 11 "/USB_D+") + (net 12 "/W_DISABLE1#") + (net 13 "/USB_D-") + (net 14 "/GPIO_9{slash}LED#1") + (net 15 "/GPIO_5") + (net 16 "/CONFIG_0") + (net 17 "/GPIO_6") + (net 18 "/DPR") + (net 19 "/GPIO_7") + (net 20 "/GPIO_11") + (net 21 "/GPIO_10") + (net 22 "/GPIO_8") + (net 23 "/UIM-RESET") + (net 24 "/UIM-CLK") + (net 25 "/UIM-DATA") + (net 26 "/PER1-") + (net 27 "/UIM-PWR") + (net 28 "/PER1+") + (net 29 "/DEVSLP") + (net 30 "/GPIO_0") + (net 31 "/GPIO_1") + (net 32 "/GPIO_2") + (net 33 "/GPIO_3") + (net 34 "/PER0-") + (net 35 "/GPIO_4") + (net 36 "/PER0+") + (net 37 "/PERST#") + (net 38 "/CLKREQ#") + (net 39 "/REFCLK-") + (net 40 "/PEWAKE#") + (net 41 "/REFCLK+") + (net 42 "unconnected-(J1-NC-Pad56)") + (net 43 "unconnected-(J1-NC-Pad58)") + (net 44 "/ANTCTL0") + (net 45 "unconnected-(J1-COEX3-Pad60)") + (net 46 "/ANTCTL1") + (net 47 "unconnected-(J1-COEX2-Pad62)") + (net 48 "/ANTCTL2") + (net 49 "unconnected-(J1-COEX1-Pad64)") + (net 50 "/ANTCTL3") + (net 51 "/SIM_DETECT") + (net 52 "/RESET#") + (net 53 "/SUSCLK") + (net 54 "/CONFIG_1") + (net 55 "/CONFIG_2") + (net 56 "/PET0+") + (net 57 "/PET1+") + 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This is a KiCad 9 template + diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3080/.gitignore b/Templates/M.2 B Key Templates/M.2 B Key 3080/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3080/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B Key Templates/M.2 B Key 3080/M.2 B Key 3080.kicad_pcb b/Templates/M.2 B Key Templates/M.2 B Key 3080/M.2 B Key 3080.kicad_pcb new file mode 100644 index 0000000..63edd08 --- /dev/null +++ b/Templates/M.2 B Key Templates/M.2 B Key 3080/M.2 B Key 3080.kicad_pcb @@ -0,0 +1,2999 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B key/PET1N") + (net 2 "/M.2 B key/PET1P") + (net 3 "/M.2 B key/PET0P") + (net 4 "/M.2 B key/PET0N") + (net 5 "/PET1-") + (net 6 "/PET0-") + (net 7 "/CONFIG_3") + (net 8 "+3.3V") + (net 9 "GND") + (net 10 "/FULL_CARD_PWR_OFF#") + (net 11 "/USB_D+") + (net 12 "/W_DISABLE1#") + (net 13 "/USB_D-") + (net 14 "/GPIO_9{slash}LED#1") + (net 15 "/GPIO_5") + (net 16 "/CONFIG_0") + (net 17 "/GPIO_6") + (net 18 "/DPR") + (net 19 "/GPIO_7") + (net 20 "/GPIO_11") + (net 21 "/GPIO_10") + (net 22 "/GPIO_8") + (net 23 "/UIM-RESET") + (net 24 "/UIM-CLK") + (net 25 "/UIM-DATA") + (net 26 "/PER1-") + (net 27 "/UIM-PWR") + (net 28 "/PER1+") + (net 29 "/DEVSLP") + (net 30 "/GPIO_0") + (net 31 "/GPIO_1") + (net 32 "/GPIO_2") + (net 33 "/GPIO_3") + (net 34 "/PER0-") + (net 35 "/GPIO_4") + (net 36 "/PER0+") + (net 37 "/PERST#") + (net 38 "/CLKREQ#") + (net 39 "/REFCLK-") + (net 40 "/PEWAKE#") + (net 41 "/REFCLK+") + (net 42 "unconnected-(J1-NC-Pad56)") + (net 43 "unconnected-(J1-NC-Pad58)") + (net 44 "/ANTCTL0") + (net 45 "unconnected-(J1-COEX3-Pad60)") + (net 46 "/ANTCTL1") + (net 47 "unconnected-(J1-COEX2-Pad62)") + (net 48 "/ANTCTL2") + (net 49 "unconnected-(J1-COEX1-Pad64)") + (net 50 "/ANTCTL3") + (net 51 "/SIM_DETECT") + (net 52 "/RESET#") + (net 53 "/SUSCLK") + (net 54 "/CONFIG_1") + (net 55 "/CONFIG_2") + (net 56 "/PET0+") + (net 57 "/PET1+") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "109443c9-78ab-4dbd-8793-15e217902c64") + (at 107.66 150.41 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C2" + (at 0 -0.73 90) + (layer "F.SilkS") + (uuid "2cf9afae-af87-4549-ad47-b9e22834034f") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "0b799439-0415-4862-bae0-4be726fe8945") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "7cda57e6-9847-4e4a-8f89-ab171517cbd4") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide 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(size 0.46 0.4) + (layers "F.Cu" "F.Mask") + (roundrect_rratio 0.25) + (net 3 "/M.2 B key/PET0P") + (pintype "passive") + (uuid "ab15bd41-b302-4c16-9fcd-ebec28f8b480") + ) + (pad "2" smd roundrect + (at 0.32 0 90) + (size 0.46 0.4) + (layers "F.Cu" "F.Mask") + (roundrect_rratio 0.25) + (net 56 "/PET0+") + (pintype "passive") + (uuid "bfe724dd-8c1c-467e-9fe4-e1a8e42c9706") + ) + (embedded_fonts no) + (model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0201_0603Metric.wrl" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "2f4d48e4-44c3-477b-ac3c-d8be59fb59e1") + (at 111.36 150.41 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C3" + (at 0 0.75 90) + (layer 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This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/M.2 B+M Key 22110.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/M.2 B+M Key 22110.kicad_pcb new file mode 100644 index 0000000..690495d --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/M.2 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0000000..a9d256e --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/M.2 B+M key.kicad_sch @@ -0,0 +1,3714 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "47267e8c-a37a-4dc6-a561-99ca5ccc9577") + (paper "A4") + (lib_symbols + (symbol "Mechanical:MountingHole_Pad" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 1.016) + (hide yes) + ) + (exclude_from_sim no) + (in_bom no) + (on_board yes) + (property "Reference" "H" + (at 0 6.35 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "MountingHole_Pad" + (at 0 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Mounting Hole with connection" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + 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yes) + ) + ) + (pin "2" + (uuid "80430cb9-b4b4-48a1-9795-86a7124d5506") + ) + (pin "1" + (uuid "5edc64c5-9f2e-445b-a6b8-138a1f7edfaa") + ) + (instances + (project "M.2 B+M Key 22110" + (path "/a237e335-d00c-4750-a072-6582cd3125fb/2543d8f5-6a71-4624-8bbc-11852c8372b1/49bba5f2-c387-43d5-bfb3-4f108d45a837" + (reference "C2") + (unit 1) + ) + (path "/a237e335-d00c-4750-a072-6582cd3125fb/2543d8f5-6a71-4624-8bbc-11852c8372b1/b5a0e78d-bc67-4b7e-8137-4f88148172fd" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/meta/info.html b/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/meta/info.html new file mode 100644 index 0000000..1658ab8 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 22110/meta/info.html @@ -0,0 +1,3 @@ +M.2 B+M Key 22110 +

This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/M.2 B+M Key 2230.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/M.2 B+M Key 2230.kicad_pcb new file mode 100644 index 0000000..5967aeb --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/M.2 B+M Key 2230.kicad_pcb @@ -0,0 +1,2988 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" 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kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C1" + (at 0 0.73 90) + (layer "F.SilkS") + (uuid "3d7a8b86-59e6-4cb0-8240-28bf06e0ae1a") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "ed2bde59-27d8-4e48-845d-d5c0570f82fd") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "bd4e5528-703f-40fc-8f5e-f222e643ae4b") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "fe2b858d-653a-46ff-a3e6-3b45c923fc33") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property ki_fp_filters "C_*") + (path "/83dcd142-0f4d-4852-9a7e-5099cdae9f20/49bba5f2-c387-43d5-bfb3-4f108d45a837/2016188b-af52-4362-a831-61bc1de993d6") + (sheetname "/M.2 B+M Key/PCIe Couple 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(property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Mounting Hole with connection" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_keywords" "mounting hole" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "ki_fp_filters" "MountingHole*Pad*" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (symbol "MountingHole_Pad_0_1" + (circle + (center 0 1.27) + (radius 1.27) + (stroke + (width 1.27) + (type default) + ) + (fill + (type none) + ) + ) + ) + (symbol "MountingHole_Pad_1_1" + (pin input line + (at 0 -2.54 90) + (length 2.54) + (name "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (number "1" + (effects + (font + (size 1.27 1.27) + ) + ) + ) + ) + ) + (embedded_fonts no) + ) + (symbol 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) + (pin "2" + (uuid "c35fad9a-89c6-4e61-8364-043394cbdf9c") + ) + (pin "1" + (uuid "b7ce36f1-5939-4685-b59e-3e9dc3714d7a") + ) + (instances + (project "M.2 B+M Key 2230" + (path "/7eaf6b55-0f11-4912-bb58-f9dbc0625108/83dcd142-0f4d-4852-9a7e-5099cdae9f20/49bba5f2-c387-43d5-bfb3-4f108d45a837" + (reference "C2") + (unit 1) + ) + (path "/7eaf6b55-0f11-4912-bb58-f9dbc0625108/83dcd142-0f4d-4852-9a7e-5099cdae9f20/b5a0e78d-bc67-4b7e-8137-4f88148172fd" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/meta/info.html b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/meta/info.html new file mode 100644 index 0000000..da38a92 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2230/meta/info.html @@ -0,0 +1,3 @@ +M.2 B+M Key 2230 +

This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/M.2 B+M Key 2242.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/M.2 B+M Key 2242.kicad_pcb new file mode 100644 index 0000000..bcc3a0b --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/M.2 B+M Key 2242.kicad_pcb @@ -0,0 +1,2965 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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0000000..f8da3f3 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/M.2 B+M key.kicad_sch @@ -0,0 +1,3714 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "47267e8c-a37a-4dc6-a561-99ca5ccc9577") + (paper "A4") + (lib_symbols + (symbol "Mechanical:MountingHole_Pad" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 1.016) + (hide yes) + ) + (exclude_from_sim no) + (in_bom no) + (on_board yes) + (property "Reference" "H" + (at 0 6.35 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "MountingHole_Pad" + (at 0 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Mounting Hole with connection" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + 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+ (path "/253eff07-53f4-4bee-bab0-3832dd5598c8/94c20632-289a-4bcd-acaf-b86d2878e857/b5a0e78d-bc67-4b7e-8137-4f88148172fd" + (reference "C3") + (unit 1) + ) + ) + ) + ) + (symbol + (lib_id "Device:C") + (at 143.51 100.33 0) + (unit 1) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (dnp no) + (fields_autoplaced yes) + (uuid "a9ef9354-d3cb-4e55-896f-ff5d6835b2b3") + (property "Reference" "C4" + (at 147.32 99.0599 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Value" "220nF" + (at 147.32 101.5999 0) + (effects + (font + (size 1.27 1.27) + ) + (justify left) + ) + ) + (property "Footprint" "Capacitor_SMD:C_0201_0603Metric" + (at 144.4752 104.14 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "563466d0-7e99-4388-b06a-311e6006e3d5") + ) + (pin "1" + (uuid "6260ba52-6ecf-488e-94dd-10d95740eca3") + ) + (instances + (project "M.2 B+M Key 2242" + (path "/253eff07-53f4-4bee-bab0-3832dd5598c8/94c20632-289a-4bcd-acaf-b86d2878e857/49bba5f2-c387-43d5-bfb3-4f108d45a837" + (reference "C2") + (unit 1) + ) + (path "/253eff07-53f4-4bee-bab0-3832dd5598c8/94c20632-289a-4bcd-acaf-b86d2878e857/b5a0e78d-bc67-4b7e-8137-4f88148172fd" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/meta/info.html b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/meta/info.html new file mode 100644 index 0000000..a078839 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2242/meta/info.html @@ -0,0 +1,3 @@ +M.2 B+M Key 2242 +

This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/M.2 B+M Key 2260.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/M.2 B+M Key 2260.kicad_pcb new file mode 100644 index 0000000..3a8ec07 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/M.2 B+M Key 2260.kicad_pcb @@ -0,0 +1,2964 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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"/GPIO_9{slash}LED#1") + (net 16 "/GPIO_5") + (net 17 "/CONFIG_0") + (net 18 "/GPIO_6") + (net 19 "/DPR") + (net 20 "/GPIO_7") + (net 21 "/GPIO_11") + (net 22 "/GPIO_10") + (net 23 "/GPIO_8") + (net 24 "/UIM-RESET") + (net 25 "/UIM-CLK") + (net 26 "/UIM-DATA") + (net 27 "/PER1-") + (net 28 "/UIM-PWR") + (net 29 "/PER1+") + (net 30 "/DEVSLP") + (net 31 "/GPIO_0") + (net 32 "/GPIO_1") + (net 33 "/GPIO_2") + (net 34 "/GPIO_3") + (net 35 "/PER0-") + (net 36 "/GPIO_4") + (net 37 "/PER0+") + (net 38 "/PERST#") + (net 39 "/CLKREQ#") + (net 40 "/REFCLK-") + (net 41 "/PEWAKE#") + (net 42 "/REFCLK+") + (net 43 "unconnected-(J1-NC-Pad56)") + (net 44 "unconnected-(J1-NC-Pad58)") + (net 45 "/RESET#") + (net 46 "/SUSCLK") + (net 47 "/CONFIG_1") + (net 48 "/CONFIG_2") + (net 49 "/PET1-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "02ee22ba-3b7a-481c-b0c4-76074c840bad") + (at 107.66 154.32 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, 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a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/M.2 B+M key.kicad_sch b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/M.2 B+M key.kicad_sch new file mode 100644 index 0000000..cace90a --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2260/M.2 B+M key.kicad_sch @@ -0,0 +1,3714 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "47267e8c-a37a-4dc6-a561-99ca5ccc9577") + (paper "A4") + (lib_symbols + (symbol "Mechanical:MountingHole_Pad" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 1.016) + (hide yes) + ) + (exclude_from_sim no) + (in_bom no) + (on_board yes) + (property "Reference" "H" + (at 0 6.35 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "MountingHole_Pad" + (at 0 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 0 0 0) + (effects + (font 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This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2280/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2280/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2280/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 2280/M.2 B+M Key 2280.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2280/M.2 B+M Key 2280.kicad_pcb new file mode 100644 index 0000000..9a4a3aa --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 2280/M.2 B+M Key 2280.kicad_pcb @@ -0,0 +1,2964 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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"/GPIO_9{slash}LED#1") + (net 16 "/GPIO_5") + (net 17 "/CONFIG_0") + (net 18 "/GPIO_6") + (net 19 "/DPR") + (net 20 "/GPIO_7") + (net 21 "/GPIO_11") + (net 22 "/GPIO_10") + (net 23 "/GPIO_8") + (net 24 "/UIM-RESET") + (net 25 "/UIM-CLK") + (net 26 "/UIM-DATA") + (net 27 "/PER1-") + (net 28 "/UIM-PWR") + (net 29 "/PER1+") + (net 30 "/DEVSLP") + (net 31 "/GPIO_0") + (net 32 "/GPIO_1") + (net 33 "/GPIO_2") + (net 34 "/GPIO_3") + (net 35 "/PER0-") + (net 36 "/GPIO_4") + (net 37 "/PER0+") + (net 38 "/PERST#") + (net 39 "/CLKREQ#") + (net 40 "/REFCLK-") + (net 41 "/PEWAKE#") + (net 42 "/REFCLK+") + (net 43 "unconnected-(J1-NC-Pad56)") + (net 44 "unconnected-(J1-NC-Pad58)") + (net 45 "/RESET#") + (net 46 "/SUSCLK") + (net 47 "/CONFIG_1") + (net 48 "/CONFIG_2") + (net 49 "/PET1-") + (footprint "Athena KiCAd library:M.2 Mounting Pad" + (layer "F.Cu") + (uuid "1aa035ee-78d3-4fc1-979a-60a8780e8d62") + (at 108.01 78.84) + (property "Reference" "H1" + (at 0 -4.82 0) + (unlocked yes) + (layer "F.Fab") + (uuid "071a7265-1a63-4f6b-a0cf-1f2845873967") + (effects + (font + (size 1 1) + (thickness 0.1) + ) + ) + ) + (property "Value" "MountingHole_Pad" + (at 0 1 0) + (unlocked yes) + (layer "F.Fab") + (uuid "46fe06ec-3d3b-44a9-bd9e-56056dd96345") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "688528e3-0ae4-43ff-ab1d-ea3558a730dd") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Description" "Mounting Hole with connection" + (at 0 0 0) + (unlocked yes) + (layer "F.Fab") + (hide yes) + (uuid "89674fbe-8a88-4b08-bd45-717009a1cb8d") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (attr smd exclude_from_bom) + (fp_text user "${REFERENCE}" + (at 0 2.5 0) + (unlocked yes) + (layer "F.Fab") + (uuid "c6a9cb81-af72-48d0-b98f-26712d25fc78") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (pad "1" thru_hole circle + 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This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 30110/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 30110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 30110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 30110/M.2 B+M Key 30110.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 30110/M.2 B+M Key 30110.kicad_pcb new file mode 100644 index 0000000..1af32fc --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 30110/M.2 B+M Key 30110.kicad_pcb @@ -0,0 +1,2988 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 B+M Key/PET0N") + (net 2 "/M.2 B+M Key/PET1N") + (net 3 "/M.2 B+M Key/PET1P") + (net 4 "/M.2 B+M Key/PET0P") + (net 5 "/PET0+") + (net 6 "GND") + (net 7 "/PET1-") + (net 8 "/PET1+") + (net 9 "/CONFIG_3") + (net 10 "+3.3V") + (net 11 "/FULL_CARD_PWR_OFF#") + (net 12 "/USB_D+") + (net 13 "/W_DISABLE1#") + (net 14 "/USB_D-") + (net 15 "/GPIO_9{slash}LED#1") + (net 16 "/GPIO_5") + (net 17 "/CONFIG_0") + (net 18 "/GPIO_6") + (net 19 "/DPR") + (net 20 "/GPIO_7") + (net 21 "/GPIO_11") + (net 22 "/GPIO_10") + (net 23 "/GPIO_8") + (net 24 "/UIM-RESET") + (net 25 "/UIM-CLK") + (net 26 "/UIM-DATA") + (net 27 "/PER1-") + (net 28 "/UIM-PWR") + (net 29 "/PER1+") + (net 30 "/DEVSLP") + (net 31 "/GPIO_0") + (net 32 "/GPIO_1") + (net 33 "/GPIO_2") + (net 34 "/GPIO_3") + (net 35 "/PER0-") + (net 36 "/GPIO_4") + (net 37 "/PER0+") + (net 38 "/PERST#") + (net 39 "/CLKREQ#") + (net 40 "/REFCLK-") + (net 41 "/PEWAKE#") + (net 42 "/REFCLK+") + (net 43 "unconnected-(J1-NC-Pad56)") + (net 44 "unconnected-(J1-NC-Pad58)") + (net 45 "/RESET#") + (net 46 "/SUSCLK") + (net 47 "/CONFIG_1") + (net 48 "/CONFIG_2") + (net 49 "/PET0-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "4a553d2a-88b4-4f75-b08f-a133d923b70e") + (at 110.66 154.57 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C4" + (at 0 -0.71 90) + (layer "F.SilkS") + (uuid "fbddb0c2-5fb7-4611-8f9d-0efd4c8361a9") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "6c435924-427b-4a65-a89a-49096df77ddb") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "d116ca1e-0469-492d-b0b3-de29ca277afe") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "da02382e-d576-4553-b141-9ebf54db5205") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr smd) + (fp_line + (start 0.7 -0.35) + (end 0.7 0.35) + (stroke + (width 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This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3030/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3030/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3030/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3030/M.2 B+M Key 3030.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3030/M.2 B+M Key 3030.kicad_pcb new file mode 100644 index 0000000..88ee5ec --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3030/M.2 B+M Key 3030.kicad_pcb @@ -0,0 +1,2988 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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"/GPIO_9{slash}LED#1") + (net 16 "/GPIO_5") + (net 17 "/CONFIG_0") + (net 18 "/GPIO_6") + (net 19 "/DPR") + (net 20 "/GPIO_7") + (net 21 "/GPIO_11") + (net 22 "/GPIO_10") + (net 23 "/GPIO_8") + (net 24 "/UIM-RESET") + (net 25 "/UIM-CLK") + (net 26 "/UIM-DATA") + (net 27 "/PER1-") + (net 28 "/UIM-PWR") + (net 29 "/PER1+") + (net 30 "/DEVSLP") + (net 31 "/GPIO_0") + (net 32 "/GPIO_1") + (net 33 "/GPIO_2") + (net 34 "/GPIO_3") + (net 35 "/PER0-") + (net 36 "/GPIO_4") + (net 37 "/PER0+") + (net 38 "/PERST#") + (net 39 "/CLKREQ#") + (net 40 "/REFCLK-") + (net 41 "/PEWAKE#") + (net 42 "/REFCLK+") + (net 43 "unconnected-(J1-NC-Pad56)") + (net 44 "unconnected-(J1-NC-Pad58)") + (net 45 "/RESET#") + (net 46 "/SUSCLK") + (net 47 "/CONFIG_1") + (net 48 "/CONFIG_2") + (net 49 "/PET1-") + (footprint "Athena KiCAd library:M.2 Mounting Pad" + (layer "F.Cu") + (uuid "1f75f327-4ad0-49d6-88c3-103bec91ef7d") + (at 109.01 130.09) + (property "Reference" "H1" + (at 0 -4.82 0) + (unlocked yes) + (layer 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This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3042/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3042/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3042/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3042/M.2 B+M Key 3042.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3042/M.2 B+M Key 3042.kicad_pcb new file mode 100644 index 0000000..b1e5d7a --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3042/M.2 B+M Key 3042.kicad_pcb @@ -0,0 +1,2988 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" 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This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3060/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3060/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3060/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3060/M.2 B+M Key 3060.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3060/M.2 B+M Key 3060.kicad_pcb new file mode 100644 index 0000000..e1f6c04 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3060/M.2 B+M Key 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0000000..5f8193a --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3060/M.2 B+M key.kicad_sch @@ -0,0 +1,3714 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "47267e8c-a37a-4dc6-a561-99ca5ccc9577") + (paper "A4") + (lib_symbols + (symbol "Mechanical:MountingHole_Pad" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 1.016) + (hide yes) + ) + (exclude_from_sim no) + (in_bom no) + (on_board yes) + (property "Reference" "H" + (at 0 6.35 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "MountingHole_Pad" + (at 0 4.445 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Datasheet" "~" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Mounting Hole with connection" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + 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This is a KiCad 9 template + diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/.gitignore b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/M.2 B+M Key 3080.kicad_pcb b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/M.2 B+M Key 3080.kicad_pcb new file mode 100644 index 0000000..22e3d36 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/M.2 B+M Key 3080.kicad_pcb @@ -0,0 +1,2988 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 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yes) + ) + ) + (pin "2" + (uuid "6fe97dc0-19fc-48a3-9809-607c5b983378") + ) + (pin "1" + (uuid "2796894e-6b08-4cf9-9752-b253378d3be3") + ) + (instances + (project "M.2 B+M Key 3080" + (path "/eeff3bcf-e91e-4d19-86e6-b188e47dcd7a/a4265a8c-dd19-4998-b67a-81893b868cd5/49bba5f2-c387-43d5-bfb3-4f108d45a837" + (reference "C2") + (unit 1) + ) + (path "/eeff3bcf-e91e-4d19-86e6-b188e47dcd7a/a4265a8c-dd19-4998-b67a-81893b868cd5/b5a0e78d-bc67-4b7e-8137-4f88148172fd" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/meta/info.html b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/meta/info.html new file mode 100644 index 0000000..2e88d66 --- /dev/null +++ b/Templates/M.2 B+M Key Templates/M.2 B+M Key 3080/meta/info.html @@ -0,0 +1,3 @@ +M.2 B+M Key 3080 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 22110/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 22110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 22110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 22110/M.2 E Key 22110.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 22110/M.2 E Key 22110.kicad_pcb new file mode 100644 index 0000000..2abfb5a --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 22110/M.2 E Key 22110.kicad_pcb @@ -0,0 +1,3021 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref 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(net 18 "/I2S_SD_OUT") + (net 19 "/SDIO_DATA0") + (net 20 "/I2S_SD_IN") + (net 21 "/SDIO_DATA3") + (net 22 "/LED#2") + (net 23 "/SDIO_DATA2") + (net 24 "/SDIO_DATA1") + (net 25 "/UART_WAKE#") + (net 26 "/SDIO__WAKE#") + (net 27 "/UART_TXD") + (net 28 "/SDIO_RESET#") + (net 29 "/UART_RXD") + (net 30 "/UARD_RTS") + (net 31 "/PER0-") + (net 32 "/UART_CTS") + (net 33 "/PER0+") + (net 34 "unconnected-(J1-Vender_Defined-Pad38)") + (net 35 "unconnected-(J1-Vender_Defined-Pad40)") + (net 36 "unconnected-(J1-Vender_Defined-Pad42)") + (net 37 "unconnected-(J1-COEX3-Pad44)") + (net 38 "unconnected-(J1-COEX2-Pad46)") + (net 39 "/REFCLK0+") + (net 40 "unconnected-(J1-COEX1-Pad48)") + (net 41 "/REFCLK0-") + (net 42 "/SUSCLK") + (net 43 "/PERST0#") + (net 44 "/CLKREQ0#") + (net 45 "/W_DISABLE2#") + (net 46 "/PEWAKE#") + (net 47 "/W_DISABLE1#") + (net 48 "/I2C_DATA") + (net 49 "/PER1+") + (net 50 "/I2C_CLK") + (net 51 "/PER1-") + (net 52 "/ALERT#") + (net 53 "unconnected-(J1-RESERVED-Pad64)") + (net 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "1e22bb1d-f2fa-45d4-810d-ab91732f939d") + ) + (pin "1" + (uuid "09bb1bd0-1ddf-4974-8e56-cba05301cedb") + ) + (instances + (project "M.2 E Key 22110" + (path "/aaf036dc-255d-4ccb-b6c3-e9d3d1ee6709/7b30a98c-45c5-49d3-9395-539ac2342c37/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/aaf036dc-255d-4ccb-b6c3-e9d3d1ee6709/7b30a98c-45c5-49d3-9395-539ac2342c37/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 22110/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 22110/meta/info.html new file mode 100644 index 0000000..570e0cd --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 22110/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 22110 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2230/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 2230/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2230/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2230/M.2 E Key 2230.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 2230/M.2 E Key 2230.kicad_pcb new file mode 100644 index 0000000..6cbbdac --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2230/M.2 E Key 2230.kicad_pcb @@ -0,0 +1,3044 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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"/I2C_DATA") + (net 17 "/USB_D-") + (net 18 "/PEWAKE#") + (net 19 "/SDIO__WAKE#") + (net 20 "/ALERT#") + (net 21 "/W_DISABLE2#") + (net 22 "unconnected-(J1-COEX2-Pad46)") + (net 23 "/PER1+") + (net 24 "+3.3V") + (net 25 "unconnected-(J1-RESERVED-Pad64)") + (net 26 "/SDIO_DATA3") + (net 27 "/SDIO_DATA1") + (net 28 "/LED#2") + (net 29 "/SDIO_RESET#") + (net 30 "/REFCLK0-") + (net 31 "/CLKREQ0#") + (net 32 "unconnected-(J1-COEX3-Pad44)") + (net 33 "/REFCLK1-") + (net 34 "/UART_RXD") + (net 35 "/USB_D+") + (net 36 "/SDIO_DATA2") + (net 37 "/PER1-") + (net 38 "unconnected-(J1-Vender_Defined-Pad42)") + (net 39 "unconnected-(J1-COEX1-Pad48)") + (net 40 "/LED#1") + (net 41 "/I2C_CLK") + (net 42 "/UARD_RTS") + (net 43 "/SUSCLK") + (net 44 "/I2S_SCK") + (net 45 "/SDIO_CLK") + (net 46 "/PER0-") + (net 47 "/UART_CTS") + (net 48 "/CLKREQ1#") + (net 49 "/SDIO_CMD") + (net 50 "/SDIO_DATA0") + (net 51 "/I2S_SD_OUT") + (net 52 "/PERST0#") + (net 53 "unconnected-(J1-Vender_Defined-Pad40)") + (net 54 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) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "37fc8c9d-488c-4f33-a2e1-9c31f8062a12") + ) + (pin "1" + (uuid "2ebb334d-38f0-4e33-b909-0e77129ac6dc") + ) + (instances + (project "M.2 E Key 2230" + (path "/c75f4d31-c8a9-4fca-a333-63a789de630e/1240ca36-3abd-446f-9cff-2fc07fb9ce0d/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/c75f4d31-c8a9-4fca-a333-63a789de630e/1240ca36-3abd-446f-9cff-2fc07fb9ce0d/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2230/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 2230/meta/info.html new file mode 100644 index 0000000..63d4c0e --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2230/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 2230 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2242/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 2242/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2242/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2242/M.2 E Key 2242.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 2242/M.2 E Key 2242.kicad_pcb new file mode 100644 index 0000000..d61b5ca --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2242/M.2 E Key 2242.kicad_pcb @@ -0,0 +1,3021 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 E Key/PET1P") + (net 2 "/M.2 E Key/PET1N") + (net 3 "/M.2 E Key/PET0P") + (net 4 "/M.2 E Key/PET0N") + (net 5 "GND") + (net 6 "/PET0-") + (net 7 "/PET1-") + (net 8 "/PET1+") + (net 9 "/PET0+") + (net 10 "+3.3V") + (net 11 "/USB_D+") + (net 12 "/USB_D-") + (net 13 "/LED#1") + (net 14 "/I2S_SCK") + (net 15 "/SDIO_CLK") + (net 16 "/I2S_WS") + (net 17 "/SDIO_CMD") + (net 18 "/I2S_SD_OUT") + (net 19 "/SDIO_DATA0") + (net 20 "/I2S_SD_IN") + (net 21 "/SDIO_DATA3") + (net 22 "/LED#2") + (net 23 "/SDIO_DATA2") + (net 24 "/SDIO_DATA1") + (net 25 "/UART_WAKE#") + (net 26 "/SDIO__WAKE#") + (net 27 "/UART_TXD") + (net 28 "/SDIO_RESET#") + (net 29 "/UART_RXD") + (net 30 "/UARD_RTS") + (net 31 "/PER0-") + (net 32 "/UART_CTS") + (net 33 "/PER0+") + (net 34 "unconnected-(J1-Vender_Defined-Pad38)") + (net 35 "unconnected-(J1-Vender_Defined-Pad40)") + (net 36 "unconnected-(J1-Vender_Defined-Pad42)") + (net 37 "unconnected-(J1-COEX3-Pad44)") + (net 38 "unconnected-(J1-COEX2-Pad46)") + (net 39 "/REFCLK0+") + (net 40 "unconnected-(J1-COEX1-Pad48)") + (net 41 "/REFCLK0-") + (net 42 "/SUSCLK") + (net 43 "/PERST0#") + (net 44 "/CLKREQ0#") + (net 45 "/W_DISABLE2#") + (net 46 "/PEWAKE#") + (net 47 "/W_DISABLE1#") + (net 48 "/I2C_DATA") + (net 49 "/PER1+") + (net 50 "/I2C_CLK") + (net 51 "/PER1-") + (net 52 "/ALERT#") + (net 53 "unconnected-(J1-RESERVED-Pad64)") + (net 54 "/PERST1#") + (net 55 "/CLKREQ1#") + (net 56 "/PEWAKE1#") + (net 57 "/REFCLK1+") + (net 58 "/REFCLK1-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "14d0c729-f8f1-4695-bfc1-62b4462de8ed") + (at 106.11 153.93 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C4" + (at 0 1.14 90) + (layer "F.SilkS") + (uuid "cbfb49f1-d7bb-4d45-a3ad-8f63fa7e06f6") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "2e67f59a-50df-4cd8-95f1-ae393808c132") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "6f30b98f-881c-40f8-b6e3-011abf2e6b4e") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "a258de6c-497a-427f-aef2-38162e3a4743") + ) + (pin "1" + (uuid "3b462b0e-1e90-4c4f-ad1e-4ec92eb6c445") + ) + (instances + (project "M.2 E Key 2242" + (path "/2eb16b5c-1f76-4937-a79c-88998ef8d219/3138746b-896d-4258-adca-d115110f81ed/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/2eb16b5c-1f76-4937-a79c-88998ef8d219/3138746b-896d-4258-adca-d115110f81ed/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2242/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 2242/meta/info.html new file mode 100644 index 0000000..f2e3ae9 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2242/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 2242 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2260/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 2260/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2260/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2260/M.2 E Key 2260.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 2260/M.2 E Key 2260.kicad_pcb new file mode 100644 index 0000000..610c255 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2260/M.2 E Key 2260.kicad_pcb @@ -0,0 +1,3021 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 E Key/PET1P") + (net 2 "/M.2 E Key/PET1N") + (net 3 "/M.2 E Key/PET0P") + (net 4 "/M.2 E Key/PET0N") + (net 5 "GND") + (net 6 "/PET0-") + (net 7 "/PET1-") + (net 8 "/PET1+") + (net 9 "/PET0+") + (net 10 "+3.3V") + (net 11 "/USB_D+") + (net 12 "/USB_D-") + (net 13 "/LED#1") + (net 14 "/I2S_SCK") + (net 15 "/SDIO_CLK") + (net 16 "/I2S_WS") + (net 17 "/SDIO_CMD") + (net 18 "/I2S_SD_OUT") + (net 19 "/SDIO_DATA0") + (net 20 "/I2S_SD_IN") + (net 21 "/SDIO_DATA3") + (net 22 "/LED#2") + (net 23 "/SDIO_DATA2") + (net 24 "/SDIO_DATA1") + (net 25 "/UART_WAKE#") + (net 26 "/SDIO__WAKE#") + (net 27 "/UART_TXD") + (net 28 "/SDIO_RESET#") + (net 29 "/UART_RXD") + (net 30 "/UARD_RTS") + (net 31 "/PER0-") + (net 32 "/UART_CTS") + (net 33 "/PER0+") + (net 34 "unconnected-(J1-Vender_Defined-Pad38)") + (net 35 "unconnected-(J1-Vender_Defined-Pad40)") + (net 36 "unconnected-(J1-Vender_Defined-Pad42)") + (net 37 "unconnected-(J1-COEX3-Pad44)") + (net 38 "unconnected-(J1-COEX2-Pad46)") + (net 39 "/REFCLK0+") + (net 40 "unconnected-(J1-COEX1-Pad48)") + (net 41 "/REFCLK0-") + (net 42 "/SUSCLK") + (net 43 "/PERST0#") + (net 44 "/CLKREQ0#") + (net 45 "/W_DISABLE2#") + (net 46 "/PEWAKE#") + (net 47 "/W_DISABLE1#") + (net 48 "/I2C_DATA") + (net 49 "/PER1+") + (net 50 "/I2C_CLK") + (net 51 "/PER1-") + (net 52 "/ALERT#") + (net 53 "unconnected-(J1-RESERVED-Pad64)") + (net 54 "/PERST1#") + (net 55 "/CLKREQ1#") + (net 56 "/PEWAKE1#") + (net 57 "/REFCLK1+") + (net 58 "/REFCLK1-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "857c5b4a-d145-4a03-95ff-56002fea7a0c") + (at 106.86 155.18 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C4" + (at 0 1.14 90) + (layer "F.SilkS") + (uuid "3a0be076-74a9-4116-8e09-28c1c83225b6") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "e7bf38ff-4b49-4d50-a59c-fe13eb8c8db9") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "0ce04ed8-fc7b-44db-891c-5fd9a7b1bd9d") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "c47d950a-87c8-4808-9a40-14fa23bfe6a8") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr smd) + (fp_line + (start 0.7 -0.35) + (end 0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "46618140-27a8-4696-a5d1-361f6e768c4a") + ) + (fp_line + (start -0.7 -0.35) + (end 0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "6af3ea31-f5cd-414f-a632-1d482a395a26") + ) + (fp_line + (start 0.7 0.35) + (end -0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "e4f29ef5-8614-44a9-b83b-c5422d8ec0dd") + ) + (fp_line + (start -0.7 0.35) + (end -0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "094c93e8-2ab4-4fe0-99e3-60d232ae47d8") + ) + (fp_line + (start 0.3 -0.15) + (end 0.3 0.15) + (stroke + (width 0.1) + (type solid) + ) + (layer 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "02c09e4c-f845-41a2-8dae-56fe38a12eb4") + ) + (pin "1" + (uuid "fbb83367-4605-4109-bd6a-0eef965a2f35") + ) + (instances + (project "M.2 E Key 2260" + (path "/46745a17-6c0a-426e-aca0-328dec31be0b/c428767f-6578-427a-bed2-1ce2d6f1fe26/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/46745a17-6c0a-426e-aca0-328dec31be0b/c428767f-6578-427a-bed2-1ce2d6f1fe26/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2260/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 2260/meta/info.html new file mode 100644 index 0000000..46e8478 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2260/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 2280 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2280/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 2280/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2280/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2280/M.2 E Key 2280.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 2280/M.2 E Key 2280.kicad_pcb new file mode 100644 index 0000000..a9c0ade --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2280/M.2 E Key 2280.kicad_pcb @@ -0,0 +1,3020 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 E Key/PET1P") + (net 2 "/M.2 E Key/PET1N") + (net 3 "/M.2 E Key/PET0P") + (net 4 "/M.2 E Key/PET0N") + (net 5 "GND") + (net 6 "/PET0-") + (net 7 "/PET1-") + (net 8 "/PET1+") + (net 9 "/PET0+") + (net 10 "+3.3V") + (net 11 "/USB_D+") + (net 12 "/USB_D-") + (net 13 "/LED#1") + (net 14 "/I2S_SCK") + (net 15 "/SDIO_CLK") + (net 16 "/I2S_WS") + (net 17 "/SDIO_CMD") + (net 18 "/I2S_SD_OUT") + (net 19 "/SDIO_DATA0") + (net 20 "/I2S_SD_IN") + (net 21 "/SDIO_DATA3") + (net 22 "/LED#2") + (net 23 "/SDIO_DATA2") + (net 24 "/SDIO_DATA1") + (net 25 "/UART_WAKE#") + (net 26 "/SDIO__WAKE#") + (net 27 "/UART_TXD") + (net 28 "/SDIO_RESET#") + (net 29 "/UART_RXD") + (net 30 "/UARD_RTS") + (net 31 "/PER0-") + (net 32 "/UART_CTS") + (net 33 "/PER0+") + (net 34 "unconnected-(J1-Vender_Defined-Pad38)") + (net 35 "unconnected-(J1-Vender_Defined-Pad40)") + (net 36 "unconnected-(J1-Vender_Defined-Pad42)") + (net 37 "unconnected-(J1-COEX3-Pad44)") + (net 38 "unconnected-(J1-COEX2-Pad46)") + (net 39 "/REFCLK0+") + (net 40 "unconnected-(J1-COEX1-Pad48)") + (net 41 "/REFCLK0-") + (net 42 "/SUSCLK") + (net 43 "/PERST0#") + (net 44 "/CLKREQ0#") + (net 45 "/W_DISABLE2#") + (net 46 "/PEWAKE#") + (net 47 "/W_DISABLE1#") + (net 48 "/I2C_DATA") + (net 49 "/PER1+") + (net 50 "/I2C_CLK") + (net 51 "/PER1-") + (net 52 "/ALERT#") + (net 53 "unconnected-(J1-RESERVED-Pad64)") + (net 54 "/PERST1#") + (net 55 "/CLKREQ1#") + (net 56 "/PEWAKE1#") + (net 57 "/REFCLK1+") + (net 58 "/REFCLK1-") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "04805688-21c5-4f01-b0ca-84226f393d0f") + (at 102.66 153.43 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C1" + (at 0 -1.05 90) + (layer "F.SilkS") + (uuid "2851165b-bb38-43e6-873a-ac4161059e0f") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "fd1de822-d599-400a-a81d-a143474d0925") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "0015770c-6043-4bed-9de4-940fe0c69e2e") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "fa655f9b-f1ad-4ef4-8419-7c8d55f71029") + ) + (pin "1" + (uuid "143964ce-0a5a-4106-a3a6-300175bc8143") + ) + (instances + (project "M.2 E Key 2280" + (path "/a24b6ca4-9876-4ae6-91ef-51d9184f5704/d48ca69b-849a-467d-9ae3-a7451b41089b/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/a24b6ca4-9876-4ae6-91ef-51d9184f5704/d48ca69b-849a-467d-9ae3-a7451b41089b/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 2280/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 2280/meta/info.html new file mode 100644 index 0000000..46e8478 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 2280/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 2280 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 30110/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 30110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 30110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 30110/M.2 E Key 30110.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 30110/M.2 E Key 30110.kicad_pcb new file mode 100644 index 0000000..a3d183e --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 30110/M.2 E Key 30110.kicad_pcb @@ -0,0 +1,3048 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "764aee26-0a19-4563-840a-c8e8f1484627") + ) + (pin "1" + (uuid "ca42e502-52c2-497d-aced-1bc253e8858f") + ) + (instances + (project "M.2 E Key 30110" + (path "/b80cfedd-1dc9-472f-9201-9442e1f5a970/525bacc7-babc-4248-90f8-34c1cf78cb24/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/b80cfedd-1dc9-472f-9201-9442e1f5a970/525bacc7-babc-4248-90f8-34c1cf78cb24/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 30110/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 30110/meta/info.html new file mode 100644 index 0000000..73b9b1b --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 30110/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 30110 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3030/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 3030/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3030/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3030/M.2 E Key 3030.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 3030/M.2 E Key 3030.kicad_pcb new file mode 100644 index 0000000..47d8edb --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3030/M.2 E Key 3030.kicad_pcb @@ -0,0 +1,3048 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "1ed5d0e7-f0f1-4a8f-bc29-1eba8a95176e") + ) + (pin "1" + (uuid "7a0edfd7-cded-4d35-b68d-167cdbfe8f40") + ) + (instances + (project "M.2 E Key 3030" + (path "/1d0f9d41-fb54-427a-b9c0-69148f17f49e/d9244323-d0d2-42d8-9562-7a770dfe078e/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/1d0f9d41-fb54-427a-b9c0-69148f17f49e/d9244323-d0d2-42d8-9562-7a770dfe078e/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3030/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 3030/meta/info.html new file mode 100644 index 0000000..cf61e11 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3030/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 3030 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3042/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 3042/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3042/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3042/M.2 E Key 3042.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 3042/M.2 E Key 3042.kicad_pcb new file mode 100644 index 0000000..367b6ba --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3042/M.2 E Key 3042.kicad_pcb @@ -0,0 +1,3048 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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"/SDIO_DATA3") + (net 18 "/LED#2") + (net 19 "/SDIO_DATA2") + (net 20 "/SDIO_DATA1") + (net 21 "/UART_WAKE#") + (net 22 "/SDIO__WAKE#") + (net 23 "/UART_TXD") + (net 24 "/SDIO_RESET#") + (net 25 "/UART_RXD") + (net 26 "/UARD_RTS") + (net 27 "/PER0-") + (net 28 "/UART_CTS") + (net 29 "/PER0+") + (net 30 "unconnected-(J1-Vender_Defined-Pad38)") + (net 31 "unconnected-(J1-Vender_Defined-Pad40)") + (net 32 "unconnected-(J1-Vender_Defined-Pad42)") + (net 33 "unconnected-(J1-COEX3-Pad44)") + (net 34 "unconnected-(J1-COEX2-Pad46)") + (net 35 "/REFCLK0+") + (net 36 "unconnected-(J1-COEX1-Pad48)") + (net 37 "/REFCLK0-") + (net 38 "/SUSCLK") + (net 39 "/PERST0#") + (net 40 "/CLKREQ0#") + (net 41 "/W_DISABLE2#") + (net 42 "/PEWAKE#") + (net 43 "/W_DISABLE1#") + (net 44 "/I2C_DATA") + (net 45 "/PER1+") + (net 46 "/I2C_CLK") + (net 47 "/PER1-") + (net 48 "/ALERT#") + (net 49 "unconnected-(J1-RESERVED-Pad64)") + (net 50 "/PERST1#") + (net 51 "/CLKREQ1#") + (net 52 "/PEWAKE1#") + (net 53 "/REFCLK1+") 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "0f08a493-1391-43fb-aa94-fc05cf5fe460") + ) + (pin "1" + (uuid "077e89cf-04a0-40bb-9805-6fc61d25f05f") + ) + (instances + (project "M.2 E Key 3042" + (path "/80102f95-40ef-457e-8ffe-1d64dea1d3f1/57f5f90c-1dca-44ef-b992-147ad2a2f3b1/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/80102f95-40ef-457e-8ffe-1d64dea1d3f1/57f5f90c-1dca-44ef-b992-147ad2a2f3b1/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3042/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 3042/meta/info.html new file mode 100644 index 0000000..86ca7ad --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3042/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 3042 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3060/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 3060/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3060/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3060/M.2 E Key 3060.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 3060/M.2 E Key 3060.kicad_pcb new file mode 100644 index 0000000..96ef34e --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3060/M.2 E Key 3060.kicad_pcb @@ -0,0 +1,3048 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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"/SDIO_DATA3") + (net 18 "/LED#2") + (net 19 "/SDIO_DATA2") + (net 20 "/SDIO_DATA1") + (net 21 "/UART_WAKE#") + (net 22 "/SDIO__WAKE#") + (net 23 "/UART_TXD") + (net 24 "/SDIO_RESET#") + (net 25 "/UART_RXD") + (net 26 "/UARD_RTS") + (net 27 "/PER0-") + (net 28 "/UART_CTS") + (net 29 "/PER0+") + (net 30 "unconnected-(J1-Vender_Defined-Pad38)") + (net 31 "unconnected-(J1-Vender_Defined-Pad40)") + (net 32 "unconnected-(J1-Vender_Defined-Pad42)") + (net 33 "unconnected-(J1-COEX3-Pad44)") + (net 34 "unconnected-(J1-COEX2-Pad46)") + (net 35 "/REFCLK0+") + (net 36 "unconnected-(J1-COEX1-Pad48)") + (net 37 "/REFCLK0-") + (net 38 "/SUSCLK") + (net 39 "/PERST0#") + (net 40 "/CLKREQ0#") + (net 41 "/W_DISABLE2#") + (net 42 "/PEWAKE#") + (net 43 "/W_DISABLE1#") + (net 44 "/I2C_DATA") + (net 45 "/PER1+") + (net 46 "/I2C_CLK") + (net 47 "/PER1-") + (net 48 "/ALERT#") + (net 49 "unconnected-(J1-RESERVED-Pad64)") + (net 50 "/PERST1#") + (net 51 "/CLKREQ1#") + (net 52 "/PEWAKE1#") + (net 53 "/REFCLK1+") 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3060/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 3060 +

This is a KiCad 9 template + diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3080/.gitignore b/Templates/M.2 E Key Templates/M.2 E Key 3080/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3080/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3080/M.2 E Key 3080.kicad_pcb b/Templates/M.2 E Key Templates/M.2 E Key 3080/M.2 E Key 3080.kicad_pcb new file mode 100644 index 0000000..480ba40 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3080/M.2 E Key 3080.kicad_pcb @@ -0,0 +1,3048 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(thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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) + (property "Datasheet" "~" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 143.51 100.33 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (pin "2" + (uuid "4acc020d-0280-4391-beca-c5f6208ca2e4") + ) + (pin "1" + (uuid "00b63c24-e90f-4fb8-ae8a-af11677ae0b1") + ) + (instances + (project "M.2 E Key 3080" + (path "/d9efee78-18a0-404a-b488-26241a73b38b/822dc00b-611a-4d5d-a02c-f12837d6df01/50ac1df9-4d43-4cce-8aa0-372f84fe8ac9" + (reference "C4") + (unit 1) + ) + (path "/d9efee78-18a0-404a-b488-26241a73b38b/822dc00b-611a-4d5d-a02c-f12837d6df01/fa8b5729-454d-4030-ab20-6e9ee0cf319c" + (reference "C2") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 E Key Templates/M.2 E Key 3080/meta/info.html b/Templates/M.2 E Key Templates/M.2 E Key 3080/meta/info.html new file mode 100644 index 0000000..11926f1 --- /dev/null +++ b/Templates/M.2 E Key Templates/M.2 E Key 3080/meta/info.html @@ -0,0 +1,3 @@ +M.2 E Key 3080 +

This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 22110/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 22110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 22110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 22110/M.2 M Key 22110.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 22110/M.2 M Key 22110.kicad_pcb new file mode 100644 index 0000000..14dd092 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 22110/M.2 M Key 22110.kicad_pcb @@ -0,0 +1,3934 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 M Key/PET1P") + (net 2 "/M.2 M Key/PET1N") + (net 3 "/M.2 M Key/PET0P") + (net 4 "/M.2 M Key/PET0N") + (net 5 "/M.2 M Key/PET2N") + (net 6 "/M.2 M Key/PET3N") + (net 7 "/M.2 M Key/PET3P") + (net 8 "/M.2 M Key/PET2P") + (net 9 "/PET2+") + (net 10 "/PET3+") + (net 11 "/PET0-") + (net 12 "/PET1-") + (net 13 "/PET1+") + (net 14 "/PET2-") + (net 15 "/PET0+") + (net 16 "/PET3-") + (net 17 "GND") + (net 18 "+3.3V") + (net 19 "unconnected-(J1-NC-Pad6)") + (net 20 "unconnected-(J1-NC-Pad8)") + (net 21 "/LED1#") + (net 22 "/PER3-") + (net 23 "/PER3+") + (net 24 "unconnected-(J1-NC-Pad20)") + (net 25 "unconnected-(J1-NC-Pad22)") + (net 26 "/PER2-") + (net 27 "unconnected-(J1-NC-Pad24)") + (net 28 "/PER2+") + (net 29 "unconnected-(J1-NC-Pad26)") + (net 30 "unconnected-(J1-NC-Pad28)") + (net 31 "unconnected-(J1-NC-Pad30)") + (net 32 "unconnected-(J1-NC-Pad32)") + (net 33 "unconnected-(J1-NC-Pad34)") + (net 34 "/PER1-") + (net 35 "unconnected-(J1-NC-Pad36)") + (net 36 "/PER1+") + (net 37 "/DEVSLP") + (net 38 "unconnected-(J1-NC-Pad40)") + (net 39 "unconnected-(J1-NC-Pad42)") + (net 40 "unconnected-(J1-NC-Pad44)") + (net 41 "unconnected-(J1-NC-Pad46)") + (net 42 "/PER0-") + (net 43 "unconnected-(J1-NC-Pad48)") + (net 44 "/PER0+") + (net 45 "/PERST#") + (net 46 "/CLKREQ#") + (net 47 "/REFCLK-") + (net 48 "/PEWAKE#") + (net 49 "/REFCLK+") + (net 50 "unconnected-(J1-NC-Pad56)") + (net 51 "unconnected-(J1-NC-Pad58)") + (net 52 "unconnected-(J1-NC-Pad67)") + (net 53 "/SUSCLK") + (net 54 "/PEDET") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "1f1458d1-35ed-44ce-9562-6b94b9bf9c03") + (at 104.86 153.02 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C2" + (at 0 -0.705 90) + (layer "F.SilkS") + (uuid "aeadc8a5-87c1-41bb-8bbb-847569ef68f8") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "50866f34-ff74-4d51-b0f4-885096325b4c") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "f5dd83da-d451-464f-a518-a366c2875790") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "1be99eef-018f-4418-beb4-b64ec1ea249c") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr smd) + (fp_line + (start 0.7 -0.35) + (end 0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "aee5a9ca-ee6c-428a-81e8-42a58c4238f8") + ) + (fp_line + (start -0.7 -0.35) + (end 0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "14316831-b1db-4efc-a50f-cfe8ce919a2a") + ) + (fp_line + (start 0.7 0.35) + (end -0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "018b7b5b-31a6-4f92-9694-46bbd27b7cf8") + ) + (fp_line + (start -0.7 0.35) + (end -0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "a0aef86f-2ffd-40bf-867f-74aed2f5701a") + ) + (fp_line + (start 0.3 -0.15) + (end 0.3 0.15) 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0.318 0.36) + (layers "F.Paste") + (roundrect_rratio 0.25) + (uuid "55d3d1d1-ad73-45bd-bea6-f545070af613") + ) + (pad "1" smd roundrect + (at -0.32 0 90) + (size 0.46 0.4) + (layers "F.Cu" "F.Mask") + (roundrect_rratio 0.25) + (net 3 "/M.2 M Key/PET0P") + (pintype "passive") + (uuid "6373c58b-424e-4541-830f-df628b86da20") + ) + (pad "2" smd roundrect + (at 0.32 0 90) + (size 0.46 0.4) + (layers "F.Cu" "F.Mask") + (roundrect_rratio 0.25) + (net 15 "/PET0+") + (pintype "passive") + (uuid "957faea4-97c9-4891-84bf-3fba17bb932c") + ) + (embedded_fonts no) + (model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0201_0603Metric.wrl" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "1f5af5aa-b225-45db-bee3-543078ced815") + (at 105.56 153.02 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: 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This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2230/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 2230/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2230/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2230/M.2 M Key 2230.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 2230/M.2 M Key 2230.kicad_pcb new file mode 100644 index 0000000..bc0dbe1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2230/M.2 M Key 2230.kicad_pcb @@ -0,0 +1,3973 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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Key/PET3P") + (net 17 "GND") + (net 18 "unconnected-(J1-NC-Pad67)") + (net 19 "/PER0-") + (net 20 "/PERST#") + (net 21 "unconnected-(J1-NC-Pad20)") + (net 22 "/CLKREQ#") + (net 23 "/PER1-") + (net 24 "+3.3V") + (net 25 "unconnected-(J1-NC-Pad30)") + (net 26 "unconnected-(J1-NC-Pad24)") + (net 27 "/SUSCLK") + (net 28 "/PER3-") + (net 29 "unconnected-(J1-NC-Pad22)") + (net 30 "/PER2-") + (net 31 "unconnected-(J1-NC-Pad32)") + (net 32 "unconnected-(J1-NC-Pad6)") + (net 33 "/REFCLK+") + (net 34 "/PEDET") + (net 35 "unconnected-(J1-NC-Pad46)") + (net 36 "unconnected-(J1-NC-Pad48)") + (net 37 "unconnected-(J1-NC-Pad56)") + (net 38 "unconnected-(J1-NC-Pad26)") + (net 39 "unconnected-(J1-NC-Pad42)") + (net 40 "/DEVSLP") + (net 41 "unconnected-(J1-NC-Pad28)") + (net 42 "/PER2+") + (net 43 "/PER0+") + (net 44 "unconnected-(J1-NC-Pad34)") + (net 45 "/PER1+") + (net 46 "unconnected-(J1-NC-Pad44)") + (net 47 "unconnected-(J1-NC-Pad36)") + (net 48 "/REFCLK-") + (net 49 "unconnected-(J1-NC-Pad8)") + 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"/1646a8b2-c07c-4f7d-b009-d69eb6a13cbe/63519646-dcc0-4eb2-a912-36e68cdd7779/f596e965-9af1-41dd-9f15-6f309ad60165" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2230/meta/info.html b/Templates/M.2 M Key Templates/M.2 M Key 2230/meta/info.html new file mode 100644 index 0000000..704ca93 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2230/meta/info.html @@ -0,0 +1,3 @@ +M.2 M Key 2230 +

This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2242/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 2242/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2242/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2242/M.2 M Key 2242.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 2242/M.2 M Key 2242.kicad_pcb new file mode 100644 index 0000000..a621991 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2242/M.2 M Key 2242.kicad_pcb @@ -0,0 +1,3933 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(thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2260/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 2260/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2260/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2260/M.2 M Key 2260.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 2260/M.2 M Key 2260.kicad_pcb new file mode 100644 index 0000000..dfa03c9 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2260/M.2 M Key 2260.kicad_pcb @@ -0,0 +1,3933 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 M Key/PET2P") + (net 2 "/PET2+") + (net 3 "/M.2 M Key/PET3P") + (net 4 "/PET3+") + (net 5 "/M.2 M Key/PET0N") + (net 6 "/PET0-") + (net 7 "/M.2 M Key/PET1N") + (net 8 "/PET1-") + (net 9 "/M.2 M Key/PET1P") + (net 10 "/PET1+") + (net 11 "/M.2 M Key/PET2N") + (net 12 "/PET2-") + (net 13 "/M.2 M Key/PET0P") + (net 14 "/PET0+") + (net 15 "/M.2 M Key/PET3N") + (net 16 "/PET3-") + (net 17 "GND") + (net 18 "+3.3V") + (net 19 "unconnected-(J1-NC-Pad6)") + (net 20 "unconnected-(J1-NC-Pad8)") + (net 21 "/LED1#") + (net 22 "/PER3-") + (net 23 "/PER3+") + (net 24 "unconnected-(J1-NC-Pad20)") + (net 25 "unconnected-(J1-NC-Pad22)") + (net 26 "/PER2-") + (net 27 "unconnected-(J1-NC-Pad24)") + (net 28 "/PER2+") + (net 29 "unconnected-(J1-NC-Pad26)") + (net 30 "unconnected-(J1-NC-Pad28)") + (net 31 "unconnected-(J1-NC-Pad30)") + (net 32 "unconnected-(J1-NC-Pad32)") + (net 33 "unconnected-(J1-NC-Pad34)") + (net 34 "/PER1-") + (net 35 "unconnected-(J1-NC-Pad36)") + (net 36 "/PER1+") + (net 37 "/DEVSLP") + (net 38 "unconnected-(J1-NC-Pad40)") + (net 39 "unconnected-(J1-NC-Pad42)") + (net 40 "unconnected-(J1-NC-Pad44)") + (net 41 "unconnected-(J1-NC-Pad46)") + (net 42 "/PER0-") + (net 43 "unconnected-(J1-NC-Pad48)") + (net 44 "/PER0+") + (net 45 "/PERST#") + (net 46 "/CLKREQ#") + (net 47 "/REFCLK-") + (net 48 "/PEWAKE#") + (net 49 "/REFCLK+") + (net 50 "unconnected-(J1-NC-Pad56)") + (net 51 "unconnected-(J1-NC-Pad58)") + (net 52 "unconnected-(J1-NC-Pad67)") + (net 53 "/SUSCLK") + (net 54 "/PEDET") + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "243a6779-9b57-4ae7-8cea-6f537120e4a6") + (at 113.805 154.75 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C5" + (at 0 0.74 90) + (layer "F.SilkS") + (uuid "b6d033a1-2e8a-4b57-b44f-c80281170030") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "885560a9-fe61-45c9-b5cc-9b8cbbfc7c88") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "e15fcb01-a79b-4f80-b72f-826faa10caf1") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "43823777-9249-43a3-a5ba-b5d34f2a4285") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr smd) + (fp_line + (start 0.7 -0.35) + (end 0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "5ff9d19b-180d-4e8b-ae85-004d96b9a727") + ) + (fp_line + (start -0.7 -0.35) + (end 0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "8bacedb0-ed22-4fd3-b74f-0e6d5c57e08b") + ) + (fp_line + (start 0.7 0.35) + (end -0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "c3dcaaa7-eb50-49b7-bf85-a77dbe6c5e49") + ) + (fp_line + (start -0.7 0.35) + (end -0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "fb4c8da8-686f-4929-8748-4d5252eb0dd3") + ) + (fp_line + (start 0.3 -0.15) + (end 0.3 0.15) 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0.318 0.36) + (layers "F.Paste") + (roundrect_rratio 0.25) + (uuid "228decbf-271e-46a8-a3c9-90b7c41c0d73") + ) + (pad "1" smd roundrect + (at -0.32 0 90) + (size 0.46 0.4) + (layers "F.Cu" "F.Mask") + (roundrect_rratio 0.25) + (net 11 "/M.2 M Key/PET2N") + (pintype "passive") + (uuid "94b18977-09b0-4830-b5aa-7a171d022f05") + ) + (pad "2" smd roundrect + (at 0.32 0 90) + (size 0.46 0.4) + (layers "F.Cu" "F.Mask") + (roundrect_rratio 0.25) + (net 12 "/PET2-") + (pintype "passive") + (uuid "1e26788a-24ad-47cb-9e31-5c6bb46ab57b") + ) + (embedded_fonts no) + (model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0201_0603Metric.wrl" + (offset + (xyz 0 0 0) + ) + (scale + (xyz 1 1 1) + ) + (rotate + (xyz 0 0 0) + ) + ) + ) + (footprint "Capacitor_SMD:C_0201_0603Metric" + (layer "F.Cu") + (uuid "29685bdf-8b79-4221-a8cc-d4020e34fe82") + (at 116.105 154.75 90) + (descr "Capacitor SMD 0201 (0603 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: https://www.vishay.com/docs/20052/crcw0201e3.pdf), generated with kicad-footprint-generator") + (tags "capacitor") + (property "Reference" "C8" + (at 0 -0.75 90) + (layer "F.SilkS") + (uuid "520afdce-61e6-42cf-ad55-947c792d8cde") + (effects + (font + (size 0.5 0.5) + (thickness 0.15) + ) + ) + ) + (property "Value" "220nF" + (at 0 1.05 90) + (layer "F.Fab") + (uuid "ead14cd9-84db-4500-8fa1-d01f6e4142b6") + (effects + (font + (size 1 1) + (thickness 0.15) + ) + ) + ) + (property "Datasheet" "" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "6ddc0e3f-3245-43e8-9a66-02131a3deb0d") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (property "Description" "Unpolarized capacitor" + (at 0 0 90) + (layer "F.Fab") + (hide yes) + (uuid "e248eaee-c64b-40f7-82cc-02ab7bc35780") + (effects + (font + (size 1.27 1.27) + (thickness 0.15) + ) + ) + ) + (attr smd) + (fp_line + (start 0.7 -0.35) + (end 0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "5cab6068-0655-407c-aa18-c2fe85e82b7c") + ) + (fp_line + (start -0.7 -0.35) + (end 0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "df12f059-90a6-4c13-bc4d-e7876554973c") + ) + (fp_line + (start 0.7 0.35) + (end -0.7 0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "4d53f922-e45a-49e8-95d2-2561900ab400") + ) + (fp_line + (start -0.7 0.35) + (end -0.7 -0.35) + (stroke + (width 0.05) + (type solid) + ) + (layer "F.CrtYd") + (uuid "6e94e793-5230-4c79-9eb5-80c2eaf417c2") + ) + (fp_line + (start 0.3 -0.15) + (end 0.3 0.15) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "cf599d7e-6715-40d7-ade1-4f957d30ae89") + ) + (fp_line + (start -0.3 -0.15) + (end 0.3 -0.15) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid "2907e22b-27bb-4729-bcc7-be573092da93") + ) + (fp_line + (start 0.3 0.15) + (end -0.3 0.15) + (stroke + (width 0.1) + (type solid) + ) + (layer "F.Fab") + (uuid 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This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2280/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 2280/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2280/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 2280/M.2 M Key 2280.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 2280/M.2 M Key 2280.kicad_pcb new file mode 100644 index 0000000..b93a63e --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 2280/M.2 M Key 2280.kicad_pcb @@ -0,0 +1,3937 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This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 30110/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 30110/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 30110/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 30110/M.2 M Key 30110.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 30110/M.2 M Key 30110.kicad_pcb new file mode 100644 index 0000000..b21789c --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 30110/M.2 M Key 30110.kicad_pcb @@ -0,0 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This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3030/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 3030/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3030/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3030/M.2 M Key 3030.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 3030/M.2 M Key 3030.kicad_pcb new file mode 100644 index 0000000..1ba8839 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3030/M.2 M Key 3030.kicad_pcb @@ -0,0 +1,3955 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + 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) + (pin "2" + (uuid "714d28f5-bc1e-48d9-8707-694d8c487cff") + ) + (pin "1" + (uuid "5137d5bb-8f6f-4891-a339-504889566ce5") + ) + (instances + (project "M.2 M key 3042" + (path "/33a896b5-698c-4421-ac90-a15bdf9e4c25/98cbbf9f-4962-4ccb-835c-8a53971f66d2/5d0595b3-944b-441f-b22b-db89ec1a22e6" + (reference "C6") + (unit 1) + ) + (path "/33a896b5-698c-4421-ac90-a15bdf9e4c25/98cbbf9f-4962-4ccb-835c-8a53971f66d2/6b0ad683-ac06-4c6d-a09c-9523f796fa3b" + (reference "C2") + (unit 1) + ) + (path "/33a896b5-698c-4421-ac90-a15bdf9e4c25/98cbbf9f-4962-4ccb-835c-8a53971f66d2/90d8a0fe-6e9e-4d1d-ad54-87aefda3ab86" + (reference "C8") + (unit 1) + ) + (path "/33a896b5-698c-4421-ac90-a15bdf9e4c25/98cbbf9f-4962-4ccb-835c-8a53971f66d2/f596e965-9af1-41dd-9f15-6f309ad60165" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3042/meta/info.html b/Templates/M.2 M Key Templates/M.2 M Key 3042/meta/info.html new file mode 100644 index 0000000..585f3d9 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3042/meta/info.html @@ -0,0 +1,3 @@ +M.2 M Key 3042 +

This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3060/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 3060/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3060/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3060/M.2 M Key 3060.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 3060/M.2 M Key 3060.kicad_pcb new file mode 100644 index 0000000..4575823 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3060/M.2 M Key 3060.kicad_pcb @@ -0,0 +1,3958 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 M Key/PET1P") + (net 2 "/M.2 M Key/PET1N") + (net 3 "/M.2 M Key/PET0N") + (net 4 "/M.2 M Key/PET0P") + (net 5 "/M.2 M Key/PET3N") + (net 6 "/M.2 M Key/PET2P") + (net 7 "/M.2 M Key/PET2N") + (net 8 "/M.2 M Key/PET3P") + (net 9 "/PET2+") + (net 10 "/PET3+") + (net 11 "/PET0-") + (net 12 "/PET1-") + (net 13 "GND") + (net 14 "+3.3V") + (net 15 "unconnected-(J1-NC-Pad6)") + (net 16 "unconnected-(J1-NC-Pad8)") + (net 17 "/LED1#") + (net 18 "/PER3-") + (net 19 "/PER3+") + (net 20 "unconnected-(J1-NC-Pad20)") + (net 21 "unconnected-(J1-NC-Pad22)") + (net 22 "/PER2-") + (net 23 "unconnected-(J1-NC-Pad24)") + (net 24 "/PER2+") + (net 25 "unconnected-(J1-NC-Pad26)") + (net 26 "unconnected-(J1-NC-Pad28)") + (net 27 "unconnected-(J1-NC-Pad30)") + (net 28 "unconnected-(J1-NC-Pad32)") + (net 29 "unconnected-(J1-NC-Pad34)") + (net 30 "/PER1-") + (net 31 "unconnected-(J1-NC-Pad36)") + (net 32 "/PER1+") + (net 33 "/DEVSLP") + (net 34 "unconnected-(J1-NC-Pad40)") + (net 35 "unconnected-(J1-NC-Pad42)") + (net 36 "unconnected-(J1-NC-Pad44)") + (net 37 "unconnected-(J1-NC-Pad46)") + (net 38 "/PER0-") + (net 39 "unconnected-(J1-NC-Pad48)") + (net 40 "/PER0+") + (net 41 "/PERST#") + (net 42 "/CLKREQ#") + (net 43 "/REFCLK-") + (net 44 "/PEWAKE#") + (net 45 "/REFCLK+") + (net 46 "unconnected-(J1-NC-Pad56)") + (net 47 "unconnected-(J1-NC-Pad58)") + (net 48 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"/ed279bd0-fd67-4e8f-9eab-d42dd1f9d5d1/b171cac5-fdcb-4065-8a18-8d019b75b0cd/f596e965-9af1-41dd-9f15-6f309ad60165" + (reference "C4") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3060/meta/info.html b/Templates/M.2 M Key Templates/M.2 M Key 3060/meta/info.html new file mode 100644 index 0000000..f5b412c --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3060/meta/info.html @@ -0,0 +1,3 @@ +M.2 M Key 3060 +

This is a KiCad 9 template + diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3080/.gitignore b/Templates/M.2 M Key Templates/M.2 M Key 3080/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3080/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/M.2 M Key Templates/M.2 M Key 3080/M.2 M Key 3080.kicad_pcb b/Templates/M.2 M Key Templates/M.2 M Key 3080/M.2 M Key 3080.kicad_pcb new file mode 100644 index 0000000..39c878c --- /dev/null +++ b/Templates/M.2 M Key Templates/M.2 M Key 3080/M.2 M Key 3080.kicad_pcb @@ -0,0 +1,3957 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 0.8) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "core") + (thickness 0.71) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "None") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "/M.2 M Key/PET1P") + (net 2 "/M.2 M Key/PET1N") + (net 3 "/M.2 M Key/PET0N") + (net 4 "/M.2 M Key/PET0P") + (net 5 "/M.2 M Key/PET3N") + (net 6 "/M.2 M Key/PET2P") + (net 7 "/M.2 M Key/PET2N") + (net 8 "/M.2 M Key/PET3P") + (net 9 "/PET2+") + (net 10 "/PET3+") + (net 11 "/PET0-") + (net 12 "/PET1-") + (net 13 "GND") + (net 14 "+3.3V") + (net 15 "unconnected-(J1-NC-Pad6)") + (net 16 "unconnected-(J1-NC-Pad8)") + (net 17 "/LED1#") + (net 18 "/PER3-") + (net 19 "/PER3+") + (net 20 "unconnected-(J1-NC-Pad20)") + (net 21 "unconnected-(J1-NC-Pad22)") + (net 22 "/PER2-") + (net 23 "unconnected-(J1-NC-Pad24)") + (net 24 "/PER2+") + (net 25 "unconnected-(J1-NC-Pad26)") + (net 26 "unconnected-(J1-NC-Pad28)") + (net 27 "unconnected-(J1-NC-Pad30)") + (net 28 "unconnected-(J1-NC-Pad32)") + (net 29 "unconnected-(J1-NC-Pad34)") + (net 30 "/PER1-") + (net 31 "unconnected-(J1-NC-Pad36)") + (net 32 "/PER1+") + (net 33 "/DEVSLP") + (net 34 "unconnected-(J1-NC-Pad40)") + (net 35 "unconnected-(J1-NC-Pad42)") + (net 36 "unconnected-(J1-NC-Pad44)") + (net 37 "unconnected-(J1-NC-Pad46)") + (net 38 "/PER0-") + (net 39 "unconnected-(J1-NC-Pad48)") + (net 40 "/PER0+") + (net 41 "/PERST#") + (net 42 "/CLKREQ#") + (net 43 "/REFCLK-") + (net 44 "/PEWAKE#") + (net 45 "/REFCLK+") + (net 46 "unconnected-(J1-NC-Pad56)") + (net 47 "unconnected-(J1-NC-Pad58)") + (net 48 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from PCIexpress_x1_full/PCIexpress_x1_full.kicad_pro rename to Templates/PCIe x1 Templates/PCIexpress_x1_full/PCIexpress_x1_full.kicad_pro index dd063bc..e7b761e 100644 --- a/PCIexpress_x1_full/PCIexpress_x1_full.kicad_pro +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_full/PCIexpress_x1_full.kicad_pro @@ -1,15 +1,19 @@ { "board": { + "3dviewports": [], "design_settings": { "defaults": { - "board_outline_line_width": 0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.08889999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.44999999999999996, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.0889, + "min_via_annular_width": 0.05, + "min_via_diameter": 0.45, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x1_full.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,25 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PER0_N", - "/PER0_P", - "/PET0_N", - "/PET0_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -415,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -433,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -451,34 +569,146 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -489,6 +719,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, @@ -509,15 +744,21 @@ }, "page_layout_descr_file": "", "plot_directory": "", + "space_save_all_events": true, "spice_adjust_passive_values": false, + "spice_current_sheet_as_root": false, "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_dissipations": false, + "spice_save_all_voltages": false, "subpart_first_id": 65, "subpart_id_separator": 0 }, "sheets": [ [ "d4a655a4-a1b2-4c75-b7b5-cc7400a5115b", - "" + "Root" ], [ "00000000-0000-0000-0000-00005d508b15", diff --git a/Templates/PCIe x1 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a/Templates/PCIe x1 Templates/PCIexpress_x1_half/.gitignore b/Templates/PCIe x1 Templates/PCIexpress_x1_half/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_half/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x1 Templates/PCIexpress_x1_half/PCIexpress_connector.kicad_sch b/Templates/PCIe x1 Templates/PCIexpress_x1_half/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..3786ef8 --- /dev/null +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_half/PCIexpress_connector.kicad_sch @@ -0,0 +1,3005 @@ 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"board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, 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+ "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x1_half.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,25 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PER0_N", - "/PER0_P", - "/PET0_N", - "/PET0_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -415,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -433,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -451,34 +569,146 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -489,6 +719,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, @@ -509,15 +744,21 @@ }, "page_layout_descr_file": "", "plot_directory": "", + "space_save_all_events": true, "spice_adjust_passive_values": false, + "spice_current_sheet_as_root": false, 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Templates/PCIexpress_x1_half/fp-lib-table similarity index 100% rename from PCIexpress_x16_half/fp-lib-table rename to Templates/PCIe x1 Templates/PCIexpress_x1_half/fp-lib-table diff --git a/Templates/PCIe x1 Templates/PCIexpress_x1_half/meta/info.html b/Templates/PCIe x1 Templates/PCIexpress_x1_half/meta/info.html new file mode 100644 index 0000000..a2d1192 --- /dev/null +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_half/meta/info.html @@ -0,0 +1,3 @@ +PCIEx1_half +

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Templates/PCIexpress_x1_low/.gitignore b/Templates/PCIe x1 Templates/PCIexpress_x1_low/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_low/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x1 Templates/PCIexpress_x1_low/PCIexpress_connector.kicad_sch b/Templates/PCIe x1 Templates/PCIexpress_x1_low/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..78a17fc --- /dev/null +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_low/PCIexpress_connector.kicad_sch @@ -0,0 +1,3005 @@ +(kicad_sch + (version 20250114) + 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(embedded_fonts no) +) diff --git a/PCIexpress_x1_low/PCIexpress_x1_low.kicad_pro b/Templates/PCIe x1 Templates/PCIexpress_x1_low/PCIexpress_x1_low.kicad_pro similarity index 57% rename from PCIexpress_x1_low/PCIexpress_x1_low.kicad_pro rename to Templates/PCIe x1 Templates/PCIexpress_x1_low/PCIexpress_x1_low.kicad_pro index 2e2cab6..dafca98 100644 --- a/PCIexpress_x1_low/PCIexpress_x1_low.kicad_pro +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_low/PCIexpress_x1_low.kicad_pro @@ -1,15 +1,19 @@ { "board": { + "3dviewports": [], "design_settings": { "defaults": { - "board_outline_line_width": 0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.08889999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.44999999999999996, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.0889, + "min_via_annular_width": 0.05, + "min_via_diameter": 0.45, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x1_low.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,25 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PER0_N", - "/PER0_P", - "/PET0_N", - "/PET0_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -415,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -433,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -451,34 +569,146 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": 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"string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -489,6 +719,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, @@ -509,15 +744,21 @@ }, "page_layout_descr_file": "", "plot_directory": "", + "space_save_all_events": true, "spice_adjust_passive_values": false, + "spice_current_sheet_as_root": false, "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_dissipations": false, + "spice_save_all_voltages": false, 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Templates/PCIexpress_x1_low/fp-lib-table diff --git a/Templates/PCIe x1 Templates/PCIexpress_x1_low/meta/info.html b/Templates/PCIe x1 Templates/PCIexpress_x1_low/meta/info.html new file mode 100644 index 0000000..ba97968 --- /dev/null +++ b/Templates/PCIe x1 Templates/PCIexpress_x1_low/meta/info.html @@ -0,0 +1,3 @@ +PCIEx1_low +

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Templates/PCIexpress_x16_full/.gitignore b/Templates/PCIe x16 Templates/PCIexpress_x16_full/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x16 Templates/PCIexpress_x16_full/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x16 Templates/PCIexpress_x16_full/PCIexpress_connector.kicad_sch b/Templates/PCIe x16 Templates/PCIexpress_x16_full/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..99ca01a --- /dev/null +++ b/Templates/PCIe x16 Templates/PCIexpress_x16_full/PCIexpress_connector.kicad_sch @@ -0,0 +1,11968 @@ +(kicad_sch + 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a/Templates/PCIe x16 Templates/PCIexpress_x16_half/.gitignore b/Templates/PCIe x16 Templates/PCIexpress_x16_half/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x16 Templates/PCIexpress_x16_half/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x16 Templates/PCIexpress_x16_half/PCIexpress_connector.kicad_sch b/Templates/PCIe x16 Templates/PCIexpress_x16_half/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..f59f7d4 --- /dev/null +++ b/Templates/PCIe x16 Templates/PCIexpress_x16_half/PCIexpress_connector.kicad_sch @@ -0,0 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/dev/null +++ b/Templates/PCIe x16 Templates/PCIexpress_x16_low/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x16 Templates/PCIexpress_x16_low/PCIexpress_connector.kicad_sch b/Templates/PCIe x16 Templates/PCIexpress_x16_low/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..390ecc2 --- /dev/null +++ b/Templates/PCIe x16 Templates/PCIexpress_x16_low/PCIexpress_connector.kicad_sch @@ -0,0 +1,11968 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "f23c0b6a-ea48-4140-bd4a-31f36366ae21") + (paper "A4" portrait) + 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Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x2 Templates/PCIexpress_x2_half/PCIexpress_connector.kicad_sch b/Templates/PCIe x2 Templates/PCIexpress_x2_half/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..ec2da9f --- /dev/null +++ b/Templates/PCIe x2 Templates/PCIexpress_x2_half/PCIexpress_connector.kicad_sch @@ -0,0 +1,3454 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "b3384f0e-6ce8-445e-a44f-564f3f460d5d") + (paper "A4") + (lib_symbols + (symbol "PCIexpress:PCIexpress_x2" + (pin_names + (offset 1.016) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 3.81 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" "PCIexpress_x2" + (at 0 1.27 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Footprint" "PCIexpress:PCIexpress_x2" + (at 0 -26.67 0) + (effects + (font + (size 1.27 1.27) + ) + (hide yes) + ) + ) + (property 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+*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x4 Templates/PCIexpress_x4_full/PCIexpress_connector.kicad_sch b/Templates/PCIe x4 Templates/PCIexpress_x4_full/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..ad32f71 --- /dev/null +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_full/PCIexpress_connector.kicad_sch @@ -0,0 +1,4870 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "ded0cf89-354f-45a0-a3e3-ec32f297c9d3") + (paper "A4" portrait) + (title_block + (title "PCIexpress_x4_full") + (company "Author: Luca Anastasio") + ) + (lib_symbols + (symbol "PCIexpress:PCIexpress_bracket" + (pin_names + (offset 1.016) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 0 0) + 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Templates/PCIexpress_x4_full/PCIexpress_x4_full.kicad_pro similarity index 54% rename from PCIexpress_x4_full/PCIexpress_x4_full.kicad_pro rename to Templates/PCIe x4 Templates/PCIexpress_x4_full/PCIexpress_x4_full.kicad_pro index 62aed77..d8c4319 100644 --- a/PCIexpress_x4_full/PCIexpress_x4_full.kicad_pro +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_full/PCIexpress_x4_full.kicad_pro @@ -1,15 +1,19 @@ { "board": { + "3dviewports": [], "design_settings": { "defaults": { - "board_outline_line_width": 0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.08889999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.44999999999999996, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.0889, + "min_via_annular_width": 0.05, + "min_via_diameter": 0.45, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x4_full.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,43 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PCIexpress_connector/_PER1_N", - "/PCIexpress_connector/_PER1_P", - "/PCIexpress_connector/_PER2_N", - "/PCIexpress_connector/_PER2_P", - "/PCIexpress_connector/_PER3_N", - "/PCIexpress_connector/_PER3_P", - "/PER0_N", - "/PER0_P", - "/PER1_N", - "/PER1_P", - "/PER2_N", - "/PER2_P", - "/PER3_N", - "/PER3_P", - "/PET0_N", - "/PET0_P", - "/PET1_N", - "/PET1_P", - "/PET2_N", - "/PET2_P", - "/PET3_N", - "/PET3_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -433,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -451,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -469,34 +569,218 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -507,6 +791,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + 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(unit 1) + ) + ) + ) + ) +) diff --git a/PCIexpress_x4_full/fp-lib-table b/Templates/PCIe x4 Templates/PCIexpress_x4_full/fp-lib-table similarity index 100% rename from PCIexpress_x4_full/fp-lib-table rename to Templates/PCIe x4 Templates/PCIexpress_x4_full/fp-lib-table diff --git a/Templates/PCIe x4 Templates/PCIexpress_x4_full/meta/info.html b/Templates/PCIe x4 Templates/PCIexpress_x4_full/meta/info.html new file mode 100644 index 0000000..bd68299 --- /dev/null +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_full/meta/info.html @@ -0,0 +1,3 @@ +PCIEx4_full +

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mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_half/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x4 Templates/PCIexpress_x4_half/PCIexpress_connector.kicad_sch b/Templates/PCIe x4 Templates/PCIexpress_x4_half/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..993fe2d --- /dev/null +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_half/PCIexpress_connector.kicad_sch @@ -0,0 +1,4870 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "1e4a9612-59cf-40c7-bea6-6e23d6a2968f") + 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0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.08889999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.44999999999999996, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.0889, + "min_via_annular_width": 0.05, + "min_via_diameter": 0.45, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x4_half.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,43 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PCIexpress_connector/_PER1_N", - "/PCIexpress_connector/_PER1_P", - "/PCIexpress_connector/_PER2_N", - "/PCIexpress_connector/_PER2_P", - "/PCIexpress_connector/_PER3_N", - "/PCIexpress_connector/_PER3_P", - "/PER0_N", - "/PER0_P", - "/PER1_N", - "/PER1_P", - "/PER2_N", - "/PER2_P", - "/PER3_N", - "/PER3_P", - "/PET0_N", - "/PET0_P", - "/PET1_N", - "/PET1_P", - "/PET2_N", - "/PET2_P", - "/PET3_N", - "/PET3_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -433,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -451,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -469,34 +569,218 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -507,6 +791,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, @@ -527,15 +816,21 @@ }, "page_layout_descr_file": "", "plot_directory": "", + "space_save_all_events": true, "spice_adjust_passive_values": false, + "spice_current_sheet_as_root": false, "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_dissipations": false, + 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+PCIEx4_half +

This is a KiCad 9 template + diff --git a/PCIexpress_x1_low/sym-lib-table b/Templates/PCIe x4 Templates/PCIexpress_x4_half/sym-lib-table similarity index 100% rename from PCIexpress_x1_low/sym-lib-table rename to Templates/PCIe x4 Templates/PCIexpress_x4_half/sym-lib-table diff --git a/Templates/PCIe x4 Templates/PCIexpress_x4_half/term.kicad_sch b/Templates/PCIe x4 Templates/PCIexpress_x4_half/term.kicad_sch new file mode 100644 index 0000000..cc26a20 --- /dev/null +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_half/term.kicad_sch @@ -0,0 +1,683 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "99ca4bd8-2e63-4ea9-b98f-e74603651e6b") + (paper "A4") + (title_block + (title "PCIexpress_x4_half") + (company "Author: Luca Anastasio") + ) + (lib_symbols + (symbol "Device:R" + (pin_numbers + (hide yes) + ) + (pin_names + (offset 0) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "R" + (at 2.032 0 90) + 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mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_low/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x4 Templates/PCIexpress_x4_low/PCIexpress_connector.kicad_sch b/Templates/PCIe x4 Templates/PCIexpress_x4_low/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..325fb49 --- /dev/null +++ b/Templates/PCIe x4 Templates/PCIexpress_x4_low/PCIexpress_connector.kicad_sch @@ -0,0 +1,4870 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "c5caf9e3-3aef-4c97-aafc-9cc651b5932f") + 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"board_outline_line_width": 0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.08889999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.44999999999999996, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.0889, + "min_via_annular_width": 0.05, + "min_via_diameter": 0.45, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x4_low.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,43 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PCIexpress_connector/_PER1_N", - "/PCIexpress_connector/_PER1_P", - "/PCIexpress_connector/_PER2_N", - "/PCIexpress_connector/_PER2_P", - "/PCIexpress_connector/_PER3_N", - "/PCIexpress_connector/_PER3_P", - "/PER0_N", - "/PER0_P", - "/PER1_N", - "/PER1_P", - "/PER2_N", - "/PER2_P", - "/PER3_N", - "/PER3_P", - "/PET0_N", - "/PET0_P", - "/PET1_N", - "/PET1_P", - "/PET2_N", - "/PET2_P", - "/PET3_N", - "/PET3_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -433,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -451,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -469,34 +569,218 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + 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mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_full/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x8 Templates/PCIexpress_x8_full/PCIexpress_connector.kicad_sch b/Templates/PCIe x8 Templates/PCIexpress_x8_full/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..b8b8626 --- /dev/null +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_full/PCIexpress_connector.kicad_sch @@ -0,0 +1,7271 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "af1ab3ef-2fef-4c42-aeac-5daa6c5c7712") + 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0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - 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1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x8_full.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,67 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PCIexpress_connector/_PER1_N", - "/PCIexpress_connector/_PER1_P", - "/PCIexpress_connector/_PER2_N", - "/PCIexpress_connector/_PER2_P", - "/PCIexpress_connector/_PER3_N", - "/PCIexpress_connector/_PER3_P", - "/PCIexpress_connector/_PER4_N", - "/PCIexpress_connector/_PER4_P", - "/PCIexpress_connector/_PER5_N", - "/PCIexpress_connector/_PER5_P", - "/PCIexpress_connector/_PER6_N", - "/PCIexpress_connector/_PER6_P", - "/PCIexpress_connector/_PER7_N", - "/PCIexpress_connector/_PER7_P", - "/PER0_N", - "/PER0_P", - "/PER1_N", - "/PER1_P", - "/PER2_N", - "/PER2_P", - "/PER3_N", - "/PER3_P", - "/PER4_N", - "/PER4_P", - "/PER5_N", - "/PER5_P", - "/PER6_N", - "/PER6_P", - "/PER7_N", - "/PER7_P", - "/PET0_N", - "/PET0_P", - "/PET1_N", - "/PET1_P", - "/PET2_N", - "/PET2_P", - "/PET3_N", - "/PET3_P", - "/PET4_N", - "/PET4_P", - "/PET5_N", - "/PET5_P", - "/PET6_N", - "/PET6_P", - "/PET7_N", - "/PET7_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -457,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -475,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -493,34 +569,314 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -531,6 +887,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, @@ -551,15 +912,21 @@ }, "page_layout_descr_file": "", "plot_directory": "", + "space_save_all_events": true, "spice_adjust_passive_values": false, + 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"/82e6c5b6-1716-450d-a32e-4c08f6bbe17c/00000000-0000-0000-0000-00005d508b15/00000000-0000-0000-0000-00005d87b440" + (reference "#PWR0120") + (unit 1) + ) + (path "/82e6c5b6-1716-450d-a32e-4c08f6bbe17c/00000000-0000-0000-0000-00005d508b15/00000000-0000-0000-0000-00005d87b446" + (reference "#PWR0122") + (unit 1) + ) + (path "/82e6c5b6-1716-450d-a32e-4c08f6bbe17c/00000000-0000-0000-0000-00005d508b15/00000000-0000-0000-0000-00005d88a9fd" + (reference "#PWR0124") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/PCIe x8 Templates/PCIexpress_x8_half/.gitignore b/Templates/PCIe x8 Templates/PCIexpress_x8_half/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_half/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x8 Templates/PCIexpress_x8_half/PCIexpress_connector.kicad_sch b/Templates/PCIe x8 Templates/PCIexpress_x8_half/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..35e2fd6 --- /dev/null +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_half/PCIexpress_connector.kicad_sch @@ -0,0 +1,7271 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "f3c0c29d-77c5-49b6-8601-bc8f895ed81a") + (paper "A4" portrait) + (title_block + (title "PCIexpress_x8_half") + (company "Author: Luca Anastasio") + ) + (lib_symbols + (symbol "PCIexpress:PCIexpress_bracket" + (pin_names + (offset 1.016) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" 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from PCIexpress_x8_half/PCIexpress_x8_half.kicad_pro rename to Templates/PCIe x8 Templates/PCIexpress_x8_half/PCIexpress_x8_half.kicad_pro index d9a3940..e81094f 100644 --- a/PCIexpress_x8_half/PCIexpress_x8_half.kicad_pro +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_half/PCIexpress_x8_half.kicad_pro @@ -1,15 +1,19 @@ { "board": { + "3dviewports": [], "design_settings": { "defaults": { - "board_outline_line_width": 0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.08889999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.44999999999999996, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.0889, + "min_via_annular_width": 0.05, + "min_via_diameter": 0.45, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x8_half.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,67 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PCIexpress_connector/_PER1_N", - "/PCIexpress_connector/_PER1_P", - "/PCIexpress_connector/_PER2_N", - "/PCIexpress_connector/_PER2_P", - "/PCIexpress_connector/_PER3_N", - "/PCIexpress_connector/_PER3_P", - "/PCIexpress_connector/_PER4_N", - "/PCIexpress_connector/_PER4_P", - "/PCIexpress_connector/_PER5_N", - "/PCIexpress_connector/_PER5_P", - "/PCIexpress_connector/_PER6_N", - "/PCIexpress_connector/_PER6_P", - "/PCIexpress_connector/_PER7_N", - "/PCIexpress_connector/_PER7_P", - "/PER0_N", - "/PER0_P", - "/PER1_N", - "/PER1_P", - "/PER2_N", - "/PER2_P", - "/PER3_N", - "/PER3_P", - "/PER4_N", - "/PER4_P", - "/PER5_N", - "/PER5_P", - "/PER6_N", - "/PER6_P", - "/PER7_N", - "/PER7_P", - "/PET0_N", - "/PET0_P", - "/PET1_N", - "/PET1_P", - "/PET2_N", - "/PET2_P", - "/PET3_N", - "/PET3_P", - "/PET4_N", - "/PET4_P", - "/PET5_N", - "/PET5_P", - "/PET6_N", - "/PET6_P", - "/PET7_N", - "/PET7_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -457,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -475,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -493,34 +569,314 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -531,6 +887,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, @@ -551,15 +912,21 @@ }, "page_layout_descr_file": "", "plot_directory": "", + "space_save_all_events": true, "spice_adjust_passive_values": false, + "spice_current_sheet_as_root": false, "spice_external_command": "spice \"%I\"", + "spice_model_current_sheet_as_root": true, + "spice_save_all_currents": false, + "spice_save_all_dissipations": false, + "spice_save_all_voltages": false, "subpart_first_id": 65, "subpart_id_separator": 0 }, "sheets": [ [ "5186319c-a7b6-4fff-abe7-9a78b1ac7ba0", - "" + "Root" ], [ "00000000-0000-0000-0000-00005d508b15", diff --git a/Templates/PCIe x8 Templates/PCIexpress_x8_half/PCIexpress_x8_half.kicad_sch b/Templates/PCIe x8 Templates/PCIexpress_x8_half/PCIexpress_x8_half.kicad_sch new file mode 100644 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"/5186319c-a7b6-4fff-abe7-9a78b1ac7ba0/00000000-0000-0000-0000-00005d508b15/00000000-0000-0000-0000-00005d87b440" + (reference "#PWR0120") + (unit 1) + ) + (path "/5186319c-a7b6-4fff-abe7-9a78b1ac7ba0/00000000-0000-0000-0000-00005d508b15/00000000-0000-0000-0000-00005d87b446" + (reference "#PWR0122") + (unit 1) + ) + (path "/5186319c-a7b6-4fff-abe7-9a78b1ac7ba0/00000000-0000-0000-0000-00005d508b15/00000000-0000-0000-0000-00005d88a9fd" + (reference "#PWR0124") + (unit 1) + ) + ) + ) + ) +) diff --git a/Templates/PCIe x8 Templates/PCIexpress_x8_low/.gitignore b/Templates/PCIe x8 Templates/PCIexpress_x8_low/.gitignore new file mode 100644 index 0000000..5cfb0c1 --- /dev/null +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_low/.gitignore @@ -0,0 +1,25 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv diff --git a/Templates/PCIe x8 Templates/PCIexpress_x8_low/PCIexpress_connector.kicad_sch b/Templates/PCIe x8 Templates/PCIexpress_x8_low/PCIexpress_connector.kicad_sch new file mode 100644 index 0000000..6fd3f20 --- /dev/null +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_low/PCIexpress_connector.kicad_sch @@ -0,0 +1,7271 @@ +(kicad_sch + (version 20250114) + (generator "eeschema") + (generator_version "9.0") + (uuid "6d2e7884-a711-4aab-9acf-e2e44a4a6cb6") + (paper "A4" portrait) + (title_block + (title "PCIexpress_x8_low") + (company "Author: Luca Anastasio") + ) + (lib_symbols + (symbol "PCIexpress:PCIexpress_bracket" + (pin_names + (offset 1.016) + ) + (exclude_from_sim no) + (in_bom yes) + (on_board yes) + (property "Reference" "J" + (at 0 0 0) + (effects + (font + (size 1.27 1.27) + ) + ) + ) + (property "Value" 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0.049999999999999996, - "copper_line_width": 0.19999999999999998, + "apply_defaults_to_fp_fields": false, + "apply_defaults_to_fp_shapes": false, + "apply_defaults_to_fp_text": false, + "board_outline_line_width": 0.05, + "copper_line_width": 0.2, "copper_text_italic": false, "copper_text_size_h": 1.5, "copper_text_size_v": 1.5, "copper_text_thickness": 0.3, "copper_text_upright": false, - "courtyard_line_width": 0.049999999999999996, + "courtyard_line_width": 0.05, "dimension_precision": 4, "dimension_units": 3, "dimensions": { @@ -20,13 +24,13 @@ "text_position": 0, "units_format": 1 }, - "fab_line_width": 0.09999999999999999, + "fab_line_width": 0.1, "fab_text_italic": false, "fab_text_size_h": 1.0, "fab_text_size_v": 1.0, "fab_text_thickness": 0.15, "fab_text_upright": false, - "other_line_width": 0.09999999999999999, + "other_line_width": 0.1, "other_text_italic": false, "other_text_size_h": 1.0, "other_text_size_v": 1.0, @@ -57,35 +61,56 @@ "rule_severities": { "annular_width": "error", "clearance": "error", + "connection_width": "warning", "copper_edge_clearance": "error", + "copper_sliver": "warning", "courtyards_overlap": "error", + "creepage": "error", "diff_pair_gap_out_of_range": "error", "diff_pair_uncoupled_length_too_long": "error", "drill_out_of_range": "error", "duplicate_footprints": "warning", "extra_footprint": "warning", + "footprint": "error", + "footprint_filters_mismatch": "ignore", + "footprint_symbol_mismatch": "warning", "footprint_type_mismatch": "error", "hole_clearance": "error", "hole_near_hole": "error", + "hole_to_hole": "error", + "holes_co_located": "warning", "invalid_outline": "error", + "isolated_copper": "warning", "item_on_disabled_layer": "error", "items_not_allowed": "error", "length_out_of_range": "error", + "lib_footprint_issues": "warning", + "lib_footprint_mismatch": "warning", "malformed_courtyard": "error", "microvia_drill_out_of_range": "error", + "mirrored_text_on_front_layer": "warning", "missing_courtyard": "ignore", "missing_footprint": "warning", "net_conflict": "warning", + "nonmirrored_text_on_back_layer": "warning", "npth_inside_courtyard": "ignore", "padstack": "error", "pth_inside_courtyard": "ignore", "shorting_items": "error", + "silk_edge_clearance": "warning", "silk_over_copper": "warning", "silk_overlap": "warning", "skew_out_of_range": "error", + "solder_mask_bridge": "error", + "starved_thermal": "error", + "text_height": "warning", + "text_on_edge_cuts": "error", + "text_thickness": "warning", "through_hole_pad_without_hole": "error", "too_many_vias": "error", + "track_angle": "error", "track_dangling": "warning", + "track_segment_length": "error", "track_width": "error", "tracks_crossing": "error", "unconnected_items": "error", @@ -101,24 +126,100 @@ "allow_microvias": false, "max_error": 0.005, "min_clearance": 0.0, + "min_connection": 0.0, "min_copper_edge_clearance": 0.075, + "min_groove_width": 0.0, "min_hole_clearance": 0.25, "min_hole_to_hole": 0.25, - "min_microvia_diameter": 0.19999999999999998, - "min_microvia_drill": 0.09999999999999999, + "min_microvia_diameter": 0.2, + "min_microvia_drill": 0.1, + "min_resolved_spokes": 2, "min_silk_clearance": 0.0, - "min_through_hole_diameter": 0.19999999999999998, - "min_track_width": 0.08889999999999999, - "min_via_annular_width": 0.049999999999999996, - "min_via_diameter": 0.44999999999999996, + "min_text_height": 0.8, + "min_text_thickness": 0.08, + "min_through_hole_diameter": 0.2, + "min_track_width": 0.0889, + "min_via_annular_width": 0.05, + "min_via_diameter": 0.45, + "solder_mask_to_copper_clearance": 0.0, "use_height_for_length_calcs": true }, + "teardrop_options": [ + { + "td_onpthpad": true, + "td_onroundshapesonly": false, + "td_onsmdpad": true, + "td_ontrackend": false, + "td_onvia": true + } + ], + "teardrop_parameters": [ + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_round_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_rect_shape", + "td_width_to_size_filter_ratio": 0.9 + }, + { + "td_allow_use_two_tracks": true, + "td_curve_segcount": 0, + "td_height_ratio": 1.0, + "td_length_ratio": 0.5, + "td_maxheight": 2.0, + "td_maxlen": 1.0, + "td_on_pad_in_zone": false, + "td_target_name": "td_track_end", + "td_width_to_size_filter_ratio": 0.9 + } + ], "track_widths": [ 0.0, 0.0889, 0.127, 0.2 ], + "tuning_pattern_settings": { + "diff_pair_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 1.0 + }, + "diff_pair_skew_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + }, + "single_track_defaults": { + "corner_radius_percentage": 80, + "corner_style": 1, + "max_amplitude": 1.0, + "min_amplitude": 0.2, + "single_sided": false, + "spacing": 0.6 + } + }, "via_dimensions": [ { "diameter": 0.0, @@ -140,7 +241,16 @@ "zones_allow_external_fillets": false, "zones_use_no_outline": true }, - "layer_presets": [] + "ipc2581": { + "dist": "", + "distpn": "", + "internal_id": "", + "mfg": "", + "mpn": "" + }, + "layer_pairs": [], + "layer_presets": [], + "viewports": [] }, "boards": [], "cvpcb": { @@ -331,11 +441,21 @@ "different_unit_net": "error", "duplicate_reference": "error", "duplicate_sheet_names": "error", + "endpoint_off_grid": "warning", "extra_units": "error", + "footprint_filter": "ignore", + "footprint_link_issues": "warning", + "four_way_junction": "ignore", "global_label_dangling": "warning", "hier_label_mismatch": "error", "label_dangling": "error", + "label_multiple_wires": "warning", "lib_symbol_issues": "warning", + "lib_symbol_mismatch": "warning", + "missing_bidi_pin": "warning", + "missing_input_pin": "warning", + "missing_power_pin": "error", + "missing_unit": "warning", "multiple_net_names": "warning", "net_not_bus_member": "warning", "no_connect_connected": "warning", @@ -344,8 +464,14 @@ "pin_not_driven": "error", "pin_to_pin": "warning", "power_pin_not_driven": "error", + "same_local_global_label": "warning", + "similar_label_and_power": "warning", "similar_labels": "warning", + "similar_power": "warning", + "simulation_model_issue": "ignore", + "single_global_label": "ignore", "unannotated": "error", + "unconnected_wire_endpoint": "warning", "unit_value_mismatch": "error", "unresolved_variable": "error", "wire_dangling": "error" @@ -357,12 +483,12 @@ }, "meta": { "filename": "PCIexpress_x8_low.kicad_pro", - "version": 1 + "version": 3 }, "net_settings": { "classes": [ { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.0889, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -372,14 +498,15 @@ "microvia_drill": 0.1, "name": "Default", "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2, "diff_pair_via_gap": 0.25, @@ -388,67 +515,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "Diff-100-PCIe", - "nets": [ - "/PCIexpress_connector/_PER0_N", - "/PCIexpress_connector/_PER0_P", - "/PCIexpress_connector/_PER1_N", - "/PCIexpress_connector/_PER1_P", - "/PCIexpress_connector/_PER2_N", - "/PCIexpress_connector/_PER2_P", - "/PCIexpress_connector/_PER3_N", - "/PCIexpress_connector/_PER3_P", - "/PCIexpress_connector/_PER4_N", - "/PCIexpress_connector/_PER4_P", - "/PCIexpress_connector/_PER5_N", - "/PCIexpress_connector/_PER5_P", - "/PCIexpress_connector/_PER6_N", - "/PCIexpress_connector/_PER6_P", - "/PCIexpress_connector/_PER7_N", - "/PCIexpress_connector/_PER7_P", - "/PER0_N", - "/PER0_P", - "/PER1_N", - "/PER1_P", - "/PER2_N", - "/PER2_P", - "/PER3_N", - "/PER3_P", - "/PER4_N", - "/PER4_P", - "/PER5_N", - "/PER5_P", - "/PER6_N", - "/PER6_P", - "/PER7_N", - "/PER7_P", - "/PET0_N", - "/PET0_P", - "/PET1_N", - "/PET1_P", - "/PET2_N", - "/PET2_P", - "/PET3_N", - "/PET3_P", - "/PET4_N", - "/PET4_P", - "/PET5_N", - "/PET5_P", - "/PET6_N", - "/PET6_P", - "/PET7_N", - "/PET7_P", - "/REFCLK+", - "/REFCLK-" - ], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 0, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.1016, "diff_pair_via_gap": 0.25, @@ -457,16 +533,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-3.5", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 1, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.1, "diff_pair_gap": 0.127, "diff_pair_via_gap": 0.25, @@ -475,16 +551,16 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC2313-100d-4", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 2, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 }, { - "bus_width": 12.0, + "bus_width": 12, "clearance": 0.2, "diff_pair_gap": 0.2032, "diff_pair_via_gap": 0.25, @@ -493,34 +569,314 @@ "microvia_diameter": 0.3, "microvia_drill": 0.1, "name": "JLC7628-100d-8", - "nets": [], "pcb_color": "rgba(0, 0, 0, 0.000)", + "priority": 3, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.0889, "via_diameter": 0.45, "via_drill": 0.2, - "wire_width": 6.0 + "wire_width": 6 } ], "meta": { - "version": 2 + "version": 4 }, - "net_colors": null + "net_colors": null, + "netclass_assignments": null, + "netclass_patterns": [ + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PCIexpress_connector/_PER7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PER7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET0_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET1_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET2_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET3_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET4_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET4_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET5_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET5_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET6_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET6_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET7_N" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/PET7_P" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK+" + }, + { + "netclass": "Diff-100-PCIe", + "pattern": "/REFCLK-" + } + ] }, "pcbnew": { "last_paths": { "gencad": "", "idf": "", "netlist": "", + "plot": "", + "pos_files": "", "specctra_dsn": "", "step": "", + "svg": "", "vrml": "" }, "page_layout_descr_file": "" }, "schematic": { "annotate_start_num": 0, + "bom_export_filename": "${PROJECTNAME}.csv", + "bom_fmt_presets": [], + "bom_fmt_settings": { + "field_delimiter": ",", + "keep_line_breaks": false, + "keep_tabs": false, + "name": "CSV", + "ref_delimiter": ",", + "ref_range_delimiter": "", + "string_delimiter": "\"" + }, + "bom_presets": [], + "bom_settings": { + "exclude_dnp": false, + "fields_ordered": [ + { + "group_by": false, + "label": "Reference", + "name": "Reference", + "show": true + }, + { + "group_by": false, + "label": "Qty", + "name": "${QUANTITY}", + "show": true + }, + { + "group_by": true, + "label": "Value", + "name": "Value", + "show": true + }, + { + "group_by": true, + "label": "DNP", + "name": "${DNP}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from BOM", + "name": "${EXCLUDE_FROM_BOM}", + "show": true + }, + { + "group_by": true, + "label": "Exclude from Board", + "name": "${EXCLUDE_FROM_BOARD}", + "show": true + }, + { + "group_by": true, + "label": "Footprint", + "name": "Footprint", + "show": true + }, + { + "group_by": false, + "label": "Datasheet", + "name": "Datasheet", + "show": true + } + ], + "filter_string": "", + "group_symbols": true, + "include_excluded_from_bom": true, + "name": "Default Editing", + "sort_asc": true, + "sort_field": "Reference" + }, + "connection_grid_size": 50.0, "drawing": { + "dashed_lines_dash_length_ratio": 12.0, + "dashed_lines_gap_length_ratio": 3.0, "default_line_thickness": 6.0, "default_text_size": 50.0, "field_names": [], @@ -531,6 +887,11 @@ "intersheets_ref_suffix": "", "junction_size_choice": 3, "label_size_ratio": 0.25, + "operating_point_overlay_i_precision": 3, + "operating_point_overlay_i_range": "~A", + "operating_point_overlay_v_precision": 3, + "operating_point_overlay_v_range": "~V", + "overbar_offset_ratio": 1.23, "pin_symbol_size": 0.0, "text_offset_ratio": 0.08 }, @@ -551,15 +912,21 @@ }, "page_layout_descr_file": "", "plot_directory": "", + "space_save_all_events": true, "spice_adjust_passive_values": false, + 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Templates/PCIexpress_x8_low/meta/info.html new file mode 100644 index 0000000..5c3dfe8 --- /dev/null +++ b/Templates/PCIe x8 Templates/PCIexpress_x8_low/meta/info.html @@ -0,0 +1,3 @@ +PCIEx8_low +

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