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    (compPin "7" (pinName "A2") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "8" (pinName "A3") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "9" (pinName "VCC") (partNum 0) (symPinNum 0) (gateEq 0) (pinEq 0) (pinType Power) )
    (compPin "10" (pinName "A4") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "11" (pinName "A5") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "12" (pinName "A6") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "13" (pinName "A7") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "14" (pinName "A8") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "15" (pinName "A9") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "16" (pinName "~CAS") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) )
    (compPin "17" (pinName "Q") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Output) )
    (compPin "18" (pinName "GND") (partNum 0) (symPinNum 0) (gateEq 0) (pinEq 0) (pinType Power) )
    (attachedSymbol (partNum 1) (altType Normal) (symbolName "DRAM-1MX1") )
    (attachedPattern (patternNum 1) (patternName "DIP-18")
      (numPads 18)
      (padPinMap 
        (padNum  1) (compPinRef "1")
        (padNum  2) (compPinRef "2")
        (padNum  3) (compPinRef "3")
        (padNum  4) (compPinRef "4")
        (padNum  5) (compPinRef "5")
        (padNum  6) (compPinRef "6")
        (padNum  7) (compPinRef "7")
        (padNum  8) (compPinRef "8")
        (padNum  9) (compPinRef "9")
        (padNum 10) (compPinRef "10")
        (padNum 11) (compPinRef "11")
        (padNum 12) (compPinRef "12")
        (padNum 13) (compPinRef "13")
        (padNum 14) (compPinRef "14")
        (padNum 15) (compPinRef "15")
        (padNum 16) (compPinRef "16")
        (padNum 17) (compPinRef "17")
        (padNum 18) (compPinRef "18")
      )
    )
  )
)

(netlist "Netlist_1"
  (compInst "X1"
    (compRef "SIMM-30-EDGE_1")
    (originalName "SIMM-30-EDGE")
    (compValue "SIMM-30-EDGE")
    (patternName "SIMM-30")
  )
  (compInst "DD1"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (compInst "DD2"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (compInst "DD3"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (compInst "DD4"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (compInst "DD5"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (compInst "DD6"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (compInst "DD7"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (compInst "DD8"
    (compRef "DRAM-1MX1-DIP_1")
    (originalName "DRAM-1MX1-DIP")
    (compValue "TC511000")
    (patternName "DIP-18")
  )
  (net "VCC"
    (node "X1" "30")
    (node "X1" "1")
    (node "DD4" "9")
    (node "DD3" "9")
    (node "DD2" "9")
    (node "DD1" "9")
    (node "DD7" "9")
    (node "DD6" "9")
    (node "DD5" "9")
    (node "DD8" "9")
  )
  (net "GND"
    (node "X1" "9")
    (node "X1" "22")
    (node "DD4" "4")
    (node "DD3" "4")
    (node "DD2" "4")
    (node "DD1" "4")
    (node "DD5" "4")
    (node "DD6" "4")
    (node "DD7" "4")
    (node "DD8" "4")
    (node "DD4" "18")
    (node "DD3" "18")
    (node "DD2" "18")
    (node "DD1" "18")
    (node "DD7" "18")
    (node "DD6" "18")
    (node "DD5" "18")
    (node "DD8" "18")
  )
  (net "A1"
    (node "X1" "5")
    (node "DD4" "6")
    (node "DD3" "6")
    (node "DD2" "6")
    (node "DD1" "6")
    (node "DD5" "6")
    (node "DD6" "6")
    (node "DD7" "6")
    (node "DD8" "6")
  )
  (net "A2"
    (node "X1" "7")
    (node "DD4" "7")
    (node "DD3" "7")
    (node "DD2" "7")
    (node "DD1" "7")
    (node "DD5" "7")
    (node "DD6" "7")
    (node "DD7" "7")
    (node "DD8" "7")
  )
  (net "A3"
    (node "X1" "8")
    (node "DD4" "8")
    (node "DD3" "8")
    (node "DD2" "8")
    (node "DD1" "8")
    (node "DD5" "8")
    (node "DD6" "8")
    (node "DD7" "8")
    (node "DD8" "8")
  )
  (net "A4"
    (node "X1" "11")
    (node "DD4" "10")
    (node "DD3" "10")
    (node "DD2" "10")
    (node "DD1" "10")
    (node "DD5" "10")
    (node "DD6" "10")
    (node "DD7" "10")
    (node "DD8" "10")
  )
  (net "A5"
    (node "X1" "12")
    (node "DD4" "11")
    (node "DD3" "11")
    (node "DD2" "11")
    (node "DD1" "11")
    (node "DD5" "11")
    (node "DD6" "11")
    (node "DD7" "11")
    (node "DD8" "11")
  )
  (net "A6"
    (node "X1" "14")
    (node "DD4" "12")
    (node "DD3" "12")
    (node "DD2" "12")
    (node "DD1" "12")
    (node "DD5" "12")
    (node "DD6" "12")
    (node "DD7" "12")
    (node "DD8" "12")
  )
  (net "A7"
    (node "X1" "15")
    (node "DD4" "13")
    (node "DD3" "13")
    (node "DD2" "13")
    (node "DD1" "13")
    (node "DD5" "13")
    (node "DD6" "13")
    (node "DD7" "13")
    (node "DD8" "13")
  )
  (net "A8"
    (node "X1" "17")
    (node "DD4" "14")
    (node "DD3" "14")
    (node "DD2" "14")
    (node "DD1" "14")
    (node "DD5" "14")
    (node "DD6" "14")
    (node "DD7" "14")
    (node "DD8" "14")
  )
  (net "~RAS"
    (node "X1" "27")
    (node "DD4" "3")
    (node "DD3" "3")
    (node "DD2" "3")
    (node "DD1" "3")
    (node "DD5" "3")
    (node "DD6" "3")
    (node "DD7" "3")
    (node "DD8" "3")
  )
  (net "~CAS"
    (node "X1" "2")
    (node "DD4" "16")
    (node "DD3" "16")
    (node "DD2" "16")
    (node "DD1" "16")
    (node "DD5" "16")
    (node "DD6" "16")
    (node "DD7" "16")
    (node "DD8" "16")
  )
  (net "~WE"
    (node "X1" "21")
    (node "DD4" "2")
    (node "DD3" "2")
    (node "DD2" "2")
    (node "DD1" "2")
    (node "DD5" "2")
    (node "DD6" "2")
    (node "DD7" "2")
    (node "DD8" "2")
  )
  (net "A9"
    (node "X1" "18")
    (node "DD4" "15")
    (node "DD3" "15")
    (node "DD2" "15")
    (node "DD1" "15")
    (node "DD5" "15")
    (node "DD6" "15")
    (node "DD7" "15")
    (node "DD8" "15")
  )
  (net "A0"
    (node "X1" "4")
    (node "DD4" "5")
    (node "DD3" "5")
    (node "DD2" "5")
    (node "DD1" "5")
    (node "DD5" "5")
    (node "DD6" "5")
    (node "DD7" "5")
    (node "DD8" "5")
  )
  (net "DQ1"
    (node "X1" "6")
    (node "DD2" "17")
    (node "DD2" "1")
  )
  (net "DQ5"
    (node "X1" "20")
    (node "DD6" "17")
    (node "DD6" "1")
  )
  (net "DQ6"
    (node "X1" "23")
    (node "DD7" "17")
    (node "DD7" "1")
  )
  (net "DQ7"
    (node "X1" "25")
    (node "DD8" "17")
    (node "DD8" "1")
  )
  (net "DQ4"
    (node "X1" "16")
    (node "DD5" "17")
    (node "DD5" "1")
  )
  (net "DQ3"
    (node "X1" "13")
    (node "DD4" "17")
    (node "DD4" "1")
  )
  (net "DQ0"
    (node "X1" "3")
    (node "DD1" "17")
    (node "DD1" "1")
  )
  (net "DQ2"
    (node "X1" "10")
    (node "DD3" "17")
    (node "DD3" "1")
  )
)

