commit e6816d073b38fa01dec27b4a6ec53037062bcd91 Author: Roman Krupnin Date: Sat Jan 25 16:04:09 2025 +0300 init repo diff --git a/README.md b/README.md new file mode 100644 index 0000000..cf5fd5b --- /dev/null +++ b/README.md @@ -0,0 +1,22 @@ +# SIMM-30 + +## Печатная плата для модуля памяти ретро компьютеров + +Переходные отверстия контактных площадок SIPP ready - можно установить угловые круглые штыри, а на материнскую плату обычные цанговые панели. +Проект выполнен в pcad 2006 sp2. + +## Особенности: +- SMUC не будет правильно работать с модулем simm30-1x-1M, ему нужны модули с типом памяти simm30-8x-1M; +- толщина платы должна быть тоньше стандартных 1.6мм, т.к. она не будет входить в разъем. Оптимальная толщина 1.4мм, но не все производители печатных плат могут изготавливать такие. Можно изготавливать 1.2мм, в случае если такая плата будет "неконтачить" в разъеме, можно напаять немного олова на все контактные площадки. Вариант проще - поместить с одной стороны полоску бумаги; + +## Модуль представлен в трех вариантах: +- 1мб, на одной микросхеме памяти 1M x 16, типа GM71C18163C +
+ +- 1мб, на восьми микросхемах памяти 1M x 1, типа TC511000P +
+
+ +- 256кб, на восьми микросхемах памяти 256K x 1, типа TMS4256, KM41C256, 565РУ7 +
+
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SIMM-30\simm30-1x-1M.drc: + + +Design Clearances (in mm): +------------------------------- +Board Edge Clearance: Not Defined +Silk Screen Clearance: Not Defined +Hole-Hole Clearance: Not Defined + + +Layer Clearances (in mm): +------------------------------- + +Layer Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + +Top 0.150 0.150 0.150 0.150 0.150 0.150 +Bottom 0.150 0.150 0.150 0.150 0.150 0.150 + + +Net Class Clearances (in mm): +------------------------------- +Net Class Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + + +Net Clearances (In mm): +------------------------- +Net Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + +Net Class To Net Class Clearances (in mm): +-------------------------------------------- +Net Class Names Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + + +Area Checked: +------------- + +DRC Extents: Entire Workspace + + +DRC Report Options: +------------------- + +Net List Compare: Off +Clearance Violations: On +Text Violations: On +Same-Parent-Component Pad Violations: On +Net List Violations: On +Unrouted Nets: On +Unconnected Pins: Off +Net Length Violations: On +Silk Violations: On +Copper Pour Violations: On +Plane Violations: On +Component Violations: On +Drill Violations: On + +---------------------------------------------------------------------- + +24-Jan-25 05:33 Page 1 + + P-CAD Design Rule Check Report + +====================================================================== + +Test Point Violations: Off + +DRC Errors: +----------- + + +NETLIST VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +CLEARANCE VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +UNROUTED NETS: + + +0 warning(s) detected. +0 error(s) detected. +Warning: Net length violation tests were not performed because + of missing MinNetLength, MaxNetLength, or MatchedLength rules. + +NETLIST LENGTH VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +SILK SCREEN CLEARANCE VIOLATIONS: + + +Warning: Silk Screen clearance violation tests were not performed because + of missing SilkscreenClearance rule. + +0 warning(s) detected. +0 error(s) detected. + +TEXT VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +WIDTH VIOLATIONS: + +Warning: Width violation tests were not performed because + of missing Width rule. + +0 warning(s) detected. +0 error(s) detected. + +COPPER POUR VIOLATIONS: + + +---------------------------------------------------------------------- + +24-Jan-25 05:33 Page 2 + + P-CAD Design Rule Check Report + +====================================================================== + + +0 warning(s) detected. +0 error(s) detected. + +PLANE VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +COMPONENT VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +DRILL VIOLATIONS: + +Warning: Hole to hole clearance violation tests were not performed because + of missing HoleToHoleClearance rule. + +0 warning(s) detected. +0 error(s) detected. + +DRC Summary: +------------ + +Netlist: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Clearance: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Unrouted Nets: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Net Length: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Silk Screen: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Text: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Width: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Copper Pour: + Errors: 0 + +---------------------------------------------------------------------- + +24-Jan-25 05:33 Page 3 + + P-CAD Design Rule Check Report + +====================================================================== + + Warnings: 0 + Ignored Errors: 0 +Plane: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Component: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Drilling: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +---------------------------------------------------------------------- + +24-Jan-25 05:33 Page 4 + diff --git a/simm30-1x-1M.net b/simm30-1x-1M.net new file mode 100644 index 0000000..1deccae --- /dev/null +++ b/simm30-1x-1M.net @@ -0,0 +1,2016 @@ +ACCEL_ASCII "C:\prj\1. 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b/simm30-8x-1M.PCB differ diff --git a/simm30-8x-1M.SCH b/simm30-8x-1M.SCH new file mode 100644 index 0000000..56603b1 Binary files /dev/null and b/simm30-8x-1M.SCH differ diff --git a/simm30-8x-1M.drc b/simm30-8x-1M.drc new file mode 100644 index 0000000..0b22502 --- /dev/null +++ b/simm30-8x-1M.drc @@ -0,0 +1,191 @@ +C:\prj\SIMM30\simm30-8x-1M.drc: + + +Design Clearances (in mm): +------------------------------- +Board Edge Clearance: Not Defined +Silk Screen Clearance: Not Defined +Hole-Hole Clearance: Not Defined + + +Layer Clearances (in mm): +------------------------------- + +Layer Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + +Top 0.200 0.200 0.200 0.200 0.200 0.200 +Bottom 0.200 0.200 0.200 0.200 0.200 0.200 + + +Net Class Clearances (in mm): +------------------------------- +Net Class Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + + +Net Clearances (In mm): +------------------------- +Net Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + +Net Class To Net Class Clearances (in mm): +-------------------------------------------- +Net Class Names Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + + +Area Checked: +------------- + +DRC Extents: Entire Workspace + + +DRC Report Options: +------------------- + +Net List Compare: Off +Clearance Violations: On +Text Violations: On +Same-Parent-Component Pad Violations: On +Net List Violations: On +Unrouted Nets: On +Unconnected Pins: Off +Net Length Violations: On +Silk Violations: On +Copper Pour Violations: On +Plane Violations: On +Component Violations: On +Drill Violations: On +Test Point Violations: Off + +DRC Errors: +----------- + + +NETLIST VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +CLEARANCE VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +UNROUTED NETS: + + +0 warning(s) detected. +0 error(s) detected. +Warning: Net length violation tests were not performed because + of missing MinNetLength, MaxNetLength, or MatchedLength rules. + +NETLIST LENGTH VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +SILK SCREEN CLEARANCE VIOLATIONS: + + +Warning: Silk Screen clearance violation tests were not performed because + of missing SilkscreenClearance rule. + +0 warning(s) detected. +0 error(s) detected. + +TEXT VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +WIDTH VIOLATIONS: + +Warning: Width violation tests were not performed because + of missing Width rule. + +0 warning(s) detected. +0 error(s) detected. + +COPPER POUR VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +PLANE VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +COMPONENT VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +DRILL VIOLATIONS: + +Warning: Hole to hole clearance violation tests were not performed because + of missing HoleToHoleClearance rule. + +0 warning(s) detected. +0 error(s) detected. + +DRC Summary: +------------ + +Netlist: + Errors: 0 + Warnings: 0 + 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b/simm30-8x-256K.SCH new file mode 100644 index 0000000..fb9d506 Binary files /dev/null and b/simm30-8x-256K.SCH differ diff --git a/simm30-8x-256K.drc b/simm30-8x-256K.drc new file mode 100644 index 0000000..52a4b54 --- /dev/null +++ b/simm30-8x-256K.drc @@ -0,0 +1,264 @@ +P-CAD Design Rule Check Report + +====================================================================== + +C:\prj\SIMM30\simm30-8x-256K.drc: + + +Design Clearances (in mm): +------------------------------- +Board Edge Clearance: Not Defined +Silk Screen Clearance: Not Defined +Hole-Hole Clearance: Not Defined + + +Layer Clearances (in mm): +------------------------------- + +Layer Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + +Top 0.200 0.200 0.200 0.200 0.200 0.200 +Bottom 0.200 0.200 0.200 0.200 0.200 0.200 + + +Net Class Clearances (in mm): +------------------------------- +Net Class Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + + +Net Clearances (In mm): +------------------------- +Net Name Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + +Net Class To Net Class Clearances (in mm): +-------------------------------------------- +Net Class Names Pad-Pad Pad-Line Line-Line Pad-Via Via-Line Via-Via + + + +Area Checked: +------------- + +DRC Extents: Entire Workspace + + +DRC Report Options: +------------------- + +Net List Compare: Off +Clearance Violations: On +Text Violations: On +Same-Parent-Component Pad Violations: On +Net List Violations: On +Unrouted Nets: On +Unconnected Pins: Off +Net Length Violations: On +Silk Violations: On +Copper Pour Violations: On +Plane Violations: On +Component Violations: On +Drill Violations: On + +---------------------------------------------------------------------- + +21-Oct-23 17:34 Page 1 + + P-CAD Design Rule Check Report + +====================================================================== + +Test Point Violations: Off + +DRC Errors: +----------- + + +NETLIST VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +CLEARANCE VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +UNROUTED NETS: + + +0 warning(s) detected. +0 error(s) detected. +Warning: Net length violation tests were not performed because + of missing MinNetLength, MaxNetLength, or MatchedLength rules. + +NETLIST LENGTH VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +SILK SCREEN CLEARANCE VIOLATIONS: + + +Warning: Silk Screen clearance violation tests were not performed because + of missing SilkscreenClearance rule. + +0 warning(s) detected. +0 error(s) detected. + +TEXT VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +WIDTH VIOLATIONS: + +Warning: Width violation tests were not performed because + of missing Width rule. + +0 warning(s) detected. +0 error(s) detected. + +COPPER POUR VIOLATIONS: + + +---------------------------------------------------------------------- + +21-Oct-23 17:34 Page 2 + + P-CAD Design Rule Check Report + +====================================================================== + + +0 warning(s) detected. +0 error(s) detected. + +PLANE VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +COMPONENT VIOLATIONS: + + +0 warning(s) detected. +0 error(s) detected. + +DRILL VIOLATIONS: + +Warning: Hole to hole clearance violation tests were not performed because + of missing HoleToHoleClearance rule. + +0 warning(s) detected. +0 error(s) detected. + +DRC Summary: +------------ + +Netlist: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Clearance: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Unrouted Nets: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Net Length: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Silk Screen: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Text: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Width: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Copper Pour: + Errors: 0 + +---------------------------------------------------------------------- + +21-Oct-23 17:34 Page 3 + + P-CAD Design Rule Check Report + +====================================================================== + + Warnings: 0 + Ignored Errors: 0 +Plane: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Component: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 +Drilling: + Errors: 0 + Warnings: 0 + Ignored Errors: 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +---------------------------------------------------------------------- + +21-Oct-23 17:34 Page 4 + diff --git a/simm30-8x-256K.net b/simm30-8x-256K.net new file mode 100644 index 0000000..5824a65 --- /dev/null +++ b/simm30-8x-256K.net @@ -0,0 +1,1209 @@ +ACCEL_ASCII "C:\prj\SIMM30\simm30-8x-256K.net" + +(asciiHeader + (asciiVersion 3 0) + (timeStamp 2023 7 8 20 28 2) + (program "P-CAD 2006 Schematic" "19.02.9589") + (copyright "Copyright 1992-2006 Altium Limited") + (fileAuthor "RomanRom2") + (headerString "") + (fileUnits mm) + (guidString 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(node "DD3" "11") + (node "DD2" "11") + (node "DD1" "11") + ) + (net "A5" + (node "X1" "12") + (node "DD5" "10") + (node "DD6" "10") + (node "DD7" "10") + (node "DD8" "10") + (node "DD4" "10") + (node "DD3" "10") + (node "DD2" "10") + (node "DD1" "10") + ) + (net "A6" + (node "X1" "14") + (node "DD5" "13") + (node "DD6" "13") + (node "DD7" "13") + (node "DD8" "13") + (node "DD4" "13") + (node "DD3" "13") + (node "DD2" "13") + (node "DD1" "13") + ) + (net "A7" + (node "X1" "15") + (node "DD5" "9") + (node "DD6" "9") + (node "DD7" "9") + (node "DD8" "9") + (node "DD4" "9") + (node "DD3" "9") + (node "DD2" "9") + (node "DD1" "9") + ) + (net "A8" + (node "X1" "17") + (node "DD5" "1") + (node "DD6" "1") + (node "DD7" "1") + (node "DD8" "1") + (node "DD4" "1") + (node "DD3" "1") + (node "DD2" "1") + (node "DD1" "1") + ) + (net "~RAS" + (node "X1" "27") + (node "DD5" "4") + (node "DD6" "4") + (node "DD7" "4") + (node "DD8" "4") + (node "DD4" "4") + (node "DD3" "4") + (node "DD2" "4") + (node "DD1" "4") + ) + (net "~CAS" + (node "X1" "2") + (node "DD5" "15") + (node "DD6" "15") + (node "DD7" "15") + (node "DD8" "15") + (node "DD4" "15") + (node "DD3" "15") + (node "DD2" "15") + (node "DD1" "15") + ) + (net "~WE" + (node "X1" "21") + (node "DD5" "3") + (node "DD6" "3") + (node "DD7" "3") + (node "DD8" "3") + (node "DD4" "3") + (node "DD3" "3") + (node "DD2" "3") + (node "DD1" "3") + ) + (net "A0" + (node "X1" "4") + (node "DD5" "5") + (node "DD6" "5") + (node "DD7" "5") + (node "DD8" "5") + (node "DD4" "5") + (node "DD3" "5") + (node "DD2" "5") + (node "DD1" "5") + ) + (net "DQ1" + (node "X1" "6") + (node "DD2" "2") + (node "DD2" "14") + ) + (net "DQ5" + (node "X1" "20") + (node "DD6" "2") + (node "DD6" "14") + ) + (net "DQ6" + (node "X1" "23") + (node "DD7" "2") + (node "DD7" "14") + ) + (net "DQ7" + (node "X1" "25") + (node "DD8" "2") + (node "DD8" "14") + ) + (net "DQ4" + (node "X1" "16") + (node "DD5" "2") + (node "DD5" "14") + ) + (net "DQ3" + (node "X1" "13") + (node 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