mirror of
https://github.com/thunderbrewhq/thunderbrew
synced 2025-10-31 00:06:05 +03:00
706c8903a1
* chore(build): add vendored SDL 3.0.0 library * chore(build): add vendored glew-cmake-2.2.0 library * feat(console): in the presence of -opengl launch flag, change GxApi to OpenGl * feat(gx): add uncompleted CGxDeviceGLSDL targeting Windows and Linux * chore(build): change SDL3 linkage from shared (bad) to to static (good)
370 lines
9.8 KiB
C
370 lines
9.8 KiB
C
/*
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Simple DirectMedia Layer
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Copyright (C) 1997-2023 Sam Lantinga <slouken@libsdl.org>
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This software is provided 'as-is', without any express or implied
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warranty. In no event will the authors be held liable for any damages
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arising from the use of this software.
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Permission is granted to anyone to use this software for any purpose,
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including commercial applications, and to alter it and redistribute it
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freely, subject to the following restrictions:
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1. The origin of this software must not be misrepresented; you must not
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claim that you wrote the original software. If you use this software
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in a product, an acknowledgment in the product documentation would be
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appreciated but is not required.
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2. Altered source versions must be plainly marked as such, and must not be
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misrepresented as being the original software.
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3. This notice may not be removed or altered from any source distribution.
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*/
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/**
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* \file SDL_cpuinfo.h
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*
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* \brief CPU feature detection for SDL.
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*/
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#ifndef SDL_cpuinfo_h_
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#define SDL_cpuinfo_h_
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#include <SDL3/SDL_stdinc.h>
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#include <SDL3/SDL_begin_code.h>
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/* Set up for C function definitions, even when using C++ */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* This is a guess for the cacheline size used for padding.
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* Most x86 processors have a 64 byte cache line.
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* The 64-bit PowerPC processors have a 128 byte cache line.
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* We'll use the larger value to be generally safe.
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*/
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#define SDL_CACHELINE_SIZE 128
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/**
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* Get the number of CPU cores available.
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*
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* \returns the total number of logical CPU cores. On CPUs that include
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* technologies such as hyperthreading, the number of logical cores
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* may be more than the number of physical cores.
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*
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* \since This function is available since SDL 3.0.0.
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*/
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extern DECLSPEC int SDLCALL SDL_GetCPUCount(void);
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/**
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* Determine the L1 cache line size of the CPU.
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*
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* This is useful for determining multi-threaded structure padding or SIMD
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* prefetch sizes.
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*
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* \returns the L1 cache line size of the CPU, in bytes.
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*
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* \since This function is available since SDL 3.0.0.
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*/
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extern DECLSPEC int SDLCALL SDL_GetCPUCacheLineSize(void);
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/**
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* Determine whether the CPU has AltiVec features.
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*
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* This always returns false on CPUs that aren't using PowerPC instruction
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* sets.
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*
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* \returns SDL_TRUE if the CPU has AltiVec features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasAltiVec(void);
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/**
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* Determine whether the CPU has MMX features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has MMX features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasMMX(void);
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/**
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* Determine whether the CPU has SSE features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has SSE features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasSSE(void);
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/**
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* Determine whether the CPU has SSE2 features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has SSE2 features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasSSE2(void);
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/**
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* Determine whether the CPU has SSE3 features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has SSE3 features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasSSE3(void);
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/**
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* Determine whether the CPU has SSE4.1 features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has SSE4.1 features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasSSE41(void);
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/**
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* Determine whether the CPU has SSE4.2 features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has SSE4.2 features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasSSE42(void);
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/**
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* Determine whether the CPU has AVX features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has AVX features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX2
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasAVX(void);
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/**
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* Determine whether the CPU has AVX2 features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has AVX2 features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX512F
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasAVX2(void);
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/**
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* Determine whether the CPU has AVX-512F (foundation) features.
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*
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* This always returns false on CPUs that aren't using Intel instruction sets.
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*
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* \returns SDL_TRUE if the CPU has AVX-512F features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasAltiVec
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* \sa SDL_HasAVX
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* \sa SDL_HasAVX2
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* \sa SDL_HasMMX
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* \sa SDL_HasSSE
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* \sa SDL_HasSSE2
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* \sa SDL_HasSSE3
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* \sa SDL_HasSSE41
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* \sa SDL_HasSSE42
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasAVX512F(void);
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/**
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* Determine whether the CPU has ARM SIMD (ARMv6) features.
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*
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* This is different from ARM NEON, which is a different instruction set.
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*
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* This always returns false on CPUs that aren't using ARM instruction sets.
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*
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* \returns SDL_TRUE if the CPU has ARM SIMD features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_HasNEON
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasARMSIMD(void);
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/**
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* Determine whether the CPU has NEON (ARM SIMD) features.
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*
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* This always returns false on CPUs that aren't using ARM instruction sets.
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*
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* \returns SDL_TRUE if the CPU has ARM NEON features or SDL_FALSE if not.
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*
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* \since This function is available since SDL 3.0.0.
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasNEON(void);
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/**
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* Determine whether the CPU has LSX (LOONGARCH SIMD) features.
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*
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* This always returns false on CPUs that aren't using LOONGARCH instruction
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* sets.
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*
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* \returns SDL_TRUE if the CPU has LOONGARCH LSX features or SDL_FALSE if
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* not.
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*
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* \since This function is available since SDL 3.0.0.
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasLSX(void);
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/**
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* Determine whether the CPU has LASX (LOONGARCH SIMD) features.
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*
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* This always returns false on CPUs that aren't using LOONGARCH instruction
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* sets.
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*
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* \returns SDL_TRUE if the CPU has LOONGARCH LASX features or SDL_FALSE if
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* not.
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*
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* \since This function is available since SDL 3.0.0.
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*/
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extern DECLSPEC SDL_bool SDLCALL SDL_HasLASX(void);
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/**
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* Get the amount of RAM configured in the system.
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*
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* \returns the amount of RAM configured in the system in MiB.
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*
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* \since This function is available since SDL 3.0.0.
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*/
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extern DECLSPEC int SDLCALL SDL_GetSystemRAM(void);
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/**
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* Report the alignment this system needs for SIMD allocations.
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*
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* This will return the minimum number of bytes to which a pointer must be
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* aligned to be compatible with SIMD instructions on the current machine. For
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* example, if the machine supports SSE only, it will return 16, but if it
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* supports AVX-512F, it'll return 64 (etc). This only reports values for
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* instruction sets SDL knows about, so if your SDL build doesn't have
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* SDL_HasAVX512F(), then it might return 16 for the SSE support it sees and
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* not 64 for the AVX-512 instructions that exist but SDL doesn't know about.
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* Plan accordingly.
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*
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* \returns the alignment in bytes needed for available, known SIMD
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* instructions.
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*
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* \since This function is available since SDL 3.0.0.
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*
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* \sa SDL_aligned_alloc
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* \sa SDL_aligned_free
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*/
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extern DECLSPEC size_t SDLCALL SDL_SIMDGetAlignment(void);
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/* Ends C function definitions when using C++ */
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#ifdef __cplusplus
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}
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#endif
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#include <SDL3/SDL_close_code.h>
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#endif /* SDL_cpuinfo_h_ */
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