--
--  Copyright (C) 1988-1998 Altera Corporation
--  Any megafunction design, and related net list (encrypted or decrypted),
--  support information, device programming or simulation file, and any other
--  associated documentation or information provided by Altera or a partner
--  under Altera's Megafunction Partnership Program may be used only to
--  program PLD devices (but not masked PLD devices) from Altera.  Any other
--  use of such megafunction design, net list, support information, device
--  programming or simulation file, or any other related documentation or
--  information is prohibited for any other purpose, including, but not
--  limited to modification, reverse engineering, de-compiling, or use with
--  any other silicon devices, unless such use is explicitly licensed under
--  a separate agreement with Altera or a megafunction partner.  Title to
--  the intellectual property, including patents, copyrights, trademarks,
--  trade secrets, or maskworks, embodied in any such megafunction design,
--  net list, support information, device programming or simulation file, or
--  any other related documentation or information provided by Altera or a
--  megafunction partner, remains with Altera, the megafunction partner, or
--  their respective licensors.  No other licenses, including any licenses
--  needed under any third party's intellectual property, are provided herein.
--
CHIP sprint08
BEGIN
	DEVICE = EPF10K10QC208-4;
	|SINC_H :	OUTPUT_PIN = 175;
	|KBD_CLK :	BIDIR_PIN = 193;
	|KBD_DAT :	BIDIR_PIN = 196;
	|BEEPER :	OUTPUT_PIN = 192;
	|/WAIT :	BIDIR_PIN = 16;
	|/INT :	BIDIR_PIN = 197;
	|/NMI :	BIDIR_PIN = 195;
	|MXA10 :	BIDIR_PIN = 200;
	|MXA9 :	BIDIR_PIN = 199;
	|MXA8 :	BIDIR_PIN = 198;
	|MXA7 :	BIDIR_PIN = 187;
	|MXA6 :	BIDIR_PIN = 174;
	|MXA5 :	BIDIR_PIN = 172;
	|MXA4 :	BIDIR_PIN = 170;
	|MXA3 :	BIDIR_PIN = 169;
	|MXA2 :	BIDIR_PIN = 168;
	|MXA1 :	BIDIR_PIN = 167;
	|MXA0 :	BIDIR_PIN = 166;
	|/WE :	OUTPUT_PIN = 208;
	|CAS_3 :	OUTPUT_PIN = 207;
	|CAS_2 :	OUTPUT_PIN = 205;
	|CAS_1 :	OUTPUT_PIN = 206;
	|CAS_0 :	OUTPUT_PIN = 204;
	|RAS_0 :	OUTPUT_PIN = 203;
	|RAS_1 :	OUTPUT_PIN = 202;
	|MS_MOUSE :	INPUT_PIN = 191;
	|TAPE_OUT :	OUTPUT_PIN = 190;
	|TURBO_LED :	OUTPUT_PIN = 189;
	|SND_R1 :	OUTPUT_PIN = 176;
	|MD0 :	BIDIR_PIN = 186;
	|TAPE_IN :	INPUT_PIN = 182;
	|MD1 :	BIDIR_PIN = 180;
	|MD2 :	BIDIR_PIN = 179;
	|MD3 :	BIDIR_PIN = 177;
	|SINC :	OUTPUT_PIN = 173;
	|MD4 :	BIDIR_PIN = 164;
	|MD5 :	BIDIR_PIN = 163;
	|MD6 :	BIDIR_PIN = 162;
	|MD7 :	BIDIR_PIN = 161;
	|SND_L1 :	OUTPUT_PIN = 160;
	|SND_R0 :	OUTPUT_PIN = 159;
	|SND_L0 :	OUTPUT_PIN = 158;
	|CLK_PIX :	OUTPUT_PIN = 157;
	|VA0 :	OUTPUT_PIN = 133;
	|VA1 :	OUTPUT_PIN = 128;
	|V_CS0 :	OUTPUT_PIN = 127;
	|VA2 :	OUTPUT_PIN = 121;
	|VA10 :	OUTPUT_PIN = 120;
	|VA3 :	OUTPUT_PIN = 116;
	|VA4 :	OUTPUT_PIN = 112;
	|VA11 :	OUTPUT_PIN = 111;
	|VA5 :	OUTPUT_PIN = 104;
	|VA9 :	OUTPUT_PIN = 102;
	|VA6 :	OUTPUT_PIN = 100;
	|VA8 :	OUTPUT_PIN = 99;
	|VA7 :	OUTPUT_PIN = 96;
	|VA13 :	OUTPUT_PIN = 95;
	|V_WR3 :	OUTPUT_PIN = 94;
	|VA12 :	OUTPUT_PIN = 93;
	|V_WR0 :	OUTPUT_PIN = 92;
	|V_WR1 :	OUTPUT_PIN = 90;
	|V_WR2 :	OUTPUT_PIN = 89;
	|VA14 :	OUTPUT_PIN = 88;
	|VA15 :	OUTPUT_PIN = 86;
	|/MR :	INPUT_PIN = 184;
	|TG42 :	INPUT_PIN = 183;
	|VD03 :	BIDIR_PIN = 150;
	|VD13 :	BIDIR_PIN = 149;
	|VD02 :	BIDIR_PIN = 148;
	|VD04 :	BIDIR_PIN = 147;
	|VD14 :	BIDIR_PIN = 144;
	|VD01 :	BIDIR_PIN = 143;
	|VD05 :	BIDIR_PIN = 142;
	|VD15 :	BIDIR_PIN = 141;
	|VD00 :	BIDIR_PIN = 136;
	|VD06 :	BIDIR_PIN = 135;
	|VD16 :	BIDIR_PIN = 134;
	|VD07 :	BIDIR_PIN = 132;
	|VD17 :	BIDIR_PIN = 131;
	|VD12 :	BIDIR_PIN = 122;
	|VD11 :	BIDIR_PIN = 119;
	|VD10 :	BIDIR_PIN = 115;
	|VD22 :	BIDIR_PIN = 103;
	|VD21 :	BIDIR_PIN = 101;
	|VD20 :	BIDIR_PIN = 97;
	|VD23 :	BIDIR_PIN = 87;
	|VD24 :	BIDIR_PIN = 85;
	|VD30 :	BIDIR_PIN = 83;
	|/WR :	INPUT_PIN = 79;
	|/RD :	INPUT_PIN = 80;
	|/IO :	INPUT_PIN = 78;
	|VD37 :	BIDIR_PIN = 75;
	|VD25 :	BIDIR_PIN = 74;
	|VD27 :	BIDIR_PIN = 73;
	|VD36 :	BIDIR_PIN = 71;
	|VD26 :	BIDIR_PIN = 70;
	|VD31 :	BIDIR_PIN = 69;
	|VD35 :	BIDIR_PIN = 68;
	|VD32 :	BIDIR_PIN = 67;
	|VD34 :	BIDIR_PIN = 65;
	|VD33 :	BIDIR_PIN = 64;
	|V_CS1 :	OUTPUT_PIN = 63;
	|CLKZ1 :	OUTPUT_PIN = 62;
	|D7 :	BIDIR_PIN = 61;
	|D6 :	BIDIR_PIN = 60;
	|D5 :	BIDIR_PIN = 58;
	|D4 :	BIDIR_PIN = 57;
	|D3 :	BIDIR_PIN = 56;
	|D2 :	BIDIR_PIN = 55;
	|D1 :	BIDIR_PIN = 54;
	|D0 :	BIDIR_PIN = 53;
	|A15 :	BIDIR_PIN = 47;
	|A14 :	BIDIR_PIN = 46;
	|A13 :	BIDIR_PIN = 45;
	|A12 :	BIDIR_PIN = 44;
	|A11 :	BIDIR_PIN = 41;
	|A10 :	BIDIR_PIN = 40;
	|A9 :	BIDIR_PIN = 39;
	|A8 :	BIDIR_PIN = 38;
	|A7 :	BIDIR_PIN = 31;
	|A6 :	BIDIR_PIN = 30;
	|A5 :	BIDIR_PIN = 29;
	|A4 :	BIDIR_PIN = 28;
	|A3 :	BIDIR_PIN = 27;
	|A2 :	BIDIR_PIN = 26;
	|A1 :	BIDIR_PIN = 25;
	|A0 :	BIDIR_PIN = 24;
	|/RF :	INPUT_PIN = 19;
	|/M1 :	INPUT_PIN = 18;
	|/RESET :	BIDIR_PIN = 17;
	|XA2 :	OUTPUT_PIN = 12;
	|XA1 :	OUTPUT_PIN = 11;
	|XA0 :	OUTPUT_PIN = 10;
	|XACS :	OUTPUT_PIN = 13;
END;

DEFAULT_DEVICES
BEGIN
	AUTO_DEVICE = EPF10K50GC403;
	AUTO_DEVICE = EPF10K50GC403ES;
	AUTO_DEVICE = EPF10K50RC240;
	AUTO_DEVICE = EPF10K30RC240;
	AUTO_DEVICE = EPF10K10QC208;
	ASK_BEFORE_ADDING_EXTRA_DEVICES = ON;
END;

TIMING_POINT
BEGIN
	DEVICE_FOR_TIMING_SYNTHESIS = EPF10K10QC208-4;
	CUT_ALL_CLEAR_PRESET = ON;
	CUT_ALL_BIDIR = ON;
	MAINTAIN_STABLE_SYNTHESIS = OFF;
END;

IGNORED_ASSIGNMENTS
BEGIN
	IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF;
	IGNORE_CHIP_ASSIGNMENTS = OFF;
	DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF;
	IGNORE_DEVICE_ASSIGNMENTS = OFF;
	IGNORE_LC_ASSIGNMENTS = OFF;
	IGNORE_PIN_ASSIGNMENTS = OFF;
	IGNORE_TIMING_ASSIGNMENTS = OFF;
	IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF;
	IGNORE_CLIQUE_ASSIGNMENTS = OFF;
END;

LOGIC_OPTIONS
BEGIN
	|ALU0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU5 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU6 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU7 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU8 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU9 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU13 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU14 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|ALU15 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q13 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q20 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q21 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q22 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q23 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q30 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q31 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q32 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|AY_Q33 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|MXA0 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA1 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA4 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA3 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA2 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA6 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA5 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA8 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA7 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA9 :	IGNORE_SOFT_BUFFERS = ON;
	|MXA10 :	IGNORE_SOFT_BUFFERS = ON;
	|SVA10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|SVA11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|SVA12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|V_WR0 :	SLOW_SLEW_RATE = OFF;
	|V_WR1 :	SLOW_SLEW_RATE = OFF;
	|V_WR2 :	SLOW_SLEW_RATE = OFF;
	|V_WR3 :	SLOW_SLEW_RATE = OFF;
	|VA0 :	SLOW_SLEW_RATE = OFF;
	|VA1 :	SLOW_SLEW_RATE = OFF;
	|VA2 :	SLOW_SLEW_RATE = OFF;
	|VA3 :	SLOW_SLEW_RATE = OFF;
	|VA4 :	SLOW_SLEW_RATE = OFF;
	|VA5 :	SLOW_SLEW_RATE = OFF;
	|VA6 :	SLOW_SLEW_RATE = OFF;
	|VA7 :	SLOW_SLEW_RATE = OFF;
	|VA8 :	SLOW_SLEW_RATE = OFF;
	|VA9 :	SLOW_SLEW_RATE = OFF;
	|VA10 :	SLOW_SLEW_RATE = OFF;
	|VA11 :	SLOW_SLEW_RATE = OFF;
	|VA12 :	SLOW_SLEW_RATE = OFF;
	|VA13 :	SLOW_SLEW_RATE = OFF;
	|VA14 :	SLOW_SLEW_RATE = OFF;
	|VA15 :	SLOW_SLEW_RATE = OFF;
	|SVA2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|RA18 :	IMPLEMENT_IN_EAB = ON;
	|RA19 :	IMPLEMENT_IN_EAB = ON;
	|RA20 :	IMPLEMENT_IN_EAB = ON;
	|RA21 :	IMPLEMENT_IN_EAB = ON;
	|VA0 :	FAST_IO = ON;
	|VA1 :	FAST_IO = ON;
	|VA2 :	FAST_IO = ON;
	|VA4 :	FAST_IO = ON;
	|VA3 :	FAST_IO = ON;
	|VA6 :	FAST_IO = ON;
	|VA5 :	FAST_IO = ON;
	|VA8 :	FAST_IO = ON;
	|VA7 :	FAST_IO = ON;
	|VA10 :	FAST_IO = ON;
	|VA9 :	FAST_IO = ON;
	|VA12 :	FAST_IO = ON;
	|VA11 :	FAST_IO = ON;
	|VA13 :	FAST_IO = ON;
	|VA14 :	FAST_IO = ON;
	|VA15 :	FAST_IO = ON;
	|VXA0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA5 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA6 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA7 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA8 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA9 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA10 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA11 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA12 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA13 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA14 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA15 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA16 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|VXA17 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|SVA0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|SVA1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|SVA3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|SVA4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|SVA5 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|MPGS0 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|MPGS1 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|MPGS2 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|MPGS3 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
	|MPGS4 :	IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON;
END;

GLOBAL_PROJECT_DEVICE_OPTIONS
BEGIN
	FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON;
	FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF;
	FLEX6000_ENABLE_JTAG = OFF;
	CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL;
	LOW_VOLTAGE_IO = OFF;
	nCEO = UNRESERVED;
	CONFIG_SCHEME_10K = PASSIVE_SERIAL;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	CONFIG_SCHEME = PASSIVE_PARALLEL_SYNCHRONOUS;
	DISABLE_TIME_OUT = ON;
	RELEASE_CLEARS = ON;
	AUTO_RESTART = ON;
	SDOUT = UNRESERVED;
	DATA0 = UNRESERVED;
	MAX7000S_USER_CODE = FFFF;
	FLEX10K_JTAG_USER_CODE = 7F;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	ENABLE_CHIP_WIDE_OE = OFF;
	ENABLE_CHIP_WIDE_RESET = OFF;
	CLKUSR = UNRESERVED;
	ADD17 = UNRESERVED;
	ADD16 = UNRESERVED;
	ADD15 = UNRESERVED;
	ADD14 = UNRESERVED;
	ADD13 = UNRESERVED;
	ADD0_TO_ADD12 = UNRESERVED;
	RDCLK = UNRESERVED;
	RDYnBUSY = UNRESERVED;
	nWS_nRS_nCS_CS = UNRESERVED;
	DATA1_TO_DATA7 = UNRESERVED;
	FLEX8000_ENABLE_JTAG = OFF;
	MAX7000S_ENABLE_JTAG = OFF;
	ENABLE_DCLK_OUTPUT = OFF;
	USER_CLOCK = OFF;
	SECURITY_BIT = OFF;
	RESERVED_PINS_PERCENT = 0;
	RESERVED_LCELLS_PERCENT = 0;
END;

GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
BEGIN
	OPTIMIZE_FOR_SPEED = 0;
	AUTO_REGISTER_PACKING = OFF;
	AUTO_FAST_IO = ON;
	AUTO_GLOBAL_OE = ON;
	AUTO_GLOBAL_PRESET = ON;
	AUTO_GLOBAL_CLEAR = ON;
	AUTO_GLOBAL_CLOCK = ON;
	AUTO_IMPLEMENT_IN_EAB = OFF;
	AUTO_OPEN_DRAIN_PINS = ON;
	DEVICE_FAMILY = FLEX10K;
	ONE_HOT_STATE_MACHINE_ENCODING = OFF;
	STYLE = NORMAL;
	MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF;
	MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF;
END;

COMPILER_PROCESSING_CONFIGURATION
BEGIN
	FITTER_SETTINGS = ADVANCED;
	SMART_RECOMPILE = ON;
	GENERATE_AHDL_TDO_FILE = OFF;
	TIMING_SNF_EXTRACTOR = OFF;
	OPTIMIZE_TIMING_SNF = OFF;
	PRESERVE_ALL_NODE_NAME_SYNONYMS = ON;
	RPT_FILE_USER_ASSIGNMENTS = ON;
	RPT_FILE_LCELL_INTERCONNECT = ON;
	RPT_FILE_HIERARCHY = ON;
	RPT_FILE_EQUATIONS = ON;
	LINKED_SNF_EXTRACTOR = OFF;
	FUNCTIONAL_SNF_EXTRACTOR = OFF;
	DESIGN_DOCTOR_RULES = EPLD;
	DESIGN_DOCTOR = OFF;
END;

COMPILER_INTERFACES_CONFIGURATION
BEGIN
	VHDL_FLATTEN_BUS = OFF;
	VERILOG_FLATTEN_BUS = OFF;
	EDIF_TRUNCATE_HIERARCHY_PATH = OFF;
	VHDL_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_TRUNCATE_HIERARCHY_PATH = OFF;
	VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_BUS_DELIMITERS = [];
	EDIF_FLATTEN_BUS = OFF;
	VHDL_WRITER_VERSION = VHDL87;
	VHDL_READER_VERSION = VHDL87;
	SYNOPSYS_MAPPING_EFFORT = MEDIUM;
	SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF;
	SYNOPSYS_HIERARCHICAL_COMPILATION = ON;
	SYNOPSYS_DESIGNWARE = OFF;
	SYNOPSYS_COMPILER = DESIGN;
	USE_SYNOPSYS_SYNTHESIS = OFF;
	NETLIST_OUTPUT_TIME_SCALE = 0.1ns;
	EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF;
	EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF;
	EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF;
	EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF;
	EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE;
	EDIF_OUTPUT_USE_EDC = OFF;
	EDIF_INPUT_USE_LMF2 = OFF;
	EDIF_INPUT_USE_LMF1 = OFF;
	EDIF_OUTPUT_GND = GND;
	EDIF_OUTPUT_VCC = VCC;
	EDIF_INPUT_GND = GND;
	EDIF_INPUT_VCC = VCC;
	EDIF_OUTPUT_EDC_FILE = *.edc;
	EDIF_INPUT_LMF2 = *.lmf;
	EDIF_INPUT_LMF1 = *.lmf;
	VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF;
	VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE;
	VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE;
	VHDL_NETLIST_WRITER = OFF;
	VERILOG_NETLIST_WRITER = OFF;
	XNF_GENERATE_AHDL_TDX_FILE = ON;
	XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON;
	XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC;
	EDIF_OUTPUT_VERSION = 200;
	EDIF_NETLIST_WRITER = OFF;
END;

CUSTOM_DESIGN_DOCTOR_RULES
BEGIN
	MASTER_RESET = OFF;
	EXPANDER_NETWORKS = ON;
	RACE_CONDITIONS = ON;
	DELAY_CHAINS = ON;
	ASYNCHRONOUS_INPUTS = ON;
	PRESET_CLEAR_NETWORKS = ON;
	STATIC_HAZARDS_AFTER_SYNTHESIS = OFF;
	STATIC_HAZARDS_BEFORE_SYNTHESIS = ON;
	MULTI_CLOCK_NETWORKS = ON;
	MULTI_LEVEL_CLOCKS = ON;
	GATED_CLOCKS = ON;
	RIPPLE_CLOCKS = ON;
END;

SIMULATOR_CONFIGURATION
BEGIN
	END_TIME = 0.0ns;
	START_TIME = 0.0ns;
	GLITCH_TIME = 0.0ns;
	GLITCH = OFF;
	OSCILLATION_TIME = 0.0ns;
	OSCILLATION = OFF;
	CHECK_OUTPUTS = OFF;
	SETUP_HOLD = OFF;
	USE_DEVICE = OFF;
END;

TIMING_ANALYZER_CONFIGURATION
BEGIN
	REGISTERED_PERFORMANCE_OPTIONS = FREQUENCY_OF_PATHS;
	LIST_PATH_FREQUENCY = 42.01MHz;
	LIST_PATH_COUNT = 10;
	INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms;
	INCLUDE_PATHS_LESS_THAN = OFF;
	INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns;
	INCLUDE_PATHS_GREATER_THAN = OFF;
	DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS;
	CELL_WIDTH = 18;
	LIST_ONLY_LONGEST_PATH = ON;
	CUT_OFF_CLEAR_AND_PRESET_PATHS = ON;
	CUT_OFF_IO_PIN_FEEDBACK = ON;
	AUTO_RECALCULATE = OFF;
	ANALYSIS_MODE = DELAY_MATRIX;
END;

OTHER_CONFIGURATION
BEGIN
	ROW_PINS_PERCENT = 95;
	CARRY_OUT_PINS_LCELL_INSERT = OFF;
	LAST_MAXPLUS2_VERSION = 8.2;
	LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100;
	ROW_PINS_LCELL_INSERT = ON;
	NORMAL_LCELL_INSERT = ON;
	COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,0,0,1,1,1";
	FLEX_10K_52_COLUMNS = 40;
	EXPLICIT_FAMILY = 1;
	DEFAULT_9K_EXP_PER_LCELL = 1/2;
	LCELLS_PER_ROW_PERCENT = 100;
	FAN_IN_PER_LCELL_PERCENT = 100;
	EXP_PER_LCELL_PERCENT = 100;
	ORIGINAL_MAXPLUS2_VERSION = 6.0;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000
BEGIN
	REGISTER_OPTIMIZATION = ON;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
	MINIMIZATION = FULL;
	FAST_IO = OFF;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000
BEGIN
	CARRY_CHAIN = AUTO;
	CARRY_CHAIN_LENGTH = 32;
	SLOW_SLEW_RATE = ON;
	CASCADE_CHAIN = AUTO;
	IGNORE_SOFT_BUFFERS = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	DECOMPOSE_GATES = ON;
	REGISTER_OPTIMIZATION = ON;
	DUPLICATE_LOGIC_EXTRACTION = ON;
	MINIMIZATION = FULL;
	CASCADE_CHAIN_LENGTH = 2;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = ON;
	REFACTORIZATION = ON;
	NOT_GATE_PUSH_BACK = ON;
	REDUCE_LOGIC = ON;
	SOFT_BUFFER_INSERTION = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000
BEGIN
	IGNORE_SOFT_BUFFERS = OFF;
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000
BEGIN
	IGNORE_SOFT_BUFFERS = OFF;
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	PARALLEL_EXPANDERS = ON;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = ON;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC
BEGIN
	IGNORE_SOFT_BUFFERS = OFF;
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	FAST_IO = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000
BEGIN
	IGNORE_SOFT_BUFFERS = OFF;
	REGISTER_OPTIMIZATION = ON;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = ON;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = ON;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = FULL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = AUTO;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = AUTO;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000
BEGIN
	IGNORE_SOFT_BUFFERS = OFF;
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000
BEGIN
	IGNORE_SOFT_BUFFERS = OFF;
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC
BEGIN
	IGNORE_SOFT_BUFFERS = OFF;
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = ON;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = ON;
	SOFT_BUFFER_INSERTION = OFF;
	FAST_IO = OFF;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = ON;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = -1;
	CARRY_CHAIN = IGNORE;
	CASCADE_CHAIN_LENGTH = -1;
	CASCADE_CHAIN = IGNORE;
END;

DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000
BEGIN
	REGISTER_OPTIMIZATION = OFF;
	USE_LPM_FOR_AHDL_OPERATORS = OFF;
	RESYNTHESIZE_NETWORK = OFF;
	MULTI_LEVEL_FACTORING = OFF;
	SUBFACTOR_EXTRACTION = OFF;
	REFACTORIZATION = OFF;
	NOT_GATE_PUSH_BACK = ON;
	DUPLICATE_LOGIC_EXTRACTION = OFF;
	REDUCE_LOGIC = OFF;
	DECOMPOSE_GATES = OFF;
	SOFT_BUFFER_INSERTION = ON;
	IGNORE_SOFT_BUFFERS = ON;
	PARALLEL_EXPANDERS = OFF;
	TURBO_BIT = OFF;
	XOR_SYNTHESIS = OFF;
	SLOW_SLEW_RATE = OFF;
	MINIMIZATION = PARTIAL;
	CARRY_CHAIN_LENGTH = 32;
	CARRY_CHAIN = MANUAL;
	CASCADE_CHAIN_LENGTH = 2;
	CASCADE_CHAIN = MANUAL;
END;

