Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 08/05/2024 18:38:47

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


SINC_controller


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

sp037032  EPM7064SLC44-10  16       16       0      35      40          54 %

User Pins:                 16       16       0  



Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Line 63, File c:\prj\sprinter\firmware\97\max\sp037032.tdf:
   Symbolic name "MXX" was declared but never used
Warning: Line 53, File c:\prj\sprinter\firmware\97\max\sp037032.tdf:
   Symbolic name "CLKZZ1" was declared but never used
Warning: Line 58, File c:\prj\sprinter\firmware\97\max\sp037032.tdf:
   Symbolic name "TB_WG" was declared but never used
Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.


Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

sp037032@27                       CLK_PRC
sp037032@33                       CLK_WG
sp037032@31                       CLKZZ
sp037032@44                       CNF_ON
sp037032@40                       /CONFIG
sp037032@34                       /DTRB
sp037032@18                       D0
sp037032@1                        EPM_RES
sp037032@11                       HD_CSS1
sp037032@12                       HD_CSS2
sp037032@9                        HD_CS1
sp037032@37                       HD_CS2
sp037032@26                       HDD_CS
sp037032@8                        HD_OE1
sp037032@5                        HD_OE2
sp037032@6                        HD_WE1
sp037032@4                        HD_WE2
sp037032@29                       /IO
sp037032@39                       MA0
sp037032@36                       MA7
sp037032@28                       /MR
sp037032@14                       QDAT
sp037032@2                        /RD
sp037032@16                       RDAT
sp037032@17                       RDATA
sp037032@21                       RSTB
sp037032@19                       STE
sp037032@43                       TG42_IN
sp037032@41                       TG42_OUT
sp037032@25                       /WR
sp037032@24                       /WRH
sp037032@20                       WSTB


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

***** Logic for device 'sp037032' compiled without errors.




Device: EPM7064SLC44-10

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = ON
    Enable JTAG Support                        = ON
    User Code                                  = ffff



Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** ERROR SUMMARY **

Info: Chip 'sp037032' in device 'EPM7064SLC44-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                         T     
                             E     T     G  /  
              H  H  H        P  C  G     4  C  
              D  D  D        M  N  4     2  O  
              _  _  _        _  F  2     _  N  
              W  O  W  V  /  R  _  _  G  O  F  
              E  E  E  C  R  E  O  I  N  U  I  
              1  2  2  C  D  S  N  N  D  T  G  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
    #TDI |  7                                39 | MA0 
  HD_OE1 |  8                                38 | #TDO 
  HD_CS1 |  9                                37 | HD_CS2 
     GND | 10                                36 | MA7 
 HD_CSS1 | 11                                35 | VCC 
 HD_CSS2 | 12        EPM7064SLC44-10         34 | /DTRB 
    #TMS | 13                                33 | CLK_WG 
    QDAT | 14                                32 | #TCK 
     VCC | 15                                31 | CLKZZ 
    RDAT | 16                                30 | GND 
   RDATA | 17                                29 | /IO 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              D  S  W  R  G  V  /  /  H  C  /  
              0  T  S  S  N  C  W  W  D  L  M  
                 E  T  T  D  C  R  R  D  K  R  
                    B  B        H     _  _     
                                      C  P     
                                      S  R     
                                         C     
                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    16/16(100%)   8/ 8(100%)  13/16( 81%)  22/36( 61%) 
B:    LC17 - LC32     8/16( 50%)   8/ 8(100%)  16/16(100%)  15/36( 41%) 
C:    LC33 - LC48     6/16( 37%)   8/ 8(100%)  13/16( 81%)  16/36( 44%) 
D:    LC49 - LC64     5/16( 31%)   8/ 8(100%)   3/16( 18%)  11/36( 30%) 


Total dedicated input pins used:                 4/4      (100%)
Total I/O pins used:                            32/32     (100%)
Total logic cells used:                         35/64     ( 54%)
Total shareable expanders used:                 40/64     ( 62%)
Total Turbo logic cells used:                   23/64     ( 35%)
Total shareable expanders not available (n/a):   5/64     (  7%)
Average fan-in:                                  4.65
Total fan-in:                                   163

Total input pins required:                      16
Total fast input logic cells required:           0
Total output pins required:                     16
Total bidirectional pins required:               0
Total reserved pins required                     4
Total logic cells required:                     35
Total flipflops required:                       20
Total product terms required:                  126
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          38

Synthesized logic cells:                         1/  64   (  1%)



Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  44      -   -       INPUT               0      0   0    0    0    2    8  CNF_ON
  34   (51)  (D)      INPUT               0      0   0    0    0    0    2  /DTRB
  18   (21)  (B)      INPUT               0      0   0    0    0    0    1  D0
   1      -   -       INPUT               0      0   0    0    0    1    0  EPM_RES
  26   (36)  (C)      INPUT               0      0   0    0    0   10    1  HDD_CS
  29   (41)  (C)      INPUT               0      0   0    0    0    5    5  /IO
  39   (57)  (D)      INPUT               0      0   0    0    0    4    0  MA0
  36   (52)  (D)      INPUT               0      0   0    0    0    3    0  MA7
  28   (40)  (C)      INPUT               0      0   0    0    0    3    1  /MR
   2      -   -       INPUT               0      0   0    0    0    4    6  /RD
  17   (24)  (B)      INPUT               0      0   0    0    0    0    2  RDATA
  21   (17)  (B)      INPUT               0      0   0    0    0    0    1  RSTB
  19   (20)  (B)      INPUT               0      0   0    0    0    0    1  STE
  43      -   -       INPUT               0      0   0    0    0    2    1  TG42_IN
  25   (35)  (C)      INPUT               0      0   0    0    0    6    1  /WR
  20   (19)  (B)      INPUT               0      0   0    0    0    0    1  WSTB


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  27     37    C         FF      t        2      2   0    0    2    1    1  CLK_PRC
  33     49    D         FF      t        2      2   0    0    4    2    1  CLK_WG
  31     46    C     TRI/FF      t        2      2   0    1    2    1    3  CLKZZ
  40     62    D     OUTPUT               0      0   0    5    0    0    5  /CONFIG
  11      3    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS1
  12      1    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS2
   9      4    A     OUTPUT               0      0   0    2    0    0    0  HD_CS1
  37     53    D     OUTPUT               0      0   0    1    1    0    0  HD_CS2
   8      5    A     OUTPUT               4      4   0    6    2    0    0  HD_OE1
   5     14    A     OUTPUT               4      4   0    5    1    0    0  HD_OE2
   6     11    A     OUTPUT               0      0   0    4    0    0    0  HD_WE1
   4     16    A     OUTPUT               4      4   0    4    0    0    0  HD_WE2
  14     30    B     OUTPUT      t        0      0   0    1    2    0    0  QDAT
  16     25    B     OUTPUT      t        0      0   0    1    2    0    0  RDAT
  41     64    D     OUTPUT      t        1      0   0    1    0    0    0  TG42_OUT
  24     33    C         FF               1      0   0    5    1    3    0  /WRH


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   -     12    A       DFFE      t        3      2   1    3    5    2    2  CODE0
   -      9    A       DFFE      t        2      2   0    2    3    0    1  CODE1
  (7)     8    A       DFFE      t        2      2   0    2    3    0    2  CODE2
   -     13    A       DFFE      t        2      2   0    2    3    0    1  CODE3
   -     15    A       DFFE      t        2      2   0    2    3    0    1  CODE4
 (26)    36    C       TFFE      t        5      0   0    4    2    2    2  CT_WG
   -     34    C       TFFE      t        3      0   0    1    2    0    8  CT_WG1
 (25)    35    C       TFFE      t        2      2   0    1    1    1    0  CT0
 (36)    52    D       TFFE      t        2      2   0    0    3    1    0  STWG1
   -      7    A       TFFE      t        1      0   1    1    7    0    5  WGR0
 (20)    19    B       DFFE      t        5      1   1    1    8    0    6  WGR1
   -     22    B       TFFE      t        8      1   0    1    7    0    6  WGR2
   -      6    A       DFFE      t        4      0   1    1    7    0    6  WGR3
 (21)    17    B       TFFE      t        0      0   0    1    7    1    0  WGR4
   -      2    A      LCELL               0      0   0    5    0    1    5  10K_CLK
   -     18    B      LCELL               0      0   0    1    1    1    7  10K_D0
   -     23    B       DFFE      t        4      4   0    1    2    1    6  :97
 (17)    24    B       DFFE      t        4      4   0    1    1    0    1  :98
   -     10    A       SOFT    s t        1      0   1    1    5    0    1  ~389~1


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                         Logic cells placed in LAB 'A'
        +------------------------------- LC12 CODE0
        | +----------------------------- LC9 CODE1
        | | +--------------------------- LC8 CODE2
        | | | +------------------------- LC13 CODE3
        | | | | +----------------------- LC15 CODE4
        | | | | | +--------------------- LC3 HD_CSS1
        | | | | | | +------------------- LC1 HD_CSS2
        | | | | | | | +----------------- LC4 HD_CS1
        | | | | | | | | +--------------- LC5 HD_OE1
        | | | | | | | | | +------------- LC14 HD_OE2
        | | | | | | | | | | +----------- LC11 HD_WE1
        | | | | | | | | | | | +--------- LC16 HD_WE2
        | | | | | | | | | | | | +------- LC7 WGR0
        | | | | | | | | | | | | | +----- LC6 WGR3
        | | | | | | | | | | | | | | +--- LC2 10K_CLK
        | | | | | | | | | | | | | | | +- LC10 ~389~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'A':
LC12 -> * * - - - - - - * * - - - - - - | * - - - | <-- CODE0
LC9  -> - - * - - - - - - - - - - - - - | * - - - | <-- CODE1
LC8  -> * - - * - - - - - - - - - - - - | * - - - | <-- CODE2
LC13 -> - - - - * - - - - - - - - - - - | * - - - | <-- CODE3
LC7  -> - - - - - - - - - - - - * * - - | * * - - | <-- WGR0
LC6  -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR3
LC2  -> * * * * * - - - - - - - - - - - | * * - - | <-- 10K_CLK

Pin
44   -> * - - - - - - - - - - - * * * * | * * - - | <-- CNF_ON
1    -> - - - - - - - - - - - - - - - - | - - - * | <-- EPM_RES
26   -> - - - - - * * * * * * * - - * - | * - * * | <-- HDD_CS
29   -> * * * * * - - - * * * * - - - - | * - * - | <-- /IO
39   -> - - - - - - - - * * - * - - - - | * - * - | <-- MA0
36   -> - - - - - * * - - - - - - - - - | * - - * | <-- MA7
28   -> - - - - - - - - * * - - - - * - | * - - * | <-- /MR
2    -> * * * * * - - - * * * - - - * - | * - * - | <-- /RD
43   -> - - - - - - - - - - - - - - - - | - - * * | <-- TG42_IN
25   -> - - - - - - - * * - * * - - * - | * - * * | <-- /WR
LC62 -> * * * * * - - - - - - - - - - - | * - - - | <-- /CONFIG
LC34 -> - - - - - - - - - - - - * * - - | * * * - | <-- CT_WG1
LC19 -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR1
LC22 -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR2
LC33 -> - - - - - - - - * - - - - - - - | * - * * | <-- /WRH
LC18 -> * - - - - - - - - - - - * * - * | * * - - | <-- 10K_D0
LC23 -> - - - - - - - - - - - - * * - * | * * - - | <-- :97


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC30 QDAT
        | +------------- LC25 RDAT
        | | +----------- LC19 WGR1
        | | | +--------- LC22 WGR2
        | | | | +------- LC17 WGR4
        | | | | | +----- LC18 10K_D0
        | | | | | | +--- LC23 :97
        | | | | | | | +- LC24 :98
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC19 -> - - * * * - - - | * * - - | <-- WGR1
LC22 -> - - * * * - - - | * * - - | <-- WGR2
LC17 -> * - - - * - - - | - * - - | <-- WGR4
LC18 -> - * * * * - - - | * * - - | <-- 10K_D0
LC23 -> - * * * * - - - | * * - - | <-- :97
LC24 -> - - - - - - * - | - * - - | <-- :98

Pin
44   -> * * * * * - - - | * * - - | <-- CNF_ON
18   -> - - - - - * - - | - * - - | <-- D0
1    -> - - - - - - - - | - - - * | <-- EPM_RES
2    -> - - - - - - - - | * - * - | <-- /RD
17   -> - - - - - - * * | - * - - | <-- RDATA
43   -> - - - - - - - - | - - * * | <-- TG42_IN
LC15 -> - - - - - * - - | - * - - | <-- CODE4
LC34 -> - - * * * - * * | * * * - | <-- CT_WG1
LC7  -> - - * * * - - - | * * - - | <-- WGR0
LC6  -> - - * * * - - - | * * - - | <-- WGR3
LC2  -> * - - - - - - - | * * - - | <-- 10K_CLK
LC10 -> - - * - - - - - | - * - - | <-- ~389~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                     Logic cells placed in LAB 'C'
        +----------- LC37 CLK_PRC
        | +--------- LC46 CLKZZ
        | | +------- LC36 CT_WG
        | | | +----- LC34 CT_WG1
        | | | | +--- LC35 CT0
        | | | | | +- LC33 /WRH
        | | | | | | 
        | | | | | |   Other LABs fed by signals
        | | | | | |   that feed LAB 'C'
LC      | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC46 -> - * * * * - | - - * - | <-- CLKZZ
LC36 -> * - * - - - | - - * * | <-- CT_WG
LC34 -> - - - * - - | * * * - | <-- CT_WG1
LC35 -> - * - - * - | - - * - | <-- CT0
LC33 -> - - - - - * | * - * * | <-- /WRH

Pin
44   -> - - - - - - | * * - - | <-- CNF_ON
34   -> - - * * - - | - - * - | <-- /DTRB
1    -> - - - - - - | - - - * | <-- EPM_RES
26   -> - - - - - * | * - * * | <-- HDD_CS
29   -> - - - - - * | * - * - | <-- /IO
39   -> - - - - - * | * - * - | <-- MA0
2    -> - - - - - * | * - * - | <-- /RD
21   -> - - * - - - | - - * - | <-- RSTB
19   -> - - * - - - | - - * - | <-- STE
43   -> - * - - * - | - - * * | <-- TG42_IN
25   -> - - - - - * | * - * * | <-- /WR
20   -> - - * - - - | - - * - | <-- WSTB
LC49 -> * - - - - - | - - * * | <-- CLK_WG


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                   Logic cells placed in LAB 'D'
        +--------- LC49 CLK_WG
        | +------- LC62 /CONFIG
        | | +----- LC53 HD_CS2
        | | | +--- LC52 STWG1
        | | | | +- LC64 TG42_OUT
        | | | | | 
        | | | | |   Other LABs fed by signals
        | | | | |   that feed LAB 'D'
LC      | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC49 -> * - - * - | - - * * | <-- CLK_WG
LC52 -> * - - * - | - - - * | <-- STWG1

Pin
44   -> - - - - - | * * - - | <-- CNF_ON
1    -> - * - - - | - - - * | <-- EPM_RES
26   -> - * * - - | * - * * | <-- HDD_CS
36   -> - * - - - | * - - * | <-- MA7
28   -> - * - - - | * - - * | <-- /MR
2    -> - - - - - | * - * - | <-- /RD
43   -> - - - - * | - - * * | <-- TG42_IN
25   -> - * - - - | * - * * | <-- /WR
LC37 -> * - - * - | - - - * | <-- CLK_PRC
LC36 -> * - - * - | - - * * | <-- CT_WG
LC33 -> - - * - - | * - * * | <-- /WRH


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp037032.rpt
sp037032

** EQUATIONS **

CNF_ON   : INPUT;
D0       : INPUT;
EPM_RES  : INPUT;
HDD_CS   : INPUT;
MA0      : INPUT;
MA7      : INPUT;
RDATA    : INPUT;
RSTB     : INPUT;
STE      : INPUT;
TG42_IN  : INPUT;
WSTB     : INPUT;
/DTRB    : INPUT;
/IO      : INPUT;
/MR      : INPUT;
/RD      : INPUT;
/WR      : INPUT;

-- Node name is 'CLK_PRC' = 'STWG0' from file "sp037032.tdf" line 54, column 6
-- Equation name is 'CLK_PRC', location is LC037, type is output.
 CLK_PRC = TFFE( VCC,  _EQ001,  VCC,  VCC,  VCC);
  _EQ001 =  _X001 &  _X002;
  _X001  = EXP(!CLK_WG & !CT_WG);
  _X002  = EXP( CLK_WG &  CT_WG);

-- Node name is 'CLK_WG' = 'STWG2' from file "sp037032.tdf" line 54, column 6
-- Equation name is 'CLK_WG', location is LC049, type is output.
 CLK_WG  = TFFE( _EQ002,  _EQ003,  VCC,  VCC,  VCC);
  _EQ002 =  CLK_PRC &  STWG1;
  _EQ003 =  _X001 &  _X002;
  _X001  = EXP(!CLK_WG & !CT_WG);
  _X002  = EXP( CLK_WG &  CT_WG);

-- Node name is 'CLKZZ' = 'CT1' from file "sp037032.tdf" line 52, column 4
-- Equation name is 'CLKZZ', location is LC046, type is output.
CLKZZ    = TRI(CT1, !CNF_ON);
CT1      = TFFE( CT0,  _EQ004,  VCC,  VCC,  VCC);
  _EQ004 =  _X003 &  _X004;
  _X003  = EXP( CT1 & !TG42_IN);
  _X004  = EXP(!CT1 &  TG42_IN);

-- Node name is 'CODE0' from file "sp037032.tdf" line 59, column 6
-- Equation name is 'CODE0', location is LC012, type is buried.
CODE0    = DFFE( _EQ005 $  GND,  10K_CLK, !_EQ006,  VCC,  VCC);
  _EQ005 = !CNF_ON &  CODE2 & !10K_D0
         # !CNF_ON & !CODE2 &  10K_D0
         #  CNF_ON & !CODE0;
  _EQ006 =  _X005 &  _X006;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);

-- Node name is 'CODE1' from file "sp037032.tdf" line 59, column 6
-- Equation name is 'CODE1', location is LC009, type is buried.
CODE1    = DFFE( CODE0 $  GND,  10K_CLK, !_EQ007,  VCC,  VCC);
  _EQ007 =  _X005 &  _X006;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);

-- Node name is 'CODE2' from file "sp037032.tdf" line 59, column 6
-- Equation name is 'CODE2', location is LC008, type is buried.
CODE2    = DFFE( CODE1 $  GND,  10K_CLK, !_EQ008,  VCC,  VCC);
  _EQ008 =  _X005 &  _X006;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);

-- Node name is 'CODE3' from file "sp037032.tdf" line 59, column 6
-- Equation name is 'CODE3', location is LC013, type is buried.
CODE3    = DFFE( CODE2 $  GND,  10K_CLK, !_EQ009,  VCC,  VCC);
  _EQ009 =  _X005 &  _X006;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);

-- Node name is 'CODE4' from file "sp037032.tdf" line 59, column 6
-- Equation name is 'CODE4', location is LC015, type is buried.
CODE4    = DFFE( CODE3 $  GND,  10K_CLK, !_EQ010,  VCC,  VCC);
  _EQ010 =  _X005 &  _X006;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);

-- Node name is 'CT_WG' from file "sp037032.tdf" line 116, column 11
-- Equation name is 'CT_WG', location is LC036, type is buried.
CT_WG    = TFFE( VCC,  _EQ011,  VCC,  VCC,  VCC);
  _EQ011 =  _X007 &  _X008 &  _X009;
  _X007  = EXP(!CT_WG & !CT1);
  _X008  = EXP( CT_WG &  CT1 &  _X010);
  _X009  = EXP(!CT1 & !/DTRB & !STE &  _X011);
  _X010  = EXP(!/DTRB & !STE &  _X011);
  _X011  = EXP(!RSTB & !WSTB &  _X010);

-- Node name is 'CT_WG1' from file "sp037032.tdf" line 118, column 12
-- Equation name is 'CT_WG1', location is LC034, type is buried.
CT_WG1   = TFFE( VCC,  _EQ012,  VCC,  VCC,  VCC);
  _EQ012 =  _X012 &  _X013 &  _X014;
  _X012  = EXP(!CT_WG1 & !CT1);
  _X013  = EXP( CT_WG1 &  CT1 &  /DTRB);
  _X014  = EXP(!CT1 & !/DTRB);

-- Node name is 'CT0' from file "sp037032.tdf" line 52, column 4
-- Equation name is 'CT0', location is LC035, type is buried.
CT0      = TFFE( VCC,  _EQ013,  VCC,  VCC,  VCC);
  _EQ013 =  _X003 &  _X004;
  _X003  = EXP( CT1 & !TG42_IN);
  _X004  = EXP(!CT1 &  TG42_IN);

-- Node name is 'HD_CSS1' 
-- Equation name is 'HD_CSS1', location is LC003, type is output.
 HD_CSS1 = LCELL( _EQ014 $  VCC);
  _EQ014 = !HDD_CS & !MA7;

-- Node name is 'HD_CSS2' 
-- Equation name is 'HD_CSS2', location is LC001, type is output.
 HD_CSS2 = LCELL( _EQ015 $  VCC);
  _EQ015 = !HDD_CS &  MA7;

-- Node name is 'HD_CS1' 
-- Equation name is 'HD_CS1', location is LC004, type is output.
 HD_CS1  = LCELL( _EQ016 $  VCC);
  _EQ016 = !HDD_CS & !/WR;

-- Node name is 'HD_CS2' = ':107' from file "sp037032.tdf" line 206, column 12
-- Equation name is 'HD_CS2', type is output 
 HD_CS2  = LCELL( _EQ017 $  VCC);
  _EQ017 = !HDD_CS & !/WRH;

-- Node name is 'HD_OE1' 
-- Equation name is 'HD_OE1', location is LC005, type is output.
 HD_OE1  = LCELL( _EQ018 $  VCC);
  _EQ018 = !HDD_CS & !/IO &  MA0 & !/WR &  /WRH &  _X015
         # !HDD_CS & !/IO &  MA0 & !/RD &  _X015
         #  CODE0 & !HDD_CS & !/MR & !/RD;
  _X015  = EXP( _X016);
  _X016  = EXP( _X017);
  _X017  = EXP( _X018);
  _X018  = EXP(!HDD_CS);

-- Node name is 'HD_OE2' 
-- Equation name is 'HD_OE2', location is LC014, type is output.
 HD_OE2  = LCELL( _EQ019 $  VCC);
  _EQ019 = !HDD_CS & !/IO & !MA0 & !/RD &  _X015
         # !CODE0 & !HDD_CS & !/MR & !/RD;
  _X015  = EXP( _X016);
  _X016  = EXP( _X017);
  _X017  = EXP( _X018);
  _X018  = EXP(!HDD_CS);

-- Node name is 'HD_WE1' 
-- Equation name is 'HD_WE1', location is LC011, type is output.
 HD_WE1  = LCELL( _EQ020 $  VCC);
  _EQ020 = !HDD_CS & !/IO & !/WR
         # !HDD_CS & !/IO & !/RD;

-- Node name is 'HD_WE2' 
-- Equation name is 'HD_WE2', location is LC016, type is output.
 HD_WE2  = LCELL( _EQ021 $  VCC);
  _EQ021 = !HDD_CS & !/IO &  MA0 & !/WR &  _X015;
  _X015  = EXP( _X016);
  _X016  = EXP( _X017);
  _X017  = EXP( _X018);
  _X018  = EXP(!HDD_CS);

-- Node name is 'QDAT' 
-- Equation name is 'QDAT', location is LC030, type is output.
 QDAT    = LCELL( _EQ022 $  GND);
  _EQ022 =  CNF_ON &  WGR4
         # !CNF_ON &  10K_CLK;

-- Node name is 'RDAT' 
-- Equation name is 'RDAT', location is LC025, type is output.
 RDAT    = LCELL( _EQ023 $  GND);
  _EQ023 =  CNF_ON &  _LC023
         # !CNF_ON &  10K_D0;

-- Node name is 'STWG1' from file "sp037032.tdf" line 54, column 6
-- Equation name is 'STWG1', location is LC052, type is buried.
STWG1    = TFFE( CLK_PRC,  _EQ024,  VCC,  VCC,  VCC);
  _EQ024 =  _X001 &  _X002;
  _X001  = EXP(!CLK_WG & !CT_WG);
  _X002  = EXP( CLK_WG &  CT_WG);

-- Node name is 'TG42_OUT' 
-- Equation name is 'TG42_OUT', location is LC064, type is output.
 TG42_OUT = LCELL( _EQ025 $  GND);
  _EQ025 =  _X019;
  _X019  = EXP( TG42_IN);

-- Node name is 'WGR0' from file "sp037032.tdf" line 55, column 5
-- Equation name is 'WGR0', location is LC007, type is buried.
WGR0     = TFFE( _EQ026,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ026 =  WGR0 &  WGR1 &  WGR2 & !WGR3
         # !WGR0 & !WGR1 & !WGR2 &  WGR3
         #  CNF_ON &  _LC023
         # !CNF_ON &  10K_D0;

-- Node name is 'WGR1' from file "sp037032.tdf" line 55, column 5
-- Equation name is 'WGR1', location is LC019, type is buried.
WGR1     = DFFE( _EQ027 $  _EQ028,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ027 =  CNF_ON & !_LC010 &  _LC023 & !WGR0 & !WGR1 &  WGR2 &  _X020 & 
              _X021 &  _X022 &  _X023
         # !CNF_ON & !_LC010 & !WGR0 & !WGR1 &  WGR2 &  _X020 &  _X021 & 
              _X022 &  _X023 &  10K_D0
         #  CNF_ON & !_LC010 &  _LC023 &  WGR0 &  WGR1 &  _X020 &  _X021 & 
              _X022 &  _X023;
  _X020  = EXP(!CNF_ON &  WGR0 &  WGR1 &  10K_D0);
  _X021  = EXP(!CNF_ON & !WGR1 & !WGR2 & !10K_D0);
  _X022  = EXP( WGR0 &  WGR1 & !WGR3);
  _X023  = EXP(!WGR0 & !WGR1 &  WGR3);
  _EQ028 = !_LC010 &  _X020 &  _X021 &  _X022 &  _X023;
  _X020  = EXP(!CNF_ON &  WGR0 &  WGR1 &  10K_D0);
  _X021  = EXP(!CNF_ON & !WGR1 & !WGR2 & !10K_D0);
  _X022  = EXP( WGR0 &  WGR1 & !WGR3);
  _X023  = EXP(!WGR0 & !WGR1 &  WGR3);

-- Node name is 'WGR2' from file "sp037032.tdf" line 55, column 5
-- Equation name is 'WGR2', location is LC022, type is buried.
WGR2     = TFFE(!_EQ029,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ029 =  _X020 &  _X024 &  _X025 &  _X026 &  _X027 &  _X028 &  _X029 & 
              _X030;
  _X020  = EXP(!CNF_ON &  WGR0 &  WGR1 &  10K_D0);
  _X024  = EXP(!CNF_ON &  WGR1 &  WGR2 & !WGR3 & !10K_D0);
  _X025  = EXP( CNF_ON & !_LC023 &  WGR1 &  WGR2 & !WGR3);
  _X026  = EXP( CNF_ON &  _LC023 &  WGR0 &  WGR1);
  _X027  = EXP( WGR0 &  WGR1 &  WGR2 & !WGR3);
  _X028  = EXP( CNF_ON & !_LC023 & !WGR2 & !WGR3);
  _X029  = EXP(!_LC023 & !WGR2 & !WGR3 & !10K_D0);
  _X030  = EXP(!CNF_ON & !WGR2 & !WGR3 & !10K_D0);

-- Node name is 'WGR3' from file "sp037032.tdf" line 55, column 5
-- Equation name is 'WGR3', location is LC006, type is buried.
WGR3     = DFFE( _EQ030 $  _EQ031,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ030 =  CNF_ON &  _LC023 &  WGR0 &  WGR1 &  WGR2 &  WGR3 &  _X031 & 
              _X032 &  _X033
         # !CNF_ON &  WGR0 &  WGR1 &  WGR2 &  WGR3 &  _X031 &  _X032 &  _X033 & 
              10K_D0
         #  CNF_ON &  _LC023 & !WGR0 & !WGR3 &  _X031 &  _X032 &  _X033;
  _X031  = EXP(!WGR1 & !WGR3);
  _X032  = EXP(!CNF_ON & !WGR0 & !WGR3 &  10K_D0);
  _X033  = EXP(!WGR2 & !WGR3);
  _EQ031 =  _X031 &  _X032 &  _X033;
  _X031  = EXP(!WGR1 & !WGR3);
  _X032  = EXP(!CNF_ON & !WGR0 & !WGR3 &  10K_D0);
  _X033  = EXP(!WGR2 & !WGR3);

-- Node name is 'WGR4' from file "sp037032.tdf" line 55, column 5
-- Equation name is 'WGR4', location is LC017, type is buried.
WGR4     = TFFE( _EQ032,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ032 =  CNF_ON &  _LC023 &  WGR0 &  WGR1 &  WGR2 &  WGR3
         # !CNF_ON &  WGR0 &  WGR1 &  WGR2 &  WGR3 &  10K_D0;

-- Node name is '10K_CLK' from file "sp037032.tdf" line 77, column 13
-- Equation name is '10K_CLK', location is LC002, type is buried.
10K_CLK  = LCELL( _EQ033 $  VCC);
  _EQ033 =  CNF_ON & !HDD_CS & !/MR & !/RD
         # !CNF_ON & !/MR & !/WR;

-- Node name is '10K_D0' from file "sp037032.tdf" line 89, column 12
-- Equation name is '10K_D0', location is LC018, type is buried.
10K_D0   = LCELL( CODE4 $  D0);

-- Node name is '/CONFIG' = ':115' from file "sp037032.tdf" line 282, column 12
-- Equation name is '/CONFIG', type is output 
 /CONFIG = LCELL( _EQ034 $  EPM_RES);
  _EQ034 =  EPM_RES & !HDD_CS & !MA7 & !/MR & !/WR;

-- Node name is '/WRH' = ':114' from file "sp037032.tdf" line 233, column 9
-- Equation name is '/WRH', type is output 
 /WRH    = DFFE( _EQ035 $  VCC,  _EQ036, !_EQ037,  VCC,  VCC);
  _EQ035 =  MA0 & !/WRH;
  _EQ036 =  _X034;
  _X034  = EXP(!HDD_CS & !/IO & !/WR);
  _EQ037 = !/IO & !/RD;

-- Node name is ':97' from file "sp037032.tdf" line 162, column 9
-- Equation name is '_LC023', type is buried 
_LC023   = DFFE( _EQ038 $  VCC,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ038 =  _LC024 &  _X035 &  _X036;
  _X035  = EXP(!CT_WG1 &  RDATA);
  _X036  = EXP( _X037 &  _X038);
  _X037  = EXP(!CT_WG1 & !RDATA);
  _X038  = EXP( _X035 &  _X036);

-- Node name is ':98' from file "sp037032.tdf" line 162, column 25
-- Equation name is '_LC024', type is buried 
_LC024   = DFFE( _EQ039 $  GND,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ039 =  _X038;
  _X038  = EXP( _X035 &  _X036);
  _X035  = EXP(!CT_WG1 &  RDATA);
  _X036  = EXP( _X037 &  _X038);
  _X037  = EXP(!CT_WG1 & !RDATA);

-- Node name is '~389~1' from file "sp037032.tdf" line 149, column 14
-- Equation name is '~389~1', location is LC010, type is buried.
-- synthesized logic cell 
_LC010   = LCELL( _EQ040 $  GND);
  _EQ040 =  CNF_ON & !_LC023 &  WGR1 & !WGR3
         #  CNF_ON & !_LC023 & !WGR1 &  WGR3
         # !CNF_ON &  WGR1 & !WGR3 & !10K_D0
         #  CNF_ON & !_LC023 & !WGR1 & !WGR2
         # !CNF_ON & !WGR1 &  WGR3 & !10K_D0;



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs C, D
--    _X002 occurs in LABs C, D




Project Information               c:\prj\sprinter\firmware\97\max\sp037032.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = off
      Automatic Global Clear              = off
      Automatic Global Preset             = off
      Automatic Global Output Enable      = off
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 0

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = ADVANCED
Smart Recompile                           = on
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,985K
