Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 08/05/2024 18:38:05

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


SINC_controller


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

sp047032  EPM7032LC44-12   17       18       0      32      27          100%

User Pins:                 17       18       0  



Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt

** PROJECT COMPILATION MESSAGES **

Warning: Line 62, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
   Symbolic name "MXX" was declared but never used
Warning: Line 30, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
   Symbolic name "/RTSB" was declared but never used
Warning: Line 52, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
   Symbolic name "CLKZZ1" was declared but never used
Warning: Line 57, File c:\prj\sprinter\firmware\97\max\sp047032.tdf:
   Symbolic name "TB_WG" was declared but never used
Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.
Info: Reserved unused input pin '/RTSB' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board


Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'CNF_ON' chosen for auto global Output Enable


Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt

** PIN/LOCATION/CHIP ASSIGNMENTS **

                  Actual                  
    User       Assignments                
Assignments   (if different)     Node Name

sp047032@27                       CLK_PRC
sp047032@13                       CLK_WG
sp047032@31                       CLKZZ
sp047032@44                       CNF_ON
sp047032@40                       /CONFIG
sp047032@34                       /DTRB
sp047032@18                       D0
sp047032@1                        EPM_RES
sp047032@11                       HD_CSS1
sp047032@12                       HD_CSS2
sp047032@9                        HD_CS1
sp047032@7                        HD_CS2
sp047032@26                       HDD_CS
sp047032@8                        HD_OE1
sp047032@5                        HD_OE2
sp047032@6                        HD_WE1
sp047032@4                        HD_WE2
sp047032@29                       /IO
sp047032@39                       MA0
sp047032@36                       MA7
sp047032@28                       /MR
sp047032@14                       QDAT
sp047032@32                       /RD
sp047032@16                       RDAT
sp047032@17                       RDATA
sp047032@21                       RSTB
sp047032@33                       /RTSB
sp047032@19                       STE
sp047032@43                       TG42_IN
sp047032@41                       TG42_OUT
sp047032@25                       /WR
sp047032@24                       /WRH
sp047032@20                       WSTB
sp047032@38                       10K_CLK
sp047032@37                       10K_D0


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

***** Logic for device 'sp047032' compiled without errors.




Device: EPM7032LC44-12

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = ON



Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** ERROR SUMMARY **

Info: Chip 'sp047032' in device 'EPM7032LC44-12' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
Info: Chip 'sp047032' in device 'EPM7032LC44-12' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
                                         T     
                             E     T     G  /  
              H  H  H        P  C  G     4  C  
              D  D  D        M  N  4     2  O  
              _  _  _        _  F  2     _  N  
              W  O  W  V  G  R  _  _  G  O  F  
              E  E  E  C  N  E  O  I  N  U  I  
              1  2  2  C  D  S  N  N  D  T  G  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
  HD_CS2 |  7                                39 | MA0 
  HD_OE1 |  8                                38 | 10K_CLK 
  HD_CS1 |  9                                37 | 10K_D0 
     GND | 10                                36 | MA7 
 HD_CSS1 | 11                                35 | VCC 
 HD_CSS2 | 12         EPM7032LC44-12         34 | /DTRB 
  CLK_WG | 13                                33 | /RTSB 
    QDAT | 14                                32 | /RD 
     VCC | 15                                31 | CLKZZ 
    RDAT | 16                                30 | GND 
   RDATA | 17                                29 | /IO 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              D  S  W  R  G  V  /  /  H  C  /  
              0  T  S  S  N  C  W  W  D  L  M  
                 E  T  T  D  C  R  R  D  K  R  
                    B  B        H     _  _     
                                      C  P     
                                      S  R     
                                         C     
                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    16/16(100%)  16/16(100%)  15/16( 93%)  26/36( 72%) 
B:    LC17 - LC32    16/16(100%)  16/16(100%)  14/16( 87%)  31/36( 86%) 


Total dedicated input pins used:                 3/4      ( 75%)
Total I/O pins used:                            32/32     (100%)
Total logic cells used:                         32/32     (100%)
Total shareable expanders used:                 27/32     ( 84%)
Total Turbo logic cells used:                   20/32     ( 62%)
Total shareable expanders not available (n/a):   2/32     (  6%)
Average fan-in:                                  4.50
Total fan-in:                                   144

Total input pins required:                      17
Total output pins required:                     18
Total bidirectional pins required:               0
Total logic cells required:                     32
Total flipflops required:                       21
Total product terms required:                  104
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          25

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  44      -   -       INPUT  G            0      0   0    0    0    1    1  CNF_ON
  34   (23)  (B)      INPUT               0      0   0    0    0    0    2  /DTRB
  18   (13)  (A)      INPUT               0      0   0    0    0    1    0  D0
   1      -   -       INPUT               0      0   0    0    0    1    0  EPM_RES
  26   (30)  (B)      INPUT               0      0   0    0    0   11    5  HDD_CS
  29   (27)  (B)      INPUT               0      0   0    0    0    4    5  /IO
  39   (19)  (B)      INPUT               0      0   0    0    0    4    0  MA0
  36   (22)  (B)      INPUT               0      0   0    0    0    3    0  MA7
  28   (28)  (B)      INPUT               0      0   0    0    0    4    0  /MR
  32   (25)  (B)      INPUT               0      0   0    0    0    5    5  /RD
  17   (12)  (A)      INPUT               0      0   0    0    0    1    1  RDATA
  21   (16)  (A)      INPUT               0      0   0    0    0    0    1  RSTB
  33   (24)  (B)      INPUT               0      0   0    0    0    0    0  /RTSB
  19   (14)  (A)      INPUT               0      0   0    0    0    0    1  STE
  43      -   -       INPUT               0      0   0    0    0    2    1  TG42_IN
  25   (31)  (B)      INPUT               0      0   0    0    0    7    0  /WR
  20   (15)  (A)      INPUT               0      0   0    0    0    0    1  WSTB


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  27     29    B         FF      t        2      2   0    0    2    1    1  CLK_PRC
  13      9    A         FF      t        2      2   0    0    4    2    1  CLK_WG
  31     26    B     TRI/FF      t        2      2   0    1    2    1    3  CLKZZ
  40     18    B     OUTPUT               0      0   0    5    0    0    5  /CONFIG
  11      7    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS1
  12      8    A     OUTPUT               0      0   0    2    0    0    0  HD_CSS2
   9      6    A     OUTPUT               0      0   0    2    0    0    0  HD_CS1
   7      4    A     OUTPUT               0      0   0    1    1    0    0  HD_CS2
   8      5    A     OUTPUT               4      4   0    6    2    0    0  HD_OE1
   5      2    A     OUTPUT               4      4   0    5    1    0    0  HD_OE2
   6      3    A         FF               0      0   0    3    0    0    0  HD_WE1
   4      1    A     OUTPUT               4      4   0    4    0    0    0  HD_WE2
  14     10    A         FF      t        0      0   0    0    6    0    0  QDAT
  16     11    A         FF      t        4      4   0    1    2    1    4  RDAT
  41     17    B     OUTPUT      t        1      0   0    1    0    0    0  TG42_OUT
  24     32    B         FF               1      0   0    5    1    3    0  /WRH
  38     20    B     OUTPUT               0      0   0    5    0    0    5  10K_CLK
  37     21    B     OUTPUT               0      0   0    1    1    0    1  10K_D0


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (26)    30    B       DFFE      t        4      3   1    4    5    2    2  CODE0
 (34)    23    B       DFFE      t        3      3   0    3    3    0    1  CODE1
 (36)    22    B       DFFE      t        3      3   0    3    3    0    2  CODE2
 (25)    31    B       DFFE      t        3      3   0    3    3    0    1  CODE3
 (29)    27    B       DFFE      t        3      3   0    3    3    1    0  CODE4
 (18)    13    A       TFFE      t        5      0   0    4    2    2    2  CT_WG
 (32)    25    B       TFFE      t        3      0   0    1    2    2    6  CT_WG1
 (28)    28    B       TFFE      t        2      2   0    1    1    1    0  CT0
 (19)    14    A       TFFE      t        2      2   0    0    3    1    0  STWG1
 (33)    24    B       TFFE      t        0      0   0    0    6    1    4  WGR0
 (39)    19    B       TFFE      t        1      0   1    0    6    1    4  WGR1
 (17)    12    A       TFFE      t        0      0   0    0    6    1    4  WGR2
 (20)    15    A       TFFE      t        0      0   0    0    6    1    4  WGR3
 (21)    16    A       DFFE      t        4      4   0    1    1    1    0  :99


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'A':

                                         Logic cells placed in LAB 'A'
        +------------------------------- LC9 CLK_WG
        | +----------------------------- LC13 CT_WG
        | | +--------------------------- LC7 HD_CSS1
        | | | +------------------------- LC8 HD_CSS2
        | | | | +----------------------- LC6 HD_CS1
        | | | | | +--------------------- LC4 HD_CS2
        | | | | | | +------------------- LC5 HD_OE1
        | | | | | | | +----------------- LC2 HD_OE2
        | | | | | | | | +--------------- LC3 HD_WE1
        | | | | | | | | | +------------- LC1 HD_WE2
        | | | | | | | | | | +----------- LC10 QDAT
        | | | | | | | | | | | +--------- LC11 RDAT
        | | | | | | | | | | | | +------- LC14 STWG1
        | | | | | | | | | | | | | +----- LC12 WGR2
        | | | | | | | | | | | | | | +--- LC15 WGR3
        | | | | | | | | | | | | | | | +- LC16 :99
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'A'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'A':
LC9  -> * - - - - - - - - - - - * - - - | * * | <-- CLK_WG
LC13 -> * * - - - - - - - - - - * - - - | * * | <-- CT_WG
LC11 -> - - - - - - - - - - * - - * * - | * * | <-- RDAT
LC14 -> * - - - - - - - - - - - * - - - | * - | <-- STWG1
LC12 -> - - - - - - - - - - * - - * * - | * * | <-- WGR2
LC15 -> - - - - - - - - - - * - - * * - | * * | <-- WGR3
LC16 -> - - - - - - - - - - - * - - - - | * - | <-- :99

Pin
44   -> - - - - - - - - - - - - - - - - | - * | <-- CNF_ON
34   -> - * - - - - - - - - - - - - - - | * * | <-- /DTRB
1    -> - - - - - - - - - - - - - - - - | - * | <-- EPM_RES
26   -> - - * * * * * * * * - - - - - - | * * | <-- HDD_CS
29   -> - - - - - - * * - * - - - - - - | * * | <-- /IO
39   -> - - - - - - * * - * - - - - - - | * * | <-- MA0
36   -> - - * * - - - - - - - - - - - - | * * | <-- MA7
28   -> - - - - - - * * - - - - - - - - | * * | <-- /MR
32   -> - - - - - - * * * - - - - - - - | * * | <-- /RD
17   -> - - - - - - - - - - - * - - - * | * - | <-- RDATA
21   -> - * - - - - - - - - - - - - - - | * - | <-- RSTB
19   -> - * - - - - - - - - - - - - - - | * - | <-- STE
43   -> - - - - - - - - - - - - - - - - | - * | <-- TG42_IN
25   -> - - - - * - * - * * - - - - - - | * * | <-- /WR
20   -> - * - - - - - - - - - - - - - - | * - | <-- WSTB
LC29 -> * - - - - - - - - - - - * - - - | * - | <-- CLK_PRC
LC26 -> - * - - - - - - - - - - - - - - | * * | <-- CLKZZ
LC30 -> - - - - - - * * - - - - - - - - | * * | <-- CODE0
LC25 -> - - - - - - - - - - * * - * * * | * * | <-- CT_WG1
LC24 -> - - - - - - - - - - * - - * * - | * * | <-- WGR0
LC19 -> - - - - - - - - - - * - - * * - | * * | <-- WGR1
LC32 -> - - - - - * * - - - - - - - - - | * * | <-- /WRH


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                         Logic cells placed in LAB 'B'
        +------------------------------- LC29 CLK_PRC
        | +----------------------------- LC26 CLKZZ
        | | +--------------------------- LC30 CODE0
        | | | +------------------------- LC23 CODE1
        | | | | +----------------------- LC22 CODE2
        | | | | | +--------------------- LC31 CODE3
        | | | | | | +------------------- LC27 CODE4
        | | | | | | | +----------------- LC18 /CONFIG
        | | | | | | | | +--------------- LC25 CT_WG1
        | | | | | | | | | +------------- LC28 CT0
        | | | | | | | | | | +----------- LC17 TG42_OUT
        | | | | | | | | | | | +--------- LC24 WGR0
        | | | | | | | | | | | | +------- LC19 WGR1
        | | | | | | | | | | | | | +----- LC32 /WRH
        | | | | | | | | | | | | | | +--- LC20 10K_CLK
        | | | | | | | | | | | | | | | +- LC21 10K_D0
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC26 -> - * - - - - - - * * - - - - - - | * * | <-- CLKZZ
LC30 -> - - * * - - - - - - - - - - - - | * * | <-- CODE0
LC23 -> - - - - * - - - - - - - - - - - | - * | <-- CODE1
LC22 -> - - * - - * - - - - - - - - - - | - * | <-- CODE2
LC31 -> - - - - - - * - - - - - - - - - | - * | <-- CODE3
LC27 -> - - - - - - - - - - - - - - - * | - * | <-- CODE4
LC18 -> - - * * * * * - - - - - - - - - | - * | <-- /CONFIG
LC25 -> - - - - - - - - * - - * * - - - | * * | <-- CT_WG1
LC28 -> - * - - - - - - - * - - - - - - | - * | <-- CT0
LC24 -> - - - - - - - - - - - * * - - - | * * | <-- WGR0
LC19 -> - - - - - - - - - - - * * - - - | * * | <-- WGR1
LC32 -> - - - - - - - - - - - - - * - - | * * | <-- /WRH
LC20 -> - - * * * * * - - - - - - - - - | - * | <-- 10K_CLK
LC21 -> - - * - - - - - - - - - - - - - | - * | <-- 10K_D0

Pin
44   -> - - * - - - - - - - - - - - * - | - * | <-- CNF_ON
34   -> - - - - - - - - * - - - - - - - | * * | <-- /DTRB
18   -> - - - - - - - - - - - - - - - * | - * | <-- D0
1    -> - - - - - - - * - - - - - - - - | - * | <-- EPM_RES
26   -> - - * * * * * * - - - - - * * - | * * | <-- HDD_CS
29   -> - - * * * * * - - - - - - * - - | * * | <-- /IO
39   -> - - - - - - - - - - - - - * - - | * * | <-- MA0
36   -> - - - - - - - * - - - - - - - - | * * | <-- MA7
28   -> - - - - - - - * - - - - - - * - | * * | <-- /MR
32   -> - - * * * * * - - - - - - * * - | * * | <-- /RD
43   -> - * - - - - - - - * * - - - - - | - * | <-- TG42_IN
25   -> - - - - - - - * - - - - - * * - | * * | <-- /WR
LC9  -> * - - - - - - - - - - - - - - - | * * | <-- CLK_WG
LC13 -> * - - - - - - - - - - - - - - - | * * | <-- CT_WG
LC11 -> - - - - - - - - - - - * * - - - | * * | <-- RDAT
LC12 -> - - - - - - - - - - - * * - - - | * * | <-- WGR2
LC15 -> - - - - - - - - - - - * * - - - | * * | <-- WGR3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:      c:\prj\sprinter\firmware\97\max\sp047032.rpt
sp047032

** EQUATIONS **

CNF_ON   : INPUT;
D0       : INPUT;
EPM_RES  : INPUT;
HDD_CS   : INPUT;
MA0      : INPUT;
MA7      : INPUT;
RDATA    : INPUT;
RSTB     : INPUT;
STE      : INPUT;
TG42_IN  : INPUT;
WSTB     : INPUT;
/DTRB    : INPUT;
/IO      : INPUT;
/MR      : INPUT;
/RD      : INPUT;
/RTSB    : INPUT;
/WR      : INPUT;

-- Node name is 'CLK_PRC' = 'STWG0' from file "sp047032.tdf" line 53, column 6
-- Equation name is 'CLK_PRC', location is LC029, type is output.
 CLK_PRC = TFFE( VCC,  _EQ001,  VCC,  VCC,  VCC);
  _EQ001 =  _X001 &  _X002;
  _X001  = EXP(!CLK_WG & !CT_WG);
  _X002  = EXP( CLK_WG &  CT_WG);

-- Node name is 'CLK_WG' = 'STWG2' from file "sp047032.tdf" line 53, column 6
-- Equation name is 'CLK_WG', location is LC009, type is output.
 CLK_WG  = TFFE( _EQ002,  _EQ003,  VCC,  VCC,  VCC);
  _EQ002 =  CLK_PRC &  STWG1;
  _EQ003 =  _X001 &  _X002;
  _X001  = EXP(!CLK_WG & !CT_WG);
  _X002  = EXP( CLK_WG &  CT_WG);

-- Node name is 'CLKZZ' = 'CT1' from file "sp047032.tdf" line 51, column 4
-- Equation name is 'CLKZZ', location is LC026, type is output.
CLKZZ    = TRI(CT1, GLOBAL(!CNF_ON));
CT1      = TFFE( CT0,  _EQ004,  VCC,  VCC,  VCC);
  _EQ004 =  _X003 &  _X004;
  _X003  = EXP( CT1 & !TG42_IN);
  _X004  = EXP(!CT1 &  TG42_IN);

-- Node name is 'CODE0' from file "sp047032.tdf" line 58, column 6
-- Equation name is 'CODE0', location is LC030, type is buried.
CODE0    = DFFE( _EQ005 $  GND,  10K_CLK, !_EQ006,  VCC,  VCC);
  _EQ005 = !CNF_ON &  CODE2 & !10K_D0
         # !CNF_ON & !CODE2 &  10K_D0
         #  CNF_ON & !CODE0;
  _EQ006 =  _X005 &  _X006 &  _X007;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);
  _X007  = EXP( /CONFIG &  HDD_CS);

-- Node name is 'CODE1' from file "sp047032.tdf" line 58, column 6
-- Equation name is 'CODE1', location is LC023, type is buried.
CODE1    = DFFE( CODE0 $  GND,  10K_CLK, !_EQ007,  VCC,  VCC);
  _EQ007 =  _X005 &  _X006 &  _X007;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);
  _X007  = EXP( /CONFIG &  HDD_CS);

-- Node name is 'CODE2' from file "sp047032.tdf" line 58, column 6
-- Equation name is 'CODE2', location is LC022, type is buried.
CODE2    = DFFE( CODE1 $  GND,  10K_CLK, !_EQ008,  VCC,  VCC);
  _EQ008 =  _X005 &  _X006 &  _X007;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);
  _X007  = EXP( /CONFIG &  HDD_CS);

-- Node name is 'CODE3' from file "sp047032.tdf" line 58, column 6
-- Equation name is 'CODE3', location is LC031, type is buried.
CODE3    = DFFE( CODE2 $  GND,  10K_CLK, !_EQ009,  VCC,  VCC);
  _EQ009 =  _X005 &  _X006 &  _X007;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);
  _X007  = EXP( /CONFIG &  HDD_CS);

-- Node name is 'CODE4' from file "sp047032.tdf" line 58, column 6
-- Equation name is 'CODE4', location is LC027, type is buried.
CODE4    = DFFE( CODE3 $  GND,  10K_CLK, !_EQ010,  VCC,  VCC);
  _EQ010 =  _X005 &  _X006 &  _X007;
  _X005  = EXP( /CONFIG &  /RD);
  _X006  = EXP( /CONFIG &  /IO);
  _X007  = EXP( /CONFIG &  HDD_CS);

-- Node name is 'CT_WG' from file "sp047032.tdf" line 113, column 11
-- Equation name is 'CT_WG', location is LC013, type is buried.
CT_WG    = TFFE( VCC,  _EQ011,  VCC,  VCC,  VCC);
  _EQ011 =  _X008 &  _X009 &  _X010;
  _X008  = EXP(!CT_WG & !CT1);
  _X009  = EXP( CT_WG &  CT1 &  _X011);
  _X010  = EXP(!CT1 & !/DTRB & !STE &  _X012);
  _X011  = EXP(!/DTRB & !STE &  _X012);
  _X012  = EXP(!RSTB & !WSTB &  _X011);

-- Node name is 'CT_WG1' from file "sp047032.tdf" line 115, column 12
-- Equation name is 'CT_WG1', location is LC025, type is buried.
CT_WG1   = TFFE( VCC,  _EQ012,  VCC,  VCC,  VCC);
  _EQ012 =  _X013 &  _X014 &  _X015;
  _X013  = EXP(!CT_WG1 & !CT1);
  _X014  = EXP( CT_WG1 &  CT1 &  /DTRB);
  _X015  = EXP(!CT1 & !/DTRB);

-- Node name is 'CT0' from file "sp047032.tdf" line 51, column 4
-- Equation name is 'CT0', location is LC028, type is buried.
CT0      = TFFE( VCC,  _EQ013,  VCC,  VCC,  VCC);
  _EQ013 =  _X003 &  _X004;
  _X003  = EXP( CT1 & !TG42_IN);
  _X004  = EXP(!CT1 &  TG42_IN);

-- Node name is 'HD_CSS1' 
-- Equation name is 'HD_CSS1', location is LC007, type is output.
 HD_CSS1 = LCELL( _EQ014 $  VCC);
  _EQ014 = !HDD_CS & !MA7;

-- Node name is 'HD_CSS2' 
-- Equation name is 'HD_CSS2', location is LC008, type is output.
 HD_CSS2 = LCELL( _EQ015 $  VCC);
  _EQ015 = !HDD_CS &  MA7;

-- Node name is 'HD_CS1' 
-- Equation name is 'HD_CS1', location is LC006, type is output.
 HD_CS1  = LCELL( _EQ016 $  VCC);
  _EQ016 = !HDD_CS & !/WR;

-- Node name is 'HD_CS2' = ':108' from file "sp047032.tdf" line 196, column 12
-- Equation name is 'HD_CS2', type is output 
 HD_CS2  = LCELL( _EQ017 $  VCC);
  _EQ017 = !HDD_CS & !/WRH;

-- Node name is 'HD_OE1' 
-- Equation name is 'HD_OE1', location is LC005, type is output.
 HD_OE1  = LCELL( _EQ018 $  VCC);
  _EQ018 = !HDD_CS & !/IO &  MA0 & !/WR &  /WRH &  _X016
         # !HDD_CS & !/IO &  MA0 & !/RD &  _X016
         #  CODE0 & !HDD_CS & !/MR & !/RD;
  _X016  = EXP( _X017);
  _X017  = EXP( _X018);
  _X018  = EXP( _X019);
  _X019  = EXP(!HDD_CS);

-- Node name is 'HD_OE2' 
-- Equation name is 'HD_OE2', location is LC002, type is output.
 HD_OE2  = LCELL( _EQ019 $  VCC);
  _EQ019 = !HDD_CS & !/IO & !MA0 & !/RD &  _X016
         # !CODE0 & !HDD_CS & !/MR & !/RD;
  _X016  = EXP( _X017);
  _X017  = EXP( _X018);
  _X018  = EXP( _X019);
  _X019  = EXP(!HDD_CS);

-- Node name is 'HD_WE1' = ':115' from file "sp047032.tdf" line 211, column 12
-- Equation name is 'HD_WE1', type is output 
 HD_WE1  = DFFE( GND $  GND, !HDD_CS,  VCC, !_EQ020,  VCC);
  _EQ020 =  /RD &  /WR;

-- Node name is 'HD_WE2' 
-- Equation name is 'HD_WE2', location is LC001, type is output.
 HD_WE2  = LCELL( _EQ021 $  VCC);
  _EQ021 = !HDD_CS & !/IO &  MA0 & !/WR &  _X016;
  _X016  = EXP( _X017);
  _X017  = EXP( _X018);
  _X018  = EXP( _X019);
  _X019  = EXP(!HDD_CS);

-- Node name is 'QDAT' = 'WGR4' from file "sp047032.tdf" line 54, column 5
-- Equation name is 'QDAT', location is LC010, type is output.
 QDAT    = TFFE( _EQ022,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ022 =  RDAT &  WGR0 &  WGR1 &  WGR2 &  WGR3;

-- Node name is 'RDAT' = ':98' from file "sp047032.tdf" line 153, column 9
-- Equation name is 'RDAT', type is output 
 RDAT    = DFFE( _EQ023 $  VCC,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ023 =  _LC016 &  _X020 &  _X021;
  _X020  = EXP(!CT_WG1 &  RDATA);
  _X021  = EXP( _X022 &  _X023);
  _X022  = EXP(!CT_WG1 & !RDATA);
  _X023  = EXP( _X020 &  _X021);

-- Node name is 'STWG1' from file "sp047032.tdf" line 53, column 6
-- Equation name is 'STWG1', location is LC014, type is buried.
STWG1    = TFFE( CLK_PRC,  _EQ024,  VCC,  VCC,  VCC);
  _EQ024 =  _X001 &  _X002;
  _X001  = EXP(!CLK_WG & !CT_WG);
  _X002  = EXP( CLK_WG &  CT_WG);

-- Node name is 'TG42_OUT' 
-- Equation name is 'TG42_OUT', location is LC017, type is output.
 TG42_OUT = LCELL( _EQ025 $  GND);
  _EQ025 =  _X024;
  _X024  = EXP( TG42_IN);

-- Node name is 'WGR0' from file "sp047032.tdf" line 54, column 5
-- Equation name is 'WGR0', location is LC024, type is buried.
WGR0     = TFFE( _EQ026,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ026 =  WGR0 &  WGR1 &  WGR2 & !WGR3
         # !WGR0 & !WGR1 & !WGR2 &  WGR3
         #  RDAT;

-- Node name is 'WGR1' from file "sp047032.tdf" line 54, column 5
-- Equation name is 'WGR1', location is LC019, type is buried.
WGR1     = TFFE( _EQ027,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ027 =  RDAT & !WGR0 & !WGR1 & !WGR2 & !WGR3
         # !RDAT & !WGR1 &  WGR2 & !WGR3
         # !RDAT &  WGR1 & !WGR3
         #  RDAT &  WGR0;

-- Node name is 'WGR2' from file "sp047032.tdf" line 54, column 5
-- Equation name is 'WGR2', location is LC012, type is buried.
WGR2     = TFFE( _EQ028,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ028 = !RDAT &  WGR1 &  WGR2 & !WGR3
         #  RDAT &  WGR0 &  WGR1
         # !RDAT & !WGR2 & !WGR3;

-- Node name is 'WGR3' from file "sp047032.tdf" line 54, column 5
-- Equation name is 'WGR3', location is LC015, type is buried.
WGR3     = TFFE( _EQ029,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ029 =  RDAT &  WGR0 &  WGR1 &  WGR2 &  WGR3
         #  WGR0 &  WGR1 &  WGR2 & !WGR3
         # !RDAT &  WGR1 &  WGR2 & !WGR3;

-- Node name is '10K_CLK' = ':87' from file "sp047032.tdf" line 75, column 13
-- Equation name is '10K_CLK', type is output 
 10K_CLK = LCELL( _EQ030 $  VCC);
  _EQ030 =  CNF_ON & !HDD_CS & !/MR & !/RD
         # !CNF_ON & !/MR & !/WR;

-- Node name is '10K_D0' = ':88' from file "sp047032.tdf" line 86, column 12
-- Equation name is '10K_D0', type is output 
 10K_D0  = LCELL( CODE4 $  D0);

-- Node name is '/CONFIG' = ':117' from file "sp047032.tdf" line 227, column 12
-- Equation name is '/CONFIG', type is output 
 /CONFIG = LCELL( _EQ031 $  EPM_RES);
  _EQ031 =  EPM_RES & !HDD_CS & !MA7 & !/MR & !/WR;

-- Node name is '/WRH' = ':116' from file "sp047032.tdf" line 223, column 9
-- Equation name is '/WRH', type is output 
 /WRH    = DFFE( _EQ032 $  VCC,  _EQ033, !_EQ034,  VCC,  VCC);
  _EQ032 =  MA0 & !/WRH;
  _EQ033 =  _X025;
  _X025  = EXP(!HDD_CS & !/IO & !/WR);
  _EQ034 = !HDD_CS & !/IO & !/RD;

-- Node name is ':99' from file "sp047032.tdf" line 153, column 25
-- Equation name is '_LC016', type is buried 
_LC016   = DFFE( _EQ035 $  GND,  CT_WG1,  VCC,  VCC,  VCC);
  _EQ035 =  _X023;
  _X023  = EXP( _X020 &  _X021);
  _X020  = EXP(!CT_WG1 &  RDATA);
  _X021  = EXP( _X022 &  _X023);
  _X022  = EXP(!CT_WG1 & !RDATA);



--     Shareable expanders that are duplicated in multiple LABs:
--    _X001 occurs in LABs A, B
--    _X002 occurs in LABs A, B




Project Information               c:\prj\sprinter\firmware\97\max\sp047032.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = off
      Automatic Global Clear              = off
      Automatic Global Preset             = off
      Automatic Global Output Enable      = off
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 0

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = ADVANCED
Smart Recompile                           = on
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,646K
