commit ae91df09e907b2f757033c2116a6c4a1ab9a1bb1 Author: Roman Krupnin Date: Sat Feb 22 18:50:46 2025 +0300 init repo diff --git a/README.md b/README.md new file mode 100644 index 0000000..ce80799 --- /dev/null +++ b/README.md @@ -0,0 +1,56 @@ +# Sprinter 97 + +## Прототип + +Начало эпохи спринтера было положено в 1995-1996 годах. До наших дней дошла одна единственная фотография прототипа. + +
+ +Возможно именно это было представлено на фестивале [Enlight'96](https://www.enlight.ru/enlight/) в Санкт-Петербурге, но это доподлинно неизвестно. К сожалению, в фотоотчетах Enlight нет ни одной фотографии, хоть как-то свидельствующих о том, что Спринтер там вообще был. Остается только на правдивость статьи в журнале [ZX-News #32](https://zxpress.ru/article.php?id=2923): + +``` +Первое знакомство "пишущих" людей - кодеров и мьюзикмейкеров (извините за такую англификацию :) с компьютером Peters'ов произошло в августе прошлого года, когда в Санкт-Петербурге проходило всем известное мероприятие Enlight-96. Тогда был представлен Scorpion'оподобный компьютер, тогда у него был реализован лишь один режим расширенной графики. +``` + +## Ранняя версия 1997 года + +  
+ +Ни одного живого экземпляра на сегодняшний день не было обнаружено, однако печатные платы очень редко еще встречаются в продаже. +Это настолько редкое и удивительное явление, что на момент создания [SprinterTeam сообщества](https://t.me/zx_sprinter) в 2020 году только один раз за 5 лет эта плата живьем [появилась](https://zx-pk.com/forum/viewtopic.php?f=4&t=24329) в продаже. Однако сканы этой платы уже были доступны в архивах. + +Плата очень сильно отличается от классических версий. Видео модуль состоит из дополнительных микросхем, возможно буферов типа 555АП6. +Расположение периферийной ПЛИС Altera MAX прямо возле процессора, слева от разъема simm модуля памяти. + +Схемы нет. Ни в сканах, ни в ФИДО переписках, ни в упоминаниях. Возможно её еще и не существовало, а появилась она начиная с классической версии. +Печатной платы в файлах каких либо КАДах так же не обнаружено. + +## Классическая версия 1998 года + +Наибольшее распространение получила плата с небольшим количеством навесных исправлений. + +    
+ +Хоть эти фотографии и называются sp97 во всех [мастер-архивах](https://winglion.sprinter.ru/), это все же больше похоже именно на версию 1998 года. Это так же подтверждает файл sp98_mont.bmp из тех же архивов. На этой монтажке указаны все доработки, которые требуется сделать на классической плате. А так как название "Sprinter 97" к этому времени уже закрепилось за этим компьютером, то и файлы именовались так же. Именно эту версию все еще можно встретить на барахолках. + +Схема была отрисована в OrCAD 2.10, там же была разработана и плата. Однако оркадовского файла схемы не сохранилось, а картинка со схемой, опубликованная авторами еще во времена ФИДО, получилась крайне низкого разрешения, что породило массу шуток (Nothing to see!). А возможно это было сделано Иваном Мак намеренно, что бы не отдавать общественности схему своего детища. + +
+ +Попытка применить современные нейронные сети для восстановления данных не улучшила ситуацию. К сожалению, можно констатировать что схема утеряна навсегда, нужно отрисовывать всё заново. + +## Версия 1999 года + +В [мастер-архивах](https://winglion.sprinter.ru/) есть файл SPRINT05.PCB - это файл печатной платы, которая выполнена в старом OrCAD 2.10 еще для MS-DOS. Открыть этот файл и что-либо сделать с этим файлом в наше время не так просто. Можно перерыть весь Интернет и все равно не найти нужную версию OrCAD. Вроде бы версия 4.40 должна была открыть файл, но она не смогла, чем окончательно запутала, чем же вообще этот файл открывать. + +  
+ +В [какой-то момент](https://t.me/zx_sprinter/237164) было принято решение просто разобрать формат этого файла путем реверс-инжиниринга и написать конвертор в более современные CAD системы. Можно отследить все этапы реверса по телеграм чату, на странице Sprinter Reverse Team [создан раздел](https://reverse.sprinter.ru/orcad210) с подробным разбором формата и онлайн парсером. + +Используя результаты работы парсера теперь необходимо сгенерировать файл печатной платы для более современных КАД систем. Был выбран формат p-cad ascii format 7.5, который понимает и множество других программ. Генератор выдал результат, который потом без проблем прочитался современным Altium Designer v21. + +    
+ +Похоже, что это плата одна из самых последних версий, от 18 августа 1999 года и скорее всего никогда не производилась. На плате видны изменения, они касаются навесных исправлений, которые делались для классической платы 1998 года. + +Таким образом получена точная конверсия печатной платы из старого OrCAD формата в современный и теперь можно попробовать воссоздать Sprinter 97 в железе, как это было в оригинале. \ No newline at end of file diff --git a/docs/Аппаратные возможности.pdf b/docs/Аппаратные возможности.pdf new file mode 100644 index 0000000..0013550 Binary files /dev/null and b/docs/Аппаратные возможности.pdf differ diff --git a/docs/Архитектура компьютера Sprinter.pdf b/docs/Архитектура компьютера Sprinter.pdf new file mode 100644 index 0000000..cb3f6bf Binary files /dev/null and b/docs/Архитектура компьютера Sprinter.pdf differ diff --git a/docs/Буклет по Sprinter-97.pdf b/docs/Буклет по Sprinter-97.pdf new file mode 100644 index 0000000..b4ab9ca Binary files /dev/null and b/docs/Буклет по Sprinter-97.pdf differ diff --git a/docs/Техническое описание и руководство по сборке.pdf b/docs/Техническое описание и руководство по сборке.pdf new file mode 100644 index 0000000..5116d6f Binary files /dev/null and b/docs/Техническое описание и руководство по сборке.pdf differ diff --git a/fw/bios/sp97-1996-01-26.BIN b/fw/bios/sp97-1996-01-26.BIN new file mode 100644 index 0000000..c8d0285 Binary files /dev/null and b/fw/bios/sp97-1996-01-26.BIN differ diff --git a/fw/bios/sp97-1998-05-15.BIN b/fw/bios/sp97-1998-05-15.BIN new file mode 100644 index 0000000..65a417b Binary files /dev/null and b/fw/bios/sp97-1998-05-15.BIN differ diff --git a/fw/bios/sp97-1998-07-07.BIN b/fw/bios/sp97-1998-07-07.BIN new file mode 100644 index 0000000..9567d03 Binary files /dev/null and b/fw/bios/sp97-1998-07-07.BIN differ diff --git a/fw/bios/sp97-1999-03-05.BIN b/fw/bios/sp97-1999-03-05.BIN new file mode 100644 index 0000000..2fe15ff Binary files /dev/null and b/fw/bios/sp97-1999-03-05.BIN differ diff --git a/fw/bios/sp97-1999-10-05.BIN b/fw/bios/sp97-1999-10-05.BIN new file mode 100644 index 0000000..a4a244f Binary files /dev/null and b/fw/bios/sp97-1999-10-05.BIN differ diff --git a/fw/bios/sp97-2000-07-10.BIN b/fw/bios/sp97-2000-07-10.BIN new file mode 100644 index 0000000..130c08a Binary files /dev/null and b/fw/bios/sp97-2000-07-10.BIN differ diff --git a/fw/bios/sp97-2000-08-01.BIN b/fw/bios/sp97-2000-08-01.BIN new file mode 100644 index 0000000..67e3966 Binary files /dev/null and b/fw/bios/sp97-2000-08-01.BIN differ diff --git a/fw/bios/sp97-2000-08-06.BIN b/fw/bios/sp97-2000-08-06.BIN new file mode 100644 index 0000000..63f147d Binary files /dev/null and b/fw/bios/sp97-2000-08-06.BIN differ diff --git a/fw/bios/sp97-2000-08-18.BIN b/fw/bios/sp97-2000-08-18.BIN new file mode 100644 index 0000000..eec3cfa Binary files /dev/null and b/fw/bios/sp97-2000-08-18.BIN differ diff --git a/fw/bios/sp97-2000-08-20.BIN b/fw/bios/sp97-2000-08-20.BIN new file mode 100644 index 0000000..eec3cfa Binary files /dev/null and b/fw/bios/sp97-2000-08-20.BIN differ diff --git a/fw/bios/sp97-2001-04-19.BIN b/fw/bios/sp97-2001-04-19.BIN new file mode 100644 index 0000000..6c3510a Binary files /dev/null and b/fw/bios/sp97-2001-04-19.BIN differ diff --git a/fw/protect/SPRINT03.BIN b/fw/protect/SPRINT03.BIN new file mode 100644 index 0000000..7433ad1 Binary files /dev/null and b/fw/protect/SPRINT03.BIN differ diff --git a/fw/protect/SPRINT03.BIN.protected b/fw/protect/SPRINT03.BIN.protected new file mode 100644 index 0000000..0c39052 Binary files /dev/null and b/fw/protect/SPRINT03.BIN.protected differ diff --git a/fw/protect/SPRINT03.BIN.protected.decoded b/fw/protect/SPRINT03.BIN.protected.decoded new file mode 100644 index 0000000..7433ad1 Binary files /dev/null and b/fw/protect/SPRINT03.BIN.protected.decoded differ diff --git a/fw/protect/SPRINT03._PR b/fw/protect/SPRINT03._PR new file mode 100644 index 0000000..0c39052 Binary files /dev/null and b/fw/protect/SPRINT03._PR differ diff --git a/fw/protect/protect05.dpr b/fw/protect/protect05.dpr new file mode 100644 index 0000000..54e7f50 --- /dev/null +++ b/fw/protect/protect05.dpr @@ -0,0 +1,163 @@ +program protect05; +{$R-} +{$APPTYPE CONSOLE} + +uses + Classes, + SysUtils; + +function GetFileSize(const FileName: String): Cardinal; +var + AFile: File of Byte; +begin + AssignFile(AFile, FileName); + Reset(AFile); + try + Result := System.FileSize(AFile); + finally + CloseFile(AFile); + end; +end; +procedure help; +begin + writeln('Usage:'); + writeln(' protect05.exe '); + writeln; +end; +function bit(const aValue: Cardinal; const BitPos: Byte): byte; +begin + if ((aValue and (1 shl BitPos)) <> 0) then + result:= 1 + else + result:= 0; +end; + +const + MAX_BUF_SIZE = 1024 * 15; + +var + data_len: longint; + o_file_name, i_file_name: string; + o_file, i_file: file of byte; + b,i, readed: longint; + buf_in, buf_out: array of byte; + CODE, D, D0_in, D0_out, todo: byte; + unprotected: boolean; + +begin + writeln('PROTECT05: Sprinter-97 FW bitstream protector/decoder'); + writeln('Copyright (c) 2024 Sprinter Team'); + + // check incoming values + if ParamCount < 1 then + begin + help; + exit; + end; + + i_file_name:= ParamStr(1); + if trim(i_file_name) = '' then + begin + writeln('ERROR: input file name is not specified'); + exit; + end; + + // check buffer size + data_len:= GetFileSize(i_file_name); + if (data_len > MAX_BUF_SIZE) then + begin + writeln('ERROR: DATA_LENGTH='+inttostr(data_len)+', MAX_BUF_SIZE='+inttostr(MAX_BUF_SIZE)); + exit; + end; + + // create buffers + SetLength(buf_in, MAX_BUF_SIZE); + FillChar(buf_in[0], length(buf_in), 0); + + SetLength(buf_out, MAX_BUF_SIZE); + FillChar(buf_out[0], length(buf_out), 0); + + // load src file +{$I-} + FileMode:= fmOpenRead; + AssignFile(i_file, i_file_name); + reset(i_file); + seek(i_file, 0); + BlockRead(i_file, buf_in[0], length(buf_in), readed); + CloseFile(i_file); +{$I+} + i:= IOResult; + if (i > 0) then + begin + writeln('ERROR: IOResult='+inttostr(i)+' during loading input file. Readed '+inttostr(readed)); + exit; + end; + writeln('readed '+inttostr(readed)+' bytes'); + + data_len:= readed; + unprotected:= false; + if (buf_in[0] = $FF) and (buf_in[1] = $FF) and (buf_in[2] = $62) and (buf_in[3] = $7B) then + unprotected:= true; + + + // protect / unprotect + CODE:= 0; + + if unprotected then + writeln('protecting ...') + else + writeln('decoding ...'); + + for b:= 0 to data_len-1 do + begin + D:= buf_in[b]; + + for i:= 0 to 7 do + begin + D0_in:= bit(D, i); + + D0_out:= bit(CODE,4) xor D0_in; + buf_out[b]:= buf_out[b] or (D0_out shl i); + + if unprotected then + todo:= D0_in // protect + else + todo:= D0_out; // unprotect + + CODE:= (CODE shl 1) or (bit(CODE,2) xor todo); + + end; + + // just header output + if b < 8 then + write(inttohex(buf_out[b])+' '); + + end; + writeln; + + // write buffer to output file + if unprotected then + o_file_name:= ParamStr(1)+'.protected' + else + o_file_name:= ParamStr(1)+'.decoded'; + +{$I-} + FileMode:= fmOpenReadWrite; + AssignFile(o_file, o_file_name); + reset(o_file); + if IOResult <> 0 then + rewrite(o_file); + seek(o_file, 0); + BlockWrite(o_file, buf_out[0], data_len); + CloseFile(o_file); +{$I+} + i:= IOResult; + if (i > 0) then + begin + writeln('ERROR: IOResult='+inttostr(i)+' during writing to output file'); + exit; + end; + + // finish + writeln(''); +end. diff --git a/fw/protect/protect05.exe b/fw/protect/protect05.exe new file mode 100644 index 0000000..4e45d82 Binary files /dev/null and b/fw/protect/protect05.exe differ diff --git a/fw/protect/protect05.jpg b/fw/protect/protect05.jpg new file mode 100644 index 0000000..f72ede0 Binary files /dev/null and b/fw/protect/protect05.jpg differ diff --git a/fw/protect/readme.txt b/fw/protect/readme.txt new file mode 100644 index 0000000..9d24b31 --- /dev/null +++ b/fw/protect/readme.txt @@ -0,0 +1,4 @@ + sprinter-97 . + . + + , . \ No newline at end of file diff --git a/fw/src/flex/KBD_INI2.MIF b/fw/src/flex/KBD_INI2.MIF new file mode 100644 index 0000000..43e7390 --- /dev/null +++ b/fw/src/flex/KBD_INI2.MIF @@ -0,0 +1,167 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 8; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = BIN; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT + BEGIN +[0..FF] : 11111111; +0 : + 11111111 % .. % + 00100001 % F9 % + 11111111 % .. % + 00011100 % F5 % + 00011010 % F3 % + 00011000 % F1 % + 00011001 % F2 % + 11111111 % F12 % + 11111111 % .. % + 00100000 % F10 % + + 00100010 % F8 % + 00100100 % F6 % + 00011011 % F4 % + 01011000 % Tab % + 10001000 % ~` % + 11111111 % .. % + 11111111 % .. % + 01111001 % Alt % + 11000000 % Left Shift % + 11111111 % .. % + + 11111001 % Ctrl % + 11010000 % 'Q' % + 11011000 % '1' % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11000001 % 'Z' % + 11001001 % 'S' % + 11001000 % 'A' % + 11010001 % 'W' % + + 11011001 % '2' % + 01110000 % left WIN % + 11111111 % .. % + 11000011 % 'C' % + 11000010 % 'X' % + 11001010 % 'D' % + 11010010 % 'E' % + 11011011 % '4' % + 11011010 % '3' % + 10110000 % Right WIN % + + 11111111 % .. % + 11111000 % ' ' % + 11000100 % 'V' % + 11001011 % 'F' % + 11010100 % 'T' % + 11010011 % 'R' % + 11011100 % '5' % + 10111000 % Right Mouse % + 11111111 % .. % + 11111011 % 'N' % + + 11111100 % 'B' % + 11110100 % 'H' % + 11001100 % 'G' % + 11101100 % 'Y' % + 11100100 % '6' % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111010 % 'M' % + 11110011 % 'J' % + + 11101011 % 'U' % + 11100011 % '7' % + 11100010 % '8' % + 11111111 % .. % + 11111111 % .. % + 10111011 % ',' % + 11110010 % 'K' % + 11101010 % 'I' % + 11101001 % 'O' % + 11100000 % '0' % + + 11100001 % '9' % + 11111111 % .. % + 11111111 % .. % + 10111010 % '.' % + 10000100 % '/' % + 11110001 % 'L' % + 10101001 % ';' % + 11101000 % 'P' % + 10110011 % '-' % + 11111111 % .. % + + 11111111 % .. % + 11111111 % .. % + 10101000 % "'" % + 11111111 % .. % + 10101100 % '[' % + 10110001 % '=' % + 11111111 % .. % + 11111111 % .. % + 01011001 % Caps Lock % + 11000000 % Right SHIFT % + + 11110000 % ENTER % + 10101011 % ']' % + 11111111 % .. % + 10001010 % '\' % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + + 11111111 % .. % + 11111111 % .. % + 01100000 % Back % + 11111111 % .. % + 11111111 % .. % + 10010010 % End % + 11111111 % .. % + 01011100 % <- % + 10010000 % Home % + 11111111 % .. % + + 11111111 % .. % + 11111111 % .. % + 10010001 % ins % + 01100001 % DEL % + 01100100 % Dn % + 10101010 % grey 5 ; ctrl + I % + 01100010 % -> % + 01100011 % Up % + 01111000 % ESC % + 00111111 % Num % + + 11111111 % F11 % + 10110010 % G+ % + 01011011 % PDn ; caps + 4 % + 10110011 % G- % + 10111100 % G* % + 01011010 % PUp ; caps + 3 % + 00000000 % Scrol Lock % + 11111111 % .. % + 11111111 % .. % + 11111111 % .. % + + 11111111 % .. % + 00100011 % F7 % ; +% !! DATA FOR CAPS !! % +C0 : + 11111101 % Function shift % + 11000000 % Left Shift % + 11111001 % Ctrl % + 11111111 ; % no shift % +END ; + + diff --git a/fw/src/flex/PGA_INI4.MIF b/fw/src/flex/PGA_INI4.MIF new file mode 100644 index 0000000..7567a07 --- /dev/null +++ b/fw/src/flex/PGA_INI4.MIF @@ -0,0 +1,60 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 8; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT +BEGIN + [0..FF] : 0; + + 0 : 40 % DCP PAGE %; + + 10 : + C0 % WG93 1F,0F % + C2 % WG93 3F % + C4 % WG93 5F % + C6 % WG93 7F % + 80 % WR_PDOS FF % + 9F % RD_KEYS/ WR_A20 %; + 18 : + B0 % CMOS_DAT % + B2 % CMOS_ADR % + B4 % CMOS_XX1 % + B6 % CMOS_XX1 % + B8 + BA + BC + BE; + 20 : + A0 % HD_CS1 ports % + A2 + A4 + A6 + A8 + AA + AC + AE + AD % HD_CS3 3F6 port % + AF % HD_CS3 3F7 port %; + 30 : + D0 % slot 1 mem % + D2 % slot 2 mem % + D4 % slot 1 ports % + D6 % slot 2 ports % + ; + +-- 40 : FF % kb read %; +-- 80 : 7F 7F 7F 7F 7F 7F 7F 7F % KBD_DAT %; +-- 90 : 7F % PORT FF %; + + C0 : 00 00 00 00 % SYS PORTS COPYES %; + + D0 : 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F; % RAM PAGES % + E0 : E0 E2 E4 E6 E8 EA EC EE 00 05 02 E0 F0 00 00 E8; % ROM PAGES % + F0 : 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F; % RAM PAGES % + +END ; diff --git a/fw/src/flex/PGA_INI5.MIF b/fw/src/flex/PGA_INI5.MIF new file mode 100644 index 0000000..a3495f8 --- /dev/null +++ b/fw/src/flex/PGA_INI5.MIF @@ -0,0 +1,50 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 8; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT +BEGIN + [0..FF] : 0; + + 0 : 40 % DCP PAGE %; + + 10 : + C0 % WG93 1F,0F % + C2 % WG93 3F % + C4 % WG93 5F % + C6 % WG93 7F % + 80 % WR_PDOS FF % + 9F % RD_KEYS/ WR_A20 %; + 18 : + B0 % CMOS_DAT % + B2 % CMOS_ADR % + B4 % CMOS_XX1 % + B6 % CMOS_XX1 %; + 20 : + A0 % HD_CS1 ports % + A2 + A4 + A6 + A8 + AA + AC + AE + AD % HD_CS3 3F6 port % + AF % HD_CS3 3F7 port %; +-- 40 : FF % kb read %; +-- 80 : 7F 7F 7F 7F 7F 7F 7F 7F % KBD_DAT %; +-- 90 : 7F % PORT FF %; + + C0 : 00 00 00 00 % SYS PORTS COPYES %; + + + E0 : E0 E2 E4 E6 E8 EA EC EE 00 05 02 10 00 00 00 11; % ROM PAGES % + F0 : 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F; % RAM PAGES % + +END ; + diff --git a/fw/src/flex/SND_INI.MIF b/fw/src/flex/SND_INI.MIF new file mode 100644 index 0000000..3c02d0e --- /dev/null +++ b/fw/src/flex/SND_INI.MIF @@ -0,0 +1,28 @@ +DEPTH = 256; % Memory depth and width are required % +WIDTH = 8; % Enter a decimal number % + +ADDRESS_RADIX = HEX; % Address and value radixes are optional % +DATA_RADIX = HEX; % Enter BIN, DEC, HEX, or OCT; unless % + % otherwise specified, radixes = HEX % + +-- Specify values for addresses, which can be single address or range + +CONTENT +BEGIN + [0..FF] : 00; + 00 : 80 00 04 06; + 04 : 00 00 04 06; + 08 : 80 40 00 06; + 0C : 00 40 00 06; + + 40 : 00 00 00 88; + 44 : 00 00 00 88; + 48 : 00 00 00 88; + 4C : 00 00 00 88; + +-- D0 : 00 80 40 C0 20 A0 60 E0 10 90 50 D0 30 B0 70 F0; +-- E0 : 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0; +-- F0 : 00 10 30 50 70 90 B0 C0 C0 B0 90 70 50 30 10 00; + +END ; + diff --git a/fw/src/flex/SPRINT08.ACF b/fw/src/flex/SPRINT08.ACF new file mode 100644 index 0000000..1ce41ad --- /dev/null +++ b/fw/src/flex/SPRINT08.ACF @@ -0,0 +1,792 @@ +-- +-- Copyright (C) 1988-1998 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP sprint08 +BEGIN + DEVICE = EPF10K10QC208-4; + |SINC_H : OUTPUT_PIN = 175; + |KBD_CLK : BIDIR_PIN = 193; + |KBD_DAT : BIDIR_PIN = 196; + |BEEPER : OUTPUT_PIN = 192; + |/WAIT : BIDIR_PIN = 16; + |/INT : BIDIR_PIN = 197; + |/NMI : BIDIR_PIN = 195; + |MXA10 : BIDIR_PIN = 200; + |MXA9 : BIDIR_PIN = 199; + |MXA8 : BIDIR_PIN = 198; + |MXA7 : BIDIR_PIN = 187; + |MXA6 : BIDIR_PIN = 174; + |MXA5 : BIDIR_PIN = 172; + |MXA4 : BIDIR_PIN = 170; + |MXA3 : BIDIR_PIN = 169; + |MXA2 : BIDIR_PIN = 168; + |MXA1 : BIDIR_PIN = 167; + |MXA0 : BIDIR_PIN = 166; + |/WE : OUTPUT_PIN = 208; + |CAS_3 : OUTPUT_PIN = 207; + |CAS_2 : OUTPUT_PIN = 205; + |CAS_1 : OUTPUT_PIN = 206; + |CAS_0 : OUTPUT_PIN = 204; + |RAS_0 : OUTPUT_PIN = 203; + |RAS_1 : OUTPUT_PIN = 202; + |MS_MOUSE : INPUT_PIN = 191; + |TAPE_OUT : OUTPUT_PIN = 190; + |TURBO_LED : OUTPUT_PIN = 189; + |SND_R1 : OUTPUT_PIN = 176; + |MD0 : BIDIR_PIN = 186; + |TAPE_IN : INPUT_PIN = 182; + |MD1 : BIDIR_PIN = 180; + |MD2 : BIDIR_PIN = 179; + |MD3 : BIDIR_PIN = 177; + |SINC : OUTPUT_PIN = 173; + |MD4 : BIDIR_PIN = 164; + |MD5 : BIDIR_PIN = 163; + |MD6 : BIDIR_PIN = 162; + |MD7 : BIDIR_PIN = 161; + |SND_L1 : OUTPUT_PIN = 160; + |SND_R0 : OUTPUT_PIN = 159; + |SND_L0 : OUTPUT_PIN = 158; + |CLK_PIX : OUTPUT_PIN = 157; + |VA0 : OUTPUT_PIN = 133; + |VA1 : OUTPUT_PIN = 128; + |V_CS0 : OUTPUT_PIN = 127; + |VA2 : OUTPUT_PIN = 121; + |VA10 : OUTPUT_PIN = 120; + |VA3 : OUTPUT_PIN = 116; + |VA4 : OUTPUT_PIN = 112; + |VA11 : OUTPUT_PIN = 111; + |VA5 : OUTPUT_PIN = 104; + |VA9 : OUTPUT_PIN = 102; + |VA6 : OUTPUT_PIN = 100; + |VA8 : OUTPUT_PIN = 99; + |VA7 : OUTPUT_PIN = 96; + |VA13 : OUTPUT_PIN = 95; + |V_WR3 : OUTPUT_PIN = 94; + |VA12 : OUTPUT_PIN = 93; + |V_WR0 : OUTPUT_PIN = 92; + |V_WR1 : OUTPUT_PIN = 90; + |V_WR2 : OUTPUT_PIN = 89; + |VA14 : OUTPUT_PIN = 88; + |VA15 : OUTPUT_PIN = 86; + |/MR : INPUT_PIN = 184; + |TG42 : INPUT_PIN = 183; + |VD03 : BIDIR_PIN = 150; + |VD13 : BIDIR_PIN = 149; + |VD02 : BIDIR_PIN = 148; + |VD04 : BIDIR_PIN = 147; + |VD14 : BIDIR_PIN = 144; + |VD01 : BIDIR_PIN = 143; + |VD05 : BIDIR_PIN = 142; + |VD15 : BIDIR_PIN = 141; + |VD00 : BIDIR_PIN = 136; + |VD06 : BIDIR_PIN = 135; + |VD16 : BIDIR_PIN = 134; + |VD07 : BIDIR_PIN = 132; + |VD17 : BIDIR_PIN = 131; + |VD12 : BIDIR_PIN = 122; + |VD11 : BIDIR_PIN = 119; + |VD10 : BIDIR_PIN = 115; + |VD22 : BIDIR_PIN = 103; + |VD21 : BIDIR_PIN = 101; + |VD20 : BIDIR_PIN = 97; + |VD23 : BIDIR_PIN = 87; + |VD24 : BIDIR_PIN = 85; + |VD30 : BIDIR_PIN = 83; + |/WR : INPUT_PIN = 79; + |/RD : INPUT_PIN = 80; + |/IO : INPUT_PIN = 78; + |VD37 : BIDIR_PIN = 75; + |VD25 : BIDIR_PIN = 74; + |VD27 : BIDIR_PIN = 73; + |VD36 : BIDIR_PIN = 71; + |VD26 : BIDIR_PIN = 70; + |VD31 : BIDIR_PIN = 69; + |VD35 : BIDIR_PIN = 68; + |VD32 : BIDIR_PIN = 67; + |VD34 : BIDIR_PIN = 65; + |VD33 : BIDIR_PIN = 64; + |V_CS1 : OUTPUT_PIN = 63; + |CLKZ1 : OUTPUT_PIN = 62; + |D7 : BIDIR_PIN = 61; + |D6 : BIDIR_PIN = 60; + |D5 : BIDIR_PIN = 58; + |D4 : BIDIR_PIN = 57; + |D3 : BIDIR_PIN = 56; + |D2 : BIDIR_PIN = 55; + |D1 : BIDIR_PIN = 54; + |D0 : BIDIR_PIN = 53; + |A15 : BIDIR_PIN = 47; + |A14 : BIDIR_PIN = 46; + |A13 : BIDIR_PIN = 45; + |A12 : BIDIR_PIN = 44; + |A11 : BIDIR_PIN = 41; + |A10 : BIDIR_PIN = 40; + |A9 : BIDIR_PIN = 39; + |A8 : BIDIR_PIN = 38; + |A7 : BIDIR_PIN = 31; + |A6 : BIDIR_PIN = 30; + |A5 : BIDIR_PIN = 29; + |A4 : BIDIR_PIN = 28; + |A3 : BIDIR_PIN = 27; + |A2 : BIDIR_PIN = 26; + |A1 : BIDIR_PIN = 25; + |A0 : BIDIR_PIN = 24; + |/RF : INPUT_PIN = 19; + |/M1 : INPUT_PIN = 18; + |/RESET : BIDIR_PIN = 17; + |XA2 : OUTPUT_PIN = 12; + |XA1 : OUTPUT_PIN = 11; + |XA0 : OUTPUT_PIN = 10; + |XACS : OUTPUT_PIN = 13; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EPF10K50GC403; + AUTO_DEVICE = EPF10K50GC403ES; + AUTO_DEVICE = EPF10K50RC240; + AUTO_DEVICE = EPF10K30RC240; + AUTO_DEVICE = EPF10K10QC208; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EPF10K10QC208-4; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; + MAINTAIN_STABLE_SYNTHESIS = OFF; +END; + +IGNORED_ASSIGNMENTS +BEGIN + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +LOGIC_OPTIONS +BEGIN + |ALU0 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU1 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU2 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU3 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU4 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU5 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU6 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU7 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU8 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU9 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU10 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU11 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU12 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU13 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU14 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |ALU15 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q10 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q11 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q13 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q12 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q20 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q21 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q22 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q23 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q30 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q31 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q32 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |AY_Q33 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |MXA0 : IGNORE_SOFT_BUFFERS = ON; + |MXA1 : IGNORE_SOFT_BUFFERS = ON; + |MXA4 : IGNORE_SOFT_BUFFERS = ON; + |MXA3 : IGNORE_SOFT_BUFFERS = ON; + |MXA2 : IGNORE_SOFT_BUFFERS = ON; + |MXA6 : IGNORE_SOFT_BUFFERS = ON; + |MXA5 : IGNORE_SOFT_BUFFERS = ON; + |MXA8 : IGNORE_SOFT_BUFFERS = ON; + |MXA7 : IGNORE_SOFT_BUFFERS = ON; + |MXA9 : IGNORE_SOFT_BUFFERS = ON; + |MXA10 : IGNORE_SOFT_BUFFERS = ON; + |SVA10 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |SVA11 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |SVA12 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |V_WR0 : SLOW_SLEW_RATE = OFF; + |V_WR1 : SLOW_SLEW_RATE = OFF; + |V_WR2 : SLOW_SLEW_RATE = OFF; + |V_WR3 : SLOW_SLEW_RATE = OFF; + |VA0 : SLOW_SLEW_RATE = OFF; + |VA1 : SLOW_SLEW_RATE = OFF; + |VA2 : SLOW_SLEW_RATE = OFF; + |VA3 : SLOW_SLEW_RATE = OFF; + |VA4 : SLOW_SLEW_RATE = OFF; + |VA5 : SLOW_SLEW_RATE = OFF; + |VA6 : SLOW_SLEW_RATE = OFF; + |VA7 : SLOW_SLEW_RATE = OFF; + |VA8 : SLOW_SLEW_RATE = OFF; + |VA9 : SLOW_SLEW_RATE = OFF; + |VA10 : SLOW_SLEW_RATE = OFF; + |VA11 : SLOW_SLEW_RATE = OFF; + |VA12 : SLOW_SLEW_RATE = OFF; + |VA13 : SLOW_SLEW_RATE = OFF; + |VA14 : SLOW_SLEW_RATE = OFF; + |VA15 : SLOW_SLEW_RATE = OFF; + |SVA2 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |RA18 : IMPLEMENT_IN_EAB = ON; + |RA19 : IMPLEMENT_IN_EAB = ON; + |RA20 : IMPLEMENT_IN_EAB = ON; + |RA21 : IMPLEMENT_IN_EAB = ON; + |VA0 : FAST_IO = ON; + |VA1 : FAST_IO = ON; + |VA2 : FAST_IO = ON; + |VA4 : FAST_IO = ON; + |VA3 : FAST_IO = ON; + |VA6 : FAST_IO = ON; + |VA5 : FAST_IO = ON; + |VA8 : FAST_IO = ON; + |VA7 : FAST_IO = ON; + |VA10 : FAST_IO = ON; + |VA9 : FAST_IO = ON; + |VA12 : FAST_IO = ON; + |VA11 : FAST_IO = ON; + |VA13 : FAST_IO = ON; + |VA14 : FAST_IO = ON; + |VA15 : FAST_IO = ON; + |VXA0 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA1 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA2 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA3 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA4 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA5 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA6 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA7 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA8 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA9 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA10 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA11 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA12 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA13 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA14 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA15 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA16 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |VXA17 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |SVA0 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |SVA1 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |SVA3 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |SVA4 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |SVA5 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |MPGS0 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |MPGS1 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |MPGS2 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |MPGS3 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; + |MPGS4 : IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL = ON; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + LOW_VOLTAGE_IO = OFF; + nCEO = UNRESERVED; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + CONFIG_SCHEME = PASSIVE_PARALLEL_SYNCHRONOUS; + DISABLE_TIME_OUT = ON; + RELEASE_CLEARS = ON; + AUTO_RESTART = ON; + SDOUT = UNRESERVED; + DATA0 = UNRESERVED; + MAX7000S_USER_CODE = FFFF; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + FLEX8000_ENABLE_JTAG = OFF; + MAX7000S_ENABLE_JTAG = OFF; + ENABLE_DCLK_OUTPUT = OFF; + USER_CLOCK = OFF; + SECURITY_BIT = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + OPTIMIZE_FOR_SPEED = 0; + AUTO_REGISTER_PACKING = OFF; + AUTO_FAST_IO = ON; + AUTO_GLOBAL_OE = ON; + AUTO_GLOBAL_PRESET = ON; + AUTO_GLOBAL_CLEAR = ON; + AUTO_GLOBAL_CLOCK = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + DEVICE_FAMILY = FLEX10K; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + STYLE = NORMAL; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; + MULTI_LEVEL_SYNTHESIS_MAX9000 = OFF; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + FITTER_SETTINGS = ADVANCED; + SMART_RECOMPILE = ON; + GENERATE_AHDL_TDO_FILE = OFF; + TIMING_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + PRESERVE_ALL_NODE_NAME_SYNONYMS = ON; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + END_TIME = 0.0ns; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + REGISTERED_PERFORMANCE_OPTIONS = FREQUENCY_OF_PATHS; + LIST_PATH_FREQUENCY = 42.01MHz; + LIST_PATH_COUNT = 10; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; + ANALYSIS_MODE = DELAY_MATRIX; +END; + +OTHER_CONFIGURATION +BEGIN + ROW_PINS_PERCENT = 95; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + LAST_MAXPLUS2_VERSION = 8.2; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + ROW_PINS_LCELL_INSERT = ON; + NORMAL_LCELL_INSERT = ON; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,0,0,1,1,1"; + FLEX_10K_52_COLUMNS = 40; + EXPLICIT_FAMILY = 1; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ORIGINAL_MAXPLUS2_VERSION = 6.0; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; + MINIMIZATION = FULL; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + CARRY_CHAIN = AUTO; + CARRY_CHAIN_LENGTH = 32; + SLOW_SLEW_RATE = ON; + CASCADE_CHAIN = AUTO; + IGNORE_SOFT_BUFFERS = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + DECOMPOSE_GATES = ON; + REGISTER_OPTIMIZATION = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + MINIMIZATION = FULL; + CASCADE_CHAIN_LENGTH = 2; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + REDUCE_LOGIC = ON; + SOFT_BUFFER_INSERTION = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + IGNORE_SOFT_BUFFERS = OFF; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + IGNORE_SOFT_BUFFERS = OFF; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + IGNORE_SOFT_BUFFERS = OFF; + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + IGNORE_SOFT_BUFFERS = OFF; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + IGNORE_SOFT_BUFFERS = OFF; + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + IGNORE_SOFT_BUFFERS = OFF; + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + IGNORE_SOFT_BUFFERS = OFF; + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/fw/src/flex/SPRINT08.TDF b/fw/src/flex/SPRINT08.TDF new file mode 100644 index 0000000..d156db5 --- /dev/null +++ b/fw/src/flex/SPRINT08.TDF @@ -0,0 +1,3584 @@ + + TITLE "Sprinter_97"; + +---------Sprinter-II-------------------------------------- +% +CONSTANT NEWS = 0; +CONSTANT TURBO_MODE = 21; -- 14 - 14MHz ; 21 - 21MHz ; 28 - 28MHZ +CONSTANT SOUND_CARD = 0; -- 0 - OFF ; 1 - ON + +CONSTANT KEYBOARD = B"00"; -- 0 - OFF ; 1 - ONLY RESET ; 2 - SPEC ; 3 - SCAN +CONSTANT VIDEO = 1; -- 0 - Spectrum 48k ; 1 - Sprinter-97 +CONSTANT COVOX = 8; -- 0 - COVOX - OFF ; 4..8 BITS +CONSTANT ACCELERAT = 1; -- 0 - not present ; 1 - simple ; 2 - Gigaccelerator +CONSTANT PORT_1F = 0; -- 0 - not correct ; 1 - correct +CONSTANT PORT_FF = 0; +CONSTANT ISD_KBD = 0; +CONSTANT CONFIGS = 1; +CONSTANT F12_TURBO = 0; +CONSTANT CASH_RAM = 0; +CONSTANT MODEM = 0; +CONSTANT SCREEN = 0; +CONSTANT MODE640 = 1; +CONSTANT ACCELER_FN = 1; +CONSTANT ACC_DECODE = 0; + +CONSTANT SPRINTER = 0; + +CONSTANT COVOX_MODE = B"00"; + +CONSTANT AY_3_8910 = 0; +CONSTANT AY_STEREO = 0; + +CONSTANT NMI_USE = 0; + +CONSTANT NO_SPEC_SCR= 0; +CONSTANT S128_OFF = 0; +CONSTANT PENTAGON512= 0; +CONSTANT READRESS = 0; + +CONSTANT MULT = 0; + +CONSTANT MAGIC = 0; +CONSTANT BITPLANES = 0; -- 0 - no bitplanes ; 1 - yes bitplanes + +CONSTANT FORTH_CPU = 0; +CONSTANT STACK_W = 6; +CONSTANT STACK_N = 4; +% +---------Sprinter-I------------------------------------------- +% CONSTANT NEWS = 0; +CONSTANT TURBO_MODE = 21; -- (not USED!) 14 - 14MHz ; 21 - 21MHz ; 28 - 28MHZ +CONSTANT SOUND_CARD = 0; -- 0 - OFF ; 1 - ON + +CONSTANT KEYBOARD = B"10"; -- 0 - OFF ; 1 - ONLY RESET ; 2 - SPEC ; 3 - SCAN +CONSTANT VIDEO = 1; -- 0 - Spectrum 48k ; 1 - Sprinter-97 +CONSTANT COVOX = 8; -- 0 - COVOX - OFF ; 4..8 BITS +CONSTANT ACCELERAT = 0; -- 0 - not present ; 1 - simple ; 2 - Gigaccelerator +CONSTANT PORT_1F = 1; -- 0 - not correct ; 1 - correct +CONSTANT PORT_FF = 0; +CONSTANT ISD_KBD = 1; +CONSTANT CONFIGS = 1; +CONSTANT F12_TURBO = 1; +CONSTANT CASH_RAM = 1; +CONSTANT MODEM = 0; +CONSTANT SCREEN = 0; -- screen for video +CONSTANT MODE640 = 0; +CONSTANT ACCELER_FN = 0; +CONSTANT ACC_DECODE = 0; + +CONSTANT SPRINTER = 0; + +CONSTANT COVOX_MODE = B"00"; -- 00 register on EAB; 11 - registr on LCELL; + -- 01 4 chanels; 10 - COVOX-Blaster +CONSTANT AY_3_8910 = 0; +CONSTANT AY_STEREO = 0; + +CONSTANT NMI_USE = 0; + +CONSTANT NO_SPEC_SCR= 0; +CONSTANT S128_OFF = 0; +CONSTANT PENTAGON512= 1; +CONSTANT READRESS = 0; + +CONSTANT MULT = 0; + +CONSTANT MAGIC = 0; +CONSTANT BITPLANES = 0; -- 0 - no bitplanes ; 1 - yes bitplanes + +CONSTANT FORTH_CPU = 0; +CONSTANT STACK_W = 6; +CONSTANT STACK_N = 4; +% +---------Sprinter-AY------------------------------------------- + CONSTANT NEWS = 0; +CONSTANT TURBO_MODE = 21; -- (not USED!) 14 - 14MHz ; 21 - 21MHz ; 28 - 28MHZ +CONSTANT SOUND_CARD = 0; -- 0 - OFF ; 1 - ON + +CONSTANT KEYBOARD = B"10"; -- 0 - OFF ; 1 - ONLY RESET ; 2 - SPEC ; 3 - SCAN +CONSTANT VIDEO = 0; -- 0 - Spectrum 48k ; 1 - Sprinter-97 +CONSTANT COVOX = 0; -- 0 - COVOX - OFF ; 4..8 BITS +CONSTANT ACCELERAT = 0; -- 0 - not present ; 1 - simple ; 2 - Gigaccelerator +CONSTANT PORT_1F = 1; -- 0 - not correct ; 1 - correct +CONSTANT PORT_FF = 0; +CONSTANT ISD_KBD = 1; +CONSTANT CONFIGS = 1; +CONSTANT F12_TURBO = 1; +CONSTANT CASH_RAM = 0; +CONSTANT MODEM = 0; +CONSTANT SCREEN = 0; -- screen for video +CONSTANT MODE640 = 0; +CONSTANT ACCELER_FN = 0; +CONSTANT ACC_DECODE = 0; + +CONSTANT SPRINTER = 0; + +CONSTANT COVOX_MODE = B"00"; -- 00 register on EAB; 11 - registr on LCELL; + -- 01 4 chanels; 10 - COVOX-Blaster +CONSTANT AY_3_8910 = 3; +CONSTANT AY_STEREO = 0; + +CONSTANT NMI_USE = 0; + +CONSTANT NO_SPEC_SCR= 0; +CONSTANT S128_OFF = 0; +CONSTANT PENTAGON512= 0; +CONSTANT READRESS = 0; + +CONSTANT MULT = 0; + +CONSTANT MAGIC = 0; +CONSTANT BITPLANES = 0; -- 0 - no bitplanes ; 1 - yes bitplanes + +CONSTANT FORTH_CPU = 0; +CONSTANT STACK_W = 6; +CONSTANT STACK_N = 4; +------------Sprinter-GAME------------------- +% +CONSTANT NEWS = 0; +CONSTANT TURBO_MODE = 21; -- 14 - 14MHz ; 21 - 21MHz ; 28 - 28MHZ +CONSTANT SOUND_CARD = 0; -- 0 - OFF ; 1 - ON + +CONSTANT KEYBOARD = B"00"; -- 0 - OFF ; 1 - ONLY RESET ; 2 - SPEC ; 3 - SCAN +CONSTANT VIDEO = 1; -- 0 - Spectrum 48k ; 1 - Sprinter-97 +CONSTANT COVOX = 8; -- 0 - COVOX - OFF ; 4..8 BITS +CONSTANT ACCELERAT = 1; -- 0 - not present ; 1 - simple ; 2 - Gigaccelerator +CONSTANT PORT_1F = 0; -- 0 - not correct ; 1 - correct +CONSTANT PORT_FF = 0; +CONSTANT ISD_KBD = 0; +CONSTANT CONFIGS = 1; +CONSTANT F12_TURBO = 0; +CONSTANT CASH_RAM = 1; +CONSTANT MODEM = 0; +CONSTANT SCREEN = 0; -- screen for DEMO-VIDEO +CONSTANT MODE640 = 0; +CONSTANT ACCELER_FN = 1; +CONSTANT ACC_DECODE = 0; + +CONSTANT SPRINTER = 0; + +CONSTANT COVOX_MODE = B"10"; + +CONSTANT AY_3_8910 = 0; +CONSTANT AY_STEREO = 0; + +CONSTANT NMI_USE = 0; + +CONSTANT NO_SPEC_SCR= 0; +CONSTANT S128_OFF = 0; +CONSTANT PENTAGON512= 0; +CONSTANT READRESS = 0; + +CONSTANT MULT = 0; + +CONSTANT MAGIC = 0; +CONSTANT BITPLANES = 0; -- 0 - no bitplanes ; 1 - yes bitplanes + +CONSTANT FORTH_CPU = 0; +CONSTANT STACK_W = 6; +CONSTANT STACK_N = 4; % +------------Sprinter-DOOM------------------- +% +CONSTANT NEWS = 0; +CONSTANT TURBO_MODE = 21; -- 14 - 14MHz ; 21 - 21MHz ; 28 - 28MHZ +CONSTANT SOUND_CARD = 0; -- 0 - OFF ; 1 - ON + +CONSTANT KEYBOARD = B"00"; -- 0 - OFF ; 1 - ONLY RESET ; 2 - SPEC ; 3 - SCAN +CONSTANT VIDEO = 1; -- 0 - Spectrum 48k ; 1 - Sprinter-97 +CONSTANT COVOX = 8; -- 0 - COVOX - OFF ; 4..8 BITS +CONSTANT ACCELERAT = 3; -- 0 - not present ; 1 - simple ; 2 - Gigaccelerator +CONSTANT PORT_1F = 0; -- 0 - not correct ; 1 - correct +CONSTANT PORT_FF = 0; +CONSTANT ISD_KBD = 0; +CONSTANT CONFIGS = 0; +CONSTANT F12_TURBO = 0; +CONSTANT CASH_RAM = 1; +CONSTANT MODEM = 0; +CONSTANT SCREEN = 0; -- screen for DEMO-VIDEO +CONSTANT MODE640 = 0; +CONSTANT ACCELER_FN = 1; +CONSTANT ACC_DECODE = 0; + +CONSTANT SPRINTER = 0; + +CONSTANT COVOX_MODE = B"10"; + +CONSTANT AY_3_8910 = 0; +CONSTANT AY_STEREO = 0; + +CONSTANT NMI_USE = 0; + +CONSTANT NO_SPEC_SCR= 0; +CONSTANT S128_OFF = 1; +CONSTANT PENTAGON512= 0; +CONSTANT READRESS = 0; + +CONSTANT MULT = 0; + +CONSTANT MAGIC = 0; +CONSTANT BITPLANES = 0; -- 0 - no bitplanes ; 1 - yes bitplanes + +CONSTANT FORTH_CPU = 0; +CONSTANT STACK_W = 6; +CONSTANT STACK_N = 4; +% +-------------------------------------------- + +INCLUDE "lpm_ram_dq"; +INCLUDE "lpm_add_sub"; +-- INCLUDE "kbd"; +-- INCLUDE "74181"; + +SUBDESIGN sprint08 + ( + TG42 : INPUT; + SINC : OUTPUT; + + A[15..0] : BIDIR; + D[7..0] : BIDIR; + /MR,/IO, + /WR,/RD, + /M1,/RF : INPUT; + + XA[2..0] : OUTPUT; + XACS : OUTPUT; + + /WAIT : BIDIR; + /INT : BIDIR; + /NMI : BIDIR; + /RESET : BIDIR; + CLKZ1 : OUTPUT; + + MXA[10..0] : OUTPUT; +-- MXA[10..0] : BIDIR; + MD[7..0] : BIDIR; + RAS_[1..0] : OUTPUT; + CAS_[3..0] : OUTPUT; + /WE : OUTPUT; + + V_CS[1..0] : OUTPUT; + V_WR[3..0] : OUTPUT; + VA[15..0] : OUTPUT; + VD0[7..0] : BIDIR; + VD1[7..0] : BIDIR; + VD2[7..0] : BIDIR; + VD3[7..0] : BIDIR; + + CLK_PIX : OUTPUT; + + SINC_H : OUTPUT; + + MS_MOUSE : INPUT; + + SND_R[1..0] : OUTPUT; + SND_L[1..0] : OUTPUT; + TURBO_LED : OUTPUT; + + TAPE_IN : INPUT; + TAPE_OUT : OUTPUT; + BEEPER : OUTPUT; + + KBD_CLK : BIDIR; + KBD_DAT : BIDIR; + + ) +VARIABLE +-- SND_L[2..0] : NODE; +-- SND_R[2..0] : NODE; + SINC : NODE; +-- TAPE_IN : NODE; + KBD_CC, + KBD_DD : NODE; + + CLK42X : NODE; + CLK84 : NODE; + CLK42 : NODE; + CT[5..0] : DFF; + + DCP[7..0] : DFF; + DD[7..0] : DFF; + + FIN[3..0] : NODE; + MA[10..0] : NODE; + RAS : NODE; + CAS : NODE; + DOS : NODE; + S128 : NODE; + E128 : NODE; + SCR128 : NODE; + XC[3..0] : NODE; + + SC[7..0] : DFFE; + PN[7..0] : DFFE; + SYS : DFFE; + AROM16 : DFFE; + TB_SW : DFFE; + BRD[7..0] : DFFE; + + DOS_ : NODE; + DOS_ON_ : NODE; + + CTH[5..0] : DFF; + CTV[8..0] : DFF; + CTF[4..0] : DFF; +-- SINC_H : NODE; + SINC_V : NODE; + BLANK : NODE; + BORD : NODE; + + TSN_W3 : DFF; + VCM[2..0] : DFF; + + V_CS[1..0] : DFF; + V_WR[3..0] : NODE; + VLA[17..0] : DFF; + VLAM[17..0] : NODE; + VLAB[17..0] : NODE; + VXA[17..0] : DFF; +-- VXA[17..0] : NODE; + SVA[17..0] : NODE; + V_WE : DFF; + + MODE0[7..0] : DFF; + MODE1[7..0] : DFF; + MODE2[7..0] : DFFE; +-- MODE3[7..0] : DFF; + WR_MODE : DFF; + WR_MODE2 : DFF; + WR_MODE2X : DFF; + + DPIC : DFF; + DCOL[7..0] : DFF; + + D_PIC0[7..0] : DFF; +-- D_PIC1[7..0] : DFF; +-- D_PIC2[7..0] : DFF; +-- D_PIC3[7..0] : DFF; + D_PIC0_[7..0] : NODE; +-- D_PIC1_[7..0] : NODE; +-- D_PIC2_[7..0] : NODE; +-- D_PIC3_[7..0] : NODE; + +-- D_COL0[7..0] : DFF; +-- D_COL1[7..0] : DFF; +-- D_COL2[7..0] : DFF; + + LD_PIC : NODE; + WR_PIC : DFF; + WR_COL : DFF; + + WR_KBD : NODE; + +-- TURBO : DFF; + TURBO : NODE; + + MC : NODE; + MC1 : NODE; + SD[7..0] : NODE; +-- SD_[7..0] : NODE; + + ROM : NODE; +-- AR[3..0] : NODE; + AR[3..0] : NODE; + PGA[7..0] : NODE; + +-- STEP,RDAT, +-- SINCIN, +-- TBS_IN : NODE; +-- RSTB,WSTB,SL,SR : NODE; +-- FOUT[7..0] : DFF; + + RGMOD[7..0] : DFFE; + RGACC[7..0] : DFF; + +-- VDX_[15..0] : NODE; + + MXVDD[7..0] : NODE; + MXVD[7..0] : DFF; + MXWE : NODE; + MXCE : NODE; + + BRVA[10..0] : NODE; + + X_MODE[7..4]: NODE; + + KB_D[10..0] : DFF; + KB_OFF : DFF; + KB_CT[2..0] : DFF; + KB_CTRL : DFF; + KB_ALT : DFF; + KB_SH : DFF; + KB_EXT : DFF; + KB_RESET : DFF; + + PGS[7..0] : NODE; + MPGS[7..0] : NODE; + WR_PG : NODE; + /IOM,/IOM1 : NODE; + CNF[7..0] : DFFE; + D_RD : NODE; + KD[7..0] : NODE; + KBD[5..0] : DFF; + KA[15..8] : NODE; + KDD[7..0] : DFF; + KDX[5..0] : DFF; + K_CLK : NODE; + + RXA[1..0] : DFF; + +-- RCCM[3..0] : DFF; + MC_START : DFF; + MC_END : NODE; + LMC_END : NODE; + + BLK_R : NODE; + /IORD,/IOWR : NODE; + + + IO_WAIT : NODE; + SC128 : NODE; + KDCA[2..0] : NODE; + LWR_PIC : NODE; + LWR_COL : NODE; + LWR_MODE : NODE; + LWR_MODE2 : NODE; + INTT : NODE; + + SND_D[7..0] : NODE; + SND_I[7..0] : NODE; + SND_A[7..0] : NODE; + SND_RR[7..0] : DFF; + SND_WR : NODE; + SND_C : DFF; + SND_TEST : DFF; + SND_OUT[7..0] : DFF; + SND_OUTL[7..0] : DFF; + SND_AMP[9..0] : DFF; + SND_AA[7..0] : DFF; + SND_A_LD : NODE; + + WR_AMP : DFF; + WR_AA : DFF; + WE_SND : DFF; + SND_OUTX : DFF; + CTH3X : DFF; + SND_SHL : NODE; + SND_SHR : NODE; + +-- COV_SINC : NODE; + + COV_DFF[7..0] : DFFE; + + COV[7..0] : NODE; + COV_WR : NODE; + COV_ADR[7..0] : NODE; + COV_CT[10..0] : DFF; + COV_BL[10..0] : DFF; + COV_BL_X[2..0] : NODE; + + STARTING : NODE; + + E_CAS_[3..0] : NODE; + + RA[21..0] : NODE; + + KB_CTRL_X : NODE; + KB_ALT_X : NODE; + KB_SH_X : NODE; + KB_XXX : NODE; + + V_WAIT : NODE; + + X_MODE_BOND : NODE; + + ACC_CNT[7..0] : DFF; +-- AA[13..0] : NODE; + AA[15..0] : DFF; + ACC_MODE[2..0] : DFF; + START_ACC : NODE; + ACC_END : DFF; + CB_CMD : DFF; + ED_CMD : DFF; + PRF_CMD : DFF; + ID_CMD : DFF; + IN_OUT_CMD : DFF; + CORRECT_1F : NODE; + + RFC : NODE; + + AY_ADR[7..0] : DFF; + AY_D_WR : NODE; + AY_AAX[7..0] : DFF; + + AY_F1[11..0] : DFF; + AY_F2[11..0] : DFF; + AY_F3[11..0] : DFF; + AY_X_[5..0] : DFFE; + + AY_S1[4..0] : DFF; + AY_A1[4..0] : DFF; + AY_A2[4..0] : DFF; + AY_A3[4..0] : DFF; + AY_GO[15..0] : DFF; +% + AY_S1[4..0] : LATCH; + AY_A1[4..0] : LATCH; + AY_A2[4..0] : LATCH; + AY_A3[4..0] : LATCH; + AY_GO[15..0] : LATCH; +% + AY_GF[3..0] : DFF; + + AY_C1[11..0] : DFF; + AY_C2[11..0] : DFF; + AY_C3[11..0] : DFF; + AY_C4[4..0] : DFF; + AY_C5[19..0] : DFF; + AY_OUT[3..1] : DFF; + AY_OUTS[3..1] : NODE; + AY_Q : NODE; + + AY_Q1[3..0] : NODE; + AY_Q2[3..0] : NODE; + AY_Q3[3..0] : NODE; + AY_CLK1 : NODE; + AY_SH[7..0] : DFFE; + AY_SHR : DFFE; + AY_AA[3..0] : DFF; + + AY_ABLK : NODE; + AY_BBLK : NODE; + AY_AINV : NODE; + AY_BINV : NODE; + AY_F_RES : NODE; + + AY_ADRX[7..0] : NODE; + AY_CCC[8..0] : DFF; + AY_DO[7..0] : NODE; + AY_DI[7..0] : NODE; + AY_AX[7..0] : NODE; + AY_C : DFFE; + AY_CX : DFFE; +-- AY_WR : DFF; + AY_WR : NODE; + AY_CH_WR : DFF; + AY_DRD : DFF; + AY_VA[3..0] : DFFE; + AY_VAR : DFFE; + AY_XX[5..0] : DFFE; + AY_XXM[5..0] : DFFE; + + AY_DAT_WR : DFFE; + AY_DAT[7..0] : DFFE; + +-- AY_DQ1[3..0] : DFFE; +-- AY_DQ2[3..0] : DFFE; +-- AY_DQ3[3..0] : DFFE; + + AY_AMP[3..0] : DFF; + + AY_DD[7..0] : DFFE; + + KB_MAGIC : DFF; + KB_MA[2..0] : DFF; + KB_MXA : NODE; + SC_PGS : NODE; + RASX : NODE; + CTRX : NODE; + /WE1 : NODE; + FN_ACC[2..0] : DFF; + MC_SYCLE : NODE; + KB_F12 : NODE; + INTT_T : NODE; + GLISSER : NODE; + + SINC_HH : NODE; + SINC_VV : NODE; + + AGR[7..0] : DFFE; + DC_CAS[1..0] : NODE; + + DCP_CX : NODE; + RBRVA[10..8] : DFF; + + ACC_RAM[7..0] : NODE; + + /WAITT : NODE; + AX128 : NODE; + + GR_Y[7..0] : NODE; + + ASS_DIR[7..0] : NODE; + + XMD[7..0] : NODE; + XXMD[7..0] : NODE; + + PG_SCR : NODE; + PRF_CMDX : NODE; + + CASH_ON : NODE; + AAA[15..14] : NODE; + COV_AR[7..6] : NODE; + V_SINC : NODE; + + SC_LCELL : NODE; + PG_SCR1 : NODE; + + KDXX[5..0] : DFF; + + A4_ZERO : NODE; + + XAGR[7..0] : DFF; + AAGR[9..0] : DFF; + XCNT[7..0] : DFF; + RETI : DFF; + ACC_BLK : DFF; + + MUL[31..0] : DFF; + PORT_NMI : NODE; + NMI_ENA : NODE; + RETN : DFF; + KBDR[2..0] : DFFE; + + SC0_X : NODE; + + % FORTH_PROCESSOR % + + ALU[15..0] : NODE; + STDO[15..0] : NODE; + STDO_[15..0] : NODE; + FDR_[15..0] : NODE; + +-- AC4,AC8,AC12 : NODE; + C_ALU : NODE; + + FDI[15..0] : NODE; + FDO[15..0] : NODE; + STA[7..0] : NODE; + + FDR[15..0] : DFF; + FCMD[15..0] : DFF; + CMD_X : NODE; + + + F_ST_[STACK_W-1..0] : NODE; + F_ST_X[STACK_W-1..0] : NODE; + F_ST_Y[STACK_W-1..0] : NODE; + F_ST0[STACK_W-1..0] : DFF; + F_ST1[STACK_W-1..0] : DFF; + F_ST2[STACK_W-1..0] : DFF; + F_ST3[STACK_W-1..0] : DFF; + ZERO[STACK_W-1..0] : NODE; + + F_CLK : DFF; + FP_CLK : NODE; + + WE_MEM : NODE; + +-- IMR[3..0] : DFF; + + CXX : DFF; +% + CXXX[4..0] : NODE; + CXX : NODE; +% +BEGIN + DEFAULTS + SND_R[] = GND; SND_L[] = GND; XC[2..0] = VCC; XC3 = GND; + V_CS[].d = VCC; V_WR[] = VCC; TSN_W3.d= VCC; V_WE.d = VCC; + WR_COL.d = VCC; WR_PIC.d = VCC; WR_MODE.d= VCC; FIN[] = VCC; + D_RD = GND; WR_KBD = VCC; SND_WR = GND; WR_AMP.d = VCC; + WR_AA.d = VCC; WE_SND.d = VCC; WR_MODE2.d= VCC; + ACC_END = VCC; KDD[].prn= VCC; WR_MODE2X.d = VCC; + F_CLK.d = VCC; +-- AY_WR.d = VCC; + AY_CH_WR.d = VCC; AY_DRD.d = VCC; + AY_C.prn = VCC; + + END DEFAULTS; + + FOR i IN 0 TO 3 GENERATE A[i] = TRI(GND,GND); END GENERATE; + FOR i IN 5 TO 15 GENERATE A[i] = TRI(GND,GND); END GENERATE; + A[4] = TRI (GND,A4_ZERO); +-- A4_ZERO = (READRESS == 1) & !/IO & (A[7..5] == B"000") & CASCADE (A[3..0] == B"1111"); + A4_ZERO = GND; + + CLK42 = TG42; + + XA[] = XC[2..0]; XACS = XC3; + +IF AY_3_8910 == 0 THEN + IF SPRINTER == 0 THEN + CASE (AAA15,AAA14) IS + WHEN 0 => MPGS[6..0] = (VCC,VCC,GND,AR[]); + WHEN 1 => MPGS[6..0] = B"1101001"; %H"E9"% + WHEN 2 => MPGS[6..0] = B"1101010"; %H"EA"% +-- WHEN 3 => MPGS[4..0] = (VCC,SC4,PN[2..0]); + WHEN 3 => MPGS[6..0] = (!PN7,!PN6,VCC,SC4,PN[2..0]); + END CASE; + MPGS[7] = VCC; + ELSE + CASE (AAA15,AAA14) IS + WHEN 0 => MPGS[4..0] = (GND,AR[]); + WHEN 1 => MPGS[4..0] = B"01001"; %H"E9"% + WHEN 2 => MPGS[4..0] = B"01010"; %H"EA"% + WHEN 3 => MPGS[4..0] = B"10000"; %H"F0"% + END CASE; + MPGS[7..5] = VCC; + END IF; +ELSE + CASE (A15,A14) IS + WHEN 0 => MPGS[6..0] = (VCC,VCC,GND,AR[]); + WHEN 1 => MPGS[6..0] = B"1101001"; %H"E9"% + WHEN 2 => MPGS[6..0] = B"1101010"; %H"EA"% + WHEN 3 => MPGS[6..0] = (!PN7,!PN6,VCC,SC4,PN[2..0]); + END CASE; + MPGS[7] = VCC; +END IF; + + SC_LCELL = LCELL(!SC1 & !(SC0 & SYS) & !CASH_ON); + + AR[] = ( LCELL(SC0 or !SYS or CASH_ON or !NMI_ENA), + LCELL(((AROM16 & !(SC0 & SYS)) or (CASH_ON & NMI_ENA))), + LCELL((DOS & SC_LCELL) or !SYS or !NMI_ENA), + LCELL(((S128 or !DOS) & SC_LCELL) or !SYS or !NMI_ENA)); + + STARTING = !(A14 & A15 & !DFF(GND,VCC,/RESET,(/IO or /RD))); + + CASE (LCELL(/IO & STARTING),MC_END) IS + WHEN B"1X" => PGS[] = MPGS[]; + WHEN B"01" => PGS[] = DCP[]; + WHEN B"00" => PGS[] = GND; + END CASE; + +IF SPRINTER == 1 THEN + PGA[] = lpm_ram_dq(D[7..0],PGS[7..0],WR_PG,!CLK42,) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="PGA_INI4.MIF", + lpm_adress_control="UNREGISTERED",lpm_indata="UNREGISTERED",lpm_outdata="UNREGISTERED"); +-- PGA[] = lpm_ram_dq(D[7..0],PGS[7..0],WR_PG,!CLK42,) +-- WITH (lpm_width=8,lpm_widthad=8,lpm_file="PGA_INI5.MIF", +-- lpm_adress_control="UNREGISTERED",lpm_indata="UNREGISTERED",lpm_outdata="UNREGISTERED"); +ELSE + PGA[] = lpm_ram_dq(D[7..0],PGS[7..0],WR_PG,!CLK42,) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="PGA_INI4.MIF", + lpm_adress_control="UNREGISTERED",lpm_indata="UNREGISTERED",lpm_outdata="UNREGISTERED"); +END IF; + + BLK_R = LCELL(!/MR & /RF & LCELL((PGA7 & PGA6 & ROM) or (PGA7 & SC_PGS))); + + SC_PGS = LCELL(A14 & A15 & SC4); + +-- IF SPRINTER == 1 THEN +-- ROM = GND; +-- ELSE + ROM = !LCELL(A14 or A15 or (SC0 & SYS & NMI_ENA)); +-- END IF; + + IF CASH_RAM == 1 THEN + CASH_ON = DFF(A7,(/IORD or !(DCP[] == H"88")),/RESET,); + ELSE + CASH_ON = GND; + END IF; + + SC0_X = LCELL(SC0 & SYS); + +-- IF DFF((/MR & /IO),!(MC_SYCLE or RAS),,!(/MR & /IO)) THEN + IF DFF((/MR & /IO),CLK42,,!(/MR & /IO)) THEN +-- IF (/MR & /IO) THEN + XC[2..0] = 6; + ELSE + XC[2..0] = PGA[6..4]; + END IF; + +-- XC3 = LCELL(BLK_R or LCELL(!/IOM1 & !DCP7 & !DCP6 & PGA7)) & !(/MR & /IO) & /RF; +-- XC3 = (BLK_R or DFF((!/IOM1 & !DCP7 & !DCP6 & PGA7),!CT2,!/IO,)) & !(/MR & /IO); + XC3 = (BLK_R or DFF((!/IOM1 & !DCP7 & !DCP6 & PGA7),!CT2,!/IO,)); + +-- IF BLK_R THEN XC[3] = /RF; END IF; +-- IF LCELL(!/IOM1 & !DCP7) THEN XC[3] = PGA[7] & /RF; END IF; + +-- IF (!/IOM1 & !DCP7) THEN XC[3] = PGA[7] & /RF; END IF; + + WR_PG = !(/IOWR or !(DCP[] == B"11XXXXXX")); + + PRF_CMD.clk = /M1 or /MR; +-- PRF_CMD.d = (D[] == H"CB") or (D[] == H"DD") or (D[] == H"ED") or (D[] == H"FD"); + + PRF_CMDX = CASCADE((D[] == B"XX00X01X") or + (D[] == B"XX01X10X") or + (D[] == B"XX10X10X") or + (D[] == B"XX11X10X")); + + PRF_CMD.d = (D[] == B"11XX1XX1") & PRF_CMDX; + +-- RETI comand + + ED_CMD.clk = /M1 or /MR; + ED_CMD.d = (D[] == H"ED"); + + RETI.clk = /M1 or /MR; + RETI.d = ED_CMD & (D[] == H"4D"); + +-- "1" on the RETI triger is the end of interupt sycle. + + RETN.clk = /M1 or /MR; + RETN.d = ED_CMD & (D[] == H"45"); + +-- The end of NMI sycle. + + ACC_BLK.clk = /M1; + ACC_BLK.d = (/IO & ACC_BLK) or (!ACC_BLK & RETI); + ACC_BLK.prn = /RESET; + +% + IMR[].clk = /M1 or /MR; + + IF ED_CMD & (D[] == B"0101X110") THEN + IMR0.d = D3; + ELSE + IMR0.d = IMR0; + END IF; + + IF ED_CMD & (D[] == B"X1X1X110") THEN + IMR1.d = D5; + IMR2.d = D7; + IMR3.d = A0; + ELSE + IMR[3..1] = IMR[3..1]; + END IF; +% + CB_CMD.clk = /M1 or /MR; + ID_CMD.clk = /M1 or /MR; + CB_CMD.d = (D[] == H"CB"); + ID_CMD.d = (D[] == B"11X11101"); + + IN_OUT_CMD.clk = /M1 or /MR; + IN_OUT_CMD.d = (D[] == B"1101X011") & !PRF_CMD; + IN_OUT_CMD.clrn = /IO; + + CORRECT_1F = LCELL(IN_OUT_CMD & (DD[] == H"1F") & !/MR & !/RD); + DD[4..3].clrn = !CORRECT_1F or (PORT_1F == 0) or !(READRESS == 0); + DCP[4..3].clrn = !CORRECT_1F or (PORT_1F == 0) or !(READRESS == 0); + +-- IF MULT == 1 THEN + + + MUL[23..16].clk = /WR or /MR or !A0; + (MUL[31..24].clk,MUL[15..0].clk) = CLK42; + + MUL[23..16].d = D[]; + + IF /WR THEN + + MUL[31..24].d = MUL[31..24] + 1; + + IF MUL15 THEN + MUL[15..0].d = (MUL[14..0],0) + (B"00000000",MUL[23..16]); + ELSE + MUL[15..0].d = (MUL[14..0],0); + END IF; + + ELSE + + MUL[31..24].d = 0; + MUL[15..0].d = (D[],B"00000000"); + + END IF; + +-- END IF; + +-- ============= ACCELERATOR ============ + +IF !(ACCELERAT == 0) THEN +IF (ACCELERAT == 1) THEN + + RGACC[].clk = (/MR or !/M1 or (/RD & /WR)) or !ASS_DIR3; + RGACC[].d = D[]; + + AGR[].ena = VCC; + AGR[].clk = (START_ACC or (!ASS_DIR4 or RAS)) & + CASCADE((/IOWR or !DCP_CX) or !(DCP[] == B"XXXXX100")); + + CASE !START_ACC IS + WHEN 1 => AGR[].d = AGR[] + 1; + WHEN 0 => AGR[].d = D[]; + END CASE; + +-- IF !START_ACC THEN AGR[].d = AGR[] + 1; ELSE AGR[].d = D[]; END IF; + + AGR[].clrn = /RESET; + + ACC_CNT[].clk = !CT2; + + ACC_END.clk = (RAS or START_ACC); + ACC_END.prn = /M1; + + ACC_END.d = (ACC_CNT[] == 1) or !ASS_DIR2; + CASE START_ACC IS + WHEN 1 => ACC_CNT[].d = RGACC[]; + WHEN 0 => ACC_CNT[].d = ACC_CNT[] - 1; + END CASE; + + FN_ACC[].clk = /M1 or /MR; + FN_ACC[].d = D7 & !D6 & !PRF_CMD & !(D[5..3]); + FN_ACC[].clrn = (ACCELER_FN == 1); + + CASE FN_ACC[1..0] IS + WHEN 0 => + XMD[] = MD[]; % BE % + WHEN 1 => + XMD[] = MD[] or ACC_RAM[]; % B6 % + WHEN 2 => + XMD[] = MD[] xor ACC_RAM[]; % AE % + WHEN 3 => + XMD[] = MD[] & ACC_RAM[]; % A6 % + END CASE; + + CXX.clk = !CT2; + CXX.clrn = !START_ACC; + +-- IF !FN_ACC2 THEN + (XXMD[],CXX) = (XMD[],CXX); +-- ELSE +-- (XXMD[],CXX) = ((GND,MD[]) + (GND,ACC_RAM[])); +-- END IF; + + ACC_MODE[].clk = (/M1 or /MR); + +% + !LCELL(((D[] == B"XXX00X00") or + (D[] == B"XXX01X01") or + (D[] == B"XXX10X10") or + (D[] == B"XXX11X11")) + & CASCADE((D[] == B"010XX0XX") or (D[] == B"011XX1XX"))); + + ACC_MODE[].d = D[2..0]; +% + CASE (LCELL(((D[] == B"XXX00X00") or + (D[] == B"XXX01X01") or + (D[] == B"XXX10X10") or + (D[] == B"XXX11X11")) + & CASCADE((D[] == B"010XX0XX") or (D[] == B"011XX1XX"))), + !PRF_CMD) IS + + WHEN 3 => ACC_MODE[].d = D[2..0]; + WHEN 2,1,0 => ACC_MODE[].d = ACC_MODE[]; + + END CASE; + +% + IF LCELL( + ( + LCELL(((D[] == B"XXX00X00") or + (D[] == B"XXX01X01") or + (D[] == B"XXX10X10") or + (D[] == B"XXX11X11")) + & CASCADE((D[] == B"010XX0XX") or (D[] == B"011XX1XX"))) +% +-- (D[] == B"01000000") % LD B,B % +-- or (D[] == B"01001001") % LD C,C % % fill by constant % +-- or (D[] == B"01010010") % LD D,D % % load count accelerator % +-- or (D[] == B"01011011") % LD E,E % % fill by constant VERTICAL % +-- or (D[] == B"01100100") % LD H,H % % set graf line % +-- or (D[] == B"01101101") % LD L,L % % copy line % +-- or (D[] == B"01110110") % HALT % +-- or (D[] == B"01111111") % LD A,A % % copy line VERTICAL % +% ) + & !PRF_CMD + ) + THEN + ACC_MODE[].d = D[2..0]; + ELSE + ACC_MODE[].d = ACC_MODE[]; + END IF; +% + ACC_MODE[].clrn = /RESET; +% + ASS_DIR0 = !((ACC_MODE[] == 0) or (ACC_MODE[] == 6)); + ASS_DIR1 = ACC_MODE0 & ACC_MODE2; + ASS_DIR2 = ACC_MODE0; + ASS_DIR3 = ACC_MODE[] == 2; + ASS_DIR4 = ACC_MODE[] == B"X11"; + ASS_DIR5 = ACC_MODE[] == B"X01"; + ASS_DIR[7..6] = GND; +% +-- CASE (!ACC_BLK,ACC_MODE[]) IS + CASE ACC_MODE[] IS + WHEN 0 => ASS_DIR[] = B"00000000"; + WHEN 1 => ASS_DIR[] = B"00100101"; + WHEN 2 => ASS_DIR[] = B"00001001"; + WHEN 3 => ASS_DIR[] = B"00010101"; + WHEN 4 => ASS_DIR[] = B"01100111"; + WHEN 5 => ASS_DIR[] = B"00100111"; + WHEN 6 => ASS_DIR[] = B"00000001"; + WHEN 7 => ASS_DIR[] = B"00010111"; +-- WHEN 8,9,10,11,12,13,14,15 => ASS_DIR[] = B"00000000"; + END CASE; + +-- START_ACC = LCELL(/MR or !/M1 or LCELL(/RD & /WR) or LCELL(!ASS_DIR0 or MC_SYCLE)); +-- START_ACC = LCELL(/MR or !/M1 or (/RD & /WR) or (!ASS_DIR0 or MC_SYCLE)); + START_ACC = !LCELL(NMI_ENA & !(/MR or !/M1 or (/RD & /WR)) & (!(!ASS_DIR0 or MC_SYCLE))); + + ACC_RAM[7..0] = lpm_ram_dq(XXMD[],ACC_CNT[],(!/RD & !START_ACC & (CT2 & CT0)),CLK42,) +-- ACC_RAM[7..0] = lpm_ram_dq(XMD[],ACC_CNT[],(!/RD & !START_ACC),LCELL(CLK42),) + WITH (lpm_width=8,lpm_widthad=8,lpm_outdata="UNREGISTERED"); + + CASE ASS_DIR1 IS + WHEN 1 => MXVDD[] = ACC_RAM[]; + WHEN 0 => MXVDD[] = D[]; + END CASE; + +-- IF ASS_DIR1 THEN MXVDD[] = ACC_RAM[]; ELSE MXVDD[] = D[]; END IF; +% + AA[7..0].clk = !(/MR & /IO) & (!ASS_DIR5 or RAS); + AA[15..8].clk = !(/MR & /IO) & (!ASS_DIR5 or !AA7); + + CASE START_ACC IS + WHEN 1 => AA[].d = (GND,GND,A[13..0]); + WHEN 0 => AA[7..0].d = AA[7..0] + 1; + AA[15..8].d = AA[15..8] + 1; + END CASE; + +% + AA[].clk = !(/MR & /IO) & (!ASS_DIR5 or RAS); + CASE START_ACC IS + WHEN 1 => AA[].d = (GND,GND,A[13..0]); + WHEN 0 => AA[].d = AA[] + 1; + END CASE; + +-- IF START_ACC THEN AA[].d = (GND,GND,A[13..0]); ELSE AA[].d = AA[] + 1; END IF; + + AAA[] = A[15..14] + AA[15..14]; + +-- MXVD[].d = MXVDD[]; + + MXVD[].clk = V_SINC; + MXVD[].d = (LCELL(MXVDD7),LCELL(MXVDD6),LCELL(MXVDD5),LCELL(MXVDD4), + LCELL(MXVDD3),LCELL(MXVDD2),LCELL(MXVDD1),LCELL(MXVDD0)); + +ELSE +-- ACCELERATOR = 3 + + RGACC[].clk = (/MR or !/M1 or (/RD & /WR)) or !ASS_DIR3; + RGACC[].d = D[]; + + AGR[].ena = VCC; + AGR[].clk = (START_ACC or (!ASS_DIR4 or RAS)) & + ((/IOWR or !DCP_CX) or !(DCP[] == B"XXXXX100")); + + (AAGR[].clk,XCNT[].clk,XAGR[].clk) = (START_ACC or (!ASS_DIR1 or CAS)) & + ((/IOWR or !DCP_CX) or !(DCP[] == B"XXXXX111")); + + CASE !START_ACC IS + WHEN 1 => AGR[].d = AGR[] + 1; + WHEN 0 => AGR[].d = D[]; + END CASE; + + AGR[].clrn = /RESET; + + ACC_CNT[].clk = !CT2; + + ACC_END.clk = (RAS or START_ACC); + ACC_END.prn = /M1; + + ACC_END.d = (ACC_CNT[] == 1) or !ASS_DIR2; + +-- (XCNT[].clrn,XAGR[].clrn) = /M1; + + CASE !START_ACC IS + WHEN 1 => AAGR[].d = AAGR[]; + (XCNT[].d,XAGR[].d) = (XCNT[],XAGR[]) + (B"000000",AAGR[]); + WHEN 0 => AAGR[].d = (A9,A8,D[]); + (XCNT[].d,XAGR[].d) = (B"00",A[15..10],B"00000000"); + END CASE; + + CASE START_ACC IS + WHEN 1 => ACC_CNT[].d = RGACC[]; + WHEN 0 => ACC_CNT[].d = ACC_CNT[] - 1; + END CASE; + + XMD[] = MD[]; + + ACC_MODE[].clk = (/M1 or /MR); + + CASE (LCELL(((D[] == B"XXX00X00") or + (D[] == B"XXX01X01") or + (D[] == B"XXX10X10") or + (D[] == B"XXX11X11")) + & CASCADE((D[] == B"010XX0XX") or (D[] == B"011XX1XX"))), + !PRF_CMD) IS + + WHEN 3 => ACC_MODE[].d = D[2..0]; + WHEN 2,1,0 => ACC_MODE[].d = ACC_MODE[]; + + END CASE; + + ACC_MODE[].clrn = /RESET; + + CASE ACC_MODE[] IS + WHEN 0 => ASS_DIR[] = B"00000000"; + WHEN 1 => ASS_DIR[] = B"00100101"; + WHEN 2 => ASS_DIR[] = B"00001001"; + WHEN 3 => ASS_DIR[] = B"00010101"; + WHEN 4 => ASS_DIR[] = B"00000001"; + WHEN 5 => ASS_DIR[] = B"00100111"; + WHEN 6 => ASS_DIR[] = B"00000000"; + WHEN 7 => ASS_DIR[] = B"00010111"; + END CASE; + + START_ACC = !LCELL(NMI_ENA & ACC_BLK & !(/MR or !/M1 or (/RD & /WR)) & (!(!ASS_DIR0 or MC_SYCLE))); + + ACC_RAM[7..0] = lpm_ram_dq(XMD[],XCNT[],(!/RD & !START_ACC & ASS_DIR1),CAS,) + WITH (lpm_width=8,lpm_widthad=8,lpm_outdata="UNREGISTERED"); + + CASE ASS_DIR1 IS + WHEN 1 => MXVDD[] = ACC_RAM[]; + WHEN 0 => MXVDD[] = D[]; + END CASE; + + AA[].clk = !(/MR & /IO) & (!ASS_DIR5 or RAS); + CASE START_ACC IS + WHEN 1 => AA[].d = (GND,GND,A[13..0]); + WHEN 0 => AA[].d = AA[] + 1; + END CASE; + + AAA[] = A[15..14] + AA[15..14]; + + MXVD[].clk = V_SINC; + MXVD[].d = (LCELL(MXVDD7),LCELL(MXVDD6),LCELL(MXVDD5),LCELL(MXVDD4), + LCELL(MXVDD3),LCELL(MXVDD2),LCELL(MXVDD1),LCELL(MXVDD0)); + +END IF; +ELSE + + + AGR[].ena = (DCP[] == B"XXXXX100"); + AGR[].clk = /IOWR or !DCP_CX; + AGR[].d = D[]; + + AGR[].clrn = /RESET & (AY_3_8910 == 0); + + START_ACC = VCC; + ACC_END.prn = GND; + AA[].clk = !(/MR & /IO); + + AA[].d = A[]; + AAA[] = A[15..14]; + + MXVDD[] = D[]; + +-- MXVD[].d = MXVDD[]; + + MXVD[].clk = V_SINC; + +% IF AY_3_8910 == 0 THEN + +ELSE % +-- MXVD[].d = (LCELL(MXVDD7),LCELL(MXVDD6),LCELL(MXVDD5),LCELL(MXVDD4), +-- LCELL(MXVDD3),LCELL(MXVDD2),LCELL(MXVDD1),LCELL(MXVDD0)); + MXVD[].d = D[]; +-- END IF; + +END IF; + +-- ===================================================== + + IF !START_ACC & ASS_DIR6 & (ACC_DECODE == 1) THEN + GR_Y[] = ACC_RAM[]; + ELSE + GR_Y[] = AGR[7..0]; + END IF; + +IF (SCREEN == 1) THEN + PG_SCR1 = (PGA[] == B"0101XXXX") or (PGA[] == B"1010XXXX"); +ELSE + PG_SCR1 = PG_SCR; +END IF; + + + +IF AY_3_8910 == 0 THEN + +IF NEWS == 1 THEN + + PG_SCR = lcell(PGA[] == B"0101XXXX"); + + RA[21..18] = PGA[7..4]; + + CASE (/IO,PG_SCR) IS + WHEN B"0X" => + RA[17..0] = (PGA[3..0],CNF4,CNF3,GND,DOS,/WR,A15,A14,AA6,AA5,AA13,AA7,AA2,AA1,AA0); + WHEN B"10" => + RA[17..0] = (PGA[3..0],AA[13..0]); + WHEN B"11" => + RA[17..0] = (AA[9..0],GR_Y[]); + END CASE; + + +% + IF /IO THEN + IF PG_SCR THEN + RA[17..0] = (AA[9..0],GR_Y[]); + ELSE + RA[17..0] = (PGA[3..0],AA[13..0]); + END IF; + ELSE + RA[17..0] = (PGA[3..0],CNF4,CNF3,GND,DOS,/WR,A15,A14,AA6,AA5,AA13,AA7,AA2,AA1,AA0); + END IF; +% + +ELSE + + PG_SCR = lcell(PGA[] == B"0101XXXX"); + + RA[21..18] = PGA[7..4]; + + RA[6..5] = AA[6..5]; RA[2..0] = AA[2..0]; + + CASE (/IO,PG_SCR) IS + WHEN B"0X" => + (RA[17..7],RA[4..3]) = (PGA[3..0],CNF4,CNF3,GND,DOS,/WR,A15,A14,AA13,AA7); + WHEN B"10" => + (RA[17..7],RA[4..3]) = (PGA[3..0],AA[13..7],AA[4..3]); + WHEN B"11" => + (RA[17..7],RA[4..3]) = (GR_Y[],AA[9..7],AA[4..3]); + END CASE; +% + IF /IO THEN + IF PG_SCR THEN + RA[17..10] = (GR_Y[]); + ELSE + RA[17..10] = (PGA[3..0],AA[13..10]); + END IF; + RA[9..0] = AA[9..0]; + ELSE + RA[17..0] = (PGA[3..0],CNF4,CNF3,GND,DOS,/WR,A15,A14,AA6,AA5,AA13,AA7,AA2,AA1,AA0); + END IF; +% + +END IF; + +ELSE + + PG_SCR = GND; + RA[21..14] = PGA[7..0]; + RA[6..5] = AA[6..5]; RA[2..0] = AA[2..0]; + + CASE /IO IS + WHEN 1 => (RA[13..7],RA4,RA3) = (AA[13..7],AA4,AA3); + WHEN 0 => (RA[13..7],RA4,RA3) = (CNF4,CNF3,GND,DOS,/WR,A15,A14,AA13,AA7); + END CASE; + +END IF; + + IF DFF(RAS,CLK42,!(BLK_R or MC_END),) THEN + MA[] = (RA17,RA[9..0]); + ELSE + MA[] = (RA[17..14],RA[21..18],RA[13..12],RA17); + END IF; + + DC_CAS[] = RA[11..10]; + +-- ===================================================== + + KBDR[].clk = /IOWR or !DCP_CX; + AROM16.clk = /IOWR or !DCP_CX; + SYS.clk = /IOWR or !DCP_CX; + TB_SW.clk = /IOWR or !DCP_CX; + CNF[].clk = /IOWR or !DCP_CX; + SC[].clk = /IOWR or !DCP_CX; + PN[].clk = /IOWR or !DCP_CX; + BRD[].clk = /IOWR or !DCP_CX; + RGMOD[].clk = /IOWR or !DCP_CX; + + + KBDR[].ena = (DCP[] == B"XXXXX110"); KBDR[] = D[7..5]; + + BRD[].ena = (DCP[] == B"XXXXX010"); BRD[].d = D[]; + + RGMOD[].ena = (DCP[] == B"XXXXX101"); RGMOD[].d = D[]; + + + DCP_CX = LCELL(DCP[] == B"1100XXXX"); + AROM16.ena = ((DCP[] == B"XXXXX110") & !D1); AROM16.d= D0; + SYS.ena = (DCP[] == B"XXXXX110"); SYS.d = !A6; + TB_SW.ena = ((DCP[] == B"XXXXX110") & D1 ); TB_SW.d = D0; + CNF[].ena = ((DCP[] == B"XXXXX110") & D2 ); CNF[].d = D[]; + SC[].ena = (DCP[] == B"XXXXX000"); SC[].d = D[]; + PN[5..0].ena = ((DCP[] == B"XXXXX001") & !E128) or (DCP[] == B"XXXX1001"); + PN[7..6].ena = (DCP[] == B"XXXX1001"); PN[].d = D[]; + +% + + IF ((DCP[] == B"XXXXX110") & !D1) THEN AROM16.d= D0; ELSE AROM16.d= AROM16; END IF; + IF ((DCP[] == B"XXXXX110") ) THEN SYS.d = !A6; ELSE SYS.d = SYS ; END IF; + IF ((DCP[] == B"XXXXX110") & D1 ) THEN TB_SW.d = D0; ELSE TB_SW.d = TB_SW ; END IF; + IF ((DCP[] == B"XXXXX110") & D2 ) THEN CNF[].d = D[]; ELSE CNF[].d = CNF[] ; END IF; + + IF (DCP[] == B"XXXXX110") THEN KBDR[] = D[7..5]; ELSE KBDR[] = KBDR[]; END IF; + + IF (DCP[] == B"XXXXX000") THEN SC[].d = D[]; ELSE SC[].d = SC[]; END IF; + + IF (DCP[] == B"XXXXX010") THEN BRD[].d = D[]; ELSE BRD[].d= BRD[]; END IF; + IF (DCP[] == B"XXXXX101") THEN RGMOD[].d = D[]; ELSE RGMOD[].d = RGMOD[]; END IF; + +-- IF (DCP[] == B"XXXXX001") THEN PN[].d = D[]; ELSE PN[].d = PN[]; END IF; + + IF ((DCP[] == B"XXXXX001") & !E128) or (DCP[] == B"XXXX1001") + THEN PN[5..0].d = D[5..0]; ELSE PN[5..0].d = PN[5..0]; END IF; + + IF (DCP[] == B"XXXX1001") THEN PN[7..6].d = D[7..6]; ELSE PN[7..6].d = PN[7..6]; END IF; +% + + +-- AGR[].clrn = /RESET; +-- CNF[].clrn = /RESET; +-- SC[].clrn = /RESET; +-- SYS.clrn = /RESET; +-- AROM16.clrn = /RESET; + +-- TB_SW.clrn = /RESET or !TBS_IN; +-- TB_SW.prn = /RESET or TBS_IN; + + IF KEYBOARD != 0 THEN + KBDR[].clrn = GND; + ELSE + KBDR[].clrn = /RESET; + END IF; + + TB_SW.clrn = VCC; + TB_SW.prn = /RESET; + SYS.clrn = /RESET; + SYS.prn = VCC; + AROM16.clrn = /RESET; + CNF[].clrn = /RESET & (CONFIGS == 1); + SC[].clrn = /RESET; + +IF S128_OFF == 0 THEN + PN6.clrn = /RESET & (PENTAGON512 == 1); + PN7.clrn = /RESET & (PENTAGON512 == 1); + PN[5..0].clrn = /RESET; + SCR128 = PN3; + S128 = PN4; + E128 = PN5; +ELSE + PN[].clrn = GND; + SCR128 = GND; + S128 = VCC; + E128 = GND; +END IF; + +-- DOS_ = (!(LCELL(S128 & A13 & A12) & LCELL(A[11..8] == B"1101")) & DOS) or LCELL(A14 or A15); + DOS_ = (!((S128 & A13 & A12) & (A[11..8] == B"1101")) & DOS) or (A14 or A15); + + IF SPRINTER == 1 THEN + DOS = VCC; + DOS_ON_ = VCC; + ELSE + DOS = DFF(DOS_,!(/M1 or /MR),,/RESET); + DOS_ON_ = DFF((DOS or !DFF(DOS,RAS,,)),RAS,,); + -- DOS_ON_ = VCC; + END IF; + + CASE (/IO,DCP7) IS + WHEN B"1X" => + + IF ((ASS_DIR6 & !LCELL(START_ACC)) & MULT) THEN +-- IF ASS_DIR6 THEN + SD[] = (MUL[15..8] & A0) or (MUL[7..0] & !A0); + ELSE + SD[] = DD[]; + END IF; + + WHEN B"01" => + SD[] = PGA[]; + WHEN B"00" => + IF (KEYBOARD != 2) THEN + SD[] = KD[]; + ELSE + IF DCP4 & (AY_3_8910 == 3) THEN + SD[] = AY_DD[]; + ELSE + IF DCP5 & (PORT_FF == 1) THEN + SD[] = (BRVA[7..0]); + ELSE + IF (ISD_KBD == 1) THEN + SD[] = (KBD5,TAPE_IN,VCC,KBD[4..0]); + ELSE + SD[] = (KD5,TAPE_IN,VCC,KD[4..0]); + END IF; + END IF; + END IF; + END IF; + END CASE; + + D_RD = !(/IORD or (DCP[7..6] == 0)) or !(DFF(/RD,!(CAS or BLK_R or !RFC),,!/MR)); + + FOR i IN 0 TO 7 GENERATE + D[i] = TRI (SD[i],D_RD); + MD[i] = TRI (MXVDD[i],!/WE); + +% + VD0[i] = TRI (MXVDD[i],!V_WR0); + VD1[i] = TRI (MXVDD[i],!V_WR1); + VD2[i] = TRI (MXVDD[i],!V_WR2); + VD3[i] = TRI (MXVDD[i],!V_WR3); +% +-- IF FORTH_CPU == 1 THEN +% + VD0[i] = TRI (FDO[i],!V_WR0); + VD1[i] = TRI (FDO[i+8],!V_WR1); + VD2[i] = TRI (FDO[i],!V_WR2); + VD3[i] = TRI (FDO[i+8],!V_WR3); +% +-- ELSE + + VD0[i] = TRI (MXVD[i],!V_WR0); + VD1[i] = TRI (MXVD[i],!V_WR1); + VD2[i] = TRI (MXVD[i],!V_WR2); + VD3[i] = TRI (MXVD[i],!V_WR3); + +-- END IF; + END GENERATE; + + MXA[] = MA[]; + +-- ============= IN-OUT PINS ================== + + TURBO_LED = !TURBO; + + CLK_PIX = LCELL(TSN_W3); + + CASE CT[5..4] IS + WHEN B"00" => BEEPER = GND; + WHEN B"01" => BEEPER = BRD4; + WHEN B"10" => BEEPER = BRD4; + WHEN B"11" => BEEPER = VCC; + END CASE; + +IF (MODEM == 1) THEN + + CASE CT[5..3] IS + WHEN B"000" => TAPE_OUT = GND; + WHEN B"001" => TAPE_OUT = BRD5; + WHEN B"01X" => TAPE_OUT = BRD5; + WHEN B"10X" => TAPE_OUT = BRD5; + WHEN B"110" => TAPE_OUT = BRD3; + WHEN B"111" => TAPE_OUT = VCC; + END CASE; + +ELSE + TAPE_OUT = BRD3; +END IF; + + KBD_CC = DFF(KBD_CLK,CTH2,,); + KBD_DD = DFF(KBD_DAT,CTH2,,); + + KBD_CLK = TRI(!KBDR2,KBDR0); + KBD_DAT = TRI(!KBDR1,KBDR0); + +-- ============== RESET & INT ==================== + + /RESET = OPNDRN(DFF(VCC,CTV0,KB_RESET,)); + +IF !(VIDEO == 0) THEN + IF KEYBOARD == 3 THEN + INTT = DFF((INTT & !/INT),(INTT_T xor (KB_CT[] == 1)),,((/IO or /M1))); + ELSE + IF (ACCELERAT == 0) THEN + INTT = DFF((INTT & !/INT),INTT_T,,((/IO or /M1) & CTH5)); + ELSE + INTT = DFF((INTT & !/INT),INTT_T,,(/IO or /M1)); + END IF; + END IF; +ELSE + INTT = DFF(GND,DFF(SINC_V,CT5,,),,((/IO or /M1) & CTH5)); +END IF; + + /INT = OPNDRN(INTT); + /NMI = OPNDRN(PORT_NMI); + +IF NMI_USE == 1 THEN +-- PORT_NMI = DFF(!(DCP[] == B"1011XXXX"),!/IOM1,,(!/WAITT & NMI_ENA)); + PORT_NMI = DFF((KB_MAGIC or PRF_CMD),!(/RF or /MR),,DFF(PORT_NMI,CLKZ1,/RESET,)); + NMI_ENA = DFF(DFF(GND,PORT_NMI,,RETN),!/M1,,/RESET); +ELSE + PORT_NMI = VCC; + NMI_ENA = VCC; +END IF; + +-- /NMI = OPNDRN(INTT); +-- /NMIT = DFF(KB_MAGIC,(/MR or /M1 or !(A14 or A15)),,DOS); + +-- ============= TURBO MODE ====================== + + IF (F12_TURBO == 1) THEN + TURBO = DFF((TB_SW & TFF(!KB_CTRL,KB_F12,,/RESET)),/M1,,); + ELSE + IF (ACCELERAT == 0) THEN + TURBO = DFF(TB_SW,/M1,,); + ELSE + TURBO = VCC; + END IF; + END IF; + +-- CTRX = LCELL(CT1 & !CT2); + + CTRX = CT0 xor CT2; + + CLKZ1 = DFF(((CTRX & TURBO) or (CT3 & !TURBO)),CLK42,,); + +--===================================================== + + /IOM = DFF(!/M1,CT0,,!/IO); + /IOM1 = DFF(!(MC_END & /M1),CT2,,!/IO); +-- /IOM1 = DFF((!(MC_END & /M1) or IO_WAIT),CT2,,!/IO); + + /IOWR = (/IOM1 or /WR); + /IORD = (/IOM1 or /RD); +-- /IOWR = DFF(!(MC_END & /M1 & !/WR),CT2,,!/IO); +-- /IORD = DFF(!(MC_END & /M1 & !/RD),CT2,,!/IO); + +-- =============== SIMM DISPATCHER ================= + + MC = ((/MR & /IOM) or LMC_END); +-- MC = ((/MR & (/IO or !/M1)) or MC_END); + + /WAITT = (IO_WAIT & V_WAIT); + + /WAIT = OPNDRN(/WAITT); + +-- MC1 = DFF((MC or DFF((/WR & /RD),CLK42,,)),CLK42,,!MC_END); + MC1 = DFF(((/MR & /IOM) or (/WR & /RD)),!CLK42,,!MC_END); + + MC_END = DFF((MC_END or (DOS_ON_ & !MC_START & ACC_END)),CAS,!(/MR & /IO),); + +-- MC_END = DFF((MC_END or (DOS_ON_ & !MC_START & ACC_END)),LCELL(RAS),!(/MR & /IO),); + +-- IO_WAIT = /IO or !/M1 or (LMC_END & DFF(!(DCP[7..6] == 0) or DFF(DFF(VCC,CT2,!/IOM1,),CT2,!/IOM1,),CT2,!/IOM1,)); + IO_WAIT = /IO or !/M1 or (!TURBO & START_ACC) or (LMC_END & DFF(!(DCP[7..6] == 0) or DFF(DFF(VCC,CT2,!/IOM1,),CT2,!/IOM1,),CT2,!/IOM1,)); + V_WAIT = (/MR or MC_END or (!TURBO & START_ACC) or +-- DFF(((PGA[7..4] == 15) or (PGA[7..4] == 10)),CLKZ1,BLK_R,)); +-- DFF(((PGA[7..4] == 15) or (PGA[7..4] == 10)),CLK42,BLK_R,)); + DFF(((PGA[7..4] == 15)),CLK42,BLK_R,)); + + MC_START.clk = !CT2; + MC_START.d = MC1; + MC_START.prn = !(/MR & /IO); + + MC_SYCLE = DFF((MC1 or BLK_R),!CT2,,); + +-- RAS = DFF(((MC_SYCLE or CT2) & (DFF(CAS,CLK42,,) or /RF or !(MC_SYCLE))),CLK42,,); +-- CAS = DFF(((MC_SYCLE or RAS) & (!RAS or /RF or !MC_SYCLE)),CLK42,,); + + RAS = DFF(CT2,CLK42,,); + RASX = DFF(RAS,CLK42,,); +-- CAS = DFF(RASX,!CLK42,,); + CAS = DFF((!CT2 xor CT1),!CLK42,,); + +-- CAS = DFF(((CT2 or CT0) & (CAS or !CT0)),CLK42,,); + +-- RAS = DFF(((MC_SYCLE or CT2) & (CAS or !MC_SYCLE)),CLK42,,); +-- CAS = DFF(((MC_SYCLE or RAS) & (CT2 or !MC_SYCLE)),CLK42,,); + + RFC = !MC_SYCLE; + + IF (AY_3_8910 != 0) THEN + /WE = /WE1; + /WE1 = (/WR or /MR or MC_SYCLE or ROM); + ELSE + /WE = /WE1 or ROM or (PG_SCR & PGA2); + /WE1 = (/WR or /MR or MC_SYCLE or GLISSER); + GLISSER = ((MXVDD[] == H"FF") & (PG_SCR & PGA3)); + END IF; + +-- E_CAS_0 = LCELL(!(DC_CAS[] == 0) or BLK_R); +-- E_CAS_1 = LCELL(!(DC_CAS[] == 1) or BLK_R); +-- E_CAS_2 = LCELL(!(DC_CAS[] == 3) or BLK_R); +-- E_CAS_3 = LCELL(!(DC_CAS[] == 2) or BLK_R); + + E_CAS_0 = DFF((!(DC_CAS[] == 0) or BLK_R),!RAS,,); + E_CAS_1 = DFF((!(DC_CAS[] == 1) or BLK_R),!RAS,,); + E_CAS_2 = DFF((!(DC_CAS[] == 3) or BLK_R),!RAS,,); + E_CAS_3 = DFF((!(DC_CAS[] == 2) or BLK_R),!RAS,,); + +-- CAS_[] = LCELL(CAS & DFF(CAS,!CLK42,,)) or (E_CAS_[] & RFC); + +-- CAS_0 = DFF((CAS or (E_CAS_0 & RFC)),!CLK42,,); +-- CAS_1 = DFF((CAS or (E_CAS_1 & RFC)),!CLK42,,); +-- CAS_2 = DFF((CAS or (E_CAS_2 & RFC)),!CLK42,,); +-- CAS_3 = DFF((CAS or (E_CAS_3 & RFC)),!CLK42,,); + + CAS_0 = ((CAS or E_CAS_0 or MC_SYCLE) & (RAS or !MC_SYCLE)); + CAS_1 = ((CAS or E_CAS_1 or MC_SYCLE) & (RAS or !MC_SYCLE)); + CAS_2 = ((CAS or E_CAS_2 or MC_SYCLE) & (RAS or !MC_SYCLE)); + CAS_3 = ((CAS or E_CAS_3 or MC_SYCLE) & (RAS or !MC_SYCLE)); + + RAS_[] = (RAS or MC_SYCLE) & (CAS or !MC_SYCLE); + + LMC_END = DFF(MC_END,CLK42,,); +-- LMC_END = DFF(MC_END,!CLK42,,); + DCP[].clk = (LMC_END); + DD[].clk = (LMC_END); + +IF (PENTAGON512 == 1) THEN + CASE (LCELL(MD[7..4] == 15),/IO) IS + WHEN 0,1,3 => DCP[].d = MD[]; DD[].d = MD[]; + WHEN 2 => DCP[].d = (VCC,!PN7,!PN6,VCC,SC4,PN[2..0]); DD[].d = (VCC,!PN7,!PN6,VCC,SC4,PN[2..0]); + END CASE; +ELSE + CASE (LCELL(MD[7..4] == 15),/IO) IS + WHEN 0,1,3 => DCP[].d = MD[]; DD[].d = MD[]; + WHEN 2 => DCP[].d = (B"1111",SC4,PN[2..0]); DD[].d = (B"1111",SC4,PN[2..0]); + END CASE; +END IF; +% + IF ((LCELL(MD[7..4] == 15) & !/IO) & (SPRINTER == 0)) THEN + DCP[].d = (MD[7..4],SC4,PN[2..0]); + DD[].d = (MD[7..4],SC4,PN[2..0]); + ELSE + DCP[].d = MD[]; + DD[].d = MD[]; + END IF; +% +-- ================= COUNTERS ================= + + CT[].clk = CLK42; + + CT[1..0].d = (CT0,!(CT1 or CT0)); + CASE CT1 IS + WHEN 1 => CT[5..2].d = CT[5..2] + 1; + WHEN 0 => CT[5..2].d = CT[5..2]; + END CASE; + + CTH[2..0].clk = !CT5; + CTH[2..0].d = CTH[2..0] + 1; + + CTH[5..3].clk = !CTH2; + + CASE CTH[5..3] IS + WHEN B"110" => CTH[5..3].d = CTH[5..3] + 2; + WHEN B"0XX",B"10X",B"111" => CTH[5..3].d = CTH[5..3] + 1; + END CASE; + + CTH3X.clk = !CT5; + IF CTH[2..0] == 7 THEN + CTH3X.d = !CTH3X; + ELSE + CTH3X.d = CTH3X; + END IF; + + CTV[2..0].clk = SINC_HH; + CTV[2..0].d = CTV[2..0] + 1; + + CTV[8..3].clk = !CTV2; + +IF !(VIDEO == 0) THEN + + CASE MODE0[1] IS + WHEN 1 => CTV[8..3].d = GND; + WHEN 0 => CTV[8..3].d = CTV[8..3] + 1; + END CASE; + + CTF[].clk = !CTV8; + CTF[].d = CTF[] + 1; + +ELSE + + IF (CTV[8..3] == B"1XX111") THEN + CTV[8..3].d = GND; + ELSE + CTV[8..3].d = CTV[8..3] + 1; + END IF; + + CTF[].clk = !CTV8; + CTF[].d = CTF[] + 1; + +END IF; + +-- ================= VIDEO ==================== + + VXA[].clk = V_SINC; + +IF (VIDEO == 0) THEN +-- ================= VIDEO Spectrum-48k ==================== + +IF FORTH_CPU == 1 THEN + V_SINC = DFF(DFF(F_CLK,CLK42,,),CLK42,,); +ELSE + V_SINC = RAS; +END IF; + + -- Sinc + -- Blank ____ Blank + -- Scr ____/ \_________ Scr + -- ____/ \____ + -- | 4 | 4 | 8 | + +-- SINC_HH = DFF(CTH5 & !CTH4,CTH2,,); +-- SINC_H = DFF((SINC_HH & !CTH3 & !CTH4),!CTH2,,); +-- SINC_V = DFF(SINC_VV,CTV4,!CTV8,); + + SINC_HH = DFF(CTH[] == B"1001XX",CTH1,,); + SINC_H = DFF(SINC_HH,!CTH1,,); + SINC_V = (CTV[] == B"X11110XXX"); + + SINC_VV = DFF(CTV7 & CTV6,CTV5,,); + BLANK = DFF(CTH5 & !CTH4,CTH2,,!SINC_VV); + + SINC = DFF((!SINC_V xor SINC_H),CT5,,); +-- SINC = (!SINC_V xor SINC_H); + + BORD = DFF((CTV8 or (CTV7 & CTV6) or CTH5),LWR_PIC,,); + +-- BLANK = DFF(CTH5 & !CTH4,CTH2,,!DFF(CTV7 & CTV6,CTV5,,)); +% + CASE CT[2..0] IS + WHEN B"001" => VCM[2..0].d = 0; + WHEN B"010" => VCM[2..0].d = 1; + WHEN B"100" => VCM[2..0].d = 2; + WHEN B"101" => VCM[2..0].d = 4; + WHEN B"110" => VCM[2..0].d = 5; + WHEN B"000" => VCM[2..0].d = 6; + END CASE; +% + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CS[].clk = CLK42; + V_WE.clk = CLK42; + VLA[].clk = CLK42; + +IF FORTH_CPU == 1 THEN + MXWE = DFF(WE_MEM,V_SINC,,V_WE); + MXCE = GND; + +ELSE + MXWE = DFF((MXCE or /WE1),V_SINC,,V_WE); + + MXCE = (AGR6 or !A14 or (A13 & !AGR7) or (A15 & !((PN[7..6] == B"00") & (PN[2..0] == B"1X1") & !SC4))); +END IF; + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; + WHEN B"000" => VCM[2..0].d = 1; + WHEN B"001" => VCM[2..0].d = 4; + WHEN B"010" => VCM[2..0].d = 3; + WHEN B"100" => VCM[2..0].d = 2; + WHEN B"101" => VCM[2..0].d = 0; + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,BRVA[10..8],VCC,VCC); +-- VLA[].d = (VCC,VCC,VCC,VCC,VLAB[13..0]); + V_CS[].d = (VCC,GND); + TSN_W3.d = VCM2; + WHEN 1,3 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CS[].d = (VCC,GND); + WHEN 2 => +-- VLA[].d = VXA[]; + + IF FORTH_CPU == 1 THEN + VLA[] = (STDO[7..0],STDO[15..8],VCC,VCC); + ELSE + VLA[] = (AA[7..0],GND,GND,AX128,AA[12..8],VCC,VCC); + END IF; + F_CLK.d = GND; + + V_CS[].d = (VCC,GND); + V_WE.d = MXWE; + END CASE; + V_CS1.prn = GND; + V_CS0.clrn = GND; + + AX128 = LCELL(A15 & PN1); + +-- VXA[] = (B"00",A[7..0],A[10..8],AX128,A12,A11,VCC,VCC); + +IF FORTH_CPU == 1 THEN + VXA[] = (STDO[7..0],STDO[15..8],VCC,VCC); +ELSE + VXA[] = (AA[7..0],GND,GND,AX128,AA[12..8],VCC,VCC); +END IF; + +-- VLAB[] = (B"1111",BRVA[7..3],VCC,BRVA[10..9],BRVA[2..0],BRVA8,GND,GND); + VLAB[] = (B"1111111",BRVA[10..0]); + +-- SVA[] = (B"00",CTV[5..3],CTH[4..0],CTV[2..0],SC128,CTV[7..6],GND,GND); +-- SVA[] = (B"00",CTV[5..3],CTH[4..0],GND,CTV[7..6],SC128,VCC,VCC,GND,GND); + + SVA[17..10] = (CTV[5..3],CTH[4..0]); + SVA[9..8] = GND; + SVA[7] = SC128; + CASE VCM2 IS + WHEN B"0" => % ZX-atr adress % (SVA[6..2]) = (VCC,VCC,GND,CTV[7..6]); + WHEN B"1" => % ZX-pic adress % (SVA[6..2]) = (CTV[7..6],CTV[2..0]); + END CASE; + + SVA[1..0] = VCC; + + SC128 = SCR128; + + VA[] = VLA[17..2]; + + WR_PIC.clk = CLK42; WR_COL.clk = CLK42; WR_MODE.clk = CLK42; + + LWR_PIC = LCELL(WR_PIC); + LWR_COL = LCELL(WR_COL); +-- LWR_PIC = DFF(WR_PIC,!CLK42,,); +-- LWR_COL = DFF(WR_COL,!CLK42,,); + + D_PIC0[].clk = (LWR_PIC); + +-- IF LD_PIC THEN D_PIC0[].d = D_PIC0_[]; ELSE D_PIC0[].d = (D_PIC0[6..0],D_PIC0_[0]); END IF; + IF LD_PIC THEN D_PIC0[].d = VD0[]; ELSE D_PIC0[].d = (D_PIC0[6..0],VD0[0]); END IF; + + DPIC.clk = CLK42; + DPIC.d = D_PIC0[7]; + + LD_PIC = LCELL(CT[5..3] == B"000"); + +-- DCOL[].d = VD0[]; + + DCOL[].clk = (LWR_COL); + IF BORD THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); +-- DCOL[].d = (B"00",AY_OUT[3..1],AY_OUT[3..1]); +-- DCOL[].d = (B"00",(AY_CX & B"111111")); + ELSE + DCOL[].d = VD0[]; + END IF; + DCOL[].clrn = !BLANK; + + BRVA[7..0] = DCOL[]; + BRVA[10..8] = (VCC,CTF4,DPIC); + +-- CASE BLANK IS +-- WHEN B"0" => +-- BRVA[10..8] = (VCC,CTF4,DPIC); +-- WHEN B"1" => +-- BRVA[10..8] = (VCC,GND,GND); +-- END CASE; + +-- CASE (BLANK,BORD) IS +-- WHEN B"00" => +-- BRVA[7..0] = DCOL[]; +-- WHEN B"01" => +-- BRVA[7..0] = (B"00",BRD[2..0],BRD[2..0]); +-- WHEN B"1X" => +-- BRVA[7..0] = GND; +-- END CASE; + + V_WE.prn = DFF(V_WE,!CLK42,,); + +-- V_WE.prn = LCELL(V_WE or CLK42); + +-- V_WR[] = (V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); +IF FORTH_CPU == 1 THEN + V_WR[] = (V_WE) OR !LCELL(/RESET); +ELSE + V_WR[] = LCELL(V_WE) or B"1110"; +END IF; +-- +ELSE +IF VIDEO == 1 THEN + +-- ================= VIDEO Sprinter-97 ==================== + +IF (SCREEN == 1) THEN + V_SINC = !PG_SCR1 or /WAITT or /MR or !/M1; +ELSE + V_SINC = RAS; +END IF; + + SINC_H = DFF(CTH[] == B"1011XX",CTH0,,); + SINC_HH = SINC_H; +-- SINC_V = DFF(CTV[] == B"1XX010XXX",!CTH5,,); + SINC_V = LCELL(CTV[] == B"1XX010XXX"); + SINC = !SINC_V xor SINC_H; +-- BORD = DFF((MODE0[4] & MODE0[3]),TSN_W3,,); +-- BLANK = DFF((MODE0[4] & MODE0[3] & MODE0[2]),TSN_W3,,); + +-- BORD = DFF((MODE0[4] & MODE0[3]),WR_PIC,,); + BORD = DFF((MODE0[7..4] == 15),WR_PIC,,); + + BLANK = DFF((BORD & MODE03 & MODE02),WR_PIC,,); + INTT_T = DFF(!(BLANK & (CTV[2..0] == 7)),CT5,,MODE0[0]); + + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CS[].clk = CLK42; + V_WE.clk = CLK42; + VLA[].clk = CLK42; + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; + WHEN B"000" => VCM[2..0].d = 1; + WHEN B"001" => VCM[2..0].d = 4; + WHEN B"010" => VCM[2..0].d = 3; + WHEN B"100" => VCM[2..0].d = 2; + WHEN B"101" => VCM[2..0].d = 0; + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (BRVA[7..0],VCC,VCC,VCC,VCC,VCC,BRVA[10..8],VCC,VCC); + V_CS[].d = (VCC,GND); + -- TSN_W3.d = ((X_MODE5 or VCM2) & (X_MODE_BOND or !VCM2)); + IF VCM2 THEN + TSN_W3.d = X_MODE5; + ELSE + TSN_W3.d = X_MODE_BOND; + END IF; + WR_MODE2.d = !MODE0[4] or VCM2; + WHEN 1 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CS[].d = (VCC,GND); + WHEN 2 => + VLA[].d = VXA[]; + V_CS[].d = (VCC,GND); + V_WE.d = MXWE; + WHEN 3 => + WR_PIC.d = X_MODE5; + VLA[].d = (VLAM[]); + WR_MODE.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); + WR_MODE2.d = !(CT[5..3] == B"111") & !(CT4 & CT3 & !MODE0[5]); + V_CS[].d = (VCC,GND); + END CASE; + V_CS1.prn = GND; + V_CS0.clrn = GND; + +IF NEWS == 1 THEN + +-- VXA[] = RA[17..0]; + +IF NO_SPEC_SCR == 1 THEN + +-- VXA[] = RA[17..0]; + + MXCE = !PG_SCR1; + VXA[] = (AA[9..0],GR_Y[]); + +ELSE + + VXA[] = RA[17..0]; + + IF PG_SCR THEN + MXCE = GND; + ELSE + MXCE = LCELL(AGR6 or !AAA14 or (AA13 & !AGR7) or (AAA15 & !((PN[2..0] == B"1X1") & !SC4))); + END IF; + +END IF; + +ELSE + +IF NO_SPEC_SCR == 1 THEN + VXA[] = (GR_Y[],RA[9..0]); + MXCE = !PG_SCR1; +ELSE + IF (PG_SCR1) THEN + VXA[] = (RA[17..0]); + MXCE = GND; + ELSE + VXA[] = (RA[7..0],AGR[4..1],LCELL(MPGS1 xor AGR0 xor RA13),RA[12..8]); + MXCE = LCELL(AGR6 or !AAA14 or (AA13 & !AGR7) or (AAA15 & !((PN[2..0] == B"1X1") & !SC4))); + END IF; +END IF; +END IF; + + +IF (SCREEN == 1) THEN + MXWE = DFF(!PG_SCR1,V_SINC,,V_WE); +ELSE + MXWE = DFF((MXCE or /WE1),V_SINC,,V_WE); +END IF; + +-- SVA[14..10] = MODE1[4..0]; +-- SVA[9..6] = MODE0[3..0]; + SVA[9..6] = MODE0[3..0]; + SVA[17..13] = MODE1[7..3]; + + CASE (VCM2,MODE0[4]) IS + WHEN B"X0" => + -- Graf adress -- + SVA[12..10] = CTV[2..0]; + SVA[5..0] = (MODE1[2..0],CT5,!CT[4..3]); + WHEN B"01" => + -- ZX-atr adress -- + SVA[12..10] = MODE1[2..0]; + SVA[5..0] = (SCR128,VCC,VCC,GND,!MODE0[7..6]); + WHEN B"11" => + -- ZX-pic adress -- + SVA[12..10] = MODE1[2..0]; + SVA[5..0] = (SCR128,MODE0[7..6],CTV2,!CTV1,!CTV0); + END CASE; + + VLAM[] = (RGMOD0,CTH[5..0],CT5,VCC,VCC,CTV[8..3],GND,GND); + + VLAB[] = (B"1111111",BRVA[10..0]); + + IF !(ACCELERAT == 0) THEN + X_MODE_BOND = GND; + ELSE + X_MODE_BOND = DFF(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & + DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,,)); + END IF; + + LD_PIC = LCELL((MODE0[5] & (CT[5..3] == B"000")) or (!MODE0[5] & (CT[4..2] == B"000"))); +% +END IF; +% + CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS + WHEN 0 => D_PIC0_[] = VD0[]; + WHEN 1 => D_PIC0_[] = VD1[]; + WHEN 2 => D_PIC0_[] = VD2[]; + WHEN 3 => D_PIC0_[] = VD3[]; + END CASE; + + MODE0[].clk = LWR_MODE; + MODE1[].clk = LWR_MODE; + MODE2[].clk = LWR_MODE; + + MODE0[].d = VD3[]; +-- MODE1[].d = VD2[]; + + WR_MODE2X.d = LWR_MODE; + WR_MODE2X.clk = WR_MODE2; + + MODE2[].ena = DFF(VCM1,CLK42,,); + MODE2[].d = VD1[]; + + IF DFF(VCM1,CLK42,,) THEN + MODE1[].d = VD2[]; + ELSE + MODE1[].d = MODE2[]; + END IF; + + X_MODE7 = DFF(MODE0[7],LWR_COL,,); + X_MODE6 = DFF(MODE0[6],LWR_COL,,); + X_MODE5 = DFF(MODE0[5],LWR_COL,,); + X_MODE4 = DFF(MODE0[4],LWR_COL,,); + + VA[] = VLA[17..2]; + + WR_PIC.clk = CLK42; + WR_COL.clk = CLK42; + WR_MODE.clk = CLK42; + WR_MODE2.clk = CLK42; + +-- LWR_MODE = (DFF(WR_MODE,!CLK42,,)); +-- LWR_MODE = LCELL(LCELL(WR_MODE)); + + LWR_MODE2 = LCELL(WR_MODE2); + LWR_MODE = LCELL(WR_MODE); + + LWR_PIC = DFF(WR_PIC,!CLK42,,); + LWR_COL = DFF(WR_COL,!CLK42,,); + + D_PIC0[].clk = (LWR_PIC); + + IF LD_PIC THEN + D_PIC0[].d = D_PIC0_[]; + ELSE + D_PIC0[].d = (D_PIC0[6..0],D_PIC0_[0]); + END IF; + + DPIC.clk = !CLK42; + DPIC.d = D_PIC0[7]; + + DCOL[].clk = (LWR_COL); + + IF LCELL(MODE0[7..4] == 15) THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); + ELSE + DCOL[].d = D_PIC0_[]; + END IF; + + DCOL[].clrn = !BLANK; + +IF MODE640 THEN + CASE (LCELL(X_MODE4 or X_MODE5),CT2) IS + WHEN B"1X" => BRVA[7..0] = DCOL[]; + WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]); + WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]); + END CASE; +ELSE + BRVA[7..0] = DCOL[]; +END IF; + + BRVA[10..8] = (x_mode4,RBRVA[9..8]); + + RBRVA[].clk = CLK42; + + CASE (BORD,X_MODE4) IS + WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + WHEN B"X1" => RBRVA[10..8].d = (VCC,(CTF4 & !BLANK),D_PIC0[7]); + END CASE; +% + CASE (CURS_MCX,X_MODE4) IS + WHEN B"00" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + WHEN B"01" => RBRVA[10..8].d = (VCC,CTF4,D_PIC0[7]); + WHEN B"1X" => RBRVA[10..8].d = (VCC,CURS_PIX[]); + END CASE; +% + RBRVA[9..8].clrn = !BORD; + RBRVA[10].prn = !BORD; + + V_WE.prn = DFF(V_WE,!CLK42,,); + + V_WR[] = (V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + +ELSE + +-- ================= VIDEO-2 Sprinter-98 ! ==================== + V_SINC = DFF((/MR or ((!PG_SCR1 or /RD) & /WR)),CLK42,,); + + SINC_H = DFF(CTH[] == B"1011XX",CTH0,,); + SINC_HH = SINC_H; +-- SINC_V = DFF(CTV[] == B"1XX010XXX",!CTH5,,); + SINC_V = LCELL(CTV[] == B"1XX010XXX"); + SINC = !SINC_V xor SINC_H; +-- BORD = DFF((MODE0[4] & MODE0[3]),TSN_W3,,); +-- BLANK = DFF((MODE0[4] & MODE0[3] & MODE0[2]),TSN_W3,,); + +-- BORD = DFF((MODE0[4] & MODE0[3]),WR_PIC,,); + + BORD = DFF((MODE0[7..4] == 15),WR_PIC,,); + + BLANK = DFF((BORD & MODE0[2]),WR_PIC,,); + INTT_T = DFF(!(BLANK & (CTV[2..0] == 7)),CT5,,MODE0[0]); + + VCM[].clk = CLK42; + TSN_W3.clk = CLK42; + V_CS[].clk = CLK42; + V_WE.clk = CLK42; + VLA[].clk = CLK42; + + CASE CT[2..0] IS + WHEN B"110" => VCM[2..0].d = 5; + WHEN B"000" => VCM[2..0].d = 1; + WHEN B"001" => VCM[2..0].d = 4; + -- WHEN B"010" => VCM[2..0].d = 2; + -- WHEN B"100" => VCM[2..0].d = 3; + WHEN B"010" => VCM[2..0].d = 3; + WHEN B"100" => VCM[2..0].d = 2; + WHEN B"101" => VCM[2..0].d = 0; + END CASE; + + CASE VCM[1..0] IS + WHEN 0 => + VLA[].d = (VCC,VCC,VCC,VCC,VLAB[13..0]); + V_CS[].d = (VCC,GND); + -- TSN_W3.d = ((X_MODE5 or VCM2) & (X_MODE_BOND or !VCM2)); + IF VCM2 THEN + TSN_W3.d = X_MODE5; + ELSE + TSN_W3.d = X_MODE_BOND; + END IF; + WHEN 1 => + WR_PIC.d = !VCM2; + WR_COL.d = VCM2; + VLA[].d = SVA[]; + V_CS[].d = (VCC,GND); + WHEN 2 => + VLA[].d = VXA[]; + V_CS[].d = (VCC,GND); + V_WE.d = MXWE; + WHEN 3 => + WR_PIC.d = X_MODE5; + VLA[].d = (VCC,GND,VCC,VCC,VLAM[13..0]); + WR_MODE.d = !(CT[5..3] == B"111"); + V_CS[].d = (VCC,GND); + END CASE; + V_CS1.prn = GND; + V_CS0.clrn = GND; + + IF (PG_SCR or PG_SCR1) THEN +-- VXA[] = (RA[9..6],RA[17..13],RA[5..3],RA[12..10],RA[2..0]); + VXA[] = (AA[9..6],GR_Y[7..3],AA[5..3],GR_Y[2..0],AA[2..0]); + MXCE = GND; + ELSE + VXA[] = (AGR[4..1],RA[7..0],RA[10..8],lcell(MPGS1 xor AGR0 xor RA13),RA12,RA11); +-- MXCE = VCC; + MXCE = LCELL(AGR6 or !AAA14 or (AA13 & !AGR7) or (AAA15 & !((PN[2..0] == B"1X1") & !SC4))); + END IF; + +-- MXWE = DFF((MXCE or /WE1),V_SINC,,V_WE); + MXWE = DFF(MXCE,V_SINC,,V_WE); + + SVA[17..6] = (MODE0[3..0],MODE1[7..0]); + SVA2 = SC128; + + CASE (VCM2,MODE0[4]) IS + WHEN B"X0" => + -- Graf adress -- + (SVA[5..3],SVA[1..0]) = (CTV[2..0],!CT[4..3]); + WHEN B"01" => + -- ZX-atr adress -- + (SVA[5..3],SVA[1..0]) = (GND,MODE0[7..6],GND,GND); + WHEN B"11" => + -- ZX-pic adress -- + (SVA[5..3],SVA[1..0]) = (CTV[2..0],!MODE0[7..6]); + END CASE; + + CASE (MODE0[4],MODE0[5]) IS + WHEN 0 => SC128 = CT5; + WHEN 1 => SC128 = CT5; + WHEN 2 => SC128 = CT5; + WHEN 3 => SC128 = SCR128; + END CASE; + +-- SC128 = ((MODE0[5] & SCR128) or (!MODE0[5] & CT5)); + + VLAM[] = (B"1011",CTV[4..3],CTH[5..0],CTV[7..5],!RGMOD0,GND,GND); + VLAB[] = (B"1111",BRVA[7..3],VCC,BRVA[10..9],BRVA[2..0],BRVA8,GND,GND); + + IF !(ACCELERAT == 0) THEN + X_MODE_BOND = GND; + ELSE + X_MODE_BOND = DFF(LCELL(DCOL[7..4] == 15) & LCELL(DCOL[3..0] == 15) & DFF((MODE0[7] & MODE0[5] & !MODE0[4]),LWR_COL,,)); + END IF; + + LD_PIC = LCELL((MODE0[5] & (CT[5..3] == B"000")) or (!MODE0[5] & (CT[4..2] == B"000"))); +% +END IF; +% + CASE (DFF(VLA1,!CLK42,,),DFF(VLA0,!CLK42,,)) IS + WHEN 0 => D_PIC0_[] = VD0[]; + WHEN 1 => D_PIC0_[] = VD1[]; + WHEN 2 => D_PIC0_[] = VD2[]; + WHEN 3 => D_PIC0_[] = VD3[]; + END CASE; + +-- IF DFF(VLA1,!CLK42,,) THEN D_PIC0_[] = VDX_[15..8]; ELSE D_PIC0_[] = VDX_[7..0]; END IF; +-- IF DFF(VLA0,!CLK42,,) THEN VDX_[] = (VD3[],VD1[]); ELSE VDX_[] = (VD2[],VD0[]); END IF; + +-- (MODE0[].d,MODE1[].d) = VDX_[]; + +-- IF DFF(VLA0,!CLK42,,) THEN + IF !CTV8 THEN + MODE0[].d = VD3[]; + MODE1[].d = VD1[]; + ELSE + MODE0[].d = VD2[]; + MODE1[].d = VD0[]; + END IF; + + MODE0[].clk = LWR_MODE; + MODE1[].clk = LWR_MODE; + + X_MODE7 = DFF(MODE0[7],LWR_COL,,); + X_MODE6 = DFF(MODE0[6],LWR_COL,,); + X_MODE5 = DFF(MODE0[5],LWR_COL,,); + X_MODE4 = DFF(MODE0[4],LWR_COL,,); + + VA[] = VLA[17..2]; + + WR_PIC.clk = CLK42; + WR_COL.clk = CLK42; + WR_MODE.clk = CLK42; + +-- LWR_MODE = (DFF(WR_MODE,!CLK42,,)); +-- LWR_MODE = LCELL(LCELL(WR_MODE)); + LWR_MODE = LCELL(WR_MODE); + +-- LWR_PIC = LCELL(WR_PIC); + LWR_PIC = DFF(WR_PIC,!CLK42,,); + LWR_COL = DFF(WR_COL,!CLK42,,); + + D_PIC0[].clk = (LWR_PIC); + + IF LD_PIC THEN + D_PIC0[].d = D_PIC0_[]; + ELSE + D_PIC0[].d = (D_PIC0[6..0],D_PIC0_[0]); + END IF; + + DPIC.clk = !CLK42; + DPIC.d = D_PIC0[7]; + + DCOL[].clk = (LWR_COL); + + IF LCELL(MODE0[4] & MODE0[3]) THEN + DCOL[].d = (B"00",BRD[2..0],BRD[2..0]); + ELSE + DCOL[].d = D_PIC0_[]; + END IF; + + DCOL[].clrn = !BLANK; + +-- BRVA[7..0] = DCOL[]; + +IF MODE640 THEN + CASE (LCELL(MODE0[4] or MODE0[5]),CT2) IS + WHEN B"1X" => BRVA[7..0] = DCOL[]; + WHEN B"01" => BRVA[7..0] = (B"0000",DCOL[7..4]); + WHEN B"00" => BRVA[7..0] = (B"0000",DCOL[3..0]); + END CASE; +ELSE + BRVA[7..0] = DCOL[]; +END IF; + + + BRVA[10..8] = (x_mode[4],RBRVA[9..8]); + + RBRVA[].clk = CLK42; + + CASE (BORD,X_MODE[4]) IS + WHEN B"X0" => RBRVA[10..8].d = (GND,X_MODE[7..6]); + -- WHEN B"01" => RBRVA[10..8].d = (VCC,CTF4,DPIC); + WHEN B"X1" => RBRVA[10..8].d = (VCC,CTF4,D_PIC0[7]); + -- WHEN B"1X" => RBRVA[10..8].d = (VCC,GND,GND); + END CASE; + RBRVA[9..8].clrn = !BORD; + RBRVA[10].prn = !BORD; + + V_WE.prn = DFF(V_WE,!CLK42,,); + + V_WR[] = (V_WE) or !((!VXA1 & !VXA0),(!VXA1 & VXA0),(VXA1 & !VXA0),(VXA1 & VXA0)); + +END IF; +END IF; + +-- =========== KEYBOARD ======================= + + + +CASE KEYBOARD IS +WHEN 0 => + KB_RESET.prn = GND; + KB_F12 = GND; + IF (COVOX_MODE == B"10") THEN + KD[] = (COV_AR7,VCC,CTV8,B"11111"); + ELSE + KD[] = VCC; + END IF; + +WHEN 1 => + + + KB_CT[].clk = CTV0; + KB_CT[].prn = KBD_CC; + KB_CT[].clrn = !KBDR0; + + CASE KB_CT[] IS + WHEN 0 => KB_CT[].d = GND; + WHEN 1,2,3,4,5,6,7 => KB_CT[].d = KB_CT[] - 1; + END CASE; + + KB_D[].clk = KBD_CC; + KB_D[].d = (KBD_DD,KB_D[10..1]); + + KB_OFF.clk = (KB_CT[] == 0); + + IF KB_EXT THEN + KB_OFF.d = KB_OFF; + ELSE + KB_OFF.d = KB_D[] == B"XX11110000X"; + END IF; + + KB_EXT.clk = (KB_CT[] == 1); + KB_EXT.d = KB_D[] == B"XX11100000X"; + + KB_CTRL.clk = (KB_CT[] == 3); + KB_ALT.clk = (KB_CT[] == 3); + KB_SH.clk = (KB_CT[] == 3); + + KB_CTRL_X = LCELL(KB_D[] == B"XXXXX1X100X"); + KB_ALT_X = LCELL(KB_D[] == B"XXXXX1X001X"); +-- KB_SH_X = LCELL(KB_D[] == B"XX00010010X") or (KB_D[] == B"XX01011001X"); + + KB_SH_X = LCELL(KB_D[] == B"XX0X01X0XXX") & + CASCADE((KB_D[] == B"XXX1XX1X01X") or (KB_D[] == B"XXX0XX0X10X")); + KB_XXX = LCELL(KB_D[] == B"XX000X0XXXX"); + + CASE KB_OFF IS + WHEN 0 => + KB_CTRL.d = (KB_CTRL_X & KB_XXX) or KB_CTRL; + KB_ALT.d = (KB_ALT_X & KB_XXX) or KB_ALT; + KB_SH.d = (KB_SH_X) or KB_SH; + WHEN 1 => + KB_CTRL.d = !(KB_CTRL_X & KB_XXX) & KB_CTRL; + KB_ALT.d = !(KB_ALT_X & KB_XXX) & KB_ALT; + KB_SH.d = !(KB_SH_X) & KB_SH; + END CASE; + + KB_F12 = DFF(!((KB_XXX & (KB_D[] == B"XXXXX0X111X")) & !KB_OFF),(KB_CT[] == 3),,!(KB_CT[] == 1)); + + KB_RESET.clk = (KB_CT[] == 3); + KB_RESET.d = !(KB_ALT_X & (KB_D[] == B"XX011X0XXXX") & !KB_OFF & KB_CTRL & KB_ALT); + KB_RESET.prn = !(KB_CT[] == 1); + + KB_MAGIC.clk = KB_F12; + KB_MAGIC.d = !KB_CTRL; + KB_MAGIC.prn = PORT_NMI; +-- KB_MAGIC.prn = DOS; + + KD[] = VCC; +% + (KD[],KB_RESET,KB_F12,KB_CTRL,KB_EXT,KB_SH) = + kbd (/RESET,CLK42,CTH5,KB_CC,KB_DD,/RF,/IO,A[15..8]); +% +WHEN 2 => + + KB_CT[].clk = CTH5; + KB_CT[].prn = KBD_CC; + KB_CT[].clrn = !KBDR0; + + CASE KB_CT[] IS + WHEN 0 => KB_CT[].d = GND; + WHEN 1,2,3,4,5,6,7 => KB_CT[].d = KB_CT[] - 1; + END CASE; + + KB_D[].clk = KBD_CC; + KB_D[].d = (KBD_DD,KB_D[10..1]); + + KB_OFF.clk = (KB_CT[] == 0); + + CASE KB_EXT IS + WHEN 1 => KB_OFF.d = KB_OFF; + WHEN 0 => KB_OFF.d = KB_D[] == B"XX11110000X"; + END CASE; + + KB_EXT.clk = (KB_CT[] == 1); + KB_EXT.d = KB_D[] == B"XX11100000X"; + +-- KB_CTRL.clk = (KB_CT[] == 3); +-- KB_ALT.clk = (KB_CT[] == 3); +-- KB_SH.clk = (KB_CT[] == 3); + KB_CTRL.clk = !KB_CT2; + KB_ALT.clk = !KB_CT2; + KB_SH.clk = !KB_CT2; + + KB_CTRL_X = LCELL(KB_D[] == B"XXXXX1X100X"); + KB_ALT_X = LCELL(KB_D[] == B"XXXXX1X001X"); +-- KB_SH_X = LCELL(KB_D[] == B"XX00010010X") or (KB_D[] == B"XX01011001X"); + + KB_SH_X = LCELL(KB_D[] == B"XX0X01X0XXX") & + CASCADE((KB_D[] == B"XXX1XX1X01X") or (KB_D[] == B"XXX0XX0X10X")); + KB_XXX = LCELL(KB_D[] == B"XX000X0XXXX"); + + CASE KB_OFF IS + WHEN 0 => + KB_CTRL.d = (KB_CTRL_X & KB_XXX) or KB_CTRL; + KB_ALT.d = (KB_ALT_X & KB_XXX) or KB_ALT; + KB_SH.d = (KB_SH_X) or KB_SH; + WHEN 1 => + KB_CTRL.d = !(KB_CTRL_X & KB_XXX) & KB_CTRL; + KB_ALT.d = !(KB_ALT_X & KB_XXX) & KB_ALT; + KB_SH.d = !(KB_SH_X) & KB_SH; + END CASE; + +-- KB_F12 = DFF(!((KB_XXX & (KB_D[] == B"XXXXX0X111X")) & !KB_OFF),(KB_CT[] == 3),,!(KB_CT[] == 1)); + KB_F12 = DFF(!((KB_XXX & LCELL(KB_D[] == B"XXXXX0X111X")) & !KB_OFF),!KB_CT2,,!(KB_CT[] == 1)); + +-- KB_RESET.clk = (KB_CT[] == 3); + KB_RESET.clk = !KB_CT2; + KB_RESET.d = !(KB_ALT_X & (KB_D[] == B"XX011X0XXXX") & !KB_OFF & KB_CTRL & KB_ALT); + KB_RESET.prn = !(KB_CT[] == 1); + + KB_MAGIC.clk = KB_F12; + KB_MAGIC.d = !KB_CTRL; + KB_MAGIC.prn = DOS; + + K_CLK = DFF(/RF,CLK42,,); + + RXA[].clk = K_CLK; + +-- CASE (LCELL(KB_CT[] == B"01X"),RXA[]) IS +-- WHEN B"000" => RXA[] = B"00"; +-- WHEN B"001" => RXA[] = (RXA0,!RXA1); +-- WHEN B"01X" => RXA[] = (RXA0,!RXA1); +-- WHEN B"1XX" => RXA[] = (RXA0,!RXA1); +-- END CASE; + + CASE LCELL(!(KB_CT[] == B"01X") & (RXA[] == 0)) IS + WHEN B"1" => RXA[] = GND; + WHEN B"0" => RXA[] = (RXA0,!RXA1); + END CASE; + +% + IF !(KB_CT[] == 2) & (RXA[] == 0) THEN + RXA[].d = GND; + ELSE + RXA[].d = (RXA0,!RXA1); + END IF; +% + CASE (LCELL(/IO & (RXA[] == 0)),LCELL(KDD7 & KDD6)) IS + WHEN B"0X" => KA[15..8] = (B"101",KDCA[],B"11"); + WHEN B"10" => KA[15..8] = (B"110000",KDD7,KDD6); + WHEN B"11" => KA[15..8] = KB_D[8..1]; + END CASE; + + KB_MA[].clk = CLK42; + KB_MA[].d = KB_MA[] + 1; + KB_MA[].clrn = !/IO; + + KB_MXA = DFF(( (((KB_MA[] == 7) & A15) or ((KB_MA[] == 6) & A14)) + or (((KB_MA[] == 5) & A13) or ((KB_MA[] == 4) & A12)) + or (((KB_MA[] == 3) & A11) or ((KB_MA[] == 2) & A10)) + or (((KB_MA[] == 1) & A9 ) or ((KB_MA[] == 0) & A8 ))),CLK42,,); + + IF !/IO THEN + IF ISD_KBD == 1 THEN + KDCA[] = KB_MA[]; + ELSE + KDCA0 = !LCELL(A15 & A13 & A11 & A9); + KDCA1 = !LCELL(A15 & A14 & A11 & A10); + KDCA2 = !LCELL(A15 & A14 & A13 & A12); + END IF; + ELSE + KDCA[] = KDD[5..3]; + END IF; + + KDD[].clk = RXA0; + KDD[].d = KD[]; + KDD[7..6].prn = !KB_CT2; + + KDXX[].clk = RXA0; + KDXX[].d = !((KD[2..0] == 5),(KD[2..0] == 4), + (KD[2..0] == 3),(KD[2..0] == 2), + (KD[2..0] == 1),(KD[2..0] == 0)); + + KDX[].clk = RXA1; + + CASE KB_OFF IS + WHEN B"0" => KDX[].d = (KD[5..0] & KDXX[]); + WHEN B"1" => KDX[].d = (KD[5..0] or !KDXX[]); + END CASE; + +-- ============================== + + WR_KBD = K_CLK or !LCELL(KB_CT[] == 2) or !(RXA[] == 3); +-- WR_KBD = K_CLK or !(RXA[] == 3) or LCELL(!(KDD[7..6] == 3) & (KB_CT0 xor KB_OFF)); + + KD[] = lpm_ram_dq((B"11",KDX[5..0]),KA[15..8],!WR_KBD,CLK42,) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="KBD_INI2.MIF", + lpm_outdata="UNREGISTERED"); + + KBD[].clk = CLK42; +-- KBD[].prn = DFF(!/IOM,CLK42,,); + KBD[].prn = DFF(VCC,KB_MA2,,!/IO); + KBD[].d = KBD[] & (KD[5..0] or KB_MXA); + +WHEN 3 => + + K_CLK = DFF(/RF,CLK42,,); + +-- KB_CT[].clk = CTV0; + KB_CT[].clk = !CTH5; + KB_CT[].prn = KBD_CC; + KB_CT[].clrn = !KBDR0; + + IF (KB_CT[] == 0) THEN + KB_CT[].d = GND; + ELSE + KB_CT[].d = KB_CT[] - 1; + END IF; + + KB_D[].clk = KBD_CC; + KB_D[].d = (KBD_DD,KB_D[10..1]); + + KB_OFF.clk = (KB_CT[] == 0); + IF KB_EXT THEN + KB_OFF.d = KB_OFF; + ELSE + KB_OFF.d = KB_D[] == B"XX11110000X"; + END IF; + + KB_EXT.clk = (KB_CT[] == 1); + KB_EXT.d = KB_D[] == B"XX11100000X"; + + KB_CTRL.clk = (KB_CT[] == 3); + KB_ALT.clk = (KB_CT[] == 3); + KB_SH.clk = (KB_CT[] == 3); + + KB_CTRL_X = (KB_D[] == B"XXXXX1X100X"); + KB_ALT_X = (KB_D[] == B"XXXXX1X001X"); + KB_SH_X = (KB_D[] == B"XX00010010X") or (KB_D[] == B"XX01011001X"); + KB_XXX = (KB_D[] == B"XX000X0XXXX"); + + CASE KB_OFF IS + WHEN 0 => + KB_CTRL.d = (KB_CTRL_X & KB_XXX) or KB_CTRL; + KB_ALT.d = (KB_ALT_X & KB_XXX) or KB_ALT; + KB_SH.d = (KB_SH_X) or KB_SH; + WHEN 1 => + KB_CTRL.d = !(KB_CTRL_X & KB_XXX) & KB_CTRL; + KB_ALT.d = !(KB_ALT_X & KB_XXX) & KB_ALT; + KB_SH.d = !(KB_SH_X) & KB_SH; + END CASE; + + KB_F12 = DFF(!((KB_XXX & (KB_D[] == B"XXXXX0X111X")) & !KB_OFF),(KB_CT[] == 3),,!(KB_CT[] == 1)); + + KB_RESET.clk = (KB_CT[] == 3); + KB_RESET.d = !(KB_ALT_X & (KB_D[] == B"XX011X0XXXX") & !KB_OFF & KB_CTRL & KB_ALT); +-- KB_RESET.prn = !(KB_CT[] == 1); + KB_RESET.prn = GND; + + KB_MAGIC.clk = KB_F12; + KB_MAGIC.d = !KB_CTRL; + KB_MAGIC.prn = DOS; + +-- KDD[].clk = DFF((KB_CT[] == 2),K_CLK,,); + +-- KDD[].clk = (KB_CT[] == 2); + (KDX[].clk,KDD[].clk) = DFF((KB_CT[] == 1),K_CLK,,); + KDD[].d = KB_D[8..1]; + KDX[].d = (VCC,!KB_EXT,!KB_OFF,!KB_ALT,!KB_CTRL,!KB_SH); + + IF (COVOX_MODE != B"10") THEN + KD[] = KDD[]; + ELSE + KD[] = (COV_AR7,VCC,CTV8,B"11",!KB_ALT,!KB_CTRL,!KB_SH); +-- KD[] = (COV_AR7,B"1111111"); + END IF; + + KDD[].prn = DFF(GND,(/IORD or !(DCP[7..4] == B"010X")),/RESET,/MR); + +END CASE; + +% + + *...... *...... *****.. ***.*** + ***.... ***.... ****... ...*... + *****.. *..**.. ****... ...*... + ******* *....** *****.. ...*... + *****.. *...*.. *..***. ...*... + *****.. ***.*.. ....*** ...*... + *..***. *..*.*. .....*. ...*... + ....**. ....**. ....... ***.*** + +% + +% +IF HARD_CURSOR THEN + + CURS_SINC = DFF((VCM[1..0] != 1),!CLK42,,); + CURS_MD[].clk = CURS_SINC; + + IF !LD_PIC & SINC_H THEN + CURS_MD[].d = (CURS_MD[7..0],D_PIC0_[7..0]); + ELSE + CURS_MD[15..8] = (CURS_MD[14..8],CURS_MD[15]); + CURS_MD[7..0] = (CURS_MD[6..0],CURS_MD[7]); + END IF; + + CURS_MC.clk = CURS_SINC; + IF CURS_MD[15] & CURS_MD[7] THEN + CURS_MC = MODE3[0] & !CURS_MC; + ELSE + CURS_MC = CURS_MC; + END IF; + + CURS_PIX[] = (CURS_MD[15],CURS_MD[7]); + CURS_MCX = CURS_MC & (CURS_MD[15] or CURS_MD[7]); + +END IF; +% + +-- ======================================= +IF SOUND_CARD THEN +-- ============ SOUND CARD =============== +-- SND_WR.clk = CLK42; + SND_RR[].clk = !CT1; + SND_C.clk = !CT1; + CASE CT[5..2] IS + WHEN B"0X00" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,GND,CTH3X,CTH[2..0],CT[5..4]); + SND_RR[].d = SND_D[]; + SND_C.d = SND_C; + WHEN B"0X01" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,VCC,CTH3X,CTH[2..0],CT[5..4]); + (SND_C.d,SND_RR[].d) = (GND,SND_D[]) + (GND,SND_RR[]) + (B"00000000",SND_C); + WHEN B"XX10" => + SND_I[] = D[]; + SND_A[] = A[7..0]; + SND_WR = !(/MR or /WR or A15 or A14 or !CT1); + SND_RR[].d = SND_RR[]; + SND_C.d = SND_C; + WHEN B"0X11" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,VCC,CTH3X,CTH[2..0],CT[5..4]); + SND_RR[].d = SND_RR[]; + SND_WR = CT1; + SND_C.d = SND_C; + WHEN B"1000" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,GND,CTH3X,CTH[2..0],CT[5..4]); + SND_RR[].d = SND_D[]; + SND_C.d = SND_C; + WHEN B"1001" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,VCC,CTH3X,CTH[2..0],CT[5..4]); + (SND_C.d,SND_RR[].d) = (GND,SND_D[]) + (GND,SND_RR[]) + (B"00000000",SND_C); + WHEN B"1011" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,VCC,CTH3X,CTH[2..0],CT[5..4]); + SND_RR[].d = SND_RR[]; + SND_WR = CT1; + SND_C.d = GND; + + WHEN B"1100" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,GND,CTH3X,CTH[2..0],CT[5..4]); +-- SND_RR[].d = (SND_RR[7..4],SND_D[3..0]); + SND_RR[].d = SND_RR[]; + SND_C.d = SND_C; + WHEN B"1101" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,GND,CTH3X,CTH[2..0],CT[5..4]); +-- SND_A[] = (VCC,SND_RR[2..0],SND_RR[7..4]); + SND_RR[].d = SND_RR[]; + SND_C.d = SND_C; + WHEN B"1111" => + SND_I[] = SND_RR[]; + SND_A[] = (GND,VCC,CTH3X,CTH[2..0],CT[5..4]); +-- SND_A[] = (VCC,SND_RR[2..0],SND_RR[7..4]); + SND_RR[].d = SND_RR[]; + SND_C.d = GND; + WR_AA.d = GND; + END CASE; + + WE_SND.clk = CLK42; + WE_SND.prn = WE_SND or CLK42; + + WR_AMP.clk = CLK42; + WR_AA.clk = CLK42; + + SND_AA[7..4].clk = LCELL(WR_AA & SND_SHR); + SND_AA[3..0].clk = LCELL(WR_AA & SND_SHL); + + IF !DFF(WR_AA,!CLK42,,) THEN + SND_AA[].d = SND_D[]; + ELSE + SND_AA[7..4].d = (SND_AA[7..4] + 1); + SND_AA[3..0].d = (SND_AA[3..0] + 1); + END IF; + + SND_SHL = LCELL(SND_AA3 or !(CT5 xor CT4) or CLK42); + SND_SHR = LCELL(SND_AA7 or !(CT5 xor CT4) or CLK42); + + SND_AMP[].clk = LCELL(WR_AMP & SND_SHR); + + IF !DFF(WR_AMP,!CLK42,,) THEN + SND_AMP[].d = (VD3[],GND,GND) - 512; + ELSE + SND_AMP[].d = (SND_AMP9,SND_AMP[9..1]) + (SND_AMP9,SND_AMP9,SND_AMP[9..2]); + END IF; + + SND_A_LD = LCELL(CT[5..3] == B"110"); + + SND_OUTX.clk = (CLK42 xor SND_OUTX); + SND_OUTX.d = !SND_OUTX; +-- SND_OUT[].clk = (CLK42 xor SND_OUTX); +-- SND_OUTL[].clk = (CLK42 xor SND_OUTX); + SND_OUT[].clk = (CLK42); + SND_OUTL[].clk = (CLK42); + + IF !(WR_AMP) THEN + SND_OUT[].d = (VCC,GND,GND,!SND_AMP9,SND_AMP[8..5]); +-- SND_OUT[].d = (VCC,GND,GND,GND,GND,SND_AMP[7..5]); + ELSE + SND_OUT[].d = SND_OUT[] - 1; + END IF; + + IF !(WR_AMP) THEN + SND_OUTL[].d = (VCC,GND,GND,SND_AMP[4..0]); +-- SND_OUTL[].d = (VCC,GND,GND,SND_AMP[4..0]); + ELSE + SND_OUTL[].d = SND_OUTL[] - 1; + END IF; + + SND_L0 = SND_OUT7; + SND_L1 = SND_OUTL7; + SND_R0 = SND_OUT7; + SND_R1 = SND_OUTL7; + + SND_TEST.clk = CLK42; + SND_TEST.d = SND_OUT4; + SND_TEST.clrn = GND; + + SND_D[] = lpm_ram_dq(SND_I[],SND_A[],SND_WR,CLK42,) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="SND_INI.MIF",lpm_outdata="UNREGISTERED"); +ELSE + +IF (AY_3_8910 != 0) THEN +IF (AY_3_8910 == 1) THEN + + AY_CLK1 = LCELL(CTH1); +-- AY_ADR[].clk = (/IOWR or !(DCP[] == H"90")); +-- AY_AAX[].clk = (/IOWR or !(DCP[] == H"90")); +-- AY_D_WR = (/IOWR or !(DCP[] == H"91")); + + (AY_ADR[].clk,AY_AAX[].clk) = DFF(!(DCP[] == H"90"),!/IOWR,,!/IO); + + AY_ADR[].d = D[]; + AY_AAX[].d = ((D2 & D3),(!D2 & D3),(D2 & !D3),(!D2 & !D3),(D0 & D1),(!D0 & D1),(D0 & !D1),(!D0 & !D1)); + + AY_D_WR = DFF(!(DCP[] == H"91"),!/IOWR,,!/IO); + + AY_F1[7..0].clk = AY_D_WR; + AY_F1[11..8].clk = AY_D_WR; + AY_F2[7..0].clk = AY_D_WR; + AY_F2[11..8].clk = AY_D_WR; + AY_F3[7..0].clk = AY_D_WR; + AY_F3[11..8].clk = AY_D_WR; + AY_S1[4..0].clk = AY_D_WR; + AY_X_[5..0].clk = AY_D_WR; + AY_A1[4..0].clk = AY_D_WR; + AY_A2[4..0].clk = AY_D_WR; + AY_A3[4..0].clk = AY_D_WR; + AY_GO[7..0].clk = AY_D_WR; + AY_GO[15..8].clk = AY_D_WR; + AY_GF[3..0].clk = AY_D_WR; + + IF (AY_AAX0 & AY_AAX4) THEN AY_F1[7..0].d = D[]; ELSE AY_F1[7..0].d = AY_F1[7..0] ; END IF; + IF (AY_AAX1 & AY_AAX4) THEN AY_F1[11..8].d = D[3..0]; ELSE AY_F1[11..8].d = AY_F1[11..8] ; END IF; + IF (AY_AAX2 & AY_AAX4) THEN AY_F2[7..0].d = D[]; ELSE AY_F2[7..0].d = AY_F2[7..0] ; END IF; + IF (AY_AAX3 & AY_AAX4) THEN AY_F2[11..8].d = D[3..0]; ELSE AY_F2[11..8].d = AY_F2[11..8] ; END IF; + IF (AY_AAX0 & AY_AAX5) THEN AY_F3[7..0].d = D[]; ELSE AY_F3[7..0].d = AY_F3[7..0] ; END IF; + IF (AY_AAX1 & AY_AAX5) THEN AY_F3[11..8].d = D[3..0]; ELSE AY_F3[11..8].d = AY_F3[11..8] ; END IF; + IF (AY_AAX2 & AY_AAX5) THEN AY_S1[4..0].d = D[4..0]; ELSE AY_S1[4..0].d = AY_S1[4..0] ; END IF; + IF (AY_AAX3 & AY_AAX5) THEN AY_X_[5..0].d = D[5..0]; ELSE AY_X_[5..0].d = AY_X_[5..0] ; END IF; + IF (AY_AAX0 & AY_AAX6) THEN AY_A1[4..0].d = D[4..0]; ELSE AY_A1[4..0].d = AY_A1[4..0] ; END IF; + IF (AY_AAX1 & AY_AAX6) THEN AY_A2[4..0].d = D[4..0]; ELSE AY_A2[4..0].d = AY_A2[4..0] ; END IF; + IF (AY_AAX2 & AY_AAX6) THEN AY_A3[4..0].d = D[4..0]; ELSE AY_A3[4..0].d = AY_A3[4..0] ; END IF; + IF (AY_AAX3 & AY_AAX6) THEN AY_GO[7..0].d = D[]; ELSE AY_GO[7..0].d = AY_GO[7..0] ; END IF; + IF (AY_AAX0 & AY_AAX7) THEN AY_GO[15..8].d = D[]; ELSE AY_GO[15..8].d = AY_GO[15..8] ; END IF; + IF (AY_AAX1 & AY_AAX7) THEN AY_GF[3..0].d = D[3..0]; ELSE AY_GF[3..0].d = AY_GF[3..0] ; END IF; +% + AY_F1[7..0].clk = DFF((AY_AAX0 & AY_AAX4),!AY_D_WR,,!/IO); + AY_F1[11..8].clk = DFF((AY_AAX1 & AY_AAX4),!AY_D_WR,,!/IO); + AY_F2[7..0].clk = DFF((AY_AAX2 & AY_AAX4),!AY_D_WR,,!/IO); + AY_F2[11..8].clk = DFF((AY_AAX3 & AY_AAX4),!AY_D_WR,,!/IO); + AY_F3[7..0].clk = DFF((AY_AAX0 & AY_AAX5),!AY_D_WR,,!/IO); + AY_F3[11..8].clk = DFF((AY_AAX1 & AY_AAX5),!AY_D_WR,,!/IO); + AY_S1[4..0].clk = DFF((AY_AAX2 & AY_AAX5),!AY_D_WR,,!/IO); + AY_X_[5..0].clk = DFF((AY_AAX3 & AY_AAX5),!AY_D_WR,,!/IO); + AY_A1[4..0].clk = DFF((AY_AAX0 & AY_AAX6),!AY_D_WR,,!/IO); + AY_A2[4..0].clk = DFF((AY_AAX1 & AY_AAX6),!AY_D_WR,,!/IO); + AY_A3[4..0].clk = DFF((AY_AAX2 & AY_AAX6),!AY_D_WR,,!/IO); + AY_GO[7..0].clk = DFF((AY_AAX3 & AY_AAX6),!AY_D_WR,,!/IO); + AY_GO[15..8].clk = DFF((AY_AAX0 & AY_AAX7),!AY_D_WR,,!/IO); + AY_GF[3..0].clk = DFF((AY_AAX1 & AY_AAX7),!AY_D_WR,,!/IO); + + AY_F1[7..0].d = D[]; + AY_F1[11..8].d = D[3..0]; + AY_F2[7..0].d = D[]; + AY_F2[11..8].d = D[3..0]; + AY_F3[7..0].d = D[]; + AY_F3[11..8].d = D[3..0]; + AY_S1[4..0].d = D[4..0]; + AY_X_[5..0].d = D[5..0]; + AY_A1[4..0].d = D[4..0]; + AY_A2[4..0].d = D[4..0]; + AY_A3[4..0].d = D[4..0]; + AY_GO[7..0].d = D[]; + AY_GO[15..8].d = D[]; + AY_GF[3..0].d = D[3..0]; +% + AY_C1[].clk = AY_CLK1; + AY_C2[].clk = AY_CLK1; + AY_C3[].clk = AY_CLK1; + AY_C4[].clk = AY_CLK1; + +-- AY_C5[].clk = AY_CLK1; + AY_C5[].clk = CTF1; + + AY_OUT[].clk= AY_CLK1; + AY_SH[].clk = AY_CLK1; +-- AY_SH[].clk = CTH2; + AY_X_[].prn = /RESET; + + IF LCELL(AY_C1[] == 1) THEN AY_C1[].d = AY_F1[]; AY_OUT1 = !AY_OUT1; + ELSE AY_C1[].d = AY_C1[] - 1; AY_OUT1 = AY_OUT1; END IF; + + IF LCELL(AY_C2[] == 1) THEN AY_C2[].d = AY_F2[]; AY_OUT2 = !AY_OUT2; + ELSE AY_C2[].d = AY_C2[] - 1; AY_OUT2 = AY_OUT2; END IF; + + IF LCELL(AY_C3[] == 1) THEN AY_C3[].d = AY_F3[]; AY_OUT3 = !AY_OUT3; + ELSE AY_C3[].d = AY_C3[] - 1; AY_OUT3 = AY_OUT3; END IF; + + IF LCELL((AY_C4[] == 1) or (AY_C4[] == 0)) THEN AY_C4[].d = AY_S1[]; AY_SH[] = ((!AY_SH0 xor AY_SH1 xor A0),AY_SH[7..1]); + ELSE AY_C4[].d = AY_C4[] - 1; AY_SH[] = AY_SH[]; END IF; + + AY_F_RES = LCELL(!(AY_AAX1 & AY_AAX7) or AY_D_WR); + +-- AY_F_RES = DFF(!(AY_AAX1 & AY_AAX7),!AY_D_WR,,!/IO); + + (AY_C5[19..1].clrn,AY_C5[0].prn) = AY_F_RES; + + IF LCELL(AY_C5[15..0] == 1) + THEN AY_C5[15..0].d = AY_GO[]; +-- AY_C5[19..16] = AY_C5[19..16]+1; + ELSE AY_C5[15..0].d = AY_C5[15..0] - 1; +-- AY_C5[19..16] = AY_C5[19..16]; + END IF; + + AY_C5[19..16] = AY_C5[19..16] + 1; + + AY_ABLK = DFF(!AY_GF3,!AY_C19,AY_F_RES,); + + AY_BBLK = DFF(AY_GF0,!AY_C19,AY_F_RES,); + AY_AINV = AY_GF2; + AY_BINV = DFF((AY_GF1 & (AY_GF0 or !AY_BINV)),!AY_C19,AY_F_RES,); + +-- AY_AA[].clrn= AY_ABLK; + AY_AA[].clk = AY_CLK1; + AY_AA[].clrn = VCC; + + AY_AA[].d = !((AY_C5[19..16] or AY_BBLK) xor AY_BINV xor AY_AINV); + +-- AY_AA[].d = !(AY_C5[19..16] or AY_BBLK); +-- AY_AA[] = B"1111"; + +-- AY_Q1[3..0] = ((AY_A1[3..0] or AY_A1[4]) & (AY_AA[] or !AY_A1[4])) & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0)); +-- AY_Q2[3..0] = ((AY_A2[3..0] or AY_A2[4]) & (AY_AA[] or !AY_A2[4])) & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0)); +-- AY_Q3[3..0] = ((AY_A3[3..0] or AY_A3[4]) & (AY_AA[] or !AY_A3[4])) & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0)); + + AY_Q1[3..0] = ((AY_A1[3..0] or AY_A1[4])) & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0)); + AY_Q2[3..0] = ((AY_A2[3..0] or AY_A2[4])) & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0)); + AY_Q3[3..0] = ((AY_A3[3..0] or AY_A3[4])) & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0)); + +IF AY_STEREO == 1 THEN + SND_L0 = (CTH[1..0],CT[5..2]) > ((GND,AY_Q1[],GND) + (GND,!BRD4,AY_Q2[])); + SND_L1 = GND; + SND_R0 = (CTH[1..0],CT[5..2]) > ((GND,AY_Q3[],GND) + (GND,!BRD4,AY_Q2[])); + SND_R1 = GND; +ELSE + + AY_XX[5..4] = 0; + + CASE CTH[1..0] IS + WHEN 0 => AY_XX[3..0] = AY_Q1[]; + WHEN 1 => AY_XX[3..0] = AY_Q2[]; + WHEN 2 => AY_XX[3..0] = AY_Q3[]; + WHEN 3 => AY_XX[3..0] = BRD4; + END CASE; + +-- AY_XX[] = (GND,GND,AY_Q1[]) + (GND,GND,AY_Q3[]); + + SND_L0 = DFF((CT[5..2] > AY_XX[3..0]),CT1,,); + + SND_R0 = SND_L0; + SND_L1 = GND; + SND_R1 = GND; + +END IF; + + BRD4.clrn = VCC; + +ELSE + +IF AY_3_8910 == 2 THEN +-- AY-3-8910 II version! + + AY_ADR[].clk = DFF(!(DCP[] == H"90"),!/IOWR,,!/IO); + AY_D_WR = DFF(!(DCP[] == H"91"),!/IOWR,,!/IO); + AY_F_RES = DFF(!(AY_ADR[] == B"XXXX1101"),!AY_D_WR,,!/IO); + + AY_ADR[].d = D[]; + + AY_X_[].prn = /RESET; + AY_X_[].clk = AY_D_WR; + AY_GF[].clk = AY_D_WR; + AY_A1[].clk = AY_D_WR; + AY_A2[].clk = AY_D_WR; + AY_A3[].clk = AY_D_WR; + + TABLE AY_ADR[3..0] => AY_ADRX[]; + B"0000" => B"00000010"; B"1000" => B"10001000"; + B"0001" => B"00000011"; B"1001" => B"10001001"; + B"0010" => B"00000110"; B"1010" => B"10001010"; + B"0011" => B"00000111"; B"1011" => B"00001110"; + B"0100" => B"00001010"; B"1100" => B"00001111"; + B"0101" => B"00001011"; B"1101" => B"10001101"; + B"0110" => B"00010010"; B"1110" => B"10001110"; + B"0111" => B"10000111"; B"1111" => B"10001111"; + END TABLE; + + IF LCELL(AY_ADR[] == B"XXXX0111") THEN AY_X_[5..0].d = D[5..0]; ELSE AY_X_[5..0].d = AY_X_[5..0] ; END IF; + IF LCELL(AY_ADR[] == B"XXXX1000") THEN AY_A1[4..0].d = D[4..0]; ELSE AY_A1[4..0].d = AY_A1[4..0] ; END IF; + IF LCELL(AY_ADR[] == B"XXXX1001") THEN AY_A2[4..0].d = D[4..0]; ELSE AY_A2[4..0].d = AY_A2[4..0] ; END IF; + IF LCELL(AY_ADR[] == B"XXXX1010") THEN AY_A3[4..0].d = D[4..0]; ELSE AY_A3[4..0].d = AY_A3[4..0] ; END IF; + IF LCELL(AY_ADR[] == B"XXXX1101") THEN AY_GF[3..0].d = D[3..0]; ELSE AY_GF[3..0].d = AY_GF[3..0] ; END IF; + + AY_CCC[].clk = CLK42; + AY_CCC[5..0].d = CT[5..0]; + AY_CCC6 = AY_CCC6 xor (!CT5 & AY_CCC5); + + AY_C.clk = CLK42; + AY_CX.clk = CLK42; +-- AY_WR.clk = CLK42; + AY_CH_WR.clk= CLK42; + AY_DRD.clk = CLK42; + + AY_DO[] = lpm_ram_dq(AY_DI[],AY_AX[],!AY_WR,CLK42,CLK42) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="AY.MIF"); + + CASE AY_CCC[1..0] IS + WHEN B"00" => + AY_CX = AY_CX & (AY_CCC2 or AY_CCC3); + AY_AX[] = (GND,GND,GND,AY_CCC[6..2]); + (AY_C,AY_DI[]) = (GND,AY_DO[]) + (B"00000000",AY_C) - 1; + AY_C = !AY_CCC2 or AY_C; + AY_CH_WR= VCC; + AY_WR = VCC; + WHEN B"X1" => + AY_AX[] = AY_ADRX[]; + AY_DI[] = D[]; + AY_WR = AY_D_WR; + AY_DRD = GND; + AY_C = AY_C; + AY_CX = AY_CX; + AY_CH_WR= VCC; + WHEN B"10" => + AY_AX[] = (GND,GND,GND,AY_CCC[6..4],GND,AY_CCC2); + (AY_C,AY_DI[]) = (GND,AY_DO[]) + (B"00000000",AY_C) - 1; + AY_CX = ((AY_DI[] != H"00") & !AY_CCC3) or AY_CX; + AY_WR = AY_CCC3 & AY_CX; + AY_CH_WR= AY_CCC2 or !AY_CCC3; + END CASE; + + (AY_SH[].clk,AY_VA[].clk,AY_OUT[].clk) = DFF(AY_CH_WR or AY_CX,CLK42,,); + + CASE AY_CCC[6..4] IS + WHEN B"000" => AY_OUT1 = !AY_OUT1; AY_OUT2 = AY_OUT2; AY_OUT3 = AY_OUT3; AY_VA[] = AY_VA[]; AY_SH[] = AY_SH[]; + WHEN B"001" => AY_OUT1 = AY_OUT1; AY_OUT2 = !AY_OUT2; AY_OUT3 = AY_OUT3; AY_VA[] = AY_VA[]; AY_SH[] = AY_SH[]; + WHEN B"010" => AY_OUT1 = AY_OUT1; AY_OUT2 = AY_OUT2; AY_OUT3 = !AY_OUT3; AY_VA[] = AY_VA[]; AY_SH[] = AY_SH[]; + WHEN B"011" => AY_OUT1 = AY_OUT1; AY_OUT2 = AY_OUT2; AY_OUT3 = AY_OUT3; AY_VA[] = AY_VA[] + 1; AY_SH[] = AY_SH[]; + WHEN B"100" => AY_OUT1 = AY_OUT1; AY_OUT2 = AY_OUT2; AY_OUT3 = AY_OUT3; AY_VA[] = AY_VA[]; AY_SH[] = ((!AY_SH0 xor AY_SH1 xor A0),AY_SH[7..1]); + WHEN B"101" => AY_OUT1 = AY_OUT1; AY_OUT2 = AY_OUT2; AY_OUT3 = AY_OUT3; AY_VA[] = AY_VA[]; AY_SH[] = AY_SH[]; + WHEN B"110" => AY_OUT1 = AY_OUT1; AY_OUT2 = AY_OUT2; AY_OUT3 = AY_OUT3; AY_VA[] = AY_VA[]; AY_SH[] = AY_SH[]; + WHEN B"111" => AY_OUT1 = AY_OUT1; AY_OUT2 = AY_OUT2; AY_OUT3 = AY_OUT3; AY_VA[] = AY_VA[]; AY_SH[] = AY_SH[]; + END CASE; + + AY_VA[].clrn= AY_F_RES; + AY_ABLK = DFF(!AY_GF3,!AY_VA3,AY_F_RES,); + AY_BBLK = DFF(AY_GF0,!AY_VA3,AY_F_RES,); + AY_AINV = AY_GF2; + AY_BINV = DFF((AY_GF1 & (AY_GF0 or !AY_BINV)),!AY_VA3,AY_F_RES,); + + AY_VA[].clrn= AY_ABLK; + AY_AA[].clk = CLK42; + AY_AA[].d = !((AY_VA[] or AY_BBLK) xor AY_BINV xor AY_AINV); + + AY_Q1[3..0] = ((AY_A1[3..0] or AY_A1[4]) & (AY_AA[] or !AY_A1[4])) & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0)); + AY_Q2[3..0] = ((AY_A2[3..0] or AY_A1[4]) & (AY_AA[] or !AY_A2[4])) & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0)); + AY_Q3[3..0] = ((AY_A3[3..0] or AY_A1[4]) & (AY_AA[] or !AY_A3[4])) & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0)); + +IF AY_STEREO == 1 THEN + SND_L0 = (CTH[1..0],CT[5..2]) > ((GND,AY_Q1[],GND) + (GND,!BRD4,AY_Q2[])); + SND_L1 = GND; + SND_R0 = (CTH[1..0],CT[5..2]) > ((GND,AY_Q3[],GND) + (GND,!BRD4,AY_Q2[])); + SND_R1 = GND; +ELSE + AY_XX[] = (GND,GND,AY_Q1[]) + (GND,GND,AY_Q3[]); + + SND_L0 = DFF(((CTH[1..0],CT[5..2]) > (AY_XX[] + (GND,BRD4,AY_Q2[]) + )),CT1,,); + SND_R0 = SND_L0; + SND_L1 = GND; + SND_R1 = GND; + +END IF; + + BRD4.clrn = VCC; +ELSE +-- ====== AY8910 III version ========= + + AY_CCC[].clk = CLK42; + AY_CCC[8..0].d = (CTH[2..0],CT[5..0]); + + AY_ADR[].d = D[]; + (AY_AAX[].clk,AY_ADR[].clk) = LCELL(!(DCP[] == H"90") or /IOWR); + +-- (AY_AAX[].clk,AY_ADR[].clk) = DFF(!(DCP[] == H"90"),!/IOWR,,!/IO); +-- AY_AAX[].d = ((D2 & D3),(!D2 & D3),(D2 & !D3),(!D2 & !D3),(D0 & D1),(!D0 & D1),(D0 & !D1),(!D0 & !D1)); + + AY_AAX0.d = (D[3..0] == B"1101"); + AY_AAX1.d = (D[3..0] == B"1000") or (D[3..0] == B"1001") or (D[3..0] == B"1010"); + +-- AY_D_WR = LCELL(!(DCP[] == H"91") or /IOWR); +-- AY_D_WR = DFF((!(DCP[] == H"91") or /IOWR),CLK42,,); + + AY_D_WR = DFF(!(DCP[] == H"91"),!/IOWR,,!/IO); + + AY_F_RES = DFF(VCC,DFF((!((AY_DO[7..5] == B"111") & AY_CCC1 & !AY_DO0) or AY_F_RES),CLK42,,),LCELL(!AY_AAX0 or AY_D_WR),); + + AY_X_[].prn = VCC; +-- AY_X_[].prn = /RESET; +-- AY_X_[].CLRN = /RESET; + AY_GF[3..0].clrn = /RESET; + AY_GF[3..0].prn = VCC; + AY_GF[3..0].clk = AY_D_WR; + + IF AY_ADR[] == B"XXXX1101" THEN AY_GF[3..0].d = D[3..0]; ELSE AY_GF[3..0].d = AY_GF[3..0] ; END IF; + + AY_CCC[].clk = CLK42; + AY_CCC[8..0].d = (CTH[2..0],CT[5..0]); + + CASE AY_CCC[1..0] IS + WHEN B"00" => + AY_AX[] = (VCC,GND,AY_CCC[7..2]); + AY_WR = GND; + AY_DI[] = AY_DAT[]; + WHEN B"01" => + AY_AX[] = (B"0000",AY_ADR[3..0]); + AY_WR = !AY_D_WR; + AY_DI[] = MXVD[]; + WHEN B"1X" => + AY_AX[] = (GND,GND,GND,AY_DO[4..0]); + AY_WR = !LCELL(!(AY_DO[7..5] == B"010") & + !((AY_DO[7..5] == B"110") & AY_CX)); + AY_DI[] = AY_DAT[]; + END CASE; + + AY_DAT_WR.clk = CLK42; + AY_DAT_WR.ena = AY_CCC1; + AY_DAT_WR = !(AY_DO[7..5] == B"X0X"); + + AY_DD[].clk = CLK42; + AY_DD[].ena = !(AY_CCC1 or AY_CCC0); + AY_DD[] = AY_DO[]; + + AY_DO[] = lpm_ram_dq(AY_DI[],AY_AX[],AY_WR,CLK42,CLK42) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="AY.MIF"); + + AY_CX.prn = !DFF((((AY_DO[7..5] == B"00X") & AY_CCC1) & (!AY_DO5 or AY_C)),CLK42,,); +-- AY_C.prn = !DFF(((AY_DO[7..5] == B"X00") & AY_CCC1),CLK42,,); + AY_C.prn = VCC; + + AY_CX.clk = CLK42; + AY_CX.ena = DFF((AY_CCC1 & (AY_DO[7..5] == B"111" or AY_DO[7..5] == B"010")),CLK42,,); + + IF DFF((AY_DO[7..5] == B"010"),CLK42,,) THEN + AY_CX = LCELL(AY_DAT[] == 0) & AY_CX; + ELSE + AY_CX = DFF(((!/RESET & AY_DO0) or (!AY_F_RES & !AY_DO0)),CLK42,,); + END IF; + + (AY_C.clk,AY_DAT[].clk) = CLK42; + (AY_C.ena,AY_DAT[].ena) = DFF(!AY_DAT_WR,CLK42,,); + + (AY_C,AY_DAT[]) = (GND,AY_DO[]) - (B"00000000",DFF((DFF(!AY_DO5,CLK42,,) or (AY_C & DFF(AY_DO7,CLK42,,))),CLK42,,)); + + AY_OUT[].clk = CLK42; + + AY_AMP[].clk = CLK42; + AY_AMP[] = ((AY_DAT[3..0] or AY_DAT[4]) & (AY_AA[] or !AY_DAT[4])); + + AY_OUTS1 = DFF(((AY_DO[7..0] == B"011XX001") & AY_CCC1),CLK42,,); + AY_OUTS2 = DFF(((AY_DO[7..0] == B"011XX010") & AY_CCC1),CLK42,,); + AY_OUTS3 = DFF(((AY_DO[7..0] == B"011XX011") & AY_CCC1),CLK42,,); + + IF AY_OUTS1 THEN + AY_OUT1 = AY_CX xor AY_OUT1; + ELSE + AY_OUT1 = AY_OUT1; + END IF; + + IF AY_OUTS2 THEN + AY_OUT2 = AY_CX xor AY_OUT2; + ELSE + AY_OUT2 = AY_OUT2; + END IF; + + IF AY_OUTS3 THEN + AY_OUT3 = AY_CX xor AY_OUT3; + ELSE + AY_OUT3 = AY_OUT3; + END IF; + + -- CHANEL 1 + AY_Q = (AY_OUTS1 & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0))) or + -- CHANEL 2 + (AY_OUTS2 & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0))) or + -- CHANEL 3 + (AY_OUTS3 & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0))); + + AY_XX[].clk = CLK42; + AY_XX[].ena = AY_Q; + AY_XX[].clrn = DFF((AY_CCC[8..5] == 0),CLK42,,); + + AY_XX[] = AY_XX[] + (GND,GND,AY_AMP[]); + + AY_XXM[] = AY_XX[]; + AY_XXM[].clk = !AY_CCC8; + + AY_SH[].clk = CLK42; + AY_SH[].clrn = VCC; + AY_SHR.clk = CLK42; + (AY_SHR.ena,AY_SH[].ena) = DFF(((AY_DO[7..0] == B"011XX100") & AY_CCC1 & AY_CX),CLK42,,); +-- (AY_SHR,AY_SH[]) = (LCELL((AY_SH0 xor AY_SH4) or ((AY_SHR,AY_SH[]) == 0)),AY_SHR,AY_SH[7..1]); + (AY_SHR,AY_SH[]) = (LCELL((AY_SH0 xor AY_SH4) xor A0),AY_SHR,AY_SH[7..1]); +% + AY_DQ1[].clk = CLK42; + AY_DQ1[].ena = AY_OUTS1; + AY_DQ1[] = AY_AMP[] & LCELL((AY_OUT1 or AY_X_0) & (AY_X_3 or AY_SH0)); + + AY_DQ2[].clk = CLK42; + AY_DQ2[].ena = AY_OUTS3; + AY_DQ2[] = AY_AMP[] & LCELL((AY_OUT2 or AY_X_1) & (AY_X_4 or AY_SH0)); + + AY_DQ3[].clk = CLK42; + AY_DQ3[].ena = AY_OUTS3; + AY_DQ3[] = AY_AMP[] & LCELL((AY_OUT3 or AY_X_2) & (AY_X_5 or AY_SH0)); +% + AY_VAR.clk = CLK42; + AY_VA[].clk = CLK42; + AY_VAR.clrn= AY_F_RES; + AY_VA[].clrn= AY_F_RES; + + (AY_VAR.ena,AY_VA[].ena) = DFF(((AY_DO[7..0] == B"011XX101") & AY_CCC1 & !AY_BBLK),CLK42,,); + (AY_VA[],AY_VAR) = (AY_VA[],AY_VAR) + (B"0000",AY_CX); + + AY_X_[].clk = CLK42; + AY_X_[].ena = DFF(((AY_DO[7..0] == B"011XX110") & AY_CCC1),CLK42,,); + AY_X_[] = AY_DAT[5..0]; + +% + AY_GF[].clk = CLK42; + IF LCELL((AY_DO[7..0] == B"011XX111") & AY_CCC1) THEN + AY_GF[] = AY_DAT[3..0]; + ELSE + AY_GF[] = AY_GF[]; END IF; +% + + AY_BBLK = DFF(AY_GF0,!AY_VA3,AY_F_RES,); -- VA_COUNT_STOP + + AY_ABLK = DFF(!AY_GF3,!AY_VA3,AY_F_RES,); -- set ALL ZERO + + AY_BINV = DFF(((AY_GF1 xor AY_GF0) & !AY_BINV),!AY_VA3,AY_F_RES,); -- inverse 2-ND + + AY_AINV = AY_GF2; -- inverse ALL + + AY_AA[].clrn= VCC; + AY_AA[].clk = CLK42; + AY_AA[].d = (AY_VA[] xor AY_BINV xor !AY_AINV) & !AY_ABLK; + +-- AY_Q1[3..0] = AY_DQ1[3..0]; +-- AY_Q2[3..0] = AY_DQ2[3..0]; +-- AY_Q3[3..0] = AY_DQ3[3..0]; + + SND_L0 = DFF(((AY_CCC[7..2]) > AY_XXM[]),AY_CCC1,,); + + SND_R0 = SND_L0; + + SND_L1 = GND; + SND_R1 = GND; + + BRD4.clrn = VCC; + +END IF; + +END IF; +ELSE +-- =============== COVOX ================= + + +-- COV_WR = !/IOWR & (DCP[] == B"10001000"); + +CASE covox_mode IS +WHEN 0 => + +-- COV_WR = !DFF(!(DCP[] == B"10001000"),!/IOWR,,!/IO); + + COV_WR = !/IOWR & (DCP[] == B"10001000"); + + COV[] = lpm_ram_dq(D[],VCC,VCC,COV_WR,CLK42,) + WITH (lpm_width=8,lpm_widthad=2,lpm_file="COVOX.MIF",lpm_outdata="UNREGISTERED"); + +% + IF !CT1 THEN + COV_ADR[] = (CTH[2..1]); + COV_WR = GND; + ELSE + COV_ADR[] = (A[6..5]); + COV_WR = !/IOWR & (DCP[] == B"10001000"); + END IF; +% + +-- COV[] = lpm_ram_dq(D[],COV_ADR[],COV_WR,CLK42,) +-- WITH (lpm_width=8,lpm_widthad=2,lpm_file="COVOX.MIF",lpm_outdata="UNREGISTERED"); + +WHEN 1 => + + IF !CT1 THEN + COV_ADR[1..0] = (CTH[2..1]); + COV_WR = GND; + ELSE + COV_ADR[1..0] = (A6,LCELL(A4 xor !A3)); + COV_WR = !/IOWR & (DCP[] == B"10001000"); +-- COV_WR = !DFF(!(DCP[] == B"10001000"),!/IOWR,,!/IO); + END IF; + +-- COV_WR = !/IOWR & (DCP[] == B"10001000"); + + COV[] = lpm_ram_dq(D[],COV_ADR[1..0],COV_WR,CLK42,) + WITH (lpm_width=8,lpm_widthad=2,lpm_file="COVOX.MIF",lpm_outdata="UNREGISTERED"); +-- COV[] = lpm_ram_dq(D[],B"00",COV_WR,CLK42,) +-- WITH (lpm_width=8,lpm_widthad=2,lpm_file="COVOX.MIF",lpm_outdata="UNREGISTERED"); +WHEN 2 => + + + COV_BL[2..0].clk = CTH2; + + IF COV_BL2 THEN + COV_BL[2..0] = GND; + ELSE + COV_BL[2..0] = COV_BL[2..0] + 1; + END IF; + + COV_BL[10..3].clk = COV_BL2; + COV_BL[10..3] = COV_BL[10..3] + 1; + + COV_BL_X[] = 4; +% + IF (COV_BL[2..0] == COV_BL_X[]) THEN + COV_BL[2..0] = 0; + COV_BL[10..3] = COV_BL[10..3] + 1; + ELSE + COV_BL[2..0] = COV_BL[2..0] + 1; + COV_BL[10..3] = COV_BL[10..3]; + END IF; +% + + IF !CT1 THEN + COV_ADR[] = COV_BL[10..3]; + +-- COV_ADR[5..0] = (CTV[5..0]); +-- COV_ADR[7..6] = COV_AR[7..6]; + + COV_WR = GND; + ELSE + COV_ADR[7..0] = !(A[15..8]); +-- COV_WR = !DFF(!(DCP[] == B"10001000"),!/IOWR,,!/IO); + COV_WR = !/IOWR & (DCP[] == B"10001000"); + END IF; + + COV_AR[7..6] = COV_BL[10..9]; + +-- COV_AR[7..6] = (DFF((COV_AR7 xor COV_AR6),!CTV5,,),DFF(!COV_AR6,!CTV5,,)); + +-- COV_ADR[7..6] = (DFF((COV_ADR7 xor COV_ADR6),!COV_ADR5,,),DFF(!COV_ADR6,!COV_ADR5,,)); + + COV[] = lpm_ram_dq(D[],COV_ADR[],COV_WR,CLK42,) + WITH (lpm_width=8,lpm_widthad=8,lpm_file="COVOX.MIF",lpm_outdata="UNREGISTERED"); + +WHEN 3 => + + COV_DFF[].clk = /IOWR; + COV_DFF[].ena = (DCP[] == B"10001000"); + COV_DFF[].d = D[]; + COV[] = COV_DFF[]; + +END CASE; + + + CLK42X = DFF(!CLK42X,CLK84,,); + CLK84 = LCELL(CLK42 xor CLK42X); + + IF !(COVOX == 0) THEN +-- BRD4.clrn = (!(DCP[] == B"100010XX") or /IOWR); + BRD4.clrn = (!COV_WR); + ELSE + BRD4.clrn = VCC; + END IF; + + +% + COV_CT[5..0].clk = CLK84; + +-- IF DFF((CT1 or CT2 or CT3),CLK42,,) THEN + + IF LCELL(CT1 or CT2 or CT3) THEN + COV_CT[5..0] = COV_CT[5..0] - 1; + ELSE + COV_CT[5..0] = (GND,GND,COV[7..4]); + END IF; + + COV_CT[10..6].clk = !COV_CT4; + +-- IF DFF((CTH2 or CTH1 or CTH0 or CT5 or CT4),CLK42,,) THEN + + IF LCELL(CTH2 or CTH1 or CTH0 or CT5 or CT4) THEN + COV_CT[10..6] = COV_CT[10..6] - 1; + ELSE + COV_CT[10..6] = (COV[4..0]); + END IF; + +-- OUT = DFF((COV_CT4 or DFF((COV_CT4 & COV_CT10),CLK42,,)),CLK42,,); +% + + IF COVOX == 8 THEN + + COV_CT[].clk = CLK42; + + IF DFF((CTH2 & CTH1 & CTH0 & CT5),CLK42,,) THEN + COV_CT[].d = (GND,GND,GND,(COV7 xor BRD4),COV[6..0]); + ELSE + COV_CT[].d = COV_CT[] - 1; + END IF; + +% + (SND_L0,SND_R0) = COV_CT9 xor BRD4; + (SND_L1,SND_R1) = VCC; +% + SND_L0 = !DFF(((CTH0,CT[5..2]) > ((BRD4 xor COV7),COV[6..3])),!CT1,,); + SND_L1 = !DFF(((CT[5..3]) > COV[2..0]),!CT1,,); + SND_R0 = SND_L0; + SND_R1 = SND_L1; +% + + + SND_L0 = DFF(((COV_CT5 or DFF((COV_CT5 & !DFF((COV[3..0] > (CTH[1..0],CT[5..4])),CT1,,)),CLK84,,)) xor BRD4),CLK84,,); + SND_L1 = GND; + +-- SND_R0 = !DFF(((CTH0,CT[5..2]) > ((BRD4 xor COV7),COV[6..3])),!CT1,,); +-- SND_R1 = !DFF(((CT[5..3]) > COV[2..0]),CT1,,); + + SND_R0 = SND_L0; + SND_R1 = SND_L1; +% + END IF; + + IF COVOX == 0 THEN +-- SND_L0 = !((CT5 & CT4) or (BRD4 & (CT5 or CT4))); + SND_L0 = BRD4; + SND_L1 = VCC; +-- SND_R0 = !((CT5 & CT4) or (BRD4 & (CT5 or CT4))); + SND_R0 = BRD4; + SND_R1 = VCC; + END IF; + + +END IF; +END IF; + +-- FORTH_PROCESSOR + +IF FORTH_CPU == 1 THEN + + F_CLK.clk = CLK42; + F_CLK.prn = DFF(/RESET,CLK42,,); + + FP_CLK = (LCELL(F_CLK)); + FP_CLK = F_CLK; + + FDR[].clk = FP_CLK; + FCMD[].clk = FP_CLK; + F_ST0[].clk = FP_CLK; + F_ST1[].clk = FP_CLK; + F_ST2[].clk = FP_CLK; + F_ST3[].clk = FP_CLK; + + FDI[] = (VD0[],VD1[]); +% + (,,ALU[3..0],,AC4) = 74181 (FCMD[3..0],FCMD4,FCMD5,STDO[3..0],FDR[3..0]); + (,,ALU[7..4],,AC8) = 74181 (FCMD[3..0],FCMD4,AC4, STDO[7..4],FDR[7..4]); + (,,ALU[11..8],,AC12)= 74181 (FCMD[3..0],FCMD4,AC8, STDO[11..8],FDR[11..8]); + (,,ALU[15..12],,) = 74181 (FCMD[3..0],FCMD4,AC12, STDO[15..12],FDR[15..12]); +% + + (ALU[],C_ALU,) = lpm_add_sub (!FCMD1,STDO_[],FDR_[],!FCMD0,,,) + WITH (LPM_WIDTH = 16,LPM_REPRESENTATION = "UNSIGNED"); + +-- (ALU[],,) = lpm_add_sub (!FCMD1,STDO_[],FDR_[],VCC,,) +-- WITH (LPM_WIDTH = 16,LPM_REPRESENTATION = "UNSIGNED"); + + CASE FCMD[3..2] IS + WHEN 0 => STDO_[] = STDO[]; + WHEN 1 => STDO_[] = STDO[] & FDR[]; + WHEN 2 => STDO_[] = !STDO[]; + WHEN 3 => STDO_[] = GND; + END CASE; + + CASE FCMD[5..4] IS + WHEN 0 => FDR_[] = GND; + WHEN 1 => FDR_[] = !FDR[]; + WHEN 2 => FDR_[] = STDO[] or FDR[]; + WHEN 3 => FDR_[] = FDR[]; + END CASE; + + CASE FCMD[7..6] IS + WHEN 0 => FDR[] = FDR[]; +-- WHEN 1 => FDR[] = FDR[] or FDI[]; + WHEN 1 => FDR[] = (B"000000000000000",C_ALU); + WHEN 2 => FDR[] = STDO[]; + WHEN 3 => FDR[] = FDI[]; + END CASE; + + FDR[].prn = /RESET; + +-- STDO[] = lpm_ram_dq(ALU[],STA[],!FCMD8,CLK42,) + STDO[] = lpm_ram_dq(ALU[],STA[],LCELL(!F_CLK & !FCMD8),CLK42,) + WITH (lpm_width=16,lpm_widthad=8,lpm_file="FORTH.MIF",lpm_outdata="UNREGISTERED"); + + FDO[] = FDR[]; + + ZERO[] = GND; + + (STA[],,) = (FCMD[10..9], + lpm_add_sub (FCMD12,F_ST_[],ZERO[],!FCMD11,,,) + WITH (LPM_WIDTH = STACK_W,LPM_REPRESENTATION = "UNSIGNED",ONE_INPUT_IS_CONSTANT = "YES")); + + CASE (LCELL((FCMD12 & FCMD11) or FCMD10),FCMD9) IS + WHEN 0 => F_ST_X[] = F_ST0[]; + WHEN 1 => F_ST_X[] = F_ST1[]; + WHEN 2 => F_ST_X[] = VCC; + WHEN 3 => F_ST_X[] = VCC; + END CASE; + + CASE (LCELL((FCMD12 & FCMD11) or !FCMD10),FCMD9) IS + WHEN 0 => F_ST_Y[] = F_ST2[]; + WHEN 1 => F_ST_Y[] = F_ST3[]; + WHEN 2 => F_ST_Y[] = VCC; + WHEN 3 => F_ST_Y[] = VCC; + END CASE; + + FOR i IN 0 TO STACK_W-1 GENERATE + F_ST_[i] = F_ST_X[i] & CASCADE(F_ST_Y[i]); + END GENERATE; + + CASE FCMD[10..9] IS + WHEN 0 => F_ST0[] = STA[STACK_W-1..0]; F_ST1[] = F_ST1[]; F_ST2[] = F_ST2[]; F_ST3[] = F_ST3[]; + WHEN 1 => F_ST1[] = STA[STACK_W-1..0]; F_ST2[] = F_ST2[]; F_ST3[] = F_ST3[]; F_ST0[] = F_ST0[]; + WHEN 2 => F_ST2[] = STA[STACK_W-1..0]; F_ST3[] = F_ST3[]; F_ST0[] = F_ST0[]; F_ST1[] = F_ST1[]; + WHEN 3 => F_ST3[] = STA[STACK_W-1..0]; F_ST0[] = F_ST0[]; F_ST1[] = F_ST1[]; F_ST2[] = F_ST2[]; + END CASE; + + WE_MEM = !FCMD13; +-- WE_MEM = VCC; + + FCMD[].clrn = /RESET; + + CMD_X = DFF(!CMD_X,FP_CLK,/RESET,); + +-- CASE (LCELL(CMD_X & FCMD15),LCELL(CMD_X & FCMD14)) IS + CASE (FCMD15,FCMD14) IS + WHEN 0 => FCMD[] = FDI[]; +-- WHEN 1 => FCMD[] = B"0000000000101111"; % NEXT % +-- WHEN 2 => FCMD[] = B"0001000000101111"; % RET_CMD % +-- WHEN 3 => FCMD[] = B"0100100000111010"; % CALL % + WHEN 1 => FCMD[] = B"0000000000000000"; % NEXT % + WHEN 2 => FCMD[] = B"0001000000000000"; % RET_CMD % + WHEN 3 => FCMD[] = B"0100100000111111"; % CALL % + END CASE; + +END IF; + + + + +END; + diff --git a/fw/src/flex/sprint08.pof b/fw/src/flex/sprint08.pof new file mode 100644 index 0000000..07b7468 Binary files /dev/null and b/fw/src/flex/sprint08.pof differ diff --git a/fw/src/flex/sprint08.rpt b/fw/src/flex/sprint08.rpt new file mode 100644 index 0000000..9ef6274 --- /dev/null +++ b/fw/src/flex/sprint08.rpt @@ -0,0 +1,5763 @@ +Project Information c:\prj\sprinter\firmware\97\flex\sprint08.rpt + +MAX+plus II Compiler Report File +Version 10.0 9/14/2000 +Compiled: 08/05/2024 19:36:00 + +Copyright (C) 1988-2000 Altera Corporation +Any megafunction design, and related net list (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only to +program PLD devices (but not masked PLD devices) from Altera. Any other +use of such megafunction design, net list, support information, device +programming or simulation file, or any other related documentation or +information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to +the intellectual property, including patents, copyrights, trademarks, +trade secrets, or maskworks, embodied in any such megafunction design, +net list, support information, device programming or simulation file, or +any other related documentation or information provided by Altera or a +megafunction partner, remains with Altera, the megafunction partner, or +their respective licensors. No other licenses, including any licenses +needed under any third party's intellectual property, are provided herein. + + + +***** Project compilation was successful + + +Sprinter_97 + + +** DEVICE SUMMARY ** + +Chip/ Input Output Bidir Memory Memory LCs +POF Device Pins Pins Pins Bits % Utilized LCs % Utilized + +sprint08 EPF10K10QC208-3 8 55 70 6144 100% 567 98 % + +User Pins: 8 55 70 + + + +Project Information c:\prj\sprinter\firmware\97\flex\sprint08.rpt + +** PROJECT COMPILATION MESSAGES ** + +Warning: Line 375, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "MC" was declared but never used +Warning: Line 271, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "MS_MOUSE" was declared but never used +Warning: Line 391, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RGMOD4" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO4" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO14" was declared but never used +Warning: Line 589, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FN_ACC2" was declared but never used +Warning: Line 418, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "CNF7" was declared but never used +Warning: Line 391, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RGMOD5" was declared but never used +Warning: Line 311, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SC5" was declared but never used +Warning: Line 643, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SC0_X" was declared but never used +Warning: Line 586, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RASX" was declared but never used +Warning: Line 565, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "AY_DRD" was declared but never used +Warning: Line 418, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "CNF6" was declared but never used +Warning: Line 391, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RGMOD6" was declared but never used +Warning: Line 311, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SC6" was declared but never used +Warning: Line 336, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "VLAB17" was declared but never used +Warning: Line 391, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RGMOD7" was declared but never used +Warning: Line 311, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SC7" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO9" was declared but never used +Warning: Line 336, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "VLAB16" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO8" was declared but never used +Warning: Line 458, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SND_A_LD" was declared but never used +Warning: Line 336, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "VLAB15" was declared but never used +Warning: Line 301, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FIN0" was declared but never used +Warning: Line 348, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "WR_MODE2X" was declared but never used +Warning: Line 602, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RBRVA10" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO3" was declared but never used +Warning: Line 336, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "VLAB14" was declared but never used +Warning: Line 453, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SND_TEST" was declared but never used +Warning: Line 311, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SC2" was declared but never used +Warning: Line 301, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FIN1" was declared but never used +Warning: Line 500, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "CB_CMD" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO2" was declared but never used +Warning: Line 503, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "ID_CMD" was declared but never used +Warning: Line 311, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "SC3" was declared but never used +Warning: Line 301, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FIN2" was declared but never used +Warning: Line 418, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "CNF1" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO1" was declared but never used +Warning: Line 477, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "COV_BL_X2" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO11" was declared but never used +Warning: Line 316, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "BRD6" was declared but never used +Warning: Line 301, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FIN3" was declared but never used +Warning: Line 418, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "CNF0" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO0" was declared but never used +Warning: Line 477, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "COV_BL_X1" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO10" was declared but never used +Warning: Line 621, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "COV_AR6" was declared but never used +Warning: Line 316, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "BRD7" was declared but never used +Warning: Line 391, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RGMOD1" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO7" was declared but never used +Warning: Line 477, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "COV_BL_X0" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO13" was declared but never used +Warning: Line 418, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "CNF2" was declared but never used +Warning: Line 391, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RGMOD2" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO6" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO12" was declared but never used +Warning: Line 611, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "ASS_DIR7" was declared but never used +Warning: Line 418, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "CNF5" was declared but never used +Warning: Line 444, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "LWR_MODE2" was declared but never used +Warning: Line 391, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "RGMOD3" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO5" was declared but never used +Warning: Line 656, File c:\prj\sprinter\firmware\97\flex\sprint08.tdf: + Symbolic name "FDO15" was declared but never used +Warning: I/O error -- can't read initial memory content file 'PGA_INI4.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'PGA_INI4.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'KBD_INI2.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'SND_INI.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'AY.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'AY.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'COVOX.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'COVOX.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'COVOX.MIF'-- setting all initial values to 0 +Warning: I/O error -- can't read initial memory content file 'FORTH.MIF'-- setting all initial values to 0 +Warning: Flipflop 'ACC_END' stuck at VCC +Warning: Flipflop 'PN7' stuck at GND +Warning: Flipflop 'PN6' stuck at GND +Warning: Flipflop 'KBDR2' stuck at GND +Warning: Flipflop 'KBDR1' stuck at GND +Warning: Flipflop 'AGR6' stuck at GND +Warning: Flipflop 'AGR7' stuck at GND +Warning: Flipflop 'KBDR0' stuck at GND +Warning: Flipflop ':637' stuck at VCC +Warning: Flipflop ':638' stuck at GND +Warning: TRI or OPNDRN buffer ':1900' is permanently disabled +Warning: TRI or OPNDRN buffer ':1911' is permanently disabled +Warning: TRI or OPNDRN buffer ':1912' is permanently disabled +Warning: TRI or OPNDRN buffer ':1908' is permanently disabled +Warning: TRI or OPNDRN buffer ':1907' is permanently disabled +Warning: TRI or OPNDRN buffer ':1909' is permanently disabled +Warning: TRI or OPNDRN buffer ':1910' is permanently disabled +Warning: TRI or OPNDRN buffer ':1914' is permanently disabled +Warning: TRI or OPNDRN buffer ':1913' is permanently disabled +Warning: TRI or OPNDRN buffer ':1905' is permanently disabled +Warning: TRI or OPNDRN buffer ':2016' is permanently disabled +Warning: TRI or OPNDRN buffer ':2017' is permanently disabled +Warning: TRI or OPNDRN buffer ':1906' is permanently disabled +Warning: TRI or OPNDRN buffer ':1904' is permanently disabled +Warning: TRI or OPNDRN buffer ':1915' is permanently disabled +Warning: TRI or OPNDRN buffer ':1903' is permanently disabled +Warning: TRI or OPNDRN buffer ':1902' is permanently disabled +Warning: TRI or OPNDRN buffer ':1901' is permanently disabled +Warning: TRI or OPNDRN buffer ':2010' is permanently disabled +Warning: TRI or OPNDRN buffer ':2004' is permanently disabled +Warning: TRI or OPNDRN buffer ':1998' is permanently disabled +Warning: TRI or OPNDRN buffer ':1992' is permanently disabled +Warning: TRI or OPNDRN buffer ':1986' is permanently disabled +Warning: TRI or OPNDRN buffer ':1980' is permanently disabled +Warning: TRI or OPNDRN buffer ':1974' is permanently disabled +Warning: TRI or OPNDRN buffer ':1968' is permanently disabled +Warning: TRI or OPNDRN buffer ':2011' is permanently disabled +Warning: TRI or OPNDRN buffer ':2005' is permanently disabled +Warning: TRI or OPNDRN buffer ':1999' is permanently disabled +Warning: TRI or OPNDRN buffer ':1993' is permanently disabled +Warning: TRI or OPNDRN buffer ':1987' is permanently disabled +Warning: TRI or OPNDRN buffer ':1981' is permanently disabled +Warning: TRI or OPNDRN buffer ':1975' is permanently disabled +Warning: TRI or OPNDRN buffer ':1969' is permanently disabled +Warning: TRI or OPNDRN buffer ':2012' is permanently disabled +Warning: TRI or OPNDRN buffer ':2006' is permanently disabled +Warning: TRI or OPNDRN buffer ':2000' is permanently disabled +Warning: TRI or OPNDRN buffer ':1994' is permanently disabled +Warning: TRI or OPNDRN buffer ':1988' is permanently disabled +Warning: TRI or OPNDRN buffer ':1982' is permanently disabled +Warning: TRI or OPNDRN buffer ':1976' is permanently disabled +Warning: TRI or OPNDRN buffer ':1970' is permanently disabled +Warning: TRI or OPNDRN buffer ':1900' is permanently disabled +Warning: TRI or OPNDRN buffer ':1911' is permanently disabled +Warning: TRI or OPNDRN buffer ':1912' is permanently disabled +Warning: TRI or OPNDRN buffer ':1908' is permanently disabled +Warning: TRI or OPNDRN buffer ':1907' is permanently disabled +Warning: TRI or OPNDRN buffer ':1909' is permanently disabled +Warning: TRI or OPNDRN buffer ':1910' is permanently disabled +Warning: TRI or OPNDRN buffer ':1914' is permanently disabled +Warning: TRI or OPNDRN buffer ':1913' is permanently disabled +Warning: TRI or OPNDRN buffer ':1905' is permanently disabled +Warning: TRI or OPNDRN buffer ':2016' is permanently disabled +Warning: TRI or OPNDRN buffer ':2017' is permanently disabled +Warning: TRI or OPNDRN buffer ':1906' is permanently disabled +Warning: TRI or OPNDRN buffer ':1904' is permanently disabled +Warning: TRI or OPNDRN buffer ':1915' is permanently disabled +Warning: TRI or OPNDRN buffer ':1903' is permanently disabled +Warning: TRI or OPNDRN buffer ':1902' is permanently disabled +Warning: TRI or OPNDRN buffer ':1901' is permanently disabled +Warning: TRI or OPNDRN buffer ':2010' is permanently disabled +Warning: TRI or OPNDRN buffer ':2004' is permanently disabled +Warning: TRI or OPNDRN buffer ':1998' is permanently disabled +Warning: TRI or OPNDRN buffer ':1992' is permanently disabled +Warning: TRI or OPNDRN buffer ':1986' is permanently disabled +Warning: TRI or OPNDRN buffer ':1980' is permanently disabled +Warning: TRI or OPNDRN buffer ':1974' is permanently disabled +Warning: TRI or OPNDRN buffer ':1968' is permanently disabled +Warning: TRI or OPNDRN buffer ':2011' is permanently disabled +Warning: TRI or OPNDRN buffer ':2005' is permanently disabled +Warning: TRI or OPNDRN buffer ':1999' is permanently disabled +Warning: TRI or OPNDRN buffer ':1993' is permanently disabled +Warning: TRI or OPNDRN buffer ':1987' is permanently disabled +Warning: TRI or OPNDRN buffer ':1981' is permanently disabled +Warning: TRI or OPNDRN buffer ':1975' is permanently disabled +Warning: TRI or OPNDRN buffer ':1969' is permanently disabled +Warning: TRI or OPNDRN buffer ':2012' is permanently disabled +Warning: TRI or OPNDRN buffer ':2006' is permanently disabled +Warning: TRI or OPNDRN buffer ':2000' is permanently disabled +Warning: TRI or OPNDRN buffer ':1994' is permanently disabled +Warning: TRI or OPNDRN buffer ':1988' is permanently disabled +Warning: TRI or OPNDRN buffer ':1982' is permanently disabled +Warning: TRI or OPNDRN buffer ':1976' is permanently disabled +Warning: TRI or OPNDRN buffer ':1970' is permanently disabled +Warning: Flipflop ':2150' stuck at VCC +Warning: No Clock transition on flipflop ':1921' +Warning: Ignored unnecessary INPUT pin 'MS_MOUSE' + + +Project Information c:\prj\sprinter\firmware\97\flex\sprint08.rpt + +** EMBEDDED ARRAYS ** + + +|lpm_ram_dq:161|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "PGA_INI4.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:161|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:161|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:161|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:161|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:161|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:161|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:161|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:161|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:195|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "PGA_INI4.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:195|altram:sram|segment0_7, + |lpm_ram_dq:195|altram:sram|segment0_6, + |lpm_ram_dq:195|altram:sram|segment0_5, + |lpm_ram_dq:195|altram:sram|segment0_4, + |lpm_ram_dq:195|altram:sram|segment0_3, + |lpm_ram_dq:195|altram:sram|segment0_2, + |lpm_ram_dq:195|altram:sram|segment0_1, + |lpm_ram_dq:195|altram:sram|segment0_0 +); + + + +|lpm_ram_dq:229|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + ) + OF SEGMENTS ( + |lpm_ram_dq:229|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:229|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:229|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:229|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:229|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:229|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:229|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:229|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:260|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + ) + OF SEGMENTS ( + |lpm_ram_dq:260|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:260|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:260|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:260|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:260|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:260|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:260|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:260|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:291|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "KBD_INI2.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:291|altram:sram|segment0_7, + |lpm_ram_dq:291|altram:sram|segment0_6, + |lpm_ram_dq:291|altram:sram|segment0_5, + |lpm_ram_dq:291|altram:sram|segment0_4, + |lpm_ram_dq:291|altram:sram|segment0_3, + |lpm_ram_dq:291|altram:sram|segment0_2, + |lpm_ram_dq:291|altram:sram|segment0_1, + |lpm_ram_dq:291|altram:sram|segment0_0 +); + + + +|lpm_ram_dq:323|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "SND_INI.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:323|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:323|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:323|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:323|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:323|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:323|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:323|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:323|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:355|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1; + file = "AY.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:355|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:355|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:355|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:355|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:355|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:355|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:355|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:355|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:386|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0#MEM_REG_DATAOUT_CLK1; + file = "AY.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:386|altram:sram|segment0_7, + |lpm_ram_dq:386|altram:sram|segment0_6, + |lpm_ram_dq:386|altram:sram|segment0_5, + |lpm_ram_dq:386|altram:sram|segment0_4, + |lpm_ram_dq:386|altram:sram|segment0_3, + |lpm_ram_dq:386|altram:sram|segment0_2, + |lpm_ram_dq:386|altram:sram|segment0_1, + |lpm_ram_dq:386|altram:sram|segment0_0 +); + + + +|lpm_ram_dq:417|altram:sram|content: MEMORY ( + width = 8; + depth = 4; + segmentsize = 4; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "COVOX.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:417|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:417|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:417|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:417|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:417|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:417|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:417|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:417|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:443|altram:sram|content: MEMORY ( + width = 8; + depth = 4; + segmentsize = 4; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "COVOX.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:443|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:443|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:443|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:443|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:443|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:443|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:443|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:443|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:469|altram:sram|content: MEMORY ( + width = 8; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "COVOX.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:469|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:469|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:469|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:469|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:469|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:469|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:469|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:469|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + +|lpm_ram_dq:559|altram:sram|content: MEMORY ( + width = 16; + depth = 256; + segmentsize = 256; + mode = MEM_INITIALIZED#MEM_REG_DATAIN_CLK0#MEM_REG_WADDR_CLK0#MEM_REG_WCTRL_CLK0; + file = "FORTH.MIF"; + ) + OF SEGMENTS ( + |lpm_ram_dq:559|altram:sram|segment0_15, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_14, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_13, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_12, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_11, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_10, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_9, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_8, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_7, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_6, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_5, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_4, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_3, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_2, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_1, /* This segment is removed by logic synthesis */ + |lpm_ram_dq:559|altram:sram|segment0_0 /* This segment is removed by logic synthesis */ +); + + + + +Project Information c:\prj\sprinter\firmware\97\flex\sprint08.rpt + +** FILE HIERARCHY ** + + + +|lpm_ram_dq:161| +|lpm_ram_dq:161|altram:sram| +|lpm_ram_dq:195| +|lpm_ram_dq:195|altram:sram| +|lpm_ram_dq:229| +|lpm_ram_dq:229|altram:sram| +|lpm_ram_dq:260| +|lpm_ram_dq:260|altram:sram| +|lpm_ram_dq:291| +|lpm_ram_dq:291|altram:sram| +|lpm_ram_dq:323| +|lpm_ram_dq:323|altram:sram| +|lpm_ram_dq:355| +|lpm_ram_dq:355|altram:sram| +|lpm_ram_dq:386| +|lpm_ram_dq:386|altram:sram| +|lpm_ram_dq:417| +|lpm_ram_dq:417|altram:sram| +|lpm_ram_dq:443| +|lpm_ram_dq:443|altram:sram| +|lpm_ram_dq:469| +|lpm_ram_dq:469|altram:sram| +|lpm_add_sub:501| +|lpm_add_sub:501|addcore:adder| +|lpm_add_sub:501|altshift:result_ext_latency_ffs| +|lpm_add_sub:501|altshift:carry_ext_latency_ffs| +|lpm_add_sub:501|altshift:oflow_ext_latency_ffs| +|lpm_ram_dq:559| +|lpm_ram_dq:559|altram:sram| +|lpm_add_sub:607| +|lpm_add_sub:607|addcore:adder| +|lpm_add_sub:607|altshift:result_ext_latency_ffs| +|lpm_add_sub:607|altshift:carry_ext_latency_ffs| +|lpm_add_sub:607|altshift:oflow_ext_latency_ffs| + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +***** Logic for device 'sprint08' compiled without errors. + + + + +Device: EPF10K10QC208-3 + +FLEX 10K Configuration Scheme: Passive Serial + +Device Options: + User-Supplied Start-Up Clock = OFF + Auto-Restart Configuration on Frame Error = OFF + Release Clears Before Tri-States = OFF + Enable Chip_Wide Reset = OFF + Enable Chip-Wide Output Enable = OFF + Enable INIT_DONE Output = OFF + JTAG User Code = 7f + MultiVolt I/O = OFF + + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** ERROR SUMMARY ** + +Info: Chip 'sprint08' in device 'EPF10K10QC208-3' has less than 20% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device +Info: Chip 'sprint08' in device 'EPF10K10QC208-3' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device + + T + U R + K R E + S B B G V S S S + V G C I V C G D O N C V E G V N N V V V / + _ / V S N L N M C A V V V V N _ _ D T C V C R V V V N _ D D C _ _ W + W V I A I D K V C X C S D D D D D D L I / G / I A D C V D D D M / D W _ V A _ C W W X A V V V + D R A A N 1 N I A A Z A _ A I _ 2 0 0 0 I A E N R 4 W N 1 1 I E 3 0 3 D W I R R A 1 R I R R A I D A A A + 2 0 2 5 T 3 C O 7 3 1 4 H 1 O 1 2 2 5 1 O T D T D 2 R T 4 6 O D 6 3 0 3 E O 3 0 5 3 1 O 2 1 2 T 6 3 6 0 + ----------------------------------------------------------------------------------------------------------_ + / 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_ + / 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 | + #TCK | 1 156 | ^DATA0 +^CONF_DONE | 2 155 | ^DCLK + ^nCEO | 3 154 | ^nCE + #TDO | 4 153 | #TDI + VCCIO | 5 152 | GNDIO + VCCINT | 6 151 | GNDINT + N.C. | 7 150 | VD17 + N.C. | 8 149 | D4 + N.C. | 9 148 | XA0 + VD31 | 10 147 | VD32 + VD21 | 11 146 | VCCIO + VD15 | 12 145 | VCCINT + VD11 | 13 144 | VD27 + N.C. | 14 143 | VD35 + N.C. | 15 142 | SND_L0 + VA8 | 16 141 | VD37 + VD14 | 17 140 | N.C. + VD25 | 18 139 | N.C. + VA11 | 19 138 | VCCIO + GNDIO | 20 137 | VCCINT + GNDINT | 21 136 | MD6 + VCCIO | 22 135 | CAS_2 + VCCINT | 23 134 | VD00 + MXA6 | 24 133 | VD07 + D5 | 25 132 | VD06 + MD5 | 26 131 | RAS_0 + MXA10 | 27 EPF10K10QC208-3 130 | GNDIO + CAS_0 | 28 129 | GNDINT + BEEPER | 29 128 | A6 + MD1 | 30 127 | A1 + MD2 | 31 126 | N.C. + GNDIO | 32 125 | N.C. + GNDINT | 33 124 | GNDIO + VCCIO | 34 123 | GNDINT + VCCINT | 35 122 | MD0 + N.C. | 36 121 | KBD_CLK + N.C. | 37 120 | MD7 + A10 | 38 119 | D3 + A9 | 39 118 | VCCIO + A8 | 40 117 | VCCINT + A11 | 41 116 | VD13 + VCCIO | 42 115 | VD23 + VCCINT | 43 114 | N.C. + VA1 | 44 113 | N.C. + D0 | 45 112 | VA7 + A4 | 46 111 | VD20 + VA15 | 47 110 | VCCIO + GNDIO | 48 109 | VCCINT + GNDINT | 49 108 | ^MSEL0 + #TMS | 50 107 | ^MSEL1 + #TRST | 51 106 | VCCINT + ^nSTATUS | 52 105 | ^nCONFIG + | 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _| + \ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 | + \----------------------------------------------------------------------------------------------------------- + M M C T V V G M V M D M A V C V M / M G V M V V V / / / G G V V / V A V V X G R D / A A V V T X M S V V + X X L A A A N X A X 1 X 2 C A D X R X N D X D C C I M M N N D C N _ 0 D D A N A 7 R 1 1 _ C A A D N A D + A A K P 1 1 D A 9 A A C S 1 A E A D 0 A 2 C C O 1 R D D 2 C M C 1 3 C D S F 2 5 C C P 1 4 D 1 3 + 7 9 _ E 4 2 I 0 8 3 I _ 2 4 S 5 I 4 2 4 I I I I 6 I I S 0 3 S I _ S I E _ 0 4 + P _ O O 3 E O N N N N O 1 O 1 0 O _ L + I O T T T T T I 1 + X U N + T + + + + +N.C. = No Connect. This pin has no internal connection to the device. +VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts). +VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts). +GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. +GNDIO = Dedicated ground pin, which MUST be connected to GND. +RESERVED = Unused I/O pin, which MUST be left unconnected. + +^ = Dedicated configuration pin. ++ = Reserved configuration pin, which is tri-stated during user mode. +* = Reserved configuration pin, which drives out in user mode. +PDn = Power Down pin. +@ = Special-purpose pin. +# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. +& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** RESOURCE USAGE ** + +Logic Column Row +Array Interconnect Interconnect Clears/ External +Block Logic Cells Driven Driven Clocks Presets Interconnect +A1 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 14/22( 63%) +A2 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 0/2 10/22( 45%) +A3 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 1/2 2/2 11/22( 50%) +A4 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 11/22( 50%) +A5 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 1/2 11/22( 50%) +A6 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 10/22( 45%) +A7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 11/22( 50%) +A8 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 2/2 0/2 11/22( 50%) +A9 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 7/22( 31%) +A10 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 9/22( 40%) +A11 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 11/22( 50%) +A12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 0/2 13/22( 59%) +A13 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 3/22( 13%) +A14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 10/22( 45%) +A15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 2/2 9/22( 40%) +A16 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 5/22( 22%) +A17 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 2/2 1/2 8/22( 36%) +A18 5/ 8( 62%) 3/ 8( 37%) 4/ 8( 50%) 2/2 0/2 5/22( 22%) +A19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 12/22( 54%) +A20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 8/22( 36%) +A21 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 10/22( 45%) +A22 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 11/22( 50%) +A23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 5/22( 22%) +A24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 11/22( 50%) +B1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 1/2 15/22( 68%) +B2 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 1/2 0/2 12/22( 54%) +B3 8/ 8(100%) 4/ 8( 50%) 3/ 8( 37%) 1/2 0/2 11/22( 50%) +B4 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 2/2 2/2 13/22( 59%) +B5 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 16/22( 72%) +B6 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 2/2 1/2 13/22( 59%) +B7 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 10/22( 45%) +B8 8/ 8(100%) 2/ 8( 25%) 6/ 8( 75%) 2/2 1/2 11/22( 50%) +B9 8/ 8(100%) 4/ 8( 50%) 8/ 8(100%) 1/2 1/2 13/22( 59%) +B10 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 2/2 13/22( 59%) +B11 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 2/2 0/2 3/22( 13%) +B12 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 13/22( 59%) +B13 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 2/2 1/2 15/22( 68%) +B14 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 2/2 0/2 13/22( 59%) +B15 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 10/22( 45%) +B16 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 2/2 12/22( 54%) +B17 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 2/2 0/2 11/22( 50%) +B18 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 8/22( 36%) +B19 8/ 8(100%) 4/ 8( 50%) 2/ 8( 25%) 2/2 1/2 15/22( 68%) +B20 8/ 8(100%) 5/ 8( 62%) 6/ 8( 75%) 2/2 1/2 3/22( 13%) +B21 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 11/22( 50%) +B22 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 2/2 1/2 13/22( 59%) +B23 8/ 8(100%) 5/ 8( 62%) 1/ 8( 12%) 2/2 2/2 11/22( 50%) +B24 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 5/22( 22%) +C1 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 2/2 0/2 8/22( 36%) +C2 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 1/2 0/2 10/22( 45%) +C3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 2/2 1/2 7/22( 31%) +C4 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 2/2 0/2 14/22( 63%) +C5 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 2/2 2/2 11/22( 50%) +C6 8/ 8(100%) 0/ 8( 0%) 8/ 8(100%) 2/2 0/2 13/22( 59%) +C7 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 14/22( 63%) +C8 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 2/2 12/22( 54%) +C9 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 10/22( 45%) +C10 8/ 8(100%) 5/ 8( 62%) 3/ 8( 37%) 1/2 0/2 3/22( 13%) +C11 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 2/2 0/2 6/22( 27%) +C12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 2/2 1/2 11/22( 50%) +C13 7/ 8( 87%) 6/ 8( 75%) 4/ 8( 50%) 2/2 0/2 9/22( 40%) +C14 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 2/22( 9%) +C15 8/ 8(100%) 6/ 8( 75%) 3/ 8( 37%) 2/2 1/2 6/22( 27%) +C16 7/ 8( 87%) 3/ 8( 37%) 3/ 8( 37%) 2/2 1/2 14/22( 63%) +C17 8/ 8(100%) 5/ 8( 62%) 4/ 8( 50%) 2/2 0/2 11/22( 50%) +C18 6/ 8( 75%) 3/ 8( 37%) 4/ 8( 50%) 2/2 0/2 4/22( 18%) +C19 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 2/2 0/2 5/22( 22%) +C20 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 14/22( 63%) +C21 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 2/2 0/2 6/22( 27%) +C22 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 2/2 1/2 11/22( 50%) +C23 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 2/2 0/2 14/22( 63%) +C24 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 14/22( 63%) + + +Embedded Column Row +Array Embedded Interconnect Interconnect Read/ External +Block Cells Driven Driven Clocks Write Interconnect +A25 8/8 (100%) 7/8 ( 87%) 8/8 (100%) 1/2 2/2 18/22( 81%) +B25 8/8 (100%) 8/8 (100%) 4/8 ( 50%) 1/2 2/2 17/22( 77%) +C25 8/8 (100%) 0/8 ( 0%) 8/8 (100%) 1/2 2/2 15/22( 68%) + + +Total dedicated input pins used: 6/6 (100%) +Total I/O pins used: 127/128 ( 99%) +Total logic cells used: 567/576 ( 98%) +Total embedded cells used: 24/24 (100%) +Total EABs used: 3/3 (100%) +Average fan-in: 2.66/4 ( 66%) +Total fan-in: 1510/2304 ( 65%) + +Total input pins required: 8 +Total input I/O cell registers required: 0 +Total output pins required: 55 +Total output I/O cell registers required: 0 +Total buried I/O cell registers required: 0 +Total bidirectional pins required: 70 +Total reserved pins required 0 +Total logic cells required: 567 +Total flipflops required: 332 +Total packed registers required: 0 +Total logic cells in carry chains: 0 +Total number of carry chains: 0 +Total logic cells in cascade chains: 0 +Total number of cascade chains: 0 +Total single-pin Clock Enables required: 0 +Total single-pin Output Enables required: 0 + +Synthesized logic cells: 85/ 576 ( 14%) + +Logic Cell and Embedded Cell Counts + +Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC) + A: 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 5 8 8 8 8 8 8 189/8 + B: 8 8 8 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 191/8 + C: 8 8 8 8 8 8 8 8 8 8 8 8 8 7 8 8 7 8 6 8 8 8 7 8 8 187/8 + +Total: 24 24 24 23 24 24 24 24 24 24 24 24 24 23 24 24 23 24 19 24 24 24 23 24 24 567/24 + + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** INPUTS ** + + Fan-In Fan-Out + Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name + 87 - - - 10 BIDIR 0 0 0 2 A0 + 127 - - B -- BIDIR 0 0 0 1 A1 + 65 - - - 18 BIDIR 0 0 0 1 A2 + 199 - - - 20 BIDIR 0 0 0 1 A3 + 46 - - C -- BIDIR 0 0 0 1 A4 + 205 - - - 23 BIDIR 0 0 0 1 A5 + 128 - - B -- BIDIR 0 0 0 2 A6 + 200 - - - 20 BIDIR 0 0 0 1 A7 + 40 - - C -- BIDIR 0 0 0 3 A8 + 39 - - C -- BIDIR 0 0 0 3 A9 + 38 - - C -- BIDIR 0 0 0 3 A10 + 41 - - C -- BIDIR 0 0 0 3 A11 + 95 - - - 06 BIDIR 0 0 0 3 A12 + 167 - - - 06 BIDIR 0 0 0 4 A13 + 180 - - - 12 BIDIR 0 0 0 10 A14 + 96 - - - 05 BIDIR 0 0 0 11 A15 + 45 - - C -- BIDIR 0 1 0 16 D0 + 63 - - - 19 BIDIR 0 1 0 16 D1 + 208 - - - 24 BIDIR 0 1 0 14 D2 + 119 - - C -- BIDIR 0 1 0 13 D3 + 149 - - A -- BIDIR 0 1 0 12 D4 + 25 - - B -- BIDIR 0 1 0 9 D5 + 160 - - - 02 BIDIR 0 1 0 8 D6 + 93 - - - 07 BIDIR 0 1 0 8 D7 + 204 - - - 22 OPNDRN 0 1 0 0 /INT + 78 - - - -- INPUT G 0 0 0 43 /IO + 121 - - C -- BIDIR 0 0 0 1 KBD_CLK + 187 - - - 13 BIDIR 0 0 0 1 KBD_DAT + 122 - - C -- BIDIR 0 1 0 1 MD0 + 30 - - B -- BIDIR 0 1 0 1 MD1 + 31 - - B -- BIDIR 0 1 0 1 MD2 + 173 - - - 09 BIDIR 0 1 0 1 MD3 + 101 - - - 03 BIDIR 0 1 0 2 MD4 + 26 - - B -- BIDIR 0 1 0 2 MD5 + 136 - - B -- BIDIR 0 1 0 2 MD6 + 120 - - C -- BIDIR 0 1 0 2 MD7 + 80 - - - -- INPUT G 0 0 0 8 /MR + 79 - - - -- INPUT G 0 0 0 5 /M1 + 85 - - - 11 OPNDRN 0 0 0 0 /NMI + 184 - - - -- INPUT 0 0 0 5 /RD + 70 - - - 15 OPNDRN 0 1 0 22 /RESET + 94 - - - 07 INPUT 0 0 0 2 /RF + 99 - - - 04 INPUT 0 0 0 1 TAPE_IN + 183 - - - -- INPUT G 0 0 0 8 TG42 + 134 - - B -- BIDIR 0 1 0 2 VD00 + 189 - - - 14 BIDIR 0 1 0 2 VD01 + 191 - - - 15 BIDIR 0 1 0 2 VD02 + 175 - - - 10 BIDIR 0 1 0 2 VD03 + 73 - - - 14 BIDIR 0 1 0 2 VD04 + 190 - - - 15 BIDIR 0 1 0 2 VD05 + 132 - - B -- BIDIR 0 1 0 2 VD06 + 133 - - B -- BIDIR 0 1 0 2 VD07 + 88 - - - 10 BIDIR 0 1 0 0 VD10 + 13 - - A -- BIDIR 0 1 0 0 VD11 + 68 - - - 16 BIDIR 0 1 0 0 VD12 + 116 - - C -- BIDIR 0 1 0 0 VD13 + 17 - - A -- BIDIR 0 1 0 0 VD14 + 12 - - A -- BIDIR 0 1 0 0 VD15 + 179 - - - 12 BIDIR 0 1 0 0 VD16 + 150 - - A -- BIDIR 0 1 0 0 VD17 + 111 - - C -- BIDIR 0 1 0 0 VD20 + 11 - - A -- BIDIR 0 1 0 0 VD21 + 192 - - - 16 BIDIR 0 1 0 0 VD22 + 115 - - C -- BIDIR 0 1 0 0 VD23 + 75 - - - 13 BIDIR 0 1 0 0 VD24 + 18 - - A -- BIDIR 0 1 0 0 VD25 + 83 - - - 12 BIDIR 0 1 0 0 VD26 + 144 - - A -- BIDIR 0 1 0 0 VD27 + 174 - - - 09 BIDIR 0 1 0 0 VD30 + 10 - - A -- BIDIR 0 1 0 0 VD31 + 147 - - A -- BIDIR 0 1 0 0 VD32 + 89 - - - 09 BIDIR 0 1 0 0 VD33 + 104 - - - 01 BIDIR 0 1 0 0 VD34 + 143 - - A -- BIDIR 0 1 0 0 VD35 + 176 - - - 11 BIDIR 0 1 0 0 VD36 + 141 - - A -- BIDIR 0 1 0 0 VD37 + 161 - - - 03 OPNDRN 0 1 0 0 /WAIT + 182 - - - -- INPUT 0 0 0 7 /WR + + +Code: + +s = Synthesized pin or logic cell ++ = Synchronous flipflop +/ = Slow slew-rate output +! = NOT gate push-back +r = Fitter-inserted logic cell +@ = Uses single-pin Clock Enable +& = Uses single-pin Output Enable +G = Global Source. Fan-out destinations counted here do not include destinations +that are driven using global routing resources. Refer to the Auto Global Signals, +Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals +Sections of this Report File for information on which signals' fan-outs are used as +Clock, Clear, Preset, Output Enable, and synchronous Load signals. + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** OUTPUTS ** + + Fed By Fed By Fan-In Fan-Out + Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name + 87 - - - 10 TRI 0 0 0 2 A0 + 127 - - B -- TRI 0 0 0 1 A1 + 65 - - - 18 TRI 0 0 0 1 A2 + 199 - - - 20 TRI 0 0 0 1 A3 + 46 - - C -- TRI 0 0 0 1 A4 + 205 - - - 23 TRI 0 0 0 1 A5 + 128 - - B -- TRI 0 0 0 2 A6 + 200 - - - 20 TRI 0 0 0 1 A7 + 40 - - C -- TRI 0 0 0 3 A8 + 39 - - C -- TRI 0 0 0 3 A9 + 38 - - C -- TRI 0 0 0 3 A10 + 41 - - C -- TRI 0 0 0 3 A11 + 95 - - - 06 TRI 0 0 0 3 A12 + 167 - - - 06 TRI 0 0 0 4 A13 + 180 - - - 12 TRI 0 0 0 10 A14 + 96 - - - 05 TRI 0 0 0 11 A15 + 29 - - B -- OUTPUT 0 1 0 0 BEEPER + 28 - - B -- OUTPUT 0 1 0 0 CAS_0 + 193 - - - 17 OUTPUT 0 1 0 0 CAS_1 + 135 - - B -- OUTPUT 0 1 0 0 CAS_2 + 67 - - - 17 OUTPUT 0 1 0 0 CAS_3 + 55 - - - 23 OUTPUT 0 1 0 0 CLK_PIX + 198 - - - 19 OUTPUT 0 1 0 0 CLKZ1 + 45 - - C -- TRI 0 1 0 16 D0 + 63 - - - 19 TRI 0 1 0 16 D1 + 208 - - - 24 TRI 0 1 0 14 D2 + 119 - - C -- TRI 0 1 0 13 D3 + 149 - - A -- TRI 0 1 0 12 D4 + 25 - - B -- TRI 0 1 0 9 D5 + 160 - - - 02 TRI 0 1 0 8 D6 + 93 - - - 07 TRI 0 1 0 8 D7 + 204 - - - 22 OPNDRN 0 1 0 0 /INT + 121 - - C -- TRI 0 0 0 1 KBD_CLK + 187 - - - 13 TRI 0 0 0 1 KBD_DAT + 122 - - C -- TRI 0 1 0 1 MD0 + 30 - - B -- TRI 0 1 0 1 MD1 + 31 - - B -- TRI 0 1 0 1 MD2 + 173 - - - 09 TRI 0 1 0 1 MD3 + 101 - - - 03 TRI 0 1 0 2 MD4 + 26 - - B -- TRI 0 1 0 2 MD5 + 136 - - B -- TRI 0 1 0 2 MD6 + 120 - - C -- TRI 0 1 0 2 MD7 + 60 - - - 21 OUTPUT 0 1 0 0 MXA0 + 195 - - - 17 OUTPUT 0 1 0 0 MXA1 + 74 - - - 13 OUTPUT 0 1 0 0 MXA2 + 64 - - - 18 OUTPUT 0 1 0 0 MXA3 + 69 - - - 16 OUTPUT 0 1 0 0 MXA4 + 71 - - - 14 OUTPUT 0 1 0 0 MXA5 + 24 - - B -- OUTPUT 0 1 0 0 MXA6 + 53 - - - 24 OUTPUT 0 1 0 0 MXA7 + 62 - - - 19 OUTPUT 0 1 0 0 MXA8 + 54 - - - 24 OUTPUT 0 1 0 0 MXA9 + 27 - - B -- OUTPUT 0 1 0 0 MXA10 + 85 - - - 11 OPNDRN 0 0 0 0 /NMI + 131 - - B -- OUTPUT 0 1 0 0 RAS_0 + 92 - - - 08 OUTPUT 0 1 0 0 RAS_1 + 70 - - - 15 OPNDRN 0 1 0 22 /RESET + 202 - - - 21 OUTPUT 0 1 0 0 SINC + 196 - - - 18 OUTPUT 0 1 0 0 SINC_H + 142 - - A -- OUTPUT 0 1 0 0 SND_L0 + 102 - - - 02 OUTPUT 0 0 0 0 SND_L1 + 169 - - - 07 OUTPUT 0 1 0 0 SND_R0 + 166 - - - 05 OUTPUT 0 0 0 0 SND_R1 + 56 - - - 22 OUTPUT 0 1 0 0 TAPE_OUT + 186 - - - 13 OUTPUT 0 1 0 0 TURBO_LED + 157 - - - 01 OUTPUT 0 1 0 0 VA0 + 44 - - C -- OUTPUT 0 1 0 0 VA1 + 206 - - - 23 OUTPUT 0 1 0 0 VA2 + 159 - - - 02 OUTPUT 0 1 0 0 VA3 + 197 - - - 18 OUTPUT 0 1 0 0 VA4 + 168 - - - 06 OUTPUT 0 1 0 0 VA5 + 158 - - - 01 OUTPUT 0 1 0 0 VA6 + 112 - - C -- OUTPUT 0 1 0 0 VA7 + 16 - - A -- OUTPUT 0 1 0 0 VA8 + 61 - - - 20 OUTPUT 0 1 0 0 VA9 + 103 - - - 01 OUTPUT 0 1 0 0 VA10 + 19 - - A -- OUTPUT 0 1 0 0 VA11 + 58 - - - 21 OUTPUT 0 1 0 0 VA12 + 203 - - - 21 OUTPUT 0 1 0 0 VA13 + 57 - - - 22 OUTPUT 0 1 0 0 VA14 + 47 - - C -- OUTPUT 0 1 0 0 VA15 + 97 - - - 05 OUTPUT 0 0 0 0 V_CS0 + 86 - - - 11 OUTPUT 0 0 0 0 V_CS1 + 134 - - B -- TRI 0 1 0 2 VD00 + 189 - - - 14 TRI 0 1 0 2 VD01 + 191 - - - 15 TRI 0 1 0 2 VD02 + 175 - - - 10 TRI 0 1 0 2 VD03 + 73 - - - 14 TRI 0 1 0 2 VD04 + 190 - - - 15 TRI 0 1 0 2 VD05 + 132 - - B -- TRI 0 1 0 2 VD06 + 133 - - B -- TRI 0 1 0 2 VD07 + 88 - - - 10 TRI 0 1 0 0 VD10 + 13 - - A -- TRI 0 1 0 0 VD11 + 68 - - - 16 TRI 0 1 0 0 VD12 + 116 - - C -- TRI 0 1 0 0 VD13 + 17 - - A -- TRI 0 1 0 0 VD14 + 12 - - A -- TRI 0 1 0 0 VD15 + 179 - - - 12 TRI 0 1 0 0 VD16 + 150 - - A -- TRI 0 1 0 0 VD17 + 111 - - C -- TRI 0 1 0 0 VD20 + 11 - - A -- TRI 0 1 0 0 VD21 + 192 - - - 16 TRI 0 1 0 0 VD22 + 115 - - C -- TRI 0 1 0 0 VD23 + 75 - - - 13 TRI 0 1 0 0 VD24 + 18 - - A -- TRI 0 1 0 0 VD25 + 83 - - - 12 TRI 0 1 0 0 VD26 + 144 - - A -- TRI 0 1 0 0 VD27 + 174 - - - 09 TRI 0 1 0 0 VD30 + 10 - - A -- TRI 0 1 0 0 VD31 + 147 - - A -- TRI 0 1 0 0 VD32 + 89 - - - 09 TRI 0 1 0 0 VD33 + 104 - - - 01 TRI 0 1 0 0 VD34 + 143 - - A -- TRI 0 1 0 0 VD35 + 176 - - - 11 TRI 0 1 0 0 VD36 + 141 - - A -- TRI 0 1 0 0 VD37 + 207 - - - 24 OUTPUT 0 1 0 0 V_WR0 + 163 - - - 04 OUTPUT 0 0 0 0 V_WR1 + 164 - - - 04 OUTPUT 0 0 0 0 V_WR2 + 170 - - - 08 OUTPUT 0 0 0 0 V_WR3 + 161 - - - 03 OPNDRN 0 1 0 0 /WAIT + 172 - - - 08 OUTPUT 0 1 0 0 /WE + 90 - - - 08 OUTPUT 0 1 0 0 XACS + 148 - - A -- OUTPUT 0 1 0 0 XA0 + 100 - - - 03 OUTPUT 0 1 0 0 XA1 + 162 - - - 03 OUTPUT 0 1 0 0 XA2 + + +Code: + +s = Synthesized pin or logic cell ++ = Synchronous flipflop +/ = Slow slew-rate output +! = NOT gate push-back +r = Fitter-inserted logic cell +@ = Uses single-pin Clock Enable +& = Uses single-pin Output Enable + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** BURIED LOGIC ** + + Fan-In Fan-Out + IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name + - 8 - A 21 DFFE 0 2 0 2 AA0 + - 2 - B 17 DFFE 0 2 0 2 AA1 + - 5 - B 14 DFFE 0 2 0 2 AA2 + - 1 - C 13 DFFE 0 2 0 2 AA3 + - 4 - C 13 DFFE 0 2 0 2 AA4 + - 4 - B 14 DFFE 0 2 0 2 AA5 + - 4 - B 13 DFFE 0 2 0 2 AA6 + - 7 - C 23 DFFE 0 2 0 3 AA7 + - 8 - C 20 DFFE 0 2 0 2 AA8 + - 4 - C 24 DFFE 0 2 0 2 AA9 + - 8 - C 13 DFFE 0 2 0 5 AA10 + - 7 - C 13 DFFE 0 2 0 4 AA11 + - 5 - B 17 DFFE 0 2 0 2 AA12 + - 3 - B 14 DFFE 0 2 0 2 AA13 + - 4 - B 01 DFFE 0 4 0 1 AROM16 + - 5 - B 12 LCELL 0 4 0 1 AR0 + - 3 - B 12 LCELL 0 3 0 1 AR1 + - 5 - B 01 LCELL 0 3 0 1 AR2 + - 2 - B 01 LCELL 0 2 0 1 AR3 + - 4 - A 05 LCELL 0 2 0 1 AX128 + - 2 - A 01 DFFE 0 5 0 1 AY_AAX0 + - 2 - A 19 DFFE + 0 4 0 1 AY_AA0 + - 4 - A 19 DFFE + 0 4 0 1 AY_AA1 + - 5 - A 19 DFFE + 0 4 0 1 AY_AA2 + - 6 - A 19 DFFE + 0 4 0 1 AY_AA3 + - 3 - A 15 DFFE 0 3 0 4 AY_ABLK + - 8 - A 01 DFFE 0 2 0 2 AY_ADR0 + - 6 - A 04 DFFE 0 2 0 2 AY_ADR1 + - 3 - A 04 DFFE 0 2 0 2 AY_ADR2 + - 2 - A 04 DFFE 0 2 0 2 AY_ADR3 + - 1 - A 19 DFFE + 0 3 0 3 AY_AMP0 + - 8 - A 19 DFFE + 0 3 0 2 AY_AMP1 + - 3 - A 19 DFFE + 0 3 0 2 AY_AMP2 + - 7 - A 19 DFFE + 0 3 0 2 AY_AMP3 + - 6 - A 01 OR2 s 0 4 0 1 AY_AX0~1 + - 1 - A 01 OR2 0 3 0 8 AY_AX0 + - 8 - A 04 OR2 s 0 4 0 1 AY_AX1~1 + - 5 - A 04 OR2 0 3 0 8 AY_AX1 + - 1 - A 04 OR2 s 0 4 0 1 AY_AX2~1 + - 1 - A 22 OR2 0 3 0 8 AY_AX2 + - 4 - A 04 OR2 s 0 4 0 1 AY_AX3~1 + - 1 - A 02 OR2 0 3 0 8 AY_AX3 + - 3 - A 24 OR2 0 4 0 8 AY_AX4 + - 5 - A 08 AND2 0 3 0 8 AY_AX5 + - 6 - A 15 DFFE 0 3 0 1 AY_BBLK + - 2 - A 15 DFFE 0 4 0 4 AY_BINV + - 8 - A 11 DFFE + 0 4 0 2 AY_C + - 1 - B 20 DFFE + 0 1 0 26 AY_CCC0 + - 8 - A 10 DFFE + 0 1 0 29 AY_CCC1 + - 7 - B 11 DFFE + 0 1 0 48 AY_CCC2 + - 3 - B 21 DFFE + 0 1 0 2 AY_CCC3 + - 2 - B 24 DFFE + 0 1 0 2 AY_CCC4 + - 8 - A 24 DFFE + 0 1 0 3 AY_CCC5 + - 1 - A 24 DFFE + 0 1 0 3 AY_CCC6 + - 7 - A 08 DFFE + 0 1 0 4 AY_CCC7 + - 6 - A 24 DFFE + 0 1 0 7 AY_CCC8 + - 6 - A 09 DFFE + ! 0 3 0 10 AY_CX + - 1 - A 03 DFFE + 0 2 0 1 AY_DAT_WR + - 7 - A 10 DFFE + 0 3 0 4 AY_DAT0 + - 8 - A 02 DFFE + 0 3 0 4 AY_DAT1 + - 5 - A 02 DFFE + 0 4 0 4 AY_DAT2 + - 7 - A 02 DFFE + 0 3 0 4 AY_DAT3 + - 4 - A 11 DFFE + 0 3 0 7 AY_DAT4 + - 7 - A 11 DFFE + 0 4 0 3 AY_DAT5 + - 5 - A 11 DFFE + 0 3 0 2 AY_DAT6 + - 6 - A 11 DFFE + 0 4 0 2 AY_DAT7 + - 5 - C 23 DFFE + 0 2 0 1 AY_DD0 + - 5 - C 20 DFFE + 0 2 0 1 AY_DD1 + - 7 - C 24 DFFE + 0 2 0 1 AY_DD2 + - 8 - C 04 DFFE + 0 2 0 1 AY_DD3 + - 8 - A 08 DFFE + 0 2 0 1 AY_DD4 + - 7 - B 03 DFFE + 0 2 0 1 AY_DD5 + - 6 - B 02 DFFE + 0 2 0 1 AY_DD6 + - 7 - C 07 DFFE + 0 2 0 1 AY_DD7 + - 2 - A 10 OR2 0 4 0 1 AY_DI0 + - 2 - A 24 OR2 0 4 0 1 AY_DI1 + - 6 - A 12 OR2 0 4 0 1 AY_DI2 + - 2 - A 02 OR2 0 4 0 1 AY_DI3 + - 4 - A 01 OR2 0 4 0 1 AY_DI4 + - 2 - A 12 OR2 0 4 0 1 AY_DI5 + - 3 - A 01 OR2 0 4 0 1 AY_DI6 + - 1 - A 11 OR2 0 4 0 1 AY_DI7 + - 7 - B 16 DFFE ! 0 5 0 6 AY_D_WR + - 7 - A 17 DFFE 0 2 0 10 AY_F_RES + - 7 - A 15 DFFE 0 4 0 2 AY_GF0 + - 4 - A 15 DFFE 0 4 0 1 AY_GF1 + - 1 - A 15 DFFE 0 4 0 4 AY_GF2 + - 8 - A 15 DFFE 0 4 0 1 AY_GF3 + - 4 - A 22 DFFE + 0 4 0 2 AY_OUTS1 + - 7 - A 07 DFFE + 0 4 0 2 AY_OUTS2 + - 6 - A 07 DFFE + 0 4 0 2 AY_OUTS3 + - 3 - A 05 DFFE + 0 2 0 1 AY_OUT1 + - 2 - A 07 DFFE + 0 2 0 1 AY_OUT2 + - 1 - A 12 DFFE + 0 2 0 1 AY_OUT3 + - 5 - A 05 OR2 0 3 0 6 AY_Q + - 8 - A 07 OR2 s 0 4 0 1 AY_Q~1 + - 3 - A 21 DFFE + 0 2 0 1 AY_SHR + - 1 - A 17 DFFE + 0 2 0 4 AY_SH0 + - 8 - A 17 DFFE + 0 2 0 1 AY_SH1 + - 5 - A 17 DFFE + 0 2 0 1 AY_SH2 + - 4 - A 17 DFFE + 0 2 0 1 AY_SH3 + - 6 - A 17 DFFE + 0 2 0 2 AY_SH4 + - 6 - A 21 DFFE + 0 2 0 1 AY_SH5 + - 7 - A 21 DFFE + 0 2 0 1 AY_SH6 + - 4 - A 21 DFFE + 0 2 0 1 AY_SH7 + - 3 - A 23 DFFE + 0 3 0 3 AY_VAR + - 8 - A 23 DFFE + 0 4 0 3 AY_VA0 + - 1 - A 23 DFFE + 0 4 0 2 AY_VA1 + - 7 - A 23 DFFE + 0 3 0 2 AY_VA2 + - 5 - A 23 DFFE + 0 4 0 4 AY_VA3 + - 1 - A 10 OR2 0 4 0 8 AY_WR + - 3 - A 14 DFFE 0 2 0 1 AY_XXM0 + - 4 - A 14 DFFE 0 2 0 1 AY_XXM1 + - 6 - A 14 DFFE 0 2 0 1 AY_XXM2 + - 8 - A 14 DFFE 0 2 0 1 AY_XXM3 + - 4 - A 24 DFFE 0 2 0 1 AY_XXM4 + - 1 - A 14 DFFE 0 2 0 2 AY_XXM5 + - 2 - A 05 DFFE + 0 3 0 3 AY_XX0 + - 3 - A 20 DFFE + 0 4 0 2 AY_XX1 + - 8 - A 20 DFFE + 0 4 0 2 AY_XX2 + - 5 - A 20 DFFE + 0 4 0 2 AY_XX3 + - 1 - A 20 DFFE + 0 3 0 2 AY_XX4 + - 4 - A 20 DFFE + 0 4 0 1 AY_XX5 + - 8 - A 05 DFFE + 0 2 0 1 AY_X_0 + - 4 - A 07 DFFE + 0 2 0 1 AY_X_1 + - 7 - A 12 DFFE + 0 2 0 1 AY_X_2 + - 7 - A 05 DFFE + 0 2 0 1 AY_X_3 + - 3 - A 07 DFFE + 0 2 0 1 AY_X_4 + - 5 - A 12 DFFE + 0 2 0 1 AY_X_5 + - 8 - C 16 DFFE ! 0 4 0 8 BLANK + - 2 - B 10 LCELL 2 1 0 8 BLK_R + - 6 - C 18 DFFE 0 5 0 8 BORD + - 2 - B 22 DFFE 0 3 0 2 BRD0 + - 5 - B 22 DFFE 0 3 0 2 BRD1 + - 1 - B 22 DFFE 0 3 0 2 BRD2 + - 6 - B 22 DFFE 0 3 1 0 BRD3 + - 7 - B 24 DFFE 0 3 0 1 BRD4 + - 2 - B 14 DFFE + 0 2 0 8 CAS + - 3 - B 13 DFFE 0 4 0 1 CNF3 + - 8 - B 13 DFFE 0 4 0 1 CNF4 + - 7 - B 05 LCELL 0 4 0 2 CORRECT_1F + - 2 - C 19 DFFE 0 1 0 2 CTF0 + - 1 - C 19 DFFE 0 2 0 1 CTF1 + - 4 - C 19 DFFE 0 2 0 2 CTF2 + - 6 - C 19 DFFE 0 3 0 1 CTF3 + - 7 - C 19 DFFE 0 4 0 1 CTF4 + - 4 - A 18 DFFE 0 1 0 4 CTH0 + - 6 - A 18 DFFE 0 2 0 5 CTH1 + - 2 - A 18 DFFE 0 3 0 9 CTH2 + - 3 - C 17 DFFE 0 3 0 4 CTH3 + - 5 - C 17 DFFE 0 3 0 5 CTH4 + - 6 - C 17 DFFE 0 3 0 9 CTH5 + - 5 - C 15 DFFE 0 1 0 4 CTV0 + - 2 - C 15 DFFE 0 2 0 2 CTV1 + - 3 - C 15 DFFE 0 3 0 7 CTV2 + - 1 - C 21 DFFE 0 1 0 5 CTV3 + - 4 - C 21 DFFE 0 3 0 4 CTV4 + - 2 - C 21 DFFE 0 4 0 4 CTV5 + - 2 - C 18 DFFE 0 3 0 8 CTV6 + - 1 - C 18 DFFE 0 4 0 7 CTV7 + - 5 - C 18 DFFE 0 4 0 7 CTV8 + - 8 - B 20 DFFE + 0 1 0 6 CT0 + - 3 - B 20 DFFE + 0 1 0 16 CT2 + - 3 - B 24 DFFE + 0 2 0 5 CT3 + - 1 - B 24 DFFE + 0 3 0 4 CT4 + - 8 - B 24 DFFE + 0 3 0 8 CT5 + - 6 - B 19 DFFE 0 5 0 1 DCOL0 + - 1 - B 19 DFFE 0 5 0 1 DCOL1 + - 4 - B 22 DFFE 0 5 0 1 DCOL2 + - 2 - B 19 DFFE 0 5 0 1 DCOL3 + - 5 - B 19 DFFE 0 5 0 1 DCOL4 + - 8 - B 22 DFFE 0 5 0 1 DCOL5 + - 8 - B 19 DFFE 0 4 0 1 DCOL6 + - 7 - B 19 DFFE 0 4 0 1 DCOL7 + - 1 - B 03 LCELL 0 4 0 1 DCP_CX + - 6 - B 05 DFFE 1 5 0 5 DCP3 + - 1 - B 09 DFFE 1 4 0 7 DCP4 + - 7 - B 09 DFFE 1 3 0 4 DCP5 + - 8 - B 09 DFFE 1 4 0 11 DD0 + - 4 - B 09 DFFE 1 4 0 11 DD1 + - 2 - B 09 DFFE 1 4 0 11 DD2 + - 3 - B 09 DFFE 1 3 0 8 DD6 + - 6 - B 09 DFFE 1 3 0 19 DD7 + - 5 - C 08 DFFE ! 0 5 0 6 DOS + - 4 - B 11 DFFE 0 3 0 1 DOS_ON_ + - 1 - C 02 DFFE + 0 1 0 1 DPIC + - 2 - B 15 DFFE 0 2 0 1 D_PIC00 + - 3 - B 15 DFFE 0 4 0 1 D_PIC01 + - 4 - B 15 DFFE 0 4 0 1 D_PIC02 + - 5 - B 15 DFFE 0 4 0 1 D_PIC03 + - 6 - B 15 DFFE 0 4 0 1 D_PIC04 + - 7 - B 15 DFFE 0 4 0 1 D_PIC05 + - 8 - B 15 DFFE 0 4 0 1 D_PIC06 + - 1 - B 15 DFFE 0 4 0 1 D_PIC07 + - 1 - B 04 OR2 1 3 0 0 D_RD + - 3 - B 18 DFFE 1 4 0 1 E_CAS_0 + - 6 - B 18 DFFE 1 4 0 1 E_CAS_1 + - 1 - B 18 DFFE 1 4 0 1 E_CAS_2 + - 8 - B 18 DFFE 1 4 0 1 E_CAS_3 + - 4 - B 17 GND s 0 0 0 8 ~GND~ + - 2 - A 06 DFFE 0 5 0 1 IN_OUT_CMD + - 1 - C 22 DFFE ! 0 2 1 0 INTT + - 2 - B 20 DFFE ! 1 1 0 1 /IOM + - 5 - B 07 DFFE ! 1 2 0 9 /IOM1 + - 2 - B 07 OR2 s 2 2 0 1 IO_WAIT~1 + - 5 - B 16 OR2 1 1 0 1 /IOWR + - 3 - C 09 OR2 0 4 0 8 KA8 + - 7 - C 09 OR2 0 4 0 8 KA9 + - 4 - C 04 OR2 0 4 0 8 KA10 + - 2 - C 12 OR2 0 4 0 8 KA11 + - 1 - C 07 OR2 0 4 0 8 KA12 + - 1 - C 09 OR2 0 3 0 8 KA13 + - 2 - C 09 OR2 0 3 0 8 KA14 + - 8 - C 09 OR2 0 3 0 8 KA15 + - 2 - C 05 DFFE 0 4 0 1 KB_ALT + - 5 - C 01 LCELL 0 4 0 2 KB_ALT_X + - 3 - C 05 DFFE 0 4 0 2 KB_CTRL + - 6 - C 01 LCELL 0 4 0 1 KB_CTRL_X + - 8 - C 03 DFFE ! 0 4 0 5 KB_CT0 + - 6 - C 03 DFFE ! 0 4 0 6 KB_CT1 + - 3 - C 03 DFFE ! 0 4 0 12 KB_CT2 + - 2 - C 16 DFFE 0 2 0 13 KBD_CC + - 7 - C 16 DFFE 0 2 0 1 KBD_DD + - 4 - C 23 DFFE + ! 0 2 0 1 KBD0 + - 3 - C 20 DFFE + ! 0 2 0 1 KBD1 + - 1 - C 01 DFFE 0 2 0 5 KB_D1 + - 6 - C 24 DFFE + ! 0 2 0 1 KBD2 + - 2 - C 01 DFFE 0 2 0 6 KB_D2 + - 7 - C 04 DFFE + ! 0 2 0 1 KBD3 + - 7 - C 14 DFFE 0 2 0 6 KB_D3 + - 7 - C 12 DFFE + ! 0 2 0 1 KBD4 + - 5 - C 14 DFFE 0 2 0 5 KB_D4 + - 5 - C 07 DFFE + ! 0 2 0 1 KBD5 + - 1 - C 14 DFFE 0 2 0 7 KB_D5 + - 6 - C 14 DFFE 0 2 0 5 KB_D6 + - 2 - C 14 DFFE 0 2 0 5 KB_D7 + - 4 - C 14 DFFE 0 2 0 5 KB_D8 + - 8 - C 14 DFFE 0 2 0 1 KB_D9 + - 3 - C 14 DFFE 0 2 0 1 KB_D10 + - 4 - C 01 DFFE 0 3 0 1 KB_EXT + - 4 - C 05 DFFE ! 0 5 0 1 KB_F12 + - 4 - C 08 DFFE + 0 0 0 6 KB_MA0 + - 1 - C 12 DFFE + 0 1 0 3 KB_MA1 + - 8 - C 12 DFFE + 0 2 0 5 KB_MA2 + - 6 - C 12 DFFE + 0 4 0 6 KB_MXA + - 5 - C 03 DFFE 0 4 0 10 KB_OFF + - 6 - C 05 DFFE ! 0 6 0 1 KB_RESET + - 1 - C 05 LCELL 0 4 0 3 KB_XXX + - 3 - B 10 DFFE + 1 0 0 3 K_CLK + - 6 - C 04 OR2 1 2 0 1 KDCA0 + - 4 - C 12 OR2 1 2 0 1 KDCA1 + - 4 - C 07 OR2 1 2 0 1 KDCA2 + - 5 - C 04 DFFE 0 2 0 1 KDD3 + - 3 - C 12 DFFE 0 2 0 1 KDD4 + - 2 - C 07 DFFE 0 2 0 1 KDD5 + - 6 - C 09 DFFE ! 0 3 0 2 KDD6 + - 4 - C 09 DFFE ! 0 3 0 2 KDD7 + - 2 - C 11 DFFE 0 4 0 1 KDXX0 + - 3 - C 11 DFFE 0 4 0 1 KDXX1 + - 5 - C 11 DFFE 0 4 0 1 KDXX2 + - 7 - C 11 DFFE 0 4 0 1 KDXX3 + - 1 - C 11 DFFE 0 4 0 1 KDXX4 + - 8 - C 11 DFFE 0 4 0 1 KDXX5 + - 6 - C 11 DFFE 0 4 0 1 KDX0 + - 4 - C 11 DFFE 0 4 0 1 KDX1 + - 8 - C 06 DFFE 0 4 0 1 KDX2 + - 7 - C 06 DFFE 0 4 0 1 KDX3 + - 5 - C 06 DFFE 0 4 0 1 KDX4 + - 3 - C 06 DFFE 0 4 0 1 KDX5 + - 6 - B 24 LCELL 0 3 0 7 LD_PIC + - 7 - B 17 DFFE + 0 1 0 9 LMC_END + - - 4 B -- MEM_SGMT 0 10 0 2 |lpm_ram_dq:195|altram:sram|segment0_0 + - - 2 B -- MEM_SGMT 0 10 0 2 |lpm_ram_dq:195|altram:sram|segment0_1 + - - 6 B -- MEM_SGMT 0 10 0 2 |lpm_ram_dq:195|altram:sram|segment0_2 + - - 7 B -- MEM_SGMT 0 10 1 2 |lpm_ram_dq:195|altram:sram|segment0_3 + - - 1 B -- MEM_SGMT 0 10 0 4 |lpm_ram_dq:195|altram:sram|segment0_4 + - - 3 B -- MEM_SGMT 0 10 0 4 |lpm_ram_dq:195|altram:sram|segment0_5 + - - 8 B -- MEM_SGMT 0 10 0 5 |lpm_ram_dq:195|altram:sram|segment0_6 + - - 5 B -- MEM_SGMT 0 10 0 5 |lpm_ram_dq:195|altram:sram|segment0_7 + - - 3 C -- MEM_SGMT 0 10 0 8 |lpm_ram_dq:291|altram:sram|segment0_0 + - - 7 C -- MEM_SGMT 0 10 0 8 |lpm_ram_dq:291|altram:sram|segment0_1 + - - 6 C -- MEM_SGMT 0 10 0 8 |lpm_ram_dq:291|altram:sram|segment0_2 + - - 1 C -- MEM_SGMT 0 10 0 3 |lpm_ram_dq:291|altram:sram|segment0_3 + - - 5 C -- MEM_SGMT 0 10 0 3 |lpm_ram_dq:291|altram:sram|segment0_4 + - - 4 C -- MEM_SGMT 0 10 0 3 |lpm_ram_dq:291|altram:sram|segment0_5 + - - 8 C -- MEM_SGMT 0 9 0 1 |lpm_ram_dq:291|altram:sram|segment0_6 + - - 2 C -- MEM_SGMT 0 9 0 1 |lpm_ram_dq:291|altram:sram|segment0_7 + - - 1 A -- MEM_SGMT 1 10 0 12 |lpm_ram_dq:386|altram:sram|segment0_0 + - - 7 A -- MEM_SGMT 1 10 0 11 |lpm_ram_dq:386|altram:sram|segment0_1 + - - 3 A -- MEM_SGMT 1 10 0 9 |lpm_ram_dq:386|altram:sram|segment0_2 + - - 4 A -- MEM_SGMT 1 10 0 4 |lpm_ram_dq:386|altram:sram|segment0_3 + - - 6 A -- MEM_SGMT 1 10 0 5 |lpm_ram_dq:386|altram:sram|segment0_4 + - - 2 A -- MEM_SGMT 1 10 0 10 |lpm_ram_dq:386|altram:sram|segment0_5 + - - 5 A -- MEM_SGMT 1 10 0 11 |lpm_ram_dq:386|altram:sram|segment0_6 + - - 8 A -- MEM_SGMT 1 10 0 10 |lpm_ram_dq:386|altram:sram|segment0_7 + - 1 - B 21 LCELL 0 1 0 8 LWR_COL + - 8 - C 18 LCELL 0 1 0 9 LWR_PIC + - 2 - A 21 OR2 0 3 1 0 MA0 + - 3 - B 17 OR2 0 3 1 0 MA1 + - 6 - B 14 OR2 0 3 1 0 MA2 + - 4 - C 17 OR2 0 3 1 0 MA3 + - 5 - C 16 OR2 0 3 1 0 MA4 + - 8 - B 14 OR2 0 3 1 0 MA5 + - 1 - B 13 OR2 0 3 1 0 MA6 + - 3 - C 23 OR2 0 3 1 0 MA7 + - 6 - C 20 OR2 0 3 1 0 MA8 + - 2 - C 24 OR2 0 3 1 0 MA9 + - 8 - B 08 DFFE 0 4 0 13 MC_END + - 3 - B 08 DFFE ! 0 3 0 1 MC_START + - 7 - B 08 DFFE 0 3 0 8 MC_SYCLE + - 3 - B 04 DFFE + ! 3 2 0 2 MC1 + - 8 - B 12 OR2 0 4 0 1 MPGS0 + - 4 - B 12 OR2 0 4 0 1 MPGS1 + - 6 - B 01 OR2 0 4 0 1 MPGS2 + - 3 - B 01 OR2 0 4 0 1 MPGS3 + - 8 - C 10 DFFE s 0 2 1 0 MXVD0~1 + - 4 - C 10 DFFE s 0 2 1 0 MXVD0~2 + - 3 - B 05 DFFE s 0 2 1 0 MXVD0~3 + - 1 - C 10 DFFE 0 2 1 1 MXVD0 + - 2 - A 13 DFFE s 0 2 1 0 MXVD1~1 + - 4 - A 13 DFFE s 0 2 1 0 MXVD1~2 + - 5 - A 13 DFFE s 0 2 1 0 MXVD1~3 + - 1 - A 13 DFFE 0 2 1 1 MXVD1 + - 1 - A 16 DFFE s 0 2 1 0 MXVD2~1 + - 8 - A 16 DFFE s 0 2 1 0 MXVD2~2 + - 7 - A 16 DFFE s 0 2 1 0 MXVD2~3 + - 4 - A 12 DFFE 0 2 1 1 MXVD2 + - 6 - C 10 DFFE s 0 2 1 0 MXVD3~1 + - 5 - C 10 DFFE s 0 2 1 0 MXVD3~2 + - 7 - C 10 DFFE s 0 2 1 0 MXVD3~3 + - 3 - C 10 DFFE 0 2 1 1 MXVD3 + - 3 - A 13 DFFE s 0 2 1 0 MXVD4~1 + - 6 - A 13 DFFE s 0 2 1 0 MXVD4~2 + - 8 - A 13 DFFE s 0 2 1 0 MXVD4~3 + - 7 - A 01 DFFE 0 2 1 1 MXVD4 + - 6 - A 16 DFFE s 0 2 1 0 MXVD5~1 + - 2 - A 16 DFFE s 0 2 1 0 MXVD5~2 + - 3 - A 16 DFFE s 0 2 1 0 MXVD5~3 + - 5 - A 16 DFFE 0 2 1 1 MXVD5 + - 8 - B 11 DFFE s 0 2 1 0 MXVD6~1 + - 2 - B 11 DFFE s 0 2 1 0 MXVD6~2 + - 5 - B 11 DFFE s 0 2 1 0 MXVD6~3 + - 6 - B 11 DFFE 0 2 1 1 MXVD6 + - 5 - A 06 DFFE s 0 2 1 0 MXVD7~1 + - 1 - A 06 DFFE s 0 2 1 0 MXVD7~2 + - 4 - A 06 DFFE s 0 2 1 0 MXVD7~3 + - 7 - A 06 DFFE 0 2 1 1 MXVD7 + - 3 - B 23 DFFE ! 0 6 0 1 MXWE + - 6 - B 12 OR2 0 4 0 8 PGS0 + - 7 - B 12 OR2 0 4 0 8 PGS1 + - 8 - B 01 OR2 0 4 0 8 PGS2 + - 1 - B 01 OR2 0 4 0 8 PGS3 + - 6 - B 10 OR2 0 4 0 8 PGS4 + - 2 - B 02 OR2 0 4 0 8 PGS5 + - 1 - B 02 OR2 0 4 0 8 PGS6 + - 3 - B 02 OR2 0 3 0 8 PGS7 + - 8 - B 06 DFFE 0 4 0 3 PN0 + - 2 - B 06 DFFE 0 4 0 3 PN1 + - 7 - B 06 DFFE 0 4 0 3 PN2 + - 5 - B 06 DFFE 0 4 0 1 PN3 + - 1 - B 06 DFFE 0 4 0 2 PN4 + - 4 - B 06 DFFE 0 4 0 1 PN5 + - 8 - A 06 DFFE 0 5 0 1 PRF_CMD + - 2 - C 17 OR2 1 2 0 1 RA3 + - 4 - C 16 OR2 1 2 0 1 RA4 + - 8 - C 23 OR2 1 2 0 1 RA7 + - 7 - C 20 OR2 1 2 0 1 RA8 + - 8 - C 24 OR2 2 1 0 1 RA9 + - 8 - B 17 OR2 1 2 0 1 RA12 + - 7 - B 14 OR2 1 2 0 1 RA13 + - 2 - C 06 DFFE 0 3 0 15 RXA0 + - 6 - C 06 DFFE 0 3 0 10 RXA1 + - 2 - B 12 LCELL 0 3 0 2 SC_LCELL + - 5 - B 10 LCELL 0 2 0 1 SC_PGS + - 3 - B 16 DFFE 0 4 0 4 SC0 + - 4 - B 16 DFFE 0 4 0 1 SC1 + - 6 - B 16 DFFE 0 4 0 4 SC4 + - 1 - C 23 OR2 s 1 3 0 1 SD0~1 + - 6 - C 23 OR2 0 4 1 0 SD0 + - 1 - C 20 OR2 s 1 3 0 1 SD1~1 + - 4 - C 20 OR2 0 4 1 0 SD1 + - 3 - C 24 OR2 s 1 3 0 1 SD2~1 + - 1 - C 24 OR2 0 4 1 0 SD2 + - 4 - B 05 OR2 s 1 3 0 1 SD3~1 + - 3 - C 04 OR2 0 4 1 0 SD3 + - 8 - B 03 OR2 s 1 3 0 1 SD4~1 + - 1 - A 08 OR2 0 4 1 0 SD4 + - 3 - B 03 OR2 s 1 3 0 1 SD5~1 + - 2 - B 03 OR2 0 4 1 0 SD5 + - 4 - B 02 OR2 s 1 3 0 1 SD6~1 + - 5 - B 02 OR2 0 4 1 0 SD6 + - 8 - C 07 OR2 s 1 3 0 1 SD7~1 + - 3 - C 07 OR2 0 4 1 0 SD7 + - 7 - C 17 DFFE 0 5 0 4 SINC_HH + - 3 - C 16 DFFE 0 3 0 1 SINC_VV + - 7 - C 22 OR2 0 3 0 1 SVA2 + - 3 - C 22 OR2 0 3 0 1 SVA3 + - 4 - C 22 OR2 0 2 0 1 SVA5 + - 1 - B 17 OR2 0 2 0 1 SVA6 + - 5 - B 13 DFFE 0 4 0 6 SYS + - 8 - B 16 DFFE ! 0 4 0 1 TB_SW + - 5 - B 23 DFFE + 0 3 0 1 TSN_W3 + - 6 - C 13 DFFE + 0 2 1 2 TURBO + - 6 - B 20 DFFE + 0 3 0 31 VCM0 + - 5 - B 20 DFFE + 0 3 0 19 VCM1 + - 4 - B 20 DFFE + 0 3 0 8 VCM2 + - 2 - C 02 DFFE + 0 3 1 0 VLA2 + - 5 - C 19 DFFE + 0 3 1 0 VLA3 + - 4 - B 23 DFFE + 0 4 1 0 VLA4 + - 7 - C 02 DFFE + 0 4 1 0 VLA5 + - 6 - B 17 DFFE + 0 4 1 0 VLA6 + - 6 - B 06 DFFE + 0 4 1 0 VLA7 + - 8 - C 02 DFFE + 0 2 1 0 VLA8 + - 6 - C 02 DFFE + 0 2 1 0 VLA9 + - 5 - A 21 DFFE + 0 4 1 0 VLA10 + - 3 - B 19 DFFE + 0 3 1 0 VLA11 + - 5 - C 02 DFFE + 0 3 1 0 VLA12 + - 8 - A 22 DFFE + 0 3 1 0 VLA13 + - 2 - B 21 DFFE + 0 3 1 0 VLA14 + - 7 - C 21 DFFE + 0 3 1 0 VLA15 + - 5 - C 21 DFFE + 0 3 1 0 VLA16 + - 8 - C 21 DFFE + 0 3 1 0 VLA17 + - 7 - B 04 OR2 s 1 2 0 1 V_WAIT~1 + - 8 - B 23 DFFE + ! 0 4 0 3 V_WE + - 4 - B 04 OR2 0 3 1 0 /WAITT + - 1 - B 08 AND2 ! 2 2 1 1 /WE1 + - 4 - B 21 DFFE + 0 2 0 1 WR_COL + - 1 - C 06 AND2 ! 0 4 0 8 WR_KBD + - 2 - B 23 DFFE + 0 2 0 1 WR_PIC + - 3 - A 03 AND2 0 2 1 0 XC0 + - 6 - A 03 OR2 0 2 1 0 XC1 + - 4 - A 03 OR2 0 2 1 0 XC2 + - 3 - B 07 OR2 0 2 1 0 XC3 + - 8 - B 10 DFFE 0 2 0 1 :1921 + - 4 - B 10 LCELL 1 2 0 9 :1922 + - 7 - B 10 LCELL 0 4 0 1 :1924 + - 1 - B 12 LCELL 0 4 0 2 :1926 + - 8 - A 03 DFFE + ! 2 1 0 3 :1929 + - 8 - B 07 DFFE 0 5 0 1 :1930 + - 7 - B 21 DFFE + 0 2 0 10 :1958 + - 3 - B 11 DFFE 0 2 0 1 :1962 + - 5 - B 04 DFFE ! 1 1 0 1 :1964 + - 1 - C 16 LCELL s 0 1 1 0 ~1966~1 + - 7 - A 13 LCELL s 0 1 1 0 ~1972~1 + - 7 - B 22 LCELL s 0 1 1 0 ~1978~1 + - 2 - C 10 LCELL s 0 1 1 0 ~1984~1 + - 2 - A 03 LCELL s 0 1 1 0 ~1990~1 + - 3 - C 13 LCELL s 0 1 1 0 ~1996~1 + - 1 - B 11 LCELL s 0 1 1 0 ~2002~1 + - 2 - C 04 LCELL s 0 1 1 0 ~2008~1 + - 7 - B 23 LCELL 0 1 1 0 :2013 + - 4 - C 15 DFFE 0 2 1 0 :2019 + - 5 - C 22 DFFE 0 4 0 1 :2024 + - 7 - C 05 DFFE ! 0 3 0 1 :2032 + - 7 - B 20 DFFE + 0 4 1 0 :2034 + - 6 - B 07 DFFE 0 5 0 1 :2040 + - 4 - B 07 DFFE 0 3 0 1 :2041 + - 1 - B 07 DFFE 0 2 0 1 :2042 + - 5 - A 03 DFFE + 0 5 0 1 :2043 + - 5 - B 09 LCELL 0 4 0 8 :2054 + - 1 - A 18 DFFE 0 2 1 1 :2058 + - 8 - C 22 DFFE 0 5 1 0 :2061 + - 6 - B 21 DFFE + 0 1 0 1 :2069 + - 1 - B 23 LCELL 0 1 1 0 :2071 + - 8 - C 01 LCELL 0 4 0 1 :2140 + - 7 - C 03 LCELL 0 4 0 2 :2142 + - 5 - C 09 LCELL 0 2 0 8 :2143 + - 4 - C 06 LCELL 1 2 0 8 :2144 + - 1 - C 03 LCELL 0 3 0 1 :2149 + - 2 - B 16 LCELL 1 3 0 5 :2195 + - 5 - A 01 LCELL 0 2 0 1 :2198 + - 3 - A 17 DFFE + 0 3 0 1 :2199 + - 8 - A 09 LCELL 0 4 0 1 :2200 + - 4 - A 09 DFFE + 0 4 0 1 :2201 + - 1 - A 09 DFFE + 0 4 0 1 :2202 + - 5 - A 09 DFFE + 0 3 0 1 :2203 + - 2 - A 11 LCELL 0 4 0 1 :2204 + - 4 - A 23 DFFE + 0 3 0 1 :2205 + - 7 - A 03 DFFE + 0 1 0 9 :2206 + - 5 - A 10 DFFE + 0 3 0 2 :2207 + - 3 - A 10 DFFE + 0 1 0 1 :2208 + - 4 - A 10 DFFE + 0 1 0 1 :2209 + - 1 - A 05 LCELL 0 4 0 1 :2213 + - 1 - A 07 LCELL 0 4 0 1 :2214 + - 3 - A 12 LCELL 0 4 0 1 :2215 + - 5 - A 24 DFFE + 0 4 0 6 :2216 + - 7 - A 22 DFFE + 0 4 0 9 :2217 + - 1 - A 21 LCELL 0 3 0 1 :2218 + - 3 - A 22 DFFE + 0 4 0 5 :2219 + - 2 - A 22 DFFE + 0 3 0 6 :2220 + - 3 - A 08 DFFE s 0 4 1 0 ~2224~1 + - 6 - A 08 DFFE 0 4 1 0 :2224 + - 1 - B 10 AND2 ! 0 2 0 3 :2292 + - 8 - B 02 AND2 0 1 0 2 :2324 + - 7 - B 07 AND2 ! 1 3 0 8 :2363 + - 3 - A 06 AND2 s 0 4 0 1 ~2463~1 + - 5 - A 15 AND2 s 0 2 0 1 ~2463~2 + - 5 - B 03 OR2 1 2 0 19 :3452 + - 3 - B 22 AND2 ! 0 3 0 5 :3466 + - 8 - C 15 AND2 0 4 0 1 :3493 + - 2 - B 13 AND2 ! 0 3 0 1 :3497 + - 7 - C 15 AND2 0 4 0 1 :3505 + - 7 - B 13 AND2 0 4 0 2 :3511 + - 1 - B 16 AND2 ! 0 3 0 4 :3513 + - 3 - B 06 OR2 0 3 0 6 :3534 + - 3 - C 08 AND2 s 0 4 0 1 ~3551~1 + - 6 - C 08 AND2 0 4 0 1 :3551 + - 4 - A 08 AND2 1 2 0 1 :3613 + - 6 - C 07 AND2 1 2 0 1 :3622 + - 6 - B 03 AND2 1 2 0 8 :3626 + - 4 - B 03 AND2 1 2 0 7 :3645 + - 2 - C 23 AND2 0 2 0 1 :3646 + - 2 - C 20 AND2 0 2 0 1 :3648 + - 5 - C 24 AND2 0 2 0 1 :3650 + - 1 - C 04 AND2 0 2 0 1 :3652 + - 7 - B 02 AND2 2 2 0 1 :3657 + - 5 - B 05 OR2 0 2 0 2 :3661 + - 5 - B 24 OR2 0 3 1 0 :3682 + - 5 - B 18 OR2 0 4 1 0 :3754 + - 4 - B 18 OR2 0 4 1 0 :3759 + - 2 - B 08 OR2 0 4 1 0 :3764 + - 7 - B 18 OR2 0 4 1 0 :3769 + - 4 - B 08 OR2 s 0 3 1 0 ~3773~1 + - 5 - B 08 OR2 0 3 1 0 :3773 + - 4 - B 24 AND2 0 2 0 1 :3864 + - 3 - C 18 OR2 0 2 0 4 :4028 + - 3 - C 21 AND2 0 3 0 4 :4039 + - 3 - C 19 AND2 0 2 0 3 :4069 + - 6 - C 21 AND2 s ! 0 3 0 2 ~4089~1 + - 7 - B 01 OR2 ! 0 4 0 1 :4106 + - 3 - C 02 OR2 s 0 4 0 1 ~4228~1 + - 8 - C 19 OR2 s 0 4 0 1 ~4231~1 + - 6 - B 23 OR2 s 0 3 0 1 ~4234~1 + - 3 - A 18 OR2 s 0 4 0 1 ~4246~1 + - 4 - B 19 OR2 s 0 4 0 1 ~4249~1 + - 4 - C 02 OR2 s 0 4 0 1 ~4252~1 + - 1 - C 17 OR2 s 0 4 0 1 ~4255~1 + - 5 - B 21 OR2 s 0 4 0 1 ~4258~1 + - 1 - B 14 OR2 s 0 4 0 1 ~4261~1 + - 6 - B 13 OR2 s 0 4 0 1 ~4264~1 + - 8 - C 17 OR2 s 0 4 0 1 ~4267~1 + - 4 - C 03 AND2 ! 0 3 0 1 :4686 + - 2 - C 03 AND2 ! 0 3 0 3 :4724 + - 7 - C 01 AND2 s 0 4 0 1 ~4735~1 + - 3 - C 01 AND2 s 0 4 0 2 ~4735~2 + - 5 - C 05 AND2 s ! 0 2 0 1 ~4777~1 + - 8 - C 05 AND2 s 0 4 0 1 ~4777~2 + - 6 - A 06 AND2 s 0 2 0 1 ~6697~1 + - 7 - A 04 OR2 0 4 0 4 :6723 + - 2 - A 08 AND2 ! 0 2 0 16 :6740 + - 6 - A 22 AND2 0 2 0 1 :6811 + - 5 - A 07 AND2 0 2 0 2 :6813 + - 7 - A 09 OR2 ! 0 4 0 1 :6854 + - 6 - A 10 AND2 ! 0 2 0 4 :6859 + - 3 - A 02 OR2 0 3 0 1 :6875 + - 4 - A 02 AND2 ! 0 4 0 3 :6881 + - 3 - A 11 AND2 ! 0 3 0 3 :6891 + - 6 - A 02 AND2 ! 0 2 0 1 :6910 + - 6 - A 05 AND2 0 2 0 1 :6943 + - 2 - A 20 OR2 0 4 0 2 :6959 + - 6 - A 20 OR2 0 3 0 2 :6969 + - 7 - A 20 OR2 0 3 0 2 :6979 + - 2 - A 23 AND2 0 2 0 1 :6994 + - 6 - A 23 AND2 0 4 0 2 :7008 + - 5 - A 14 OR2 0 4 0 1 :7357 + - 7 - A 14 OR2 0 3 0 1 :7364 + - 2 - A 14 OR2 0 3 0 1 :7371 + - 7 - A 24 OR2 0 3 0 2 :7379 + - 2 - A 09 AND2 s 0 3 0 4 ~7404~1 + - 5 - A 22 AND2 s 0 3 0 3 ~7404~2 + - 8 - A 12 AND2 s 0 4 0 1 ~7491~1 + - 3 - A 09 OR2 0 2 0 1 :7513 + - 2 - A 17 OR2 s 0 4 0 1 ~7536~1 + - 2 - B 05 OR2 s 0 4 0 2 ~7548~1 + - 6 - C 15 AND2 s ! 0 3 0 1 ~7548~2 + - 7 - C 08 OR2 s 0 4 0 1 ~7980~1 + - 5 - C 12 OR2 s 0 4 0 1 ~7980~2 + - 1 - C 08 OR2 s 0 3 0 1 ~7980~3 + - 2 - C 08 OR2 s 0 3 0 1 ~7980~4 + - 8 - C 08 OR2 s 0 3 0 1 ~7980~5 + - 2 - B 18 OR2 s 1 2 0 2 ~8352~1 + - 2 - C 13 OR2 ! 2 0 0 17 :8372 + - 2 - C 22 OR2 2 1 0 1 :8399 + - 6 - B 08 AND2 ! 0 3 0 1 :8459 + - 6 - B 04 AND2 ! 2 0 0 3 :8464 + - 8 - B 21 AND2 ! 0 2 0 1 :8472 + - 1 - B 05 OR2 s ! 0 2 0 2 ~8621~1 + - 1 - C 15 AND2 s 0 3 0 1 ~8621~2 + - 8 - B 05 AND2 s 2 2 0 1 ~8621~3 + - 4 - A 16 OR2 0 4 0 1 :8648 + - 2 - B 04 OR2 2 0 0 1 :8687 + + +Code: + +s = Synthesized pin or logic cell ++ = Synchronous flipflop +/ = Slow slew-rate output +! = NOT gate push-back +r = Fitter-inserted logic cell +p = Packed register + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** FASTTRACK INTERCONNECT UTILIZATION ** + +Row FastTrack Interconnect: + + Global Left Half- Right Half- + FastTrack FastTrack FastTrack +Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins +A: 71/ 96( 73%) 43/ 48( 89%) 38/ 48( 79%) 0/16( 0%) 4/16( 25%) 12/16( 75%) +B: 81/ 96( 84%) 40/ 48( 83%) 37/ 48( 77%) 0/16( 0%) 6/16( 37%) 10/16( 62%) +C: 78/ 96( 81%) 43/ 48( 89%) 34/ 48( 70%) 0/16( 0%) 3/16( 18%) 13/16( 81%) + + +Column FastTrack Interconnect: + + FastTrack +Column Interconnect Input Pins Output Pins Bidir Pins +01: 4/24( 16%) 0/4( 0%) 3/4( 75%) 1/4( 25%) +02: 4/24( 16%) 0/4( 0%) 2/4( 50%) 1/4( 25%) +03: 8/24( 33%) 0/4( 0%) 2/4( 50%) 2/4( 50%) +04: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%) +05: 4/24( 16%) 0/4( 0%) 2/4( 50%) 1/4( 25%) +06: 6/24( 25%) 0/4( 0%) 1/4( 25%) 2/4( 50%) +07: 6/24( 25%) 1/4( 25%) 1/4( 25%) 1/4( 25%) +08: 4/24( 16%) 0/4( 0%) 4/4(100%) 0/4( 0%) +09: 7/24( 29%) 0/4( 0%) 0/4( 0%) 3/4( 75%) +10: 7/24( 29%) 0/4( 0%) 0/4( 0%) 3/4( 75%) +11: 3/24( 12%) 0/4( 0%) 1/4( 25%) 2/4( 50%) +12: 3/24( 12%) 0/4( 0%) 0/4( 0%) 3/4( 75%) +13: 9/24( 37%) 0/4( 0%) 2/4( 50%) 2/4( 50%) +14: 11/24( 45%) 0/4( 0%) 1/4( 25%) 2/4( 50%) +15: 13/24( 54%) 0/4( 0%) 0/4( 0%) 3/4( 75%) +16: 8/24( 33%) 0/4( 0%) 1/4( 25%) 2/4( 50%) +17: 10/24( 41%) 0/4( 0%) 3/4( 75%) 0/4( 0%) +18: 10/24( 41%) 0/4( 0%) 3/4( 75%) 1/4( 25%) +19: 7/24( 29%) 0/4( 0%) 2/4( 50%) 1/4( 25%) +20: 7/24( 29%) 0/4( 0%) 1/4( 25%) 2/4( 50%) +21: 7/24( 29%) 0/4( 0%) 4/4(100%) 0/4( 0%) +22: 5/24( 20%) 0/4( 0%) 2/4( 50%) 1/4( 25%) +23: 6/24( 25%) 0/4( 0%) 2/4( 50%) 1/4( 25%) +24: 8/24( 33%) 0/4( 0%) 3/4( 75%) 1/4( 25%) +EA: 9/24( 37%) 0/4( 0%) 0/4( 0%) 0/4( 0%) + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** CLOCK SIGNALS ** + +Type Fan-out Name +INPUT 153 TG42 +DFF 48 AY_CCC2 +DFF 29 AY_CCC1 +LCELL 19 :3452 +DFF 17 CT2 +LCELL 17 :8372 +DFF 15 RXA0 +DFF 13 KBD_CC +DFF 13 KB_CT2 +DFF 10 CTH5 +DFF 10 CTH2 +DFF 10 RXA1 +DFF 9 CT5 +LCELL 9 LWR_PIC +DFF 9 LMC_END +DFF 8 CTV2 +DFF 8 CTV8 +LCELL 8 LWR_COL +DFF 8 CAS +DFF 7 CT0 +DFF 7 AY_CCC8 +DFF 6 CTH1 +DFF 6 AY_D_WR +INPUT 6 /M1 +LCELL 5 :2195 +DFF 5 AY_VA3 +DFF 5 CTV5 +DFF 5 CTV0 +DFF 4 SINC_HH +DFF 3 K_CLK +LCELL 3 :4724 +LCELL 3 :8464 +DFF 1 :2024 +DFF 1 KB_F12 +DFF 1 :2199 +LCELL 1 :4686 +LCELL 1 /IOWR +LCELL 1 :8459 + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** CLEAR SIGNALS ** + +Type Fan-out Name +INPUT 51 /IO +INPUT 22 /RESET +LCELL 17 :8372 +DFF 14 MC_END +DFF 13 KB_CT2 +DFF 13 KBD_CC +DFF 10 AY_F_RES +INPUT 9 /MR +DFF 9 /IOM1 +LCELL 8 BLK_R +DFF 8 BLANK +DFF 6 :2216 +DFF 3 V_WE +LCELL 3 :4724 +LCELL 2 CORRECT_1F +DFF 1 KB_RESET +LCELL 1 :8399 +DFF 1 :2201 +LCELL 1 :2198 +DFF 1 :2069 +DFF 1 SINC_VV +LCELL 1 :8472 + + +Device-Specific Information: c:\prj\sprinter\firmware\97\flex\sprint08.rpt +sprint08 + +** EQUATIONS ** + +TAPE_IN : INPUT; +TG42 : INPUT; +/IO : INPUT; +/MR : INPUT; +/M1 : INPUT; +/RD : INPUT; +/RF : INPUT; +/WR : INPUT; + +-- Node name is 'AA0' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA0', location is LC8_A21, type is buried. +AA0 = DFFE( A0, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA1' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA1', location is LC2_B17, type is buried. +AA1 = DFFE( A1, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA2' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA2', location is LC5_B14, type is buried. +AA2 = DFFE( A2, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA3' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA3', location is LC1_C13, type is buried. +AA3 = DFFE( A3, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA4' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA4', location is LC4_C13, type is buried. +AA4 = DFFE( A4, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA5' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA5', location is LC4_B14, type is buried. +AA5 = DFFE( A5, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA6' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA6', location is LC4_B13, type is buried. +AA6 = DFFE( A6, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA7' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA7', location is LC7_C23, type is buried. +AA7 = DFFE( A7, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA8' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA8', location is LC8_C20, type is buried. +AA8 = DFFE( A8, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA9' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA9', location is LC4_C24, type is buried. +AA9 = DFFE( A9, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA10' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA10', location is LC8_C13, type is buried. +AA10 = DFFE( A10, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA11' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA11', location is LC7_C13, type is buried. +AA11 = DFFE( A11, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA12' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA12', location is LC5_B17, type is buried. +AA12 = DFFE( A12, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AA13' from file "sprint08.tdf" line 496, column 4 +-- Equation name is 'AA13', location is LC3_B14, type is buried. +AA13 = DFFE( A13, !_LC2_C13, VCC, VCC, VCC); + +-- Node name is 'AROM16' from file "sprint08.tdf" line 314, column 2 +-- Equation name is 'AROM16', location is LC4_B1, type is buried. +AROM16 = DFFE( D0, _LC5_B3, /RESET, VCC, _LC8_C15); + +-- Node name is 'AR0' from file "sprint08.tdf" line 744, column 5 +-- Equation name is 'AR0', location is LC5_B12, type is buried. +AR0 = LCELL( _EQ001); + _EQ001 = !DOS & SC_LCELL + # PN4 & SC_LCELL + # !SYS; + +-- Node name is 'AR1' from file "sprint08.tdf" line 743, column 5 +-- Equation name is 'AR1', location is LC3_B12, type is buried. +AR1 = LCELL( _EQ002); + _EQ002 = DOS & SC_LCELL + # !SYS; + +-- Node name is 'AR2' from file "sprint08.tdf" line 742, column 5 +-- Equation name is 'AR2', location is LC5_B1, type is buried. +AR2 = LCELL( _EQ003); + _EQ003 = AROM16 & !SYS + # AROM16 & !SC0; + +-- Node name is 'AR3' from file "sprint08.tdf" line 741, column 11 +-- Equation name is 'AR3', location is LC2_B1, type is buried. +AR3 = LCELL( _EQ004); + _EQ004 = !SYS + # SC0; + +-- Node name is 'AX128' from file "sprint08.tdf" line 1797, column 10 +-- Equation name is 'AX128', location is LC4_A5, type is buried. +AX128 = LCELL( _EQ005); + _EQ005 = A15 & PN1; + +-- Node name is 'AY_AAX0' from file "sprint08.tdf" line 511, column 8 +-- Equation name is 'AY_AAX0', location is LC2_A1, type is buried. +AY_AAX0 = DFFE( _EQ006, _LC2_B16, VCC, VCC, VCC); + _EQ006 = D0 & !D1 & D2 & D3; + +-- Node name is 'AY_AA0' from file "sprint08.tdf" line 547, column 7 +-- Equation name is 'AY_AA0', location is LC2_A19, type is buried. +AY_AA0 = DFFE( _EQ007, GLOBAL( TG42), VCC, VCC, VCC); + _EQ007 = !AY_ABLK & AY_BINV & AY_GF2 & !AY_VA0 + # !AY_ABLK & !AY_BINV & AY_GF2 & AY_VA0 + # !AY_ABLK & AY_BINV & !AY_GF2 & AY_VA0 + # !AY_ABLK & !AY_BINV & !AY_GF2 & !AY_VA0; + +-- Node name is 'AY_AA1' from file "sprint08.tdf" line 547, column 7 +-- Equation name is 'AY_AA1', location is LC4_A19, type is buried. +AY_AA1 = DFFE( _EQ008, GLOBAL( TG42), VCC, VCC, VCC); + _EQ008 = !AY_ABLK & AY_BINV & AY_GF2 & !AY_VA1 + # !AY_ABLK & !AY_BINV & AY_GF2 & AY_VA1 + # !AY_ABLK & AY_BINV & !AY_GF2 & AY_VA1 + # !AY_ABLK & !AY_BINV & !AY_GF2 & !AY_VA1; + +-- Node name is 'AY_AA2' from file "sprint08.tdf" line 547, column 7 +-- Equation name is 'AY_AA2', location is LC5_A19, type is buried. +AY_AA2 = DFFE( _EQ009, GLOBAL( TG42), VCC, VCC, VCC); + _EQ009 = !AY_ABLK & AY_BINV & AY_GF2 & !AY_VA2 + # !AY_ABLK & !AY_BINV & AY_GF2 & AY_VA2 + # !AY_ABLK & AY_BINV & !AY_GF2 & AY_VA2 + # !AY_ABLK & !AY_BINV & !AY_GF2 & !AY_VA2; + +-- Node name is 'AY_AA3' from file "sprint08.tdf" line 547, column 7 +-- Equation name is 'AY_AA3', location is LC6_A19, type is buried. +AY_AA3 = DFFE( _EQ010, GLOBAL( TG42), VCC, VCC, VCC); + _EQ010 = !AY_ABLK & !AY_BINV & AY_GF2 & AY_VA3 + # !AY_ABLK & AY_BINV & AY_GF2 & !AY_VA3 + # !AY_ABLK & AY_BINV & !AY_GF2 & AY_VA3 + # !AY_ABLK & !AY_BINV & !AY_GF2 & !AY_VA3; + +-- Node name is 'AY_ABLK' from file "sprint08.tdf" line 3259, column 13 +-- Equation name is 'AY_ABLK', location is LC3_A15, type is buried. +AY_ABLK = DFFE(!AY_GF3, !AY_VA3, AY_F_RES, VCC, VCC); + +-- Node name is 'AY_ADR0' from file "sprint08.tdf" line 509, column 8 +-- Equation name is 'AY_ADR0', location is LC8_A1, type is buried. +AY_ADR0 = DFFE( D0, _LC2_B16, VCC, VCC, VCC); + +-- Node name is 'AY_ADR1' from file "sprint08.tdf" line 509, column 8 +-- Equation name is 'AY_ADR1', location is LC6_A4, type is buried. +AY_ADR1 = DFFE( D1, _LC2_B16, VCC, VCC, VCC); + +-- Node name is 'AY_ADR2' from file "sprint08.tdf" line 509, column 8 +-- Equation name is 'AY_ADR2', location is LC3_A4, type is buried. +AY_ADR2 = DFFE( D2, _LC2_B16, VCC, VCC, VCC); + +-- Node name is 'AY_ADR3' from file "sprint08.tdf" line 509, column 8 +-- Equation name is 'AY_ADR3', location is LC2_A4, type is buried. +AY_ADR3 = DFFE( D3, _LC2_B16, VCC, VCC, VCC); + +-- Node name is 'AY_AMP0' from file "sprint08.tdf" line 578, column 8 +-- Equation name is 'AY_AMP0', location is LC1_A19, type is buried. +AY_AMP0 = DFFE( _EQ011, GLOBAL( TG42), VCC, VCC, VCC); + _EQ011 = AY_DAT0 & !AY_DAT4 + # AY_AA0 & AY_DAT4 + # AY_AA0 & AY_DAT0; + +-- Node name is 'AY_AMP1' from file "sprint08.tdf" line 578, column 8 +-- Equation name is 'AY_AMP1', location is LC8_A19, type is buried. +AY_AMP1 = DFFE( _EQ012, GLOBAL( TG42), VCC, VCC, VCC); + _EQ012 = AY_DAT1 & !AY_DAT4 + # AY_AA1 & AY_DAT4 + # AY_AA1 & AY_DAT1; + +-- Node name is 'AY_AMP2' from file "sprint08.tdf" line 578, column 8 +-- Equation name is 'AY_AMP2', location is LC3_A19, type is buried. +AY_AMP2 = DFFE( _EQ013, GLOBAL( TG42), VCC, VCC, VCC); + _EQ013 = AY_DAT2 & !AY_DAT4 + # AY_AA2 & AY_DAT4 + # AY_AA2 & AY_DAT2; + +-- Node name is 'AY_AMP3' from file "sprint08.tdf" line 578, column 8 +-- Equation name is 'AY_AMP3', location is LC7_A19, type is buried. +AY_AMP3 = DFFE( _EQ014, GLOBAL( TG42), VCC, VCC, VCC); + _EQ014 = AY_AA3 & AY_DAT4 + # AY_AA3 & AY_DAT3 + # AY_DAT3 & !AY_DAT4; + +-- Node name is 'AY_AX0~1' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX0~1', location is LC6_A1, type is buried. +-- synthesized logic cell +_LC6_A1 = LCELL( _EQ015); + _EQ015 = AY_ADR0 & AY_CCC0 & !AY_CCC1 + # !AY_CCC0 & !AY_CCC1 & AY_CCC2; + +-- Node name is 'AY_AX0' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX0', location is LC1_A1, type is buried. +AY_AX0 = LCELL( _EQ016); + _EQ016 = AY_CCC1 & _EC1_A + # _LC6_A1; + +-- Node name is 'AY_AX1~1' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX1~1', location is LC8_A4, type is buried. +-- synthesized logic cell +_LC8_A4 = LCELL( _EQ017); + _EQ017 = AY_ADR1 & AY_CCC0 & !AY_CCC1 + # !AY_CCC0 & !AY_CCC1 & AY_CCC3; + +-- Node name is 'AY_AX1' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX1', location is LC5_A4, type is buried. +AY_AX1 = LCELL( _EQ018); + _EQ018 = AY_CCC1 & _EC7_A + # _LC8_A4; + +-- Node name is 'AY_AX2~1' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX2~1', location is LC1_A4, type is buried. +-- synthesized logic cell +_LC1_A4 = LCELL( _EQ019); + _EQ019 = AY_ADR2 & AY_CCC0 & !AY_CCC1 + # !AY_CCC0 & !AY_CCC1 & AY_CCC4; + +-- Node name is 'AY_AX2' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX2', location is LC1_A22, type is buried. +AY_AX2 = LCELL( _EQ020); + _EQ020 = AY_CCC1 & _EC3_A + # _LC1_A4; + +-- Node name is 'AY_AX3~1' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX3~1', location is LC4_A4, type is buried. +-- synthesized logic cell +_LC4_A4 = LCELL( _EQ021); + _EQ021 = AY_ADR3 & AY_CCC0 & !AY_CCC1 + # !AY_CCC0 & !AY_CCC1 & AY_CCC5; + +-- Node name is 'AY_AX3' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX3', location is LC1_A2, type is buried. +AY_AX3 = LCELL( _EQ022); + _EQ022 = AY_CCC1 & _EC4_A + # _LC4_A4; + +-- Node name is 'AY_AX4' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is 'AY_AX4', location is LC3_A24, type is buried. +AY_AX4 = LCELL( _EQ023); + _EQ023 = AY_CCC1 & _EC6_A + # !AY_CCC0 & !AY_CCC1 & AY_CCC6; + +-- Node name is 'AY_AX5' from file "sprint08.tdf" line 3132, column 13 +-- Equation name is 'AY_AX5', location is LC5_A8, type is buried. +AY_AX5 = LCELL( _EQ024); + _EQ024 = !AY_CCC0 & !AY_CCC1 & AY_CCC7; + +-- Node name is 'AY_BBLK' from file "sprint08.tdf" line 3257, column 13 +-- Equation name is 'AY_BBLK', location is LC6_A15, type is buried. +AY_BBLK = DFFE( AY_GF0, !AY_VA3, AY_F_RES, VCC, VCC); + +-- Node name is 'AY_BINV' from file "sprint08.tdf" line 3261, column 13 +-- Equation name is 'AY_BINV', location is LC2_A15, type is buried. +AY_BINV = DFFE( _EQ025, !AY_VA3, AY_F_RES, VCC, VCC); + _EQ025 = !AY_BINV & AY_GF0 & !AY_GF1 + # !AY_BINV & !AY_GF0 & AY_GF1; + +-- Node name is 'AY_C' from file "sprint08.tdf" line 560, column 2 +-- Equation name is 'AY_C', location is LC8_A11, type is buried. +AY_C = DFFE( _EQ026, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ026 = !_EC5_A & !_EC8_A & !_LC3_A11; + +-- Node name is 'AY_CCC0' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC0', location is LC1_B20, type is buried. +AY_CCC0 = DFFE( CT0, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC1' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC1', location is LC8_A10, type is buried. +AY_CCC1 = DFFE( AY_CCC0, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC2' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC2', location is LC7_B11, type is buried. +AY_CCC2 = DFFE( CT2, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC3' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC3', location is LC3_B21, type is buried. +AY_CCC3 = DFFE( CT3, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC4' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC4', location is LC2_B24, type is buried. +AY_CCC4 = DFFE( CT4, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC5' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC5', location is LC8_A24, type is buried. +AY_CCC5 = DFFE( CT5, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC6' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC6', location is LC1_A24, type is buried. +AY_CCC6 = DFFE( CTH0, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC7' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC7', location is LC7_A8, type is buried. +AY_CCC7 = DFFE( CTH1, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CCC8' from file "sprint08.tdf" line 556, column 8 +-- Equation name is 'AY_CCC8', location is LC6_A24, type is buried. +AY_CCC8 = DFFE( CTH2, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'AY_CX' from file "sprint08.tdf" line 561, column 2 +-- Equation name is 'AY_CX', location is LC6_A9, type is buried. +!AY_CX = AY_CX~NOT; +AY_CX~NOT = DFFE(!_LC7_A9, GLOBAL( TG42), !_LC4_A9, VCC, _LC1_A9); + +-- Node name is 'AY_DAT_WR' from file "sprint08.tdf" line 571, column 2 +-- Equation name is 'AY_DAT_WR', location is LC1_A3, type is buried. +AY_DAT_WR = DFFE( _EC5_A, GLOBAL( TG42), VCC, VCC, AY_CCC1); + +-- Node name is 'AY_DAT0' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT0', location is LC7_A10, type is buried. +AY_DAT0 = DFFE( _EQ027, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ027 = _EC1_A & !_LC5_A10 + # !_EC1_A & _LC5_A10; + +-- Node name is 'AY_DAT1' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT1', location is LC8_A2, type is buried. +AY_DAT1 = DFFE( _EQ028, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ028 = !_EC7_A & !_LC6_A10 + # _EC7_A & _LC6_A10; + +-- Node name is 'AY_DAT2' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT2', location is LC5_A2, type is buried. +AY_DAT2 = DFFE( _EQ029, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ029 = !_EC3_A & !_EC7_A & !_LC6_A10 + # _EC3_A & _EC7_A + # _EC3_A & _LC6_A10; + +-- Node name is 'AY_DAT3' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT3', location is LC7_A2, type is buried. +AY_DAT3 = DFFE( _EQ030, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ030 = !_EC4_A & !_LC3_A2 + # _EC4_A & _LC3_A2; + +-- Node name is 'AY_DAT4' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT4', location is LC4_A11, type is buried. +AY_DAT4 = DFFE( _EQ031, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ031 = !_EC6_A & !_LC4_A2 + # _EC6_A & _LC4_A2; + +-- Node name is 'AY_DAT5' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT5', location is LC7_A11, type is buried. +AY_DAT5 = DFFE( _EQ032, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ032 = !_EC2_A & !_EC6_A & !_LC4_A2 + # _EC2_A & _EC6_A + # _EC2_A & _LC4_A2; + +-- Node name is 'AY_DAT6' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT6', location is LC5_A11, type is buried. +AY_DAT6 = DFFE( _EQ033, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ033 = !_EC5_A & !_LC3_A11 + # _EC5_A & _LC3_A11; + +-- Node name is 'AY_DAT7' from file "sprint08.tdf" line 572, column 8 +-- Equation name is 'AY_DAT7', location is LC6_A11, type is buried. +AY_DAT7 = DFFE( _EQ034, GLOBAL( TG42), VCC, VCC, _LC7_A3); + _EQ034 = !_EC5_A & !_EC8_A & !_LC3_A11 + # _EC5_A & _EC8_A + # _EC8_A & _LC3_A11; + +-- Node name is 'AY_DD0' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD0', location is LC5_C23, type is buried. +AY_DD0 = DFFE( _EC1_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DD1' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD1', location is LC5_C20, type is buried. +AY_DD1 = DFFE( _EC7_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DD2' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD2', location is LC7_C24, type is buried. +AY_DD2 = DFFE( _EC3_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DD3' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD3', location is LC8_C4, type is buried. +AY_DD3 = DFFE( _EC4_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DD4' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD4', location is LC8_A8, type is buried. +AY_DD4 = DFFE( _EC6_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DD5' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD5', location is LC7_B3, type is buried. +AY_DD5 = DFFE( _EC2_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DD6' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD6', location is LC6_B2, type is buried. +AY_DD6 = DFFE( _EC5_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DD7' from file "sprint08.tdf" line 580, column 7 +-- Equation name is 'AY_DD7', location is LC7_C7, type is buried. +AY_DD7 = DFFE( _EC8_A, GLOBAL( TG42), VCC, VCC, !_LC2_A8); + +-- Node name is 'AY_DI0' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI0', location is LC2_A10, type is buried. +AY_DI0 = LCELL( _EQ035); + _EQ035 = AY_CCC0 & !AY_CCC1 & MXVD0 + # AY_CCC1 & AY_DAT0 + # !AY_CCC0 & AY_DAT0; + +-- Node name is 'AY_DI1' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI1', location is LC2_A24, type is buried. +AY_DI1 = LCELL( _EQ036); + _EQ036 = AY_CCC0 & !AY_CCC1 & MXVD1 + # AY_CCC1 & AY_DAT1 + # !AY_CCC0 & AY_DAT1; + +-- Node name is 'AY_DI2' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI2', location is LC6_A12, type is buried. +AY_DI2 = LCELL( _EQ037); + _EQ037 = AY_CCC0 & !AY_CCC1 & MXVD2 + # AY_CCC1 & AY_DAT2 + # !AY_CCC0 & AY_DAT2; + +-- Node name is 'AY_DI3' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI3', location is LC2_A2, type is buried. +AY_DI3 = LCELL( _EQ038); + _EQ038 = AY_CCC0 & !AY_CCC1 & MXVD3 + # AY_CCC1 & AY_DAT3 + # !AY_CCC0 & AY_DAT3; + +-- Node name is 'AY_DI4' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI4', location is LC4_A1, type is buried. +AY_DI4 = LCELL( _EQ039); + _EQ039 = AY_CCC0 & !AY_CCC1 & MXVD4 + # AY_CCC1 & AY_DAT4 + # !AY_CCC0 & AY_DAT4; + +-- Node name is 'AY_DI5' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI5', location is LC2_A12, type is buried. +AY_DI5 = LCELL( _EQ040); + _EQ040 = AY_CCC0 & !AY_CCC1 & MXVD5 + # AY_CCC1 & AY_DAT5 + # !AY_CCC0 & AY_DAT5; + +-- Node name is 'AY_DI6' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI6', location is LC3_A1, type is buried. +AY_DI6 = LCELL( _EQ041); + _EQ041 = AY_CCC0 & !AY_CCC1 & MXVD6 + # AY_CCC1 & AY_DAT6 + # !AY_CCC0 & AY_DAT6; + +-- Node name is 'AY_DI7' from file "sprint08.tdf" line 3143, column 13 +-- Equation name is 'AY_DI7', location is LC1_A11, type is buried. +AY_DI7 = LCELL( _EQ042); + _EQ042 = AY_CCC0 & !AY_CCC1 & MXVD7 + # AY_CCC1 & AY_DAT7 + # !AY_CCC0 & AY_DAT7; + +-- Node name is 'AY_D_WR' from file "sprint08.tdf" line 3114, column 13 +-- Equation name is 'AY_D_WR', location is LC7_B16, type is buried. +!AY_D_WR = AY_D_WR~NOT; +AY_D_WR~NOT = DFFE( _EQ043, !/IOWR, GLOBAL(!/IO), VCC, VCC); + _EQ043 = DD0 & !DD1 & !DD2 & !_LC2_B5; + +-- Node name is 'AY_F_RES' from file "sprint08.tdf" line 3116, column 13 +-- Equation name is 'AY_F_RES', location is LC7_A17, type is buried. +AY_F_RES = DFFE( VCC, _LC3_A17, _LC5_A1, VCC, VCC); + +-- Node name is 'AY_GF0' from file "sprint08.tdf" line 530, column 7 +-- Equation name is 'AY_GF0', location is LC7_A15, type is buried. +AY_GF0 = DFFE( _EQ044, AY_D_WR, /RESET, VCC, VCC); + _EQ044 = D0 & !_LC7_A4 + # AY_GF0 & _LC7_A4; + +-- Node name is 'AY_GF1' from file "sprint08.tdf" line 530, column 7 +-- Equation name is 'AY_GF1', location is LC4_A15, type is buried. +AY_GF1 = DFFE( _EQ045, AY_D_WR, /RESET, VCC, VCC); + _EQ045 = D1 & !_LC7_A4 + # AY_GF1 & _LC7_A4; + +-- Node name is 'AY_GF2' from file "sprint08.tdf" line 530, column 7 +-- Equation name is 'AY_GF2', location is LC1_A15, type is buried. +AY_GF2 = DFFE( _EQ046, AY_D_WR, /RESET, VCC, VCC); + _EQ046 = D2 & !_LC7_A4 + # AY_GF2 & _LC7_A4; + +-- Node name is 'AY_GF3' from file "sprint08.tdf" line 530, column 7 +-- Equation name is 'AY_GF3', location is LC8_A15, type is buried. +AY_GF3 = DFFE( _EQ047, AY_D_WR, /RESET, VCC, VCC); + _EQ047 = D3 & !_LC7_A4 + # AY_GF3 & _LC7_A4; + +-- Node name is 'AY_OUTS1' from file "sprint08.tdf" line 3180, column 13 +-- Equation name is 'AY_OUTS1', location is LC4_A22, type is buried. +AY_OUTS1 = DFFE( _EQ048, GLOBAL( TG42), VCC, VCC, VCC); + _EQ048 = !_EC3_A & !_EC7_A & _LC2_A9 & _LC6_A22; + +-- Node name is 'AY_OUTS2' from file "sprint08.tdf" line 3181, column 13 +-- Equation name is 'AY_OUTS2', location is LC7_A7, type is buried. +AY_OUTS2 = DFFE( _EQ049, GLOBAL( TG42), VCC, VCC, VCC); + _EQ049 = !_EC1_A & !_EC3_A & _LC2_A9 & _LC5_A7; + +-- Node name is 'AY_OUTS3' from file "sprint08.tdf" line 3182, column 13 +-- Equation name is 'AY_OUTS3', location is LC6_A7, type is buried. +AY_OUTS3 = DFFE( _EQ050, GLOBAL( TG42), VCC, VCC, VCC); + _EQ050 = _EC1_A & !_EC3_A & _LC2_A9 & _LC5_A7; + +-- Node name is 'AY_OUT1' from file "sprint08.tdf" line 537, column 8 +-- Equation name is 'AY_OUT1', location is LC3_A5, type is buried. +AY_OUT1 = DFFE( _EQ051, GLOBAL( TG42), VCC, VCC, VCC); + _EQ051 = !AY_CX & AY_OUT1 + # AY_CX & AY_OUTS1 & !AY_OUT1 + # !AY_OUTS1 & AY_OUT1; + +-- Node name is 'AY_OUT2' from file "sprint08.tdf" line 537, column 8 +-- Equation name is 'AY_OUT2', location is LC2_A7, type is buried. +AY_OUT2 = DFFE( _EQ052, GLOBAL( TG42), VCC, VCC, VCC); + _EQ052 = !AY_CX & AY_OUT2 + # AY_CX & AY_OUTS2 & !AY_OUT2 + # !AY_OUTS2 & AY_OUT2; + +-- Node name is 'AY_OUT3' from file "sprint08.tdf" line 537, column 8 +-- Equation name is 'AY_OUT3', location is LC1_A12, type is buried. +AY_OUT3 = DFFE( _EQ053, GLOBAL( TG42), VCC, VCC, VCC); + _EQ053 = !AY_CX & AY_OUT3 + # AY_CX & AY_OUTS3 & !AY_OUT3 + # !AY_OUTS3 & AY_OUT3; + +-- Node name is 'AY_Q' from file "sprint08.tdf" line 3205, column 67 +-- Equation name is 'AY_Q', location is LC5_A5, type is buried. +AY_Q = LCELL( _EQ054); + _EQ054 = _LC8_A7 + # AY_OUTS1 & _LC1_A5; + +-- Node name is 'AY_Q~1' from file "sprint08.tdf" line 3205, column 67 +-- Equation name is 'AY_Q~1', location is LC8_A7, type is buried. +-- synthesized logic cell +_LC8_A7 = LCELL( _EQ055); + _EQ055 = AY_OUTS2 & _LC1_A7 + # AY_OUTS3 & _LC3_A12; + +-- Node name is 'AY_SHR' from file "sprint08.tdf" line 546, column 2 +-- Equation name is 'AY_SHR', location is LC3_A21, type is buried. +AY_SHR = DFFE( _LC1_A21, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH0' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH0', location is LC1_A17, type is buried. +AY_SH0 = DFFE( AY_SH1, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH1' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH1', location is LC8_A17, type is buried. +AY_SH1 = DFFE( AY_SH2, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH2' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH2', location is LC5_A17, type is buried. +AY_SH2 = DFFE( AY_SH3, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH3' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH3', location is LC4_A17, type is buried. +AY_SH3 = DFFE( AY_SH4, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH4' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH4', location is LC6_A17, type is buried. +AY_SH4 = DFFE( AY_SH5, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH5' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH5', location is LC6_A21, type is buried. +AY_SH5 = DFFE( AY_SH6, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH6' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH6', location is LC7_A21, type is buried. +AY_SH6 = DFFE( AY_SH7, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_SH7' from file "sprint08.tdf" line 545, column 7 +-- Equation name is 'AY_SH7', location is LC4_A21, type is buried. +AY_SH7 = DFFE( AY_SHR, GLOBAL( TG42), VCC, VCC, _LC7_A22); + +-- Node name is 'AY_VAR' from file "sprint08.tdf" line 567, column 2 +-- Equation name is 'AY_VAR', location is LC3_A23, type is buried. +AY_VAR = DFFE( _EQ056, GLOBAL( TG42), AY_F_RES, VCC, _LC3_A22); + _EQ056 = !AY_CX & AY_VAR + # AY_CX & !AY_VAR; + +-- Node name is 'AY_VA0' from file "sprint08.tdf" line 566, column 7 +-- Equation name is 'AY_VA0', location is LC8_A23, type is buried. +AY_VA0 = DFFE( _EQ057, GLOBAL( TG42), AY_F_RES, VCC, _LC3_A22); + _EQ057 = !AY_CX & AY_VA0 + # !AY_VAR & AY_VA0 + # AY_CX & AY_VAR & !AY_VA0; + +-- Node name is 'AY_VA1' from file "sprint08.tdf" line 566, column 7 +-- Equation name is 'AY_VA1', location is LC1_A23, type is buried. +AY_VA1 = DFFE( _EQ058, GLOBAL( TG42), AY_F_RES, VCC, _LC3_A22); + _EQ058 = AY_VA1 & !_LC2_A23 + # !AY_VA0 & AY_VA1 + # AY_VA0 & !AY_VA1 & _LC2_A23; + +-- Node name is 'AY_VA2' from file "sprint08.tdf" line 566, column 7 +-- Equation name is 'AY_VA2', location is LC7_A23, type is buried. +AY_VA2 = DFFE( _EQ059, GLOBAL( TG42), AY_F_RES, VCC, _LC3_A22); + _EQ059 = AY_VA2 & !_LC6_A23 + # !AY_VA2 & _LC6_A23; + +-- Node name is 'AY_VA3' from file "sprint08.tdf" line 566, column 7 +-- Equation name is 'AY_VA3', location is LC5_A23, type is buried. +AY_VA3 = DFFE( _EQ060, GLOBAL( TG42), AY_F_RES, VCC, _LC3_A22); + _EQ060 = !AY_VA2 & AY_VA3 + # AY_VA3 & !_LC6_A23 + # AY_VA2 & !AY_VA3 & _LC6_A23; + +-- Node name is 'AY_WR' from file "sprint08.tdf" line 3141, column 11 +-- Equation name is 'AY_WR', location is LC1_A10, type is buried. +AY_WR = LCELL( _EQ061); + _EQ061 = AY_CCC1 & !_LC8_A9 + # AY_CCC0 & !AY_CCC1 & !AY_D_WR; + +-- Node name is 'AY_XXM0' from file "sprint08.tdf" line 569, column 8 +-- Equation name is 'AY_XXM0', location is LC3_A14, type is buried. +AY_XXM0 = DFFE( AY_XX0, !AY_CCC8, VCC, VCC, VCC); + +-- Node name is 'AY_XXM1' from file "sprint08.tdf" line 569, column 8 +-- Equation name is 'AY_XXM1', location is LC4_A14, type is buried. +AY_XXM1 = DFFE( AY_XX1, !AY_CCC8, VCC, VCC, VCC); + +-- Node name is 'AY_XXM2' from file "sprint08.tdf" line 569, column 8 +-- Equation name is 'AY_XXM2', location is LC6_A14, type is buried. +AY_XXM2 = DFFE( AY_XX2, !AY_CCC8, VCC, VCC, VCC); + +-- Node name is 'AY_XXM3' from file "sprint08.tdf" line 569, column 8 +-- Equation name is 'AY_XXM3', location is LC8_A14, type is buried. +AY_XXM3 = DFFE( AY_XX3, !AY_CCC8, VCC, VCC, VCC); + +-- Node name is 'AY_XXM4' from file "sprint08.tdf" line 569, column 8 +-- Equation name is 'AY_XXM4', location is LC4_A24, type is buried. +AY_XXM4 = DFFE( AY_XX4, !AY_CCC8, VCC, VCC, VCC); + +-- Node name is 'AY_XXM5' from file "sprint08.tdf" line 569, column 8 +-- Equation name is 'AY_XXM5', location is LC1_A14, type is buried. +AY_XXM5 = DFFE( AY_XX5, !AY_CCC8, VCC, VCC, VCC); + +-- Node name is 'AY_XX0' from file "sprint08.tdf" line 568, column 7 +-- Equation name is 'AY_XX0', location is LC2_A5, type is buried. +AY_XX0 = DFFE( _EQ062, GLOBAL( TG42), _LC5_A24, VCC, AY_Q); + _EQ062 = !AY_AMP0 & AY_XX0 + # AY_AMP0 & !AY_XX0; + +-- Node name is 'AY_XX1' from file "sprint08.tdf" line 568, column 7 +-- Equation name is 'AY_XX1', location is LC3_A20, type is buried. +AY_XX1 = DFFE( _EQ063, GLOBAL( TG42), _LC5_A24, VCC, AY_Q); + _EQ063 = !AY_AMP1 & !AY_XX1 & _LC6_A5 + # AY_AMP1 & AY_XX1 & _LC6_A5 + # AY_AMP1 & !AY_XX1 & !_LC6_A5 + # !AY_AMP1 & AY_XX1 & !_LC6_A5; + +-- Node name is 'AY_XX2' from file "sprint08.tdf" line 568, column 7 +-- Equation name is 'AY_XX2', location is LC8_A20, type is buried. +AY_XX2 = DFFE( _EQ064, GLOBAL( TG42), _LC5_A24, VCC, AY_Q); + _EQ064 = !AY_AMP2 & !AY_XX2 & _LC2_A20 + # AY_AMP2 & AY_XX2 & _LC2_A20 + # AY_AMP2 & !AY_XX2 & !_LC2_A20 + # !AY_AMP2 & AY_XX2 & !_LC2_A20; + +-- Node name is 'AY_XX3' from file "sprint08.tdf" line 568, column 7 +-- Equation name is 'AY_XX3', location is LC5_A20, type is buried. +AY_XX3 = DFFE( _EQ065, GLOBAL( TG42), _LC5_A24, VCC, AY_Q); + _EQ065 = !AY_AMP3 & !AY_XX3 & _LC6_A20 + # AY_AMP3 & AY_XX3 & _LC6_A20 + # AY_AMP3 & !AY_XX3 & !_LC6_A20 + # !AY_AMP3 & AY_XX3 & !_LC6_A20; + +-- Node name is 'AY_XX4' from file "sprint08.tdf" line 568, column 7 +-- Equation name is 'AY_XX4', location is LC1_A20, type is buried. +AY_XX4 = DFFE( _EQ066, GLOBAL( TG42), _LC5_A24, VCC, AY_Q); + _EQ066 = AY_XX4 & !_LC7_A20 + # !AY_XX4 & _LC7_A20; + +-- Node name is 'AY_XX5' from file "sprint08.tdf" line 568, column 7 +-- Equation name is 'AY_XX5', location is LC4_A20, type is buried. +AY_XX5 = DFFE( _EQ067, GLOBAL( TG42), _LC5_A24, VCC, AY_Q); + _EQ067 = !AY_XX4 & AY_XX5 + # AY_XX5 & !_LC7_A20 + # AY_XX4 & !AY_XX5 & _LC7_A20; + +-- Node name is 'AY_X_0' from file "sprint08.tdf" line 516, column 7 +-- Equation name is 'AY_X_0', location is LC8_A5, type is buried. +AY_X_0 = DFFE( AY_DAT0, GLOBAL( TG42), VCC, VCC, _LC2_A22); + +-- Node name is 'AY_X_1' from file "sprint08.tdf" line 516, column 7 +-- Equation name is 'AY_X_1', location is LC4_A7, type is buried. +AY_X_1 = DFFE( AY_DAT1, GLOBAL( TG42), VCC, VCC, _LC2_A22); + +-- Node name is 'AY_X_2' from file "sprint08.tdf" line 516, column 7 +-- Equation name is 'AY_X_2', location is LC7_A12, type is buried. +AY_X_2 = DFFE( AY_DAT2, GLOBAL( TG42), VCC, VCC, _LC2_A22); + +-- Node name is 'AY_X_3' from file "sprint08.tdf" line 516, column 7 +-- Equation name is 'AY_X_3', location is LC7_A5, type is buried. +AY_X_3 = DFFE( AY_DAT3, GLOBAL( TG42), VCC, VCC, _LC2_A22); + +-- Node name is 'AY_X_4' from file "sprint08.tdf" line 516, column 7 +-- Equation name is 'AY_X_4', location is LC3_A7, type is buried. +AY_X_4 = DFFE( AY_DAT4, GLOBAL( TG42), VCC, VCC, _LC2_A22); + +-- Node name is 'AY_X_5' from file "sprint08.tdf" line 516, column 7 +-- Equation name is 'AY_X_5', location is LC5_A12, type is buried. +AY_X_5 = DFFE( AY_DAT5, GLOBAL( TG42), VCC, VCC, _LC2_A22); + +-- Node name is 'A0' from file "sprint08.tdf" line 700, column 29 +-- Equation name is 'A0', type is bidir +A0 = TRI(GND, GND); + +-- Node name is 'A1' from file "sprint08.tdf" line 700, column 29 +-- Equation name is 'A1', type is bidir +A1 = TRI(GND, GND); + +-- Node name is 'A2' from file "sprint08.tdf" line 700, column 29 +-- Equation name is 'A2', type is bidir +A2 = TRI(GND, GND); + +-- Node name is 'A3' from file "sprint08.tdf" line 700, column 29 +-- Equation name is 'A3', type is bidir +A3 = TRI(GND, GND); + +-- Node name is 'A4' from file "sprint08.tdf" line 702, column 3 +-- Equation name is 'A4', type is bidir +A4 = TRI(GND, GND); + +-- Node name is 'A5' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A5', type is bidir +A5 = TRI(GND, GND); + +-- Node name is 'A6' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A6', type is bidir +A6 = TRI(GND, GND); + +-- Node name is 'A7' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A7', type is bidir +A7 = TRI(GND, GND); + +-- Node name is 'A8' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A8', type is bidir +A8 = TRI(GND, GND); + +-- Node name is 'A9' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A9', type is bidir +A9 = TRI(GND, GND); + +-- Node name is 'A10' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A10', type is bidir +A10 = TRI(GND, GND); + +-- Node name is 'A11' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A11', type is bidir +A11 = TRI(GND, GND); + +-- Node name is 'A12' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A12', type is bidir +A12 = TRI(GND, GND); + +-- Node name is 'A13' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A13', type is bidir +A13 = TRI(GND, GND); + +-- Node name is 'A14' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A14', type is bidir +A14 = TRI(GND, GND); + +-- Node name is 'A15' from file "sprint08.tdf" line 701, column 29 +-- Equation name is 'A15', type is bidir +A15 = TRI(GND, GND); + +-- Node name is 'BEEPER' from file "sprint08.tdf" line 1456, column 17 +-- Equation name is 'BEEPER', type is output +BEEPER = _LC5_B24; + +-- Node name is 'BLANK' from file "sprint08.tdf" line 1727, column 10 +-- Equation name is 'BLANK', location is LC8_C16, type is buried. +!BLANK = BLANK~NOT; +BLANK~NOT = DFFE( _EQ068, CTH2, !SINC_VV, VCC, VCC); + _EQ068 = CTH4 + # !CTH5; + +-- Node name is 'BLK_R' from file "sprint08.tdf" line 767, column 10 +-- Equation name is 'BLK_R', location is LC2_B10, type is buried. +BLK_R = LCELL( _EQ069); + _EQ069 = _LC7_B10 & !/MR & /RF; + +-- Node name is 'BORD' from file "sprint08.tdf" line 1732, column 9 +-- Equation name is 'BORD', location is LC6_C18, type is buried. +BORD = DFFE( _EQ070, LWR_PIC, VCC, VCC, VCC); + _EQ070 = CTV6 & CTV7 + # CTH5 + # CTV8; + +-- Node name is 'BRD0' from file "sprint08.tdf" line 316, column 5 +-- Equation name is 'BRD0', location is LC2_B22, type is buried. +BRD0 = DFFE( D0, _LC5_B3, VCC, VCC, !_LC3_B22); + +-- Node name is 'BRD1' from file "sprint08.tdf" line 316, column 5 +-- Equation name is 'BRD1', location is LC5_B22, type is buried. +BRD1 = DFFE( D1, _LC5_B3, VCC, VCC, !_LC3_B22); + +-- Node name is 'BRD2' from file "sprint08.tdf" line 316, column 5 +-- Equation name is 'BRD2', location is LC1_B22, type is buried. +BRD2 = DFFE( D2, _LC5_B3, VCC, VCC, !_LC3_B22); + +-- Node name is 'BRD3' from file "sprint08.tdf" line 316, column 5 +-- Equation name is 'BRD3', location is LC6_B22, type is buried. +BRD3 = DFFE( D3, _LC5_B3, VCC, VCC, !_LC3_B22); + +-- Node name is 'BRD4' from file "sprint08.tdf" line 316, column 5 +-- Equation name is 'BRD4', location is LC7_B24, type is buried. +BRD4 = DFFE( D4, _LC5_B3, VCC, VCC, !_LC3_B22); + +-- Node name is 'CAS' from file "sprint08.tdf" line 1577, column 8 +-- Equation name is 'CAS', location is LC2_B14, type is buried. +CAS = DFFE( _EQ071, GLOBAL(!TG42), VCC, VCC, VCC); + _EQ071 = !AY_CCC0 & !CT2 + # AY_CCC0 & CT2; + +-- Node name is 'CAS_0' from file "sprint08.tdf" line 1612, column 2 +-- Equation name is 'CAS_0', type is output +CAS_0 = _LC5_B18; + +-- Node name is 'CAS_1' from file "sprint08.tdf" line 1613, column 2 +-- Equation name is 'CAS_1', type is output +CAS_1 = _LC4_B18; + +-- Node name is 'CAS_2' from file "sprint08.tdf" line 1614, column 2 +-- Equation name is 'CAS_2', type is output +CAS_2 = _LC2_B8; + +-- Node name is 'CAS_3' from file "sprint08.tdf" line 1615, column 2 +-- Equation name is 'CAS_3', type is output +CAS_3 = _LC7_B18; + +-- Node name is 'CLK_PIX' from file "sprint08.tdf" line 1450, column 2 +-- Equation name is 'CLK_PIX', type is output +CLK_PIX = _LC7_B23; + +-- Node name is 'CLKZ1' from file "sprint08.tdf" line 1529, column 2 +-- Equation name is 'CLKZ1', type is output +CLKZ1 = _LC7_B20; + +-- Node name is 'CNF3' from file "sprint08.tdf" line 418, column 5 +-- Equation name is 'CNF3', location is LC3_B13, type is buried. +CNF3 = DFFE( D3, _LC5_B3, /RESET, VCC, _LC7_B13); + +-- Node name is 'CNF4' from file "sprint08.tdf" line 418, column 5 +-- Equation name is 'CNF4', location is LC8_B13, type is buried. +CNF4 = DFFE( D4, _LC5_B3, /RESET, VCC, _LC7_B13); + +-- Node name is 'CORRECT_1F' from file "sprint08.tdf" line 859, column 16 +-- Equation name is 'CORRECT_1F', location is LC7_B5, type is buried. +CORRECT_1F = LCELL( _EQ072); + _EQ072 = _LC1_B5 & _LC1_C15 & !_LC5_B5 & _LC8_B5; + +-- Node name is 'CTF0' from file "sprint08.tdf" line 323, column 5 +-- Equation name is 'CTF0', location is LC2_C19, type is buried. +CTF0 = DFFE(!CTF0, !CTV8, VCC, VCC, VCC); + +-- Node name is 'CTF1' from file "sprint08.tdf" line 323, column 5 +-- Equation name is 'CTF1', location is LC1_C19, type is buried. +CTF1 = DFFE( _EQ073, !CTV8, VCC, VCC, VCC); + _EQ073 = CTF0 & !CTF1 + # !CTF0 & CTF1; + +-- Node name is 'CTF2' from file "sprint08.tdf" line 323, column 5 +-- Equation name is 'CTF2', location is LC4_C19, type is buried. +CTF2 = DFFE( _EQ074, !CTV8, VCC, VCC, VCC); + _EQ074 = CTF2 & !_LC3_C19 + # !CTF2 & _LC3_C19; + +-- Node name is 'CTF3' from file "sprint08.tdf" line 323, column 5 +-- Equation name is 'CTF3', location is LC6_C19, type is buried. +CTF3 = DFFE( _EQ075, !CTV8, VCC, VCC, VCC); + _EQ075 = !CTF2 & CTF3 + # CTF3 & !_LC3_C19 + # CTF2 & !CTF3 & _LC3_C19; + +-- Node name is 'CTF4' from file "sprint08.tdf" line 323, column 5 +-- Equation name is 'CTF4', location is LC7_C19, type is buried. +CTF4 = DFFE( _EQ076, !CTV8, VCC, VCC, VCC); + _EQ076 = !CTF2 & CTF4 + # CTF4 & !_LC3_C19 + # !CTF3 & CTF4 + # CTF2 & CTF3 & !CTF4 & _LC3_C19; + +-- Node name is 'CTH0' from file "sprint08.tdf" line 321, column 5 +-- Equation name is 'CTH0', location is LC4_A18, type is buried. +CTH0 = DFFE(!CTH0, !CT5, VCC, VCC, VCC); + +-- Node name is 'CTH1' from file "sprint08.tdf" line 321, column 5 +-- Equation name is 'CTH1', location is LC6_A18, type is buried. +CTH1 = DFFE( _EQ077, !CT5, VCC, VCC, VCC); + _EQ077 = !CTH0 & CTH1 + # CTH0 & !CTH1; + +-- Node name is 'CTH2' from file "sprint08.tdf" line 321, column 5 +-- Equation name is 'CTH2', location is LC2_A18, type is buried. +CTH2 = DFFE( _EQ078, !CT5, VCC, VCC, VCC); + _EQ078 = !CTH1 & CTH2 + # !CTH0 & CTH2 + # CTH0 & CTH1 & !CTH2; + +-- Node name is 'CTH3' from file "sprint08.tdf" line 321, column 5 +-- Equation name is 'CTH3', location is LC3_C17, type is buried. +CTH3 = DFFE( _EQ079, !CTH2, VCC, VCC, VCC); + _EQ079 = !CTH3 & !CTH4 + # !CTH3 & !CTH5; + +-- Node name is 'CTH4' from file "sprint08.tdf" line 321, column 5 +-- Equation name is 'CTH4', location is LC5_C17, type is buried. +CTH4 = DFFE( _EQ080, !CTH2, VCC, VCC, VCC); + _EQ080 = CTH3 & !CTH4 + # !CTH3 & CTH4 & !CTH5; + +-- Node name is 'CTH5' from file "sprint08.tdf" line 321, column 5 +-- Equation name is 'CTH5', location is LC6_C17, type is buried. +CTH5 = DFFE( _EQ081, !CTH2, VCC, VCC, VCC); + _EQ081 = !CTH4 & CTH5 + # CTH3 & CTH4 & !CTH5; + +-- Node name is 'CTV0' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV0', location is LC5_C15, type is buried. +CTV0 = DFFE(!CTV0, SINC_HH, VCC, VCC, VCC); + +-- Node name is 'CTV1' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV1', location is LC2_C15, type is buried. +CTV1 = DFFE( _EQ082, SINC_HH, VCC, VCC, VCC); + _EQ082 = CTV0 & !CTV1 + # !CTV0 & CTV1; + +-- Node name is 'CTV2' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV2', location is LC3_C15, type is buried. +CTV2 = DFFE( _EQ083, SINC_HH, VCC, VCC, VCC); + _EQ083 = !CTV0 & CTV2 + # !CTV1 & CTV2 + # CTV0 & CTV1 & !CTV2; + +-- Node name is 'CTV3' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV3', location is LC1_C21, type is buried. +CTV3 = DFFE(!CTV3, !CTV2, VCC, VCC, VCC); + +-- Node name is 'CTV4' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV4', location is LC4_C21, type is buried. +CTV4 = DFFE( _EQ084, !CTV2, VCC, VCC, VCC); + _EQ084 = !CTV3 & CTV4 & _LC3_C18 + # CTV3 & !CTV4 & _LC3_C18; + +-- Node name is 'CTV5' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV5', location is LC2_C21, type is buried. +CTV5 = DFFE( _EQ085, !CTV2, VCC, VCC, VCC); + _EQ085 = !CTV4 & CTV5 & _LC3_C18 + # !CTV3 & CTV5 & _LC3_C18 + # CTV3 & CTV4 & !CTV5 & _LC3_C18; + +-- Node name is 'CTV6' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV6', location is LC2_C18, type is buried. +CTV6 = DFFE( _EQ086, !CTV2, VCC, VCC, VCC); + _EQ086 = CTV6 & _LC3_C18 & !_LC3_C21 + # !CTV6 & _LC3_C18 & _LC3_C21; + +-- Node name is 'CTV7' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV7', location is LC1_C18, type is buried. +CTV7 = DFFE( _EQ087, !CTV2, VCC, VCC, VCC); + _EQ087 = !CTV6 & CTV7 & _LC3_C18 + # CTV7 & _LC3_C18 & !_LC3_C21 + # CTV6 & !CTV7 & _LC3_C18 & _LC3_C21; + +-- Node name is 'CTV8' from file "sprint08.tdf" line 322, column 5 +-- Equation name is 'CTV8', location is LC5_C18, type is buried. +CTV8 = DFFE( _EQ088, !CTV2, VCC, VCC, VCC); + _EQ088 = CTV8 & !_LC3_C21 + # CTV6 & CTV7 & !CTV8 & _LC3_C21; + +-- Node name is 'CT0' from file "sprint08.tdf" line 296, column 4 +-- Equation name is 'CT0', location is LC8_B20, type is buried. +CT0 = DFFE( _EQ089, GLOBAL( TG42), VCC, VCC, VCC); + _EQ089 = !AY_CCC0 & !CT0; + +-- Node name is 'CT2' from file "sprint08.tdf" line 296, column 4 +-- Equation name is 'CT2', location is LC3_B20, type is buried. +CT2 = DFFE( _EQ090, GLOBAL( TG42), VCC, VCC, VCC); + _EQ090 = AY_CCC0 & !CT2 + # !AY_CCC0 & CT2; + +-- Node name is 'CT3' from file "sprint08.tdf" line 296, column 4 +-- Equation name is 'CT3', location is LC3_B24, type is buried. +CT3 = DFFE( _EQ091, GLOBAL( TG42), VCC, VCC, VCC); + _EQ091 = AY_CCC0 & CT2 & !CT3 + # !CT2 & CT3 + # !AY_CCC0 & CT3; + +-- Node name is 'CT4' from file "sprint08.tdf" line 296, column 4 +-- Equation name is 'CT4', location is LC1_B24, type is buried. +CT4 = DFFE( _EQ092, GLOBAL( TG42), VCC, VCC, VCC); + _EQ092 = !CT2 & CT4 + # !CT3 & CT4 + # AY_CCC0 & CT2 & CT3 & !CT4 + # !AY_CCC0 & CT4; + +-- Node name is 'CT5' from file "sprint08.tdf" line 296, column 4 +-- Equation name is 'CT5', location is LC8_B24, type is buried. +CT5 = DFFE( _EQ093, GLOBAL( TG42), VCC, VCC, VCC); + _EQ093 = CT5 & !_LC4_B24 + # !CT4 & CT5 + # AY_CCC0 & CT4 & !CT5 & _LC4_B24 + # !AY_CCC0 & CT5; + +-- Node name is 'DCOL0' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL0', location is LC6_B19, type is buried. +DCOL0 = DFFE( _EQ094, LWR_COL, !BLANK, VCC, VCC); + _EQ094 = BORD & BRD0 + # !BORD & VD00; + +-- Node name is 'DCOL1' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL1', location is LC1_B19, type is buried. +DCOL1 = DFFE( _EQ095, LWR_COL, !BLANK, VCC, VCC); + _EQ095 = BORD & BRD1 + # !BORD & VD01; + +-- Node name is 'DCOL2' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL2', location is LC4_B22, type is buried. +DCOL2 = DFFE( _EQ096, LWR_COL, !BLANK, VCC, VCC); + _EQ096 = BORD & BRD2 + # !BORD & VD02; + +-- Node name is 'DCOL3' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL3', location is LC2_B19, type is buried. +DCOL3 = DFFE( _EQ097, LWR_COL, !BLANK, VCC, VCC); + _EQ097 = !BORD & VD03 + # BORD & BRD0; + +-- Node name is 'DCOL4' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL4', location is LC5_B19, type is buried. +DCOL4 = DFFE( _EQ098, LWR_COL, !BLANK, VCC, VCC); + _EQ098 = !BORD & VD04 + # BORD & BRD1; + +-- Node name is 'DCOL5' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL5', location is LC8_B22, type is buried. +DCOL5 = DFFE( _EQ099, LWR_COL, !BLANK, VCC, VCC); + _EQ099 = !BORD & VD05 + # BORD & BRD2; + +-- Node name is 'DCOL6' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL6', location is LC8_B19, type is buried. +DCOL6 = DFFE( _EQ100, LWR_COL, !BLANK, VCC, VCC); + _EQ100 = !BORD & VD06; + +-- Node name is 'DCOL7' from file "sprint08.tdf" line 351, column 6 +-- Equation name is 'DCOL7', location is LC7_B19, type is buried. +DCOL7 = DFFE( _EQ101, LWR_COL, !BLANK, VCC, VCC); + _EQ101 = !BORD & VD07; + +-- Node name is 'DCP_CX' from file "sprint08.tdf" line 1302, column 11 +-- Equation name is 'DCP_CX', location is LC1_B3, type is buried. +DCP_CX = LCELL( _EQ102); + _EQ102 = !DCP4 & !DCP5 & DD6 & DD7; + +-- Node name is 'DCP3' from file "sprint08.tdf" line 298, column 5 +-- Equation name is 'DCP3', location is LC6_B5, type is buried. +DCP3 = DFFE( _EQ103, LMC_END, !CORRECT_1F, VCC, VCC); + _EQ103 = !/IO & _LC5_B9 & SC4 + # /IO & MD3 + # !_LC5_B9 & MD3; + +-- Node name is 'DCP4' from file "sprint08.tdf" line 298, column 5 +-- Equation name is 'DCP4', location is LC1_B9, type is buried. +DCP4 = DFFE( _EQ104, LMC_END, !CORRECT_1F, VCC, VCC); + _EQ104 = !/IO & _LC5_B9 + # MD4; + +-- Node name is 'DCP5' from file "sprint08.tdf" line 298, column 5 +-- Equation name is 'DCP5', location is LC7_B9, type is buried. +DCP5 = DFFE( _EQ105, LMC_END, VCC, VCC, VCC); + _EQ105 = !/IO & _LC5_B9 + # MD5; + +-- Node name is 'DD0' from file "sprint08.tdf" line 299, column 4 +-- Equation name is 'DD0', location is LC8_B9, type is buried. +DD0 = DFFE( _EQ106, LMC_END, VCC, VCC, VCC); + _EQ106 = !/IO & _LC5_B9 & PN0 + # /IO & MD0 + # !_LC5_B9 & MD0; + +-- Node name is 'DD1' from file "sprint08.tdf" line 299, column 4 +-- Equation name is 'DD1', location is LC4_B9, type is buried. +DD1 = DFFE( _EQ107, LMC_END, VCC, VCC, VCC); + _EQ107 = !/IO & _LC5_B9 & PN1 + # /IO & MD1 + # !_LC5_B9 & MD1; + +-- Node name is 'DD2' from file "sprint08.tdf" line 299, column 4 +-- Equation name is 'DD2', location is LC2_B9, type is buried. +DD2 = DFFE( _EQ108, LMC_END, VCC, VCC, VCC); + _EQ108 = !/IO & _LC5_B9 & PN2 + # /IO & MD2 + # !_LC5_B9 & MD2; + +-- Node name is 'DD6' from file "sprint08.tdf" line 299, column 4 +-- Equation name is 'DD6', location is LC3_B9, type is buried. +DD6 = DFFE( _EQ109, LMC_END, VCC, VCC, VCC); + _EQ109 = !/IO & _LC5_B9 + # MD6; + +-- Node name is 'DD7' from file "sprint08.tdf" line 299, column 4 +-- Equation name is 'DD7', location is LC6_B9, type is buried. +DD7 = DFFE( _EQ110, LMC_END, VCC, VCC, VCC); + _EQ110 = !/IO & _LC5_B9 + # MD7; + +-- Node name is 'DOS' from file "sprint08.tdf" line 1378, column 10 +-- Equation name is 'DOS', location is LC5_C8, type is buried. +!DOS = DOS~NOT; +DOS~NOT = DFFE( _EQ111, !_LC6_B4, /RESET, VCC, VCC); + _EQ111 = !A14 & !A15 & !DOS + # !A14 & !A15 & _LC6_C8; + +-- Node name is 'DOS_ON_' from file "sprint08.tdf" line 1379, column 13 +-- Equation name is 'DOS_ON_', location is LC4_B11, type is buried. +DOS_ON_ = DFFE( _EQ112, AY_CCC2, VCC, VCC, VCC); + _EQ112 = !_LC3_B11 + # DOS; + +-- Node name is 'DPIC' from file "sprint08.tdf" line 350, column 2 +-- Equation name is 'DPIC', location is LC1_C2, type is buried. +DPIC = DFFE( D_PIC07, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'D_PIC00' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC00', location is LC2_B15, type is buried. +D_PIC00 = DFFE( VD00, LWR_PIC, VCC, VCC, VCC); + +-- Node name is 'D_PIC01' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC01', location is LC3_B15, type is buried. +D_PIC01 = DFFE( _EQ113, LWR_PIC, VCC, VCC, VCC); + _EQ113 = LD_PIC & VD01 + # D_PIC00 & !LD_PIC; + +-- Node name is 'D_PIC02' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC02', location is LC4_B15, type is buried. +D_PIC02 = DFFE( _EQ114, LWR_PIC, VCC, VCC, VCC); + _EQ114 = LD_PIC & VD02 + # D_PIC01 & !LD_PIC; + +-- Node name is 'D_PIC03' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC03', location is LC5_B15, type is buried. +D_PIC03 = DFFE( _EQ115, LWR_PIC, VCC, VCC, VCC); + _EQ115 = LD_PIC & VD03 + # D_PIC02 & !LD_PIC; + +-- Node name is 'D_PIC04' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC04', location is LC6_B15, type is buried. +D_PIC04 = DFFE( _EQ116, LWR_PIC, VCC, VCC, VCC); + _EQ116 = LD_PIC & VD04 + # D_PIC03 & !LD_PIC; + +-- Node name is 'D_PIC05' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC05', location is LC7_B15, type is buried. +D_PIC05 = DFFE( _EQ117, LWR_PIC, VCC, VCC, VCC); + _EQ117 = LD_PIC & VD05 + # D_PIC04 & !LD_PIC; + +-- Node name is 'D_PIC06' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC06', location is LC8_B15, type is buried. +D_PIC06 = DFFE( _EQ118, LWR_PIC, VCC, VCC, VCC); + _EQ118 = LD_PIC & VD06 + # D_PIC05 & !LD_PIC; + +-- Node name is 'D_PIC07' from file "sprint08.tdf" line 353, column 8 +-- Equation name is 'D_PIC07', location is LC1_B15, type is buried. +D_PIC07 = DFFE( _EQ119, LWR_PIC, VCC, VCC, VCC); + _EQ119 = LD_PIC & VD07 + # D_PIC06 & !LD_PIC; + +-- Node name is 'D_RD' from file "sprint08.tdf" line 1415, column 38 +-- Equation name is 'D_RD', location is LC1_B4, type is buried. +D_RD = LCELL( _EQ120); + _EQ120 = !_LC5_B4 + # !/IOM1 & _LC5_B5 & !/RD; + +-- Node name is 'D0' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D0', type is bidir +D0 = TRI(SD0, D_RD); + +-- Node name is 'D1' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D1', type is bidir +D1 = TRI(SD1, D_RD); + +-- Node name is 'D2' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D2', type is bidir +D2 = TRI(SD2, D_RD); + +-- Node name is 'D3' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D3', type is bidir +D3 = TRI(SD3, D_RD); + +-- Node name is 'D4' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D4', type is bidir +D4 = TRI(SD4, D_RD); + +-- Node name is 'D5' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D5', type is bidir +D5 = TRI(SD5, D_RD); + +-- Node name is 'D6' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D6', type is bidir +D6 = TRI(SD6, D_RD); + +-- Node name is 'D7' from file "sprint08.tdf" line 1418, column 4 +-- Equation name is 'D7', type is bidir +D7 = TRI(SD7, D_RD); + +-- Node name is 'E_CAS_0' from file "sprint08.tdf" line 1600, column 12 +-- Equation name is 'E_CAS_0', location is LC3_B18, type is buried. +E_CAS_0 = DFFE( _EQ121, !AY_CCC2, VCC, VCC, VCC); + _EQ121 = _LC2_B18 + # AA10 & /IO + # DOS & !/IO; + +-- Node name is 'E_CAS_1' from file "sprint08.tdf" line 1601, column 12 +-- Equation name is 'E_CAS_1', location is LC6_B18, type is buried. +E_CAS_1 = DFFE( _EQ122, !AY_CCC2, VCC, VCC, VCC); + _EQ122 = !AA10 & /IO + # !AA10 & !DOS + # !DOS & !/IO + # _LC2_B18; + +-- Node name is 'E_CAS_2' from file "sprint08.tdf" line 1602, column 12 +-- Equation name is 'E_CAS_2', location is LC1_B18, type is buried. +E_CAS_2 = DFFE( _EQ123, !AY_CCC2, VCC, VCC, VCC); + _EQ123 = !AA11 + # !/IO + # BLK_R + # !AA10; + +-- Node name is 'E_CAS_3' from file "sprint08.tdf" line 1603, column 12 +-- Equation name is 'E_CAS_3', location is LC8_B18, type is buried. +E_CAS_3 = DFFE( _EQ124, !AY_CCC2, VCC, VCC, VCC); + _EQ124 = !AA11 + # !/IO + # BLK_R + # AA10; + +-- Node name is 'IN_OUT_CMD' from file "sprint08.tdf" line 504, column 2 +-- Equation name is 'IN_OUT_CMD', location is LC2_A6, type is buried. +IN_OUT_CMD = DFFE( _EQ125, _LC6_B4, GLOBAL( /IO), VCC, VCC); + _EQ125 = !D5 & _LC3_A6 & _LC5_A15 & !PRF_CMD; + +-- Node name is 'INTT' from file "sprint08.tdf" line 1495, column 9 +-- Equation name is 'INTT', location is LC1_C22, type is buried. +!INTT = INTT~NOT; +INTT~NOT = DFFE( VCC, _LC5_C22, _LC2_C22, VCC, VCC); + +-- Node name is 'IO_WAIT~1' from file "sprint08.tdf" line 1559, column 48 +-- Equation name is 'IO_WAIT~1', location is LC2_B7, type is buried. +-- synthesized logic cell +_LC2_B7 = LCELL( _EQ126); + _EQ126 = _LC6_B7 & LMC_END + # !/M1 + # /IO; + +-- Node name is 'KA8' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA8', location is LC3_C9, type is buried. +KA8 = LCELL( _EQ127); + _EQ127 = KB_D1 & _LC5_C9 + # KDD6 & !_LC5_C9 + # !_LC4_C6; + +-- Node name is 'KA9' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA9', location is LC7_C9, type is buried. +KA9 = LCELL( _EQ128); + _EQ128 = KB_D2 & _LC5_C9 + # KDD7 & !_LC5_C9 + # !_LC4_C6; + +-- Node name is 'KA10' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA10', location is LC4_C4, type is buried. +KA10 = LCELL( _EQ129); + _EQ129 = KDCA0 & !_LC4_C6 + # KB_D3 & _LC4_C6 & _LC5_C9; + +-- Node name is 'KA11' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA11', location is LC2_C12, type is buried. +KA11 = LCELL( _EQ130); + _EQ130 = KDCA1 & !_LC4_C6 + # KB_D4 & _LC4_C6 & _LC5_C9; + +-- Node name is 'KA12' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA12', location is LC1_C7, type is buried. +KA12 = LCELL( _EQ131); + _EQ131 = KDCA2 & !_LC4_C6 + # KB_D5 & _LC4_C6 & _LC5_C9; + +-- Node name is 'KA13' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA13', location is LC1_C9, type is buried. +KA13 = LCELL( _EQ132); + _EQ132 = KB_D6 & _LC5_C9 + # !_LC4_C6; + +-- Node name is 'KA14' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA14', location is LC2_C9, type is buried. +KA14 = LCELL( _EQ133); + _EQ133 = _LC4_C6 & !_LC5_C9 + # KB_D7 & _LC4_C6; + +-- Node name is 'KA15' from file "sprint08.tdf" line 2516, column 27 +-- Equation name is 'KA15', location is LC8_C9, type is buried. +KA15 = LCELL( _EQ134); + _EQ134 = KB_D8 + # !_LC5_C9 + # !_LC4_C6; + +-- Node name is 'KB_ALT' from file "sprint08.tdf" line 409, column 2 +-- Equation name is 'KB_ALT', location is LC2_C5, type is buried. +KB_ALT = DFFE( _EQ135, !KB_CT2, VCC, VCC, VCC); + _EQ135 = KB_ALT & !KB_ALT_X + # KB_ALT & !KB_XXX + # KB_ALT_X & !KB_OFF & KB_XXX; + +-- Node name is 'KB_ALT_X' from file "sprint08.tdf" line 2460, column 13 +-- Equation name is 'KB_ALT_X', location is LC5_C1, type is buried. +KB_ALT_X = LCELL( _EQ136); + _EQ136 = KB_D1 & !KB_D2 & !KB_D3 & KB_D5; + +-- Node name is 'KB_CTRL' from file "sprint08.tdf" line 408, column 2 +-- Equation name is 'KB_CTRL', location is LC3_C5, type is buried. +KB_CTRL = DFFE( _EQ137, !KB_CT2, VCC, VCC, VCC); + _EQ137 = KB_CTRL & !KB_CTRL_X + # KB_CTRL & !KB_XXX + # KB_CTRL_X & !KB_OFF & KB_XXX; + +-- Node name is 'KB_CTRL_X' from file "sprint08.tdf" line 2459, column 14 +-- Equation name is 'KB_CTRL_X', location is LC6_C1, type is buried. +KB_CTRL_X = LCELL( _EQ138); + _EQ138 = !KB_D1 & !KB_D2 & KB_D3 & KB_D5; + +-- Node name is 'KB_CT0' from file "sprint08.tdf" line 407, column 7 +-- Equation name is 'KB_CT0', location is LC8_C3, type is buried. +!KB_CT0 = KB_CT0~NOT; +KB_CT0~NOT = DFFE( _EQ139, CTH5, KBD_CC, VCC, VCC); + _EQ139 = KB_CT0 + # !KB_CT1 & !KB_CT2; + +-- Node name is 'KB_CT1' from file "sprint08.tdf" line 407, column 7 +-- Equation name is 'KB_CT1', location is LC6_C3, type is buried. +!KB_CT1 = KB_CT1~NOT; +KB_CT1~NOT = DFFE( _EQ140, CTH5, KBD_CC, VCC, VCC); + _EQ140 = !KB_CT1 & !KB_CT2 + # KB_CT0 & !KB_CT1 + # !KB_CT0 & KB_CT1; + +-- Node name is 'KB_CT2' from file "sprint08.tdf" line 407, column 7 +-- Equation name is 'KB_CT2', location is LC3_C3, type is buried. +!KB_CT2 = KB_CT2~NOT; +KB_CT2~NOT = DFFE( _EQ141, CTH5, KBD_CC, VCC, VCC); + _EQ141 = !KB_CT2 + # !KB_CT0 & !KB_CT1; + +-- Node name is 'KBD_CC' from file "sprint08.tdf" line 1474, column 11 +-- Equation name is 'KBD_CC', location is LC2_C16, type is buried. +KBD_CC = DFFE( KBD_CLK, CTH2, VCC, VCC, VCC); + +-- Node name is 'KBD_CLK' from file "sprint08.tdf" line 1477, column 2 +-- Equation name is 'KBD_CLK', type is bidir +KBD_CLK = TRI(VCC, GND); + +-- Node name is 'KBD_DAT' from file "sprint08.tdf" line 1478, column 2 +-- Equation name is 'KBD_DAT', type is bidir +KBD_DAT = TRI(VCC, GND); + +-- Node name is 'KBD_DD' from file "sprint08.tdf" line 1475, column 11 +-- Equation name is 'KBD_DD', location is LC7_C16, type is buried. +KBD_DD = DFFE( KBD_DAT, CTH2, VCC, VCC, VCC); + +-- Node name is 'KBD0' from file "sprint08.tdf" line 421, column 5 +-- Equation name is 'KBD0', location is LC4_C23, type is buried. +!KBD0 = KBD0~NOT; +KBD0~NOT = DFFE( _EQ142, GLOBAL( TG42), VCC, VCC, VCC); + _EQ142 = !KBD0 + # !_EC3_C & !KB_MXA; + +-- Node name is 'KBD1' from file "sprint08.tdf" line 421, column 5 +-- Equation name is 'KBD1', location is LC3_C20, type is buried. +!KBD1 = KBD1~NOT; +KBD1~NOT = DFFE( _EQ143, GLOBAL( TG42), VCC, VCC, VCC); + _EQ143 = !KBD1 + # !_EC7_C & !KB_MXA; + +-- Node name is 'KB_D1' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D1', location is LC1_C1, type is buried. +KB_D1 = DFFE( KB_D2, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KBD2' from file "sprint08.tdf" line 421, column 5 +-- Equation name is 'KBD2', location is LC6_C24, type is buried. +!KBD2 = KBD2~NOT; +KBD2~NOT = DFFE( _EQ144, GLOBAL( TG42), VCC, VCC, VCC); + _EQ144 = !KBD2 + # !_EC6_C & !KB_MXA; + +-- Node name is 'KB_D2' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D2', location is LC2_C1, type is buried. +KB_D2 = DFFE( KB_D3, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KBD3' from file "sprint08.tdf" line 421, column 5 +-- Equation name is 'KBD3', location is LC7_C4, type is buried. +!KBD3 = KBD3~NOT; +KBD3~NOT = DFFE( _EQ145, GLOBAL( TG42), VCC, VCC, VCC); + _EQ145 = !KBD3 + # !_EC1_C & !KB_MXA; + +-- Node name is 'KB_D3' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D3', location is LC7_C14, type is buried. +KB_D3 = DFFE( KB_D4, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KBD4' from file "sprint08.tdf" line 421, column 5 +-- Equation name is 'KBD4', location is LC7_C12, type is buried. +!KBD4 = KBD4~NOT; +KBD4~NOT = DFFE( _EQ146, GLOBAL( TG42), VCC, VCC, VCC); + _EQ146 = !KBD4 + # !_EC5_C & !KB_MXA; + +-- Node name is 'KB_D4' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D4', location is LC5_C14, type is buried. +KB_D4 = DFFE( KB_D5, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KBD5' from file "sprint08.tdf" line 421, column 5 +-- Equation name is 'KBD5', location is LC5_C7, type is buried. +!KBD5 = KBD5~NOT; +KBD5~NOT = DFFE( _EQ147, GLOBAL( TG42), VCC, VCC, VCC); + _EQ147 = !KBD5 + # !_EC4_C & !KB_MXA; + +-- Node name is 'KB_D5' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D5', location is LC1_C14, type is buried. +KB_D5 = DFFE( KB_D6, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KB_D6' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D6', location is LC6_C14, type is buried. +KB_D6 = DFFE( KB_D7, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KB_D7' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D7', location is LC2_C14, type is buried. +KB_D7 = DFFE( KB_D8, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KB_D8' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D8', location is LC4_C14, type is buried. +KB_D8 = DFFE( KB_D9, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KB_D9' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D9', location is LC8_C14, type is buried. +KB_D9 = DFFE( KB_D10, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KB_D10' from file "sprint08.tdf" line 405, column 6 +-- Equation name is 'KB_D10', location is LC3_C14, type is buried. +KB_D10 = DFFE( KBD_DD, KBD_CC, VCC, VCC, VCC); + +-- Node name is 'KB_EXT' from file "sprint08.tdf" line 411, column 2 +-- Equation name is 'KB_EXT', location is LC4_C1, type is buried. +KB_EXT = DFFE( _EQ148, !_LC2_C3, VCC, VCC, VCC); + _EQ148 = !KB_D5 & _LC3_C1; + +-- Node name is 'KB_F12' from file "sprint08.tdf" line 2479, column 12 +-- Equation name is 'KB_F12', location is LC4_C5, type is buried. +!KB_F12 = KB_F12~NOT; +KB_F12~NOT = DFFE( _EQ149, !KB_CT2, _LC2_C3, VCC, VCC); + _EQ149 = !KB_OFF & KB_XXX & _LC8_C1; + +-- Node name is 'KB_MA0' from file "sprint08.tdf" line 583, column 7 +-- Equation name is 'KB_MA0', location is LC4_C8, type is buried. +KB_MA0 = DFFE(!KB_MA0, GLOBAL( TG42), GLOBAL(!/IO), VCC, VCC); + +-- Node name is 'KB_MA1' from file "sprint08.tdf" line 583, column 7 +-- Equation name is 'KB_MA1', location is LC1_C12, type is buried. +KB_MA1 = DFFE( _EQ150, GLOBAL( TG42), GLOBAL(!/IO), VCC, VCC); + _EQ150 = !KB_MA0 & KB_MA1 + # KB_MA0 & !KB_MA1; + +-- Node name is 'KB_MA2' from file "sprint08.tdf" line 583, column 7 +-- Equation name is 'KB_MA2', location is LC8_C12, type is buried. +KB_MA2 = DFFE( _EQ151, GLOBAL( TG42), GLOBAL(!/IO), VCC, VCC); + _EQ151 = !KB_MA1 & KB_MA2 + # !KB_MA0 & KB_MA2 + # KB_MA0 & KB_MA1 & !KB_MA2; + +-- Node name is 'KB_MXA' from file "sprint08.tdf" line 2523, column 11 +-- Equation name is 'KB_MXA', location is LC6_C12, type is buried. +KB_MXA = DFFE( _EQ152, GLOBAL( TG42), VCC, VCC, VCC); + _EQ152 = KB_MA1 & _LC7_C8 + # KB_MA1 & _LC5_C12 + # !KB_MA1 & _LC8_C8; + +-- Node name is 'KB_OFF' from file "sprint08.tdf" line 406, column 2 +-- Equation name is 'KB_OFF', location is LC5_C3, type is buried. +KB_OFF = DFFE( _EQ153, !_LC4_C3, VCC, VCC, VCC); + _EQ153 = KB_D5 & !KB_EXT & _LC3_C1 + # KB_EXT & KB_OFF; + +-- Node name is 'KB_RESET' from file "sprint08.tdf" line 412, column 2 +-- Equation name is 'KB_RESET', location is LC6_C5, type is buried. +!KB_RESET = KB_RESET~NOT; +KB_RESET~NOT = DFFE( _EQ154, !KB_CT2, _LC2_C3, VCC, VCC); + _EQ154 = KB_ALT_X & KB_D6 & KB_D7 & _LC8_C5; + +-- Node name is 'KB_XXX' from file "sprint08.tdf" line 2465, column 12 +-- Equation name is 'KB_XXX', location is LC1_C5, type is buried. +KB_XXX = LCELL( _EQ155); + _EQ155 = !KB_D4 & !KB_D6 & !KB_D7 & !KB_D8; + +-- Node name is 'K_CLK' from file "sprint08.tdf" line 2490, column 11 +-- Equation name is 'K_CLK', location is LC3_B10, type is buried. +K_CLK = DFFE( /RF, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'KDCA0' from file "sprint08.tdf" line 2537, column 10 +-- Equation name is 'KDCA0', location is LC6_C4, type is buried. +KDCA0 = LCELL( _EQ156); + _EQ156 = /IO & KDD3 + # !/IO & KB_MA0; + +-- Node name is 'KDCA1' from file "sprint08.tdf" line 2537, column 10 +-- Equation name is 'KDCA1', location is LC4_C12, type is buried. +KDCA1 = LCELL( _EQ157); + _EQ157 = /IO & KDD4 + # !/IO & KB_MA1; + +-- Node name is 'KDCA2' from file "sprint08.tdf" line 2537, column 10 +-- Equation name is 'KDCA2', location is LC4_C7, type is buried. +KDCA2 = LCELL( _EQ158); + _EQ158 = /IO & KDD5 + # !/IO & KB_MA2; + +-- Node name is 'KDD3' from file "sprint08.tdf" line 423, column 5 +-- Equation name is 'KDD3', location is LC5_C4, type is buried. +KDD3 = DFFE( _EC1_C, RXA0, VCC, VCC, VCC); + +-- Node name is 'KDD4' from file "sprint08.tdf" line 423, column 5 +-- Equation name is 'KDD4', location is LC3_C12, type is buried. +KDD4 = DFFE( _EC5_C, RXA0, VCC, VCC, VCC); + +-- Node name is 'KDD5' from file "sprint08.tdf" line 423, column 5 +-- Equation name is 'KDD5', location is LC2_C7, type is buried. +KDD5 = DFFE( _EC4_C, RXA0, VCC, VCC, VCC); + +-- Node name is 'KDD6' from file "sprint08.tdf" line 423, column 5 +-- Equation name is 'KDD6', location is LC6_C9, type is buried. +!KDD6 = KDD6~NOT; +KDD6~NOT = DFFE(!_EC8_C, RXA0, !KB_CT2, VCC, VCC); + +-- Node name is 'KDD7' from file "sprint08.tdf" line 423, column 5 +-- Equation name is 'KDD7', location is LC4_C9, type is buried. +!KDD7 = KDD7~NOT; +KDD7~NOT = DFFE(!_EC2_C, RXA0, !KB_CT2, VCC, VCC); + +-- Node name is 'KDXX0' from file "sprint08.tdf" line 627, column 6 +-- Equation name is 'KDXX0', location is LC2_C11, type is buried. +KDXX0 = DFFE( _EQ159, RXA0, VCC, VCC, VCC); + _EQ159 = _EC6_C + # _EC7_C + # _EC3_C; + +-- Node name is 'KDXX1' from file "sprint08.tdf" line 627, column 6 +-- Equation name is 'KDXX1', location is LC3_C11, type is buried. +KDXX1 = DFFE( _EQ160, RXA0, VCC, VCC, VCC); + _EQ160 = _EC6_C + # _EC7_C + # !_EC3_C; + +-- Node name is 'KDXX2' from file "sprint08.tdf" line 627, column 6 +-- Equation name is 'KDXX2', location is LC5_C11, type is buried. +KDXX2 = DFFE( _EQ161, RXA0, VCC, VCC, VCC); + _EQ161 = _EC6_C + # !_EC7_C + # _EC3_C; + +-- Node name is 'KDXX3' from file "sprint08.tdf" line 627, column 6 +-- Equation name is 'KDXX3', location is LC7_C11, type is buried. +KDXX3 = DFFE( _EQ162, RXA0, VCC, VCC, VCC); + _EQ162 = _EC6_C + # !_EC7_C + # !_EC3_C; + +-- Node name is 'KDXX4' from file "sprint08.tdf" line 627, column 6 +-- Equation name is 'KDXX4', location is LC1_C11, type is buried. +KDXX4 = DFFE( _EQ163, RXA0, VCC, VCC, VCC); + _EQ163 = !_EC6_C + # _EC7_C + # _EC3_C; + +-- Node name is 'KDXX5' from file "sprint08.tdf" line 627, column 6 +-- Equation name is 'KDXX5', location is LC8_C11, type is buried. +KDXX5 = DFFE( _EQ164, RXA0, VCC, VCC, VCC); + _EQ164 = _EC7_C + # !_EC3_C + # !_EC6_C; + +-- Node name is 'KDX0' from file "sprint08.tdf" line 424, column 5 +-- Equation name is 'KDX0', location is LC6_C11, type is buried. +KDX0 = DFFE( _EQ165, RXA1, VCC, VCC, VCC); + _EQ165 = _EC3_C & KDXX0 + # KB_OFF & !KDXX0; + +-- Node name is 'KDX1' from file "sprint08.tdf" line 424, column 5 +-- Equation name is 'KDX1', location is LC4_C11, type is buried. +KDX1 = DFFE( _EQ166, RXA1, VCC, VCC, VCC); + _EQ166 = _EC7_C & KDXX1 + # KB_OFF & !KDXX1; + +-- Node name is 'KDX2' from file "sprint08.tdf" line 424, column 5 +-- Equation name is 'KDX2', location is LC8_C6, type is buried. +KDX2 = DFFE( _EQ167, RXA1, VCC, VCC, VCC); + _EQ167 = _EC6_C & KDXX2 + # KB_OFF & !KDXX2; + +-- Node name is 'KDX3' from file "sprint08.tdf" line 424, column 5 +-- Equation name is 'KDX3', location is LC7_C6, type is buried. +KDX3 = DFFE( _EQ168, RXA1, VCC, VCC, VCC); + _EQ168 = _EC1_C & KDXX3 + # KB_OFF & !KDXX3; + +-- Node name is 'KDX4' from file "sprint08.tdf" line 424, column 5 +-- Equation name is 'KDX4', location is LC5_C6, type is buried. +KDX4 = DFFE( _EQ169, RXA1, VCC, VCC, VCC); + _EQ169 = _EC5_C & KDXX4 + # KB_OFF & !KDXX4; + +-- Node name is 'KDX5' from file "sprint08.tdf" line 424, column 5 +-- Equation name is 'KDX5', location is LC3_C6, type is buried. +KDX5 = DFFE( _EQ170, RXA1, VCC, VCC, VCC); + _EQ170 = _EC4_C & KDXX5 + # KB_OFF & !KDXX5; + +-- Node name is 'LD_PIC' from file "sprint08.tdf" line 1842, column 12 +-- Equation name is 'LD_PIC', location is LC6_B24, type is buried. +LD_PIC = LCELL( _EQ171); + _EQ171 = !CT3 & !CT4 & !CT5; + +-- Node name is 'LMC_END' from file "sprint08.tdf" line 1619, column 13 +-- Equation name is 'LMC_END', location is LC7_B17, type is buried. +LMC_END = DFFE( MC_END, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is 'LWR_COL' from file "sprint08.tdf" line 1830, column 13 +-- Equation name is 'LWR_COL', location is LC1_B21, type is buried. +LWR_COL = LCELL( WR_COL); + +-- Node name is 'LWR_PIC' from file "sprint08.tdf" line 1829, column 13 +-- Equation name is 'LWR_PIC', location is LC8_C18, type is buried. +LWR_PIC = LCELL( WR_PIC); + +-- Node name is 'MA0' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA0', location is LC2_A21, type is buried. +MA0 = LCELL( _EQ172); + _EQ172 = _EC7_B & !_LC7_B21 + # AA0 & _LC7_B21; + +-- Node name is 'MA1' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA1', location is LC3_B17, type is buried. +MA1 = LCELL( _EQ173); + _EQ173 = !_LC7_B21 & RA12 + # AA1 & _LC7_B21; + +-- Node name is 'MA2' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA2', location is LC6_B14, type is buried. +MA2 = LCELL( _EQ174); + _EQ174 = !_LC7_B21 & RA13 + # AA2 & _LC7_B21; + +-- Node name is 'MA3' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA3', location is LC4_C17, type is buried. +MA3 = LCELL( _EQ175); + _EQ175 = _EC1_B & !_LC7_B21 + # _LC7_B21 & RA3; + +-- Node name is 'MA4' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA4', location is LC5_C16, type is buried. +MA4 = LCELL( _EQ176); + _EQ176 = _EC3_B & !_LC7_B21 + # _LC7_B21 & RA4; + +-- Node name is 'MA5' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA5', location is LC8_B14, type is buried. +MA5 = LCELL( _EQ177); + _EQ177 = _EC8_B & !_LC7_B21 + # AA5 & _LC7_B21; + +-- Node name is 'MA6' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA6', location is LC1_B13, type is buried. +MA6 = LCELL( _EQ178); + _EQ178 = _EC5_B & !_LC7_B21 + # AA6 & _LC7_B21; + +-- Node name is 'MA7' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA7', location is LC3_C23, type is buried. +MA7 = LCELL( _EQ179); + _EQ179 = _EC4_B & !_LC7_B21 + # _LC7_B21 & RA7; + +-- Node name is 'MA8' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA8', location is LC6_C20, type is buried. +MA8 = LCELL( _EQ180); + _EQ180 = _EC2_B & !_LC7_B21 + # _LC7_B21 & RA8; + +-- Node name is 'MA9' from file "sprint08.tdf" line 1277, column 8 +-- Equation name is 'MA9', location is LC2_C24, type is buried. +MA9 = LCELL( _EQ181); + _EQ181 = _EC6_B & !_LC7_B21 + # _LC7_B21 & RA9; + +-- Node name is 'MC_END' from file "sprint08.tdf" line 1554, column 11 +-- Equation name is 'MC_END', location is LC8_B8, type is buried. +MC_END = DFFE( _EQ182, CAS, !_LC2_C13, VCC, VCC); + _EQ182 = MC_END + # DOS_ON_ & !MC_START; + +-- Node name is 'MC_START' from file "sprint08.tdf" line 430, column 2 +-- Equation name is 'MC_START', location is LC3_B8, type is buried. +!MC_START = MC_START~NOT; +MC_START~NOT = DFFE(!MC1, !CT2, !_LC2_C13, VCC, VCC); + +-- Node name is 'MC_SYCLE' from file "sprint08.tdf" line 1569, column 13 +-- Equation name is 'MC_SYCLE', location is LC7_B8, type is buried. +MC_SYCLE = DFFE( _EQ183, !CT2, VCC, VCC, VCC); + _EQ183 = BLK_R + # MC1; + +-- Node name is 'MC1' from file "sprint08.tdf" line 1552, column 9 +-- Equation name is 'MC1', location is LC3_B4, type is buried. +!MC1 = MC1~NOT; +MC1~NOT = DFFE( _EQ184, GLOBAL(!TG42), !MC_END, VCC, VCC); + _EQ184 = !/MR & !/WR + # !/IOM & !/WR + # !/MR & !/RD + # !/IOM & !/RD; + +-- Node name is 'MD0' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD0', type is bidir +MD0 = TRI(_LC1_C16, !/WE1); + +-- Node name is 'MD1' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD1', type is bidir +MD1 = TRI(_LC7_A13, !/WE1); + +-- Node name is 'MD2' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD2', type is bidir +MD2 = TRI(_LC7_B22, !/WE1); + +-- Node name is 'MD3' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD3', type is bidir +MD3 = TRI(_LC2_C10, !/WE1); + +-- Node name is 'MD4' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD4', type is bidir +MD4 = TRI(_LC2_A3, !/WE1); + +-- Node name is 'MD5' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD5', type is bidir +MD5 = TRI(_LC3_C13, !/WE1); + +-- Node name is 'MD6' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD6', type is bidir +MD6 = TRI(_LC1_B11, !/WE1); + +-- Node name is 'MD7' from file "sprint08.tdf" line 1419, column 5 +-- Equation name is 'MD7', type is bidir +MD7 = TRI(_LC2_C4, !/WE1); + +-- Node name is 'MPGS0' from file "sprint08.tdf" line 734, column 24 +-- Equation name is 'MPGS0', location is LC8_B12, type is buried. +MPGS0 = LCELL( _EQ185); + _EQ185 = AR0 & !A15 + # A14 & PN0 + # A14 & !A15; + +-- Node name is 'MPGS1' from file "sprint08.tdf" line 734, column 24 +-- Equation name is 'MPGS1', location is LC4_B12, type is buried. +MPGS1 = LCELL( _EQ186); + _EQ186 = AR1 & !A14 + # A15 & PN1 + # !A14 & A15; + +-- Node name is 'MPGS2' from file "sprint08.tdf" line 734, column 24 +-- Equation name is 'MPGS2', location is LC6_B1, type is buried. +MPGS2 = LCELL( _EQ187); + _EQ187 = AR2 & !A14 & !A15 + # A14 & A15 & PN2; + +-- Node name is 'MPGS3' from file "sprint08.tdf" line 734, column 24 +-- Equation name is 'MPGS3', location is LC3_B1, type is buried. +MPGS3 = LCELL( _EQ188); + _EQ188 = !A14 & A15 + # A14 & !A15 + # AR3 & !A14 + # A15 & SC4; + +-- Node name is 'MXA0' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA0', type is output +MXA0 = MA0; + +-- Node name is 'MXA1' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA1', type is output +MXA1 = MA1; + +-- Node name is 'MXA2' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA2', type is output +MXA2 = MA2; + +-- Node name is 'MXA3' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA3', type is output +MXA3 = MA3; + +-- Node name is 'MXA4' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA4', type is output +MXA4 = MA4; + +-- Node name is 'MXA5' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA5', type is output +MXA5 = MA5; + +-- Node name is 'MXA6' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA6', type is output +MXA6 = MA6; + +-- Node name is 'MXA7' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA7', type is output +MXA7 = MA7; + +-- Node name is 'MXA8' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA8', type is output +MXA8 = MA8; + +-- Node name is 'MXA9' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA9', type is output +MXA9 = MA9; + +-- Node name is 'MXA10' from file "sprint08.tdf" line 1444, column 5 +-- Equation name is 'MXA10', type is output +MXA10 = _EC7_B; + +-- Node name is 'MXVD0~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD0~1', location is LC8_C10, type is buried. +-- synthesized logic cell +_LC8_C10 = DFFE( D0, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD0~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD0~2', location is LC4_C10, type is buried. +-- synthesized logic cell +_LC4_C10 = DFFE( D0, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD0~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD0~3', location is LC3_B5, type is buried. +-- synthesized logic cell +_LC3_B5 = DFFE( D0, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD0' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD0', location is LC1_C10, type is buried. +MXVD0 = DFFE( D0, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD1~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD1~1', location is LC2_A13, type is buried. +-- synthesized logic cell +_LC2_A13 = DFFE( D1, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD1~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD1~2', location is LC4_A13, type is buried. +-- synthesized logic cell +_LC4_A13 = DFFE( D1, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD1~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD1~3', location is LC5_A13, type is buried. +-- synthesized logic cell +_LC5_A13 = DFFE( D1, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD1', location is LC1_A13, type is buried. +MXVD1 = DFFE( D1, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD2~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD2~1', location is LC1_A16, type is buried. +-- synthesized logic cell +_LC1_A16 = DFFE( D2, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD2~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD2~2', location is LC8_A16, type is buried. +-- synthesized logic cell +_LC8_A16 = DFFE( D2, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD2~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD2~3', location is LC7_A16, type is buried. +-- synthesized logic cell +_LC7_A16 = DFFE( D2, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD2', location is LC4_A12, type is buried. +MXVD2 = DFFE( D2, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD3~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD3~1', location is LC6_C10, type is buried. +-- synthesized logic cell +_LC6_C10 = DFFE( D3, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD3~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD3~2', location is LC5_C10, type is buried. +-- synthesized logic cell +_LC5_C10 = DFFE( D3, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD3~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD3~3', location is LC7_C10, type is buried. +-- synthesized logic cell +_LC7_C10 = DFFE( D3, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD3', location is LC3_C10, type is buried. +MXVD3 = DFFE( D3, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD4~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD4~1', location is LC3_A13, type is buried. +-- synthesized logic cell +_LC3_A13 = DFFE( D4, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD4~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD4~2', location is LC6_A13, type is buried. +-- synthesized logic cell +_LC6_A13 = DFFE( D4, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD4~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD4~3', location is LC8_A13, type is buried. +-- synthesized logic cell +_LC8_A13 = DFFE( D4, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD4' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD4', location is LC7_A1, type is buried. +MXVD4 = DFFE( D4, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD5~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD5~1', location is LC6_A16, type is buried. +-- synthesized logic cell +_LC6_A16 = DFFE( D5, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD5~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD5~2', location is LC2_A16, type is buried. +-- synthesized logic cell +_LC2_A16 = DFFE( D5, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD5~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD5~3', location is LC3_A16, type is buried. +-- synthesized logic cell +_LC3_A16 = DFFE( D5, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD5' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD5', location is LC5_A16, type is buried. +MXVD5 = DFFE( D5, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD6~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD6~1', location is LC8_B11, type is buried. +-- synthesized logic cell +_LC8_B11 = DFFE( D6, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD6~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD6~2', location is LC2_B11, type is buried. +-- synthesized logic cell +_LC2_B11 = DFFE( D6, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD6~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD6~3', location is LC5_B11, type is buried. +-- synthesized logic cell +_LC5_B11 = DFFE( D6, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD6' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD6', location is LC6_B11, type is buried. +MXVD6 = DFFE( D6, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD7~1' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD7~1', location is LC5_A6, type is buried. +-- synthesized logic cell +_LC5_A6 = DFFE( D7, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD7~2' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD7~2', location is LC1_A6, type is buried. +-- synthesized logic cell +_LC1_A6 = DFFE( D7, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD7~3' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD7~3', location is LC4_A6, type is buried. +-- synthesized logic cell +_LC4_A6 = DFFE( D7, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXVD7' from file "sprint08.tdf" line 397, column 6 +-- Equation name is 'MXVD7', location is LC7_A6, type is buried. +MXVD7 = DFFE( D7, AY_CCC2, VCC, VCC, VCC); + +-- Node name is 'MXWE' from file "sprint08.tdf" line 1756, column 9 +-- Equation name is 'MXWE', location is LC3_B23, type is buried. +!MXWE = MXWE~NOT; +MXWE~NOT = DFFE( _EQ189, AY_CCC2, V_WE, VCC, VCC); + _EQ189 = !A13 & A14 & !_LC7_B1 & !/WE1; + +-- Node name is 'PGS0' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS0', location is LC6_B12, type is buried. +PGS0 = LCELL( _EQ190); + _EQ190 = _LC4_B10 & MPGS0 + # DD0 & !_LC4_B10 & MC_END; + +-- Node name is 'PGS1' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS1', location is LC7_B12, type is buried. +PGS1 = LCELL( _EQ191); + _EQ191 = _LC4_B10 & MPGS1 + # DD1 & !_LC4_B10 & MC_END; + +-- Node name is 'PGS2' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS2', location is LC8_B1, type is buried. +PGS2 = LCELL( _EQ192); + _EQ192 = _LC4_B10 & MPGS2 + # DD2 & !_LC4_B10 & MC_END; + +-- Node name is 'PGS3' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS3', location is LC1_B1, type is buried. +PGS3 = LCELL( _EQ193); + _EQ193 = _LC4_B10 & MPGS3 + # DCP3 & !_LC4_B10 & MC_END; + +-- Node name is 'PGS4' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS4', location is LC6_B10, type is buried. +PGS4 = LCELL( _EQ194); + _EQ194 = DCP4 & !_LC4_B10 & MC_END + # !_LC1_B10 & _LC4_B10; + +-- Node name is 'PGS5' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS5', location is LC2_B2, type is buried. +PGS5 = LCELL( _EQ195); + _EQ195 = DCP5 & !_LC4_B10 & MC_END + # _LC8_B2; + +-- Node name is 'PGS6' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS6', location is LC1_B2, type is buried. +PGS6 = LCELL( _EQ196); + _EQ196 = _LC8_B2 + # DD6 & !_LC4_B10 & MC_END; + +-- Node name is 'PGS7' from file "sprint08.tdf" line 750, column 23 +-- Equation name is 'PGS7', location is LC3_B2, type is buried. +PGS7 = LCELL( _EQ197); + _EQ197 = DD7 & MC_END + # _LC4_B10; + +-- Node name is 'PN0' from file "sprint08.tdf" line 312, column 4 +-- Equation name is 'PN0', location is LC8_B6, type is buried. +PN0 = DFFE( D0, _LC5_B3, /RESET, VCC, _LC3_B6); + +-- Node name is 'PN1' from file "sprint08.tdf" line 312, column 4 +-- Equation name is 'PN1', location is LC2_B6, type is buried. +PN1 = DFFE( D1, _LC5_B3, /RESET, VCC, _LC3_B6); + +-- Node name is 'PN2' from file "sprint08.tdf" line 312, column 4 +-- Equation name is 'PN2', location is LC7_B6, type is buried. +PN2 = DFFE( D2, _LC5_B3, /RESET, VCC, _LC3_B6); + +-- Node name is 'PN3' from file "sprint08.tdf" line 312, column 4 +-- Equation name is 'PN3', location is LC5_B6, type is buried. +PN3 = DFFE( D3, _LC5_B3, /RESET, VCC, _LC3_B6); + +-- Node name is 'PN4' from file "sprint08.tdf" line 312, column 4 +-- Equation name is 'PN4', location is LC1_B6, type is buried. +PN4 = DFFE( D4, _LC5_B3, /RESET, VCC, _LC3_B6); + +-- Node name is 'PN5' from file "sprint08.tdf" line 312, column 4 +-- Equation name is 'PN5', location is LC4_B6, type is buried. +PN5 = DFFE( D5, _LC5_B3, /RESET, VCC, _LC3_B6); + +-- Node name is 'PRF_CMD' from file "sprint08.tdf" line 502, column 2 +-- Equation name is 'PRF_CMD', location is LC8_A6, type is buried. +PRF_CMD = DFFE( _EQ198, _LC6_B4, VCC, VCC, VCC); + _EQ198 = D6 & D7 & _LC4_A16 & _LC6_A6; + +-- Node name is 'RAS_0' from file "sprint08.tdf" line 1617, column 6 +-- Equation name is 'RAS_0', type is output +RAS_0 = _LC5_B8; + +-- Node name is 'RAS_1' from file "sprint08.tdf" line 1617, column 6 +-- Equation name is 'RAS_1', type is output +RAS_1 = _LC4_B8; + +-- Node name is 'RA3' from file "sprint08.tdf" line 1269, column 33 +-- Equation name is 'RA3', location is LC2_C17, type is buried. +RA3 = LCELL( _EQ199); + _EQ199 = AA7 & !/IO + # AA3 & /IO; + +-- Node name is 'RA4' from file "sprint08.tdf" line 1269, column 33 +-- Equation name is 'RA4', location is LC4_C16, type is buried. +RA4 = LCELL( _EQ200); + _EQ200 = AA13 & !/IO + # AA4 & /IO; + +-- Node name is 'RA7' from file "sprint08.tdf" line 1269, column 33 +-- Equation name is 'RA7', location is LC8_C23, type is buried. +RA7 = LCELL( _EQ201); + _EQ201 = AA7 & /IO + # A14 & !/IO; + +-- Node name is 'RA8' from file "sprint08.tdf" line 1269, column 33 +-- Equation name is 'RA8', location is LC7_C20, type is buried. +RA8 = LCELL( _EQ202); + _EQ202 = AA8 & /IO + # A15 & !/IO; + +-- Node name is 'RA9' from file "sprint08.tdf" line 1269, column 33 +-- Equation name is 'RA9', location is LC8_C24, type is buried. +RA9 = LCELL( _EQ203); + _EQ203 = AA9 & /IO + # !/IO & /WR; + +-- Node name is 'RA12' from file "sprint08.tdf" line 1269, column 33 +-- Equation name is 'RA12', location is LC8_B17, type is buried. +RA12 = LCELL( _EQ204); + _EQ204 = CNF3 & !/IO + # AA12 & /IO; + +-- Node name is 'RA13' from file "sprint08.tdf" line 1269, column 33 +-- Equation name is 'RA13', location is LC7_B14, type is buried. +RA13 = LCELL( _EQ205); + _EQ205 = CNF4 & !/IO + # AA13 & /IO; + +-- Node name is 'RXA0' from file "sprint08.tdf" line 427, column 5 +-- Equation name is 'RXA0', location is LC2_C6, type is buried. +RXA0 = DFFE( _EQ206, K_CLK, VCC, VCC, VCC); + _EQ206 = !_LC7_C3 & !RXA1; + +-- Node name is 'RXA1' from file "sprint08.tdf" line 427, column 5 +-- Equation name is 'RXA1', location is LC6_C6, type is buried. +RXA1 = DFFE( _EQ207, K_CLK, VCC, VCC, VCC); + _EQ207 = !_LC7_C3 & RXA0; + +-- Node name is 'SC_LCELL' from file "sprint08.tdf" line 739, column 13 +-- Equation name is 'SC_LCELL', location is LC2_B12, type is buried. +SC_LCELL = LCELL( _EQ208); + _EQ208 = !SC1 & !SYS + # !SC0 & !SC1; + +-- Node name is 'SC_PGS' from file "sprint08.tdf" line 769, column 11 +-- Equation name is 'SC_PGS', location is LC5_B10, type is buried. +SC_PGS = LCELL( _EQ209); + _EQ209 = !_LC1_B10 & SC4; + +-- Node name is 'SC0' from file "sprint08.tdf" line 311, column 4 +-- Equation name is 'SC0', location is LC3_B16, type is buried. +SC0 = DFFE( D0, _LC5_B3, /RESET, VCC, !_LC1_B16); + +-- Node name is 'SC1' from file "sprint08.tdf" line 311, column 4 +-- Equation name is 'SC1', location is LC4_B16, type is buried. +SC1 = DFFE( D1, _LC5_B3, /RESET, VCC, !_LC1_B16); + +-- Node name is 'SC4' from file "sprint08.tdf" line 311, column 4 +-- Equation name is 'SC4', location is LC6_B16, type is buried. +SC4 = DFFE( D4, _LC5_B3, /RESET, VCC, !_LC1_B16); + +-- Node name is 'SD0~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD0~1', location is LC1_C23, type is buried. +-- synthesized logic cell +_LC1_C23 = LCELL( _EQ210); + _EQ210 = DD7 & _EC4_B & !/IO + # DD0 & /IO; + +-- Node name is 'SD0' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD0', location is LC6_C23, type is buried. +SD0 = LCELL( _EQ211); + _EQ211 = _LC1_C23 + # AY_DD0 & _LC6_B3 + # _LC2_C23; + +-- Node name is 'SD1~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD1~1', location is LC1_C20, type is buried. +-- synthesized logic cell +_LC1_C20 = LCELL( _EQ212); + _EQ212 = DD7 & _EC2_B & !/IO + # DD1 & /IO; + +-- Node name is 'SD1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD1', location is LC4_C20, type is buried. +SD1 = LCELL( _EQ213); + _EQ213 = _LC1_C20 + # AY_DD1 & _LC6_B3 + # _LC2_C20; + +-- Node name is 'SD2~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD2~1', location is LC3_C24, type is buried. +-- synthesized logic cell +_LC3_C24 = LCELL( _EQ214); + _EQ214 = DD7 & _EC6_B & !/IO + # DD2 & /IO; + +-- Node name is 'SD2' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD2', location is LC1_C24, type is buried. +SD2 = LCELL( _EQ215); + _EQ215 = _LC3_C24 + # AY_DD2 & _LC6_B3 + # _LC5_C24; + +-- Node name is 'SD3~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD3~1', location is LC4_B5, type is buried. +-- synthesized logic cell +_LC4_B5 = LCELL( _EQ216); + _EQ216 = DD7 & _EC7_B & !/IO + # DCP3 & /IO; + +-- Node name is 'SD3' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD3', location is LC3_C4, type is buried. +SD3 = LCELL( _EQ217); + _EQ217 = _LC4_B5 + # AY_DD3 & _LC6_B3 + # _LC1_C4; + +-- Node name is 'SD4~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD4~1', location is LC8_B3, type is buried. +-- synthesized logic cell +_LC8_B3 = LCELL( _EQ218); + _EQ218 = KBD4 & _LC4_B3 + # DCP4 & /IO; + +-- Node name is 'SD4' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD4', location is LC1_A8, type is buried. +SD4 = LCELL( _EQ219); + _EQ219 = _LC4_A8 + # _LC8_B3 + # AY_DD4 & _LC6_B3; + +-- Node name is 'SD5~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD5~1', location is LC3_B3, type is buried. +-- synthesized logic cell +_LC3_B3 = LCELL( _EQ220); + _EQ220 = DD7 & _EC3_B & !/IO + # DCP5 & /IO; + +-- Node name is 'SD5' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD5', location is LC2_B3, type is buried. +SD5 = LCELL( _EQ221); + _EQ221 = _LC3_B3 + # AY_DD5 & _LC6_B3 + # _LC4_B3; + +-- Node name is 'SD6~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD6~1', location is LC4_B2, type is buried. +-- synthesized logic cell +_LC4_B2 = LCELL( _EQ222); + _EQ222 = DD7 & _EC8_B & !/IO + # DD6 & /IO; + +-- Node name is 'SD6' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD6', location is LC5_B2, type is buried. +SD6 = LCELL( _EQ223); + _EQ223 = _LC4_B2 + # AY_DD6 & _LC6_B3 + # _LC7_B2; + +-- Node name is 'SD7~1' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD7~1', location is LC8_C7, type is buried. +-- synthesized logic cell +_LC8_C7 = LCELL( _EQ224); + _EQ224 = DD7 & /IO + # AY_DD7 & _LC6_B3; + +-- Node name is 'SD7' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is 'SD7', location is LC3_C7, type is buried. +SD7 = LCELL( _EQ225); + _EQ225 = _LC6_C7 + # _LC8_C7 + # KBD5 & _LC4_B3; + +-- Node name is 'SINC' from file "sprint08.tdf" line 288, column 2 +-- Equation name is 'SINC', type is output +SINC = _LC8_C22; + +-- Node name is 'SINC_H' from file "sprint08.tdf" line 2142, column 2 +-- Equation name is 'SINC_H', type is output +SINC_H = _LC1_A18; + +-- Node name is 'SINC_HH' from file "sprint08.tdf" line 1722, column 12 +-- Equation name is 'SINC_HH', location is LC7_C17, type is buried. +SINC_HH = DFFE( _EQ226, CTH1, VCC, VCC, VCC); + _EQ226 = CTH2 & !CTH3 & !CTH4 & CTH5; + +-- Node name is 'SINC_VV' from file "sprint08.tdf" line 1726, column 12 +-- Equation name is 'SINC_VV', location is LC3_C16, type is buried. +SINC_VV = DFFE( _EQ227, CTV5, VCC, VCC, VCC); + _EQ227 = CTV6 & CTV7; + +-- Node name is 'SND_L0' from file "sprint08.tdf" line 3457, column 3 +-- Equation name is 'SND_L0', type is output +SND_L0 = _LC6_A8; + +-- Node name is 'SND_L1' from file "sprint08.tdf" line 3458, column 3 +-- Equation name is 'SND_L1', type is output +SND_L1 = GND; + +-- Node name is 'SND_R0' from file "sprint08.tdf" line 3460, column 3 +-- Equation name is 'SND_R0', type is output +SND_R0 = _LC3_A8; + +-- Node name is 'SND_R1' from file "sprint08.tdf" line 3461, column 3 +-- Equation name is 'SND_R1', type is output +SND_R1 = GND; + +-- Node name is 'SVA2' from file "sprint08.tdf" line 1818, column 46 +-- Equation name is 'SVA2', location is LC7_C22, type is buried. +SVA2 = LCELL( _EQ228); + _EQ228 = CTV6 & !VCM2 + # CTV0 & VCM2; + +-- Node name is 'SVA3' from file "sprint08.tdf" line 1818, column 46 +-- Equation name is 'SVA3', location is LC3_C22, type is buried. +SVA3 = LCELL( _EQ229); + _EQ229 = CTV7 & !VCM2 + # CTV1 & VCM2; + +-- Node name is 'SVA5' from file "sprint08.tdf" line 1818, column 46 +-- Equation name is 'SVA5', location is LC4_C22, type is buried. +SVA5 = LCELL( _EQ230); + _EQ230 = !VCM2 + # CTV6; + +-- Node name is 'SVA6' from file "sprint08.tdf" line 1818, column 46 +-- Equation name is 'SVA6', location is LC1_B17, type is buried. +SVA6 = LCELL( _EQ231); + _EQ231 = !VCM2 + # CTV7; + +-- Node name is 'SYS' from file "sprint08.tdf" line 313, column 2 +-- Equation name is 'SYS', location is LC5_B13, type is buried. +SYS = DFFE(!A6, _LC5_B3, /RESET, VCC, !_LC2_B13); + +-- Node name is 'TAPE_OUT' from file "sprint08.tdf" line 1471, column 2 +-- Equation name is 'TAPE_OUT', type is output +TAPE_OUT = BRD3; + +-- Node name is 'TB_SW' from file "sprint08.tdf" line 315, column 2 +-- Equation name is 'TB_SW', location is LC8_B16, type is buried. +!TB_SW = TB_SW~NOT; +TB_SW~NOT = DFFE(!D0, _LC5_B3, /RESET, VCC, _LC7_C15); + +-- Node name is 'TSN_W3' from file "sprint08.tdf" line 329, column 2 +-- Equation name is 'TSN_W3', location is LC5_B23, type is buried. +TSN_W3 = DFFE( _EQ232, GLOBAL( TG42), VCC, VCC, VCC); + _EQ232 = VCM2 + # VCM0 + # VCM1; + +-- Node name is 'TURBO' from file "sprint08.tdf" line 1516, column 12 +-- Equation name is 'TURBO', location is LC6_C13, type is buried. +TURBO = DFFE( _EQ233, GLOBAL( /M1), VCC, VCC, VCC); + _EQ233 = _LC7_C5 & TB_SW; + +-- Node name is 'TURBO_LED' from file "sprint08.tdf" line 1448, column 2 +-- Equation name is 'TURBO_LED', type is output +TURBO_LED = !TURBO; + +-- Node name is 'VA0' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA0', type is output +VA0 = VLA2; + +-- Node name is 'VA1' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA1', type is output +VA1 = VLA3; + +-- Node name is 'VA2' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA2', type is output +VA2 = VLA4; + +-- Node name is 'VA3' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA3', type is output +VA3 = VLA5; + +-- Node name is 'VA4' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA4', type is output +VA4 = VLA6; + +-- Node name is 'VA5' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA5', type is output +VA5 = VLA7; + +-- Node name is 'VA6' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA6', type is output +VA6 = VLA8; + +-- Node name is 'VA7' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA7', type is output +VA7 = VLA9; + +-- Node name is 'VA8' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA8', type is output +VA8 = VLA10; + +-- Node name is 'VA9' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA9', type is output +VA9 = VLA11; + +-- Node name is 'VA10' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA10', type is output +VA10 = VLA12; + +-- Node name is 'VA11' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA11', type is output +VA11 = VLA13; + +-- Node name is 'VA12' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA12', type is output +VA12 = VLA14; + +-- Node name is 'VA13' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA13', type is output +VA13 = VLA15; + +-- Node name is 'VA14' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA14', type is output +VA14 = VLA16; + +-- Node name is 'VA15' from file "sprint08.tdf" line 2281, column 4 +-- Equation name is 'VA15', type is output +VA15 = VLA17; + +-- Node name is 'VCM0' from file "sprint08.tdf" line 330, column 5 +-- Equation name is 'VCM0', location is LC6_B20, type is buried. +VCM0 = DFFE( _EQ234, GLOBAL( TG42), VCC, VCC, VCC); + _EQ234 = !CT0 & !CT2 + # AY_CCC0 & !CT0; + +-- Node name is 'VCM1' from file "sprint08.tdf" line 330, column 5 +-- Equation name is 'VCM1', location is LC5_B20, type is buried. +VCM1 = DFFE( _EQ235, GLOBAL( TG42), VCC, VCC, VCC); + _EQ235 = AY_CCC0 & !CT0 & !CT2 + # !AY_CCC0 & !CT0 & CT2; + +-- Node name is 'VCM2' from file "sprint08.tdf" line 330, column 5 +-- Equation name is 'VCM2', location is LC4_B20, type is buried. +VCM2 = DFFE( _EQ236, GLOBAL( TG42), VCC, VCC, VCC); + _EQ236 = AY_CCC0 & !CT0 & CT2 + # !AY_CCC0 & CT0 & !CT2; + +-- Node name is 'V_CS0' from file "sprint08.tdf" line 332, column 6 +-- Equation name is 'V_CS0', type is output +V_CS0 = GND; + +-- Node name is 'V_CS1' from file "sprint08.tdf" line 332, column 6 +-- Equation name is 'V_CS1', type is output +V_CS1 = VCC; + +-- Node name is 'VD00' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD00', type is bidir +VD00 = TRI(_LC3_B5, !_LC1_B23); + +-- Node name is 'VD01' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD01', type is bidir +VD01 = TRI(_LC5_A13, !_LC1_B23); + +-- Node name is 'VD02' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD02', type is bidir +VD02 = TRI(_LC7_A16, !_LC1_B23); + +-- Node name is 'VD03' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD03', type is bidir +VD03 = TRI(_LC7_C10, !_LC1_B23); + +-- Node name is 'VD04' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD04', type is bidir +VD04 = TRI(_LC8_A13, !_LC1_B23); + +-- Node name is 'VD05' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD05', type is bidir +VD05 = TRI(_LC3_A16, !_LC1_B23); + +-- Node name is 'VD06' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD06', type is bidir +VD06 = TRI(_LC5_B11, !_LC1_B23); + +-- Node name is 'VD07' from file "sprint08.tdf" line 1436, column 6 +-- Equation name is 'VD07', type is bidir +VD07 = TRI(_LC4_A6, !_LC1_B23); + +-- Node name is 'VD10' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD10', type is bidir +VD10 = TRI(_LC4_C10, GND); + +-- Node name is 'VD11' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD11', type is bidir +VD11 = TRI(_LC4_A13, GND); + +-- Node name is 'VD12' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD12', type is bidir +VD12 = TRI(_LC8_A16, GND); + +-- Node name is 'VD13' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD13', type is bidir +VD13 = TRI(_LC5_C10, GND); + +-- Node name is 'VD14' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD14', type is bidir +VD14 = TRI(_LC6_A13, GND); + +-- Node name is 'VD15' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD15', type is bidir +VD15 = TRI(_LC2_A16, GND); + +-- Node name is 'VD16' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD16', type is bidir +VD16 = TRI(_LC2_B11, GND); + +-- Node name is 'VD17' from file "sprint08.tdf" line 1437, column 6 +-- Equation name is 'VD17', type is bidir +VD17 = TRI(_LC1_A6, GND); + +-- Node name is 'VD20' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD20', type is bidir +VD20 = TRI(_LC8_C10, GND); + +-- Node name is 'VD21' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD21', type is bidir +VD21 = TRI(_LC2_A13, GND); + +-- Node name is 'VD22' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD22', type is bidir +VD22 = TRI(_LC1_A16, GND); + +-- Node name is 'VD23' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD23', type is bidir +VD23 = TRI(_LC6_C10, GND); + +-- Node name is 'VD24' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD24', type is bidir +VD24 = TRI(_LC3_A13, GND); + +-- Node name is 'VD25' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD25', type is bidir +VD25 = TRI(_LC6_A16, GND); + +-- Node name is 'VD26' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD26', type is bidir +VD26 = TRI(_LC8_B11, GND); + +-- Node name is 'VD27' from file "sprint08.tdf" line 1438, column 6 +-- Equation name is 'VD27', type is bidir +VD27 = TRI(_LC5_A6, GND); + +-- Node name is 'VD30' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD30', type is bidir +VD30 = TRI(MXVD0, GND); + +-- Node name is 'VD31' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD31', type is bidir +VD31 = TRI(MXVD1, GND); + +-- Node name is 'VD32' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD32', type is bidir +VD32 = TRI(MXVD2, GND); + +-- Node name is 'VD33' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD33', type is bidir +VD33 = TRI(MXVD3, GND); + +-- Node name is 'VD34' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD34', type is bidir +VD34 = TRI(MXVD4, GND); + +-- Node name is 'VD35' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD35', type is bidir +VD35 = TRI(MXVD5, GND); + +-- Node name is 'VD36' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD36', type is bidir +VD36 = TRI(MXVD6, GND); + +-- Node name is 'VD37' from file "sprint08.tdf" line 1439, column 6 +-- Equation name is 'VD37', type is bidir +VD37 = TRI(MXVD7, GND); + +-- Node name is 'VLA2' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA2', location is LC2_C2, type is buried. +VLA2 = DFFE( _EQ237, GLOBAL( TG42), VCC, VCC, VCC); + _EQ237 = SVA2 & VCM0 + # _LC3_C2; + +-- Node name is 'VLA3' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA3', location is LC5_C19, type is buried. +VLA3 = DFFE( _EQ238, GLOBAL( TG42), VCC, VCC, VCC); + _EQ238 = _LC8_C19 + # SVA3 & VCM0; + +-- Node name is 'VLA4' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA4', location is LC4_B23, type is buried. +VLA4 = DFFE( _EQ239, GLOBAL( TG42), VCC, VCC, VCC); + _EQ239 = CTV2 & VCM0 & VCM2 + # _LC6_B23; + +-- Node name is 'VLA5' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA5', location is LC7_C2, type is buried. +VLA5 = DFFE( _EQ240, GLOBAL( TG42), VCC, VCC, VCC); + _EQ240 = SVA5 & VCM0 + # !VCM0 & !VCM1 + # AA11 & !VCM0; + +-- Node name is 'VLA6' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA6', location is LC6_B17, type is buried. +VLA6 = DFFE( _EQ241, GLOBAL( TG42), VCC, VCC, VCC); + _EQ241 = SVA6 & VCM0 + # !VCM0 & !VCM1 + # AA12 & !VCM0; + +-- Node name is 'VLA7' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA7', location is LC6_B6, type is buried. +VLA7 = DFFE( _EQ242, GLOBAL( TG42), VCC, VCC, VCC); + _EQ242 = !VCM0 & !VCM1 + # AX128 & !VCM0 + # PN3 & VCM0; + +-- Node name is 'VLA8' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA8', location is LC8_C2, type is buried. +VLA8 = DFFE( _EQ243, GLOBAL( TG42), VCC, VCC, VCC); + _EQ243 = !VCM0 & !VCM1; + +-- Node name is 'VLA9' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA9', location is LC6_C2, type is buried. +VLA9 = DFFE( _EQ244, GLOBAL( TG42), VCC, VCC, VCC); + _EQ244 = !VCM0 & !VCM1; + +-- Node name is 'VLA10' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA10', location is LC5_A21, type is buried. +VLA10 = DFFE( _EQ245, GLOBAL( TG42), VCC, VCC, VCC); + _EQ245 = _LC3_A18 + # AA0 & !VCM0 & VCM1; + +-- Node name is 'VLA11' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA11', location is LC3_B19, type is buried. +VLA11 = DFFE( _EQ246, GLOBAL( TG42), VCC, VCC, VCC); + _EQ246 = _LC4_B19 + # CTH1 & VCM0; + +-- Node name is 'VLA12' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA12', location is LC5_C2, type is buried. +VLA12 = DFFE( _EQ247, GLOBAL( TG42), VCC, VCC, VCC); + _EQ247 = _LC4_C2 + # CTH2 & VCM0; + +-- Node name is 'VLA13' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA13', location is LC8_A22, type is buried. +VLA13 = DFFE( _EQ248, GLOBAL( TG42), VCC, VCC, VCC); + _EQ248 = CTH3 & VCM0 + # _LC1_C17; + +-- Node name is 'VLA14' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA14', location is LC2_B21, type is buried. +VLA14 = DFFE( _EQ249, GLOBAL( TG42), VCC, VCC, VCC); + _EQ249 = CTH4 & VCM0 + # _LC5_B21; + +-- Node name is 'VLA15' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA15', location is LC7_C21, type is buried. +VLA15 = DFFE( _EQ250, GLOBAL( TG42), VCC, VCC, VCC); + _EQ250 = CTV3 & VCM0 + # _LC1_B14; + +-- Node name is 'VLA16' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA16', location is LC5_C21, type is buried. +VLA16 = DFFE( _EQ251, GLOBAL( TG42), VCC, VCC, VCC); + _EQ251 = CTV4 & VCM0 + # _LC6_B13; + +-- Node name is 'VLA17' from file "sprint08.tdf" line 334, column 5 +-- Equation name is 'VLA17', location is LC8_C21, type is buried. +VLA17 = DFFE( _EQ252, GLOBAL( TG42), VCC, VCC, VCC); + _EQ252 = CTV5 & VCM0 + # _LC8_C17; + +-- Node name is 'V_WAIT~1' from file "sprint08.tdf" line 1560, column 50 +-- Equation name is 'V_WAIT~1', location is LC7_B4, type is buried. +-- synthesized logic cell +_LC7_B4 = LCELL( _EQ253); + _EQ253 = _LC5_A3 + # /MR + # MC_END; + +-- Node name is 'V_WE' from file "sprint08.tdf" line 340, column 2 +-- Equation name is 'V_WE', location is LC8_B23, type is buried. +!V_WE = V_WE~NOT; +V_WE~NOT = DFFE( _EQ254, GLOBAL( TG42), _LC6_B21, VCC, VCC); + _EQ254 = !MXWE & !VCM0 & VCM1; + +-- Node name is 'V_WR0' from file "sprint08.tdf" line 333, column 6 +-- Equation name is 'V_WR0', type is output +V_WR0 = _LC1_B23; + +-- Node name is 'V_WR1' from file "sprint08.tdf" line 333, column 6 +-- Equation name is 'V_WR1', type is output +V_WR1 = VCC; + +-- Node name is 'V_WR2' from file "sprint08.tdf" line 333, column 6 +-- Equation name is 'V_WR2', type is output +V_WR2 = VCC; + +-- Node name is 'V_WR3' from file "sprint08.tdf" line 333, column 6 +-- Equation name is 'V_WR3', type is output +V_WR3 = VCC; + +-- Node name is 'WR_COL' from file "sprint08.tdf" line 368, column 2 +-- Equation name is 'WR_COL', location is LC4_B21, type is buried. +WR_COL = DFFE( _EQ255, GLOBAL( TG42), VCC, VCC, VCC); + _EQ255 = VCM2 + # !VCM0; + +-- Node name is 'WR_KBD' from file "sprint08.tdf" line 2558, column 41 +-- Equation name is 'WR_KBD', location is LC1_C6, type is buried. +!WR_KBD = WR_KBD~NOT; +WR_KBD~NOT = LCELL( _EQ256); + _EQ256 = !K_CLK & _LC1_C3 & RXA0 & RXA1; + +-- Node name is 'WR_PIC' from file "sprint08.tdf" line 367, column 2 +-- Equation name is 'WR_PIC', location is LC2_B23, type is buried. +WR_PIC = DFFE( _EQ257, GLOBAL( TG42), VCC, VCC, VCC); + _EQ257 = !VCM2 + # !VCM0; + +-- Node name is 'XACS' from file "sprint08.tdf" line 708, column 19 +-- Equation name is 'XACS', type is output +XACS = XC3; + +-- Node name is 'XA0' from file "sprint08.tdf" line 708, column 4 +-- Equation name is 'XA0', type is output +XA0 = XC0; + +-- Node name is 'XA1' from file "sprint08.tdf" line 708, column 4 +-- Equation name is 'XA1', type is output +XA1 = XC1; + +-- Node name is 'XA2' from file "sprint08.tdf" line 708, column 4 +-- Equation name is 'XA2', type is output +XA2 = XC2; + +-- Node name is 'XC0' from file "sprint08.tdf" line 790, column 12 +-- Equation name is 'XC0', location is LC3_A3, type is buried. +XC0 = LCELL( _EQ258); + _EQ258 = _EC1_B & !_LC8_A3; + +-- Node name is 'XC1' from file "sprint08.tdf" line 790, column 12 +-- Equation name is 'XC1', location is LC6_A3, type is buried. +XC1 = LCELL( _EQ259); + _EQ259 = _LC8_A3 + # _EC3_B; + +-- Node name is 'XC2' from file "sprint08.tdf" line 790, column 12 +-- Equation name is 'XC2', location is LC4_A3, type is buried. +XC2 = LCELL( _EQ260); + _EQ260 = _LC8_A3 + # _EC8_B; + +-- Node name is 'XC3' from file "sprint08.tdf" line 795, column 15 +-- Equation name is 'XC3', location is LC3_B7, type is buried. +XC3 = LCELL( _EQ261); + _EQ261 = _LC8_B7 + # BLK_R; + +-- Node name is '~GND~' +-- Equation name is '~GND~', location is LC4_B17, type is buried. +-- synthesized logic cell +_LC4_B17 = LCELL( GND); + +-- Node name is '/INT' from file "sprint08.tdf" line 1498, column 2 +-- Equation name is '/INT', type is bidir +/INT = OPNDRN(INTT); + +-- Node name is '/IOM' from file "sprint08.tdf" line 1533, column 9 +-- Equation name is '/IOM', location is LC2_B20, type is buried. +!/IOM = /IOM~NOT; +/IOM~NOT = DFFE( /M1, CT0, GLOBAL(!/IO), VCC, VCC); + +-- Node name is '/IOM1' from file "sprint08.tdf" line 1534, column 10 +-- Equation name is '/IOM1', location is LC5_B7, type is buried. +!/IOM1 = /IOM1~NOT; +/IOM1~NOT = DFFE( _EQ262, CT2, GLOBAL(!/IO), VCC, VCC); + _EQ262 = MC_END & /M1; + +-- Node name is '/IOWR' from file "sprint08.tdf" line 1537, column 17 +-- Equation name is '/IOWR', location is LC5_B16, type is buried. +/IOWR = LCELL( _EQ263); + _EQ263 = /IOM1 + # /WR; + +-- Node name is '/NMI' from file "sprint08.tdf" line 1499, column 2 +-- Equation name is '/NMI', type is bidir +/NMI = OPNDRN(VCC); + +-- Node name is '/RESET' from file "sprint08.tdf" line 1482, column 2 +-- Equation name is '/RESET', type is bidir +/RESET = OPNDRN(_LC4_C15); + +-- Node name is '/WAIT' from file "sprint08.tdf" line 1549, column 2 +-- Equation name is '/WAIT', type is bidir +/WAIT = OPNDRN(/WAITT); + +-- Node name is '/WAITT' from file "sprint08.tdf" line 1547, column 20 +-- Equation name is '/WAITT', location is LC4_B4, type is buried. +/WAITT = LCELL( _EQ264); + _EQ264 = !TURBO + # _LC2_B7 & _LC7_B4; + +-- Node name is '/WE' from file "sprint08.tdf" line 1590, column 3 +-- Equation name is '/WE', type is output +/WE = /WE1; + +-- Node name is '/WE1' from file "sprint08.tdf" line 1588, column 34 +-- Equation name is '/WE1', location is LC1_B8, type is buried. +!/WE1 = /WE1~NOT; +/WE1~NOT = LCELL( _EQ265); + _EQ265 = _LC1_B12 & !MC_SYCLE & !/MR & !/WR; + +-- Node name is ':1921' from file "sprint08.tdf" line 746, column 28 +-- Equation name is '_LC8_B10', type is buried +_LC8_B10 = DFFE( GND, VCC, /RESET, _LC2_B4, VCC); + +-- Node name is ':1922' from file "sprint08.tdf" line 748, column 8 +-- Equation name is '_LC4_B10', type is buried +_LC4_B10 = LCELL( _EQ266); + _EQ266 = /IO & _LC8_B10 + # /IO & _LC1_B10; + +-- Node name is ':1924' from file "sprint08.tdf" line 767, column 29 +-- Equation name is '_LC7_B10', type is buried +_LC7_B10 = LCELL( _EQ267); + _EQ267 = _EC5_B & _EC8_B & !_LC1_B12 + # _EC5_B & SC_PGS; + +-- Node name is ':1926' from file "sprint08.tdf" line 774, column 11 +-- Equation name is '_LC1_B12', type is buried +_LC1_B12 = LCELL( _EQ268); + _EQ268 = A15 + # A14 + # SC0 & SYS; + +-- Node name is ':1929' from file "sprint08.tdf" line 786, column 5 +-- Equation name is '_LC8_A3', type is buried +!_LC8_A3 = _LC8_A3~NOT; +_LC8_A3~NOT = DFFE( _EQ269, GLOBAL( TG42), !_LC2_C13, VCC, VCC); + _EQ269 = !/IO + # !/MR; + +-- Node name is ':1930' from file "sprint08.tdf" line 795, column 18 +-- Equation name is '_LC8_B7', type is buried +_LC8_B7 = DFFE( _EQ270, !CT2, GLOBAL(!/IO), VCC, VCC); + _EQ270 = !DD6 & !DD7 & _EC5_B & !/IOM1; + +-- Node name is ':1958' from file "sprint08.tdf" line 1274, column 5 +-- Equation name is '_LC7_B21', type is buried +_LC7_B21 = DFFE( AY_CCC2, GLOBAL( TG42), !_LC8_B21, VCC, VCC); + +-- Node name is ':1962' from file "sprint08.tdf" line 1379, column 26 +-- Equation name is '_LC3_B11', type is buried +_LC3_B11 = DFFE( DOS, AY_CCC2, VCC, VCC, VCC); + +-- Node name is ':1964' from file "sprint08.tdf" line 1415, column 43 +-- Equation name is '_LC5_B4', type is buried +!_LC5_B4 = _LC5_B4~NOT; +_LC5_B4~NOT = DFFE(!/RD, !_LC6_B8, GLOBAL(!/MR), VCC, VCC); + +-- Node name is '~1966~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~1966~1', location is LC1_C16, type is buried. +-- synthesized logic cell +_LC1_C16 = LCELL( D0); + +-- Node name is '~1972~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~1972~1', location is LC7_A13, type is buried. +-- synthesized logic cell +_LC7_A13 = LCELL( D1); + +-- Node name is '~1978~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~1978~1', location is LC7_B22, type is buried. +-- synthesized logic cell +_LC7_B22 = LCELL( D2); + +-- Node name is '~1984~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~1984~1', location is LC2_C10, type is buried. +-- synthesized logic cell +_LC2_C10 = LCELL( D3); + +-- Node name is '~1990~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~1990~1', location is LC2_A3, type is buried. +-- synthesized logic cell +_LC2_A3 = LCELL( D4); + +-- Node name is '~1996~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~1996~1', location is LC3_C13, type is buried. +-- synthesized logic cell +_LC3_C13 = LCELL( D5); + +-- Node name is '~2002~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~2002~1', location is LC1_B11, type is buried. +-- synthesized logic cell +_LC1_B11 = LCELL( D6); + +-- Node name is '~2008~1' from file "sprint08.tdf" line 1419, column 11 +-- Equation name is '~2008~1', location is LC2_C4, type is buried. +-- synthesized logic cell +_LC2_C4 = LCELL( D7); + +-- Node name is ':2013' from file "sprint08.tdf" line 1450, column 13 +-- Equation name is '_LC7_B23', type is buried +_LC7_B23 = LCELL( TSN_W3); + +-- Node name is ':2019' from file "sprint08.tdf" line 1482, column 19 +-- Equation name is '_LC4_C15', type is buried +_LC4_C15 = DFFE( VCC, CTV0, KB_RESET, VCC, VCC); + +-- Node name is ':2024' from file "sprint08.tdf" line 1495, column 17 +-- Equation name is '_LC5_C22', type is buried +_LC5_C22 = DFFE( _EQ271, CT5, VCC, VCC, VCC); + _EQ271 = CTV6 & CTV7 & !_LC6_C21; + +-- Node name is ':2032' from file "sprint08.tdf" line 1516, column 25 +-- Equation name is '_LC7_C5', type is buried +!_LC7_C5 = _LC7_C5~NOT; +_LC7_C5~NOT = DFFE( _EQ272, KB_F12, /RESET, VCC, VCC); + _EQ272 = !KB_CTRL & _LC7_C5 + # KB_CTRL & !_LC7_C5; + +-- Node name is ':2034' from file "sprint08.tdf" line 1529, column 10 +-- Equation name is '_LC7_B20', type is buried +_LC7_B20 = DFFE( _EQ273, GLOBAL( TG42), VCC, VCC, VCC); + _EQ273 = !CT0 & CT2 & TURBO + # CT0 & !CT2 & TURBO + # CT3 & !TURBO; + +-- Node name is ':2040' from file "sprint08.tdf" line 1559, column 62 +-- Equation name is '_LC6_B7', type is buried +_LC6_B7 = DFFE( _EQ274, CT2, !/IOM1, VCC, VCC); + _EQ274 = DD7 + # DD6 + # _LC4_B7; + +-- Node name is ':2041' from file "sprint08.tdf" line 1559, column 87 +-- Equation name is '_LC4_B7', type is buried +_LC4_B7 = DFFE( _LC1_B7, CT2, !/IOM1, VCC, VCC); + +-- Node name is ':2042' from file "sprint08.tdf" line 1559, column 91 +-- Equation name is '_LC1_B7', type is buried +_LC1_B7 = DFFE( VCC, CT2, !/IOM1, VCC, VCC); + +-- Node name is ':2043' from file "sprint08.tdf" line 1563, column 4 +-- Equation name is '_LC5_A3', type is buried +_LC5_A3 = DFFE( _EQ275, GLOBAL( TG42), BLK_R, VCC, VCC); + _EQ275 = _EC1_B & _EC3_B & _EC5_B & _EC8_B; + +-- Node name is ':2054' from file "sprint08.tdf" line 1630, column 8 +-- Equation name is '_LC5_B9', type is buried +_LC5_B9 = LCELL( _EQ276); + _EQ276 = MD4 & MD5 & MD6 & MD7; + +-- Node name is ':2058' from file "sprint08.tdf" line 1723, column 11 +-- Equation name is '_LC1_A18', type is buried +_LC1_A18 = DFFE( SINC_HH, !CTH1, VCC, VCC, VCC); + +-- Node name is ':2061' from file "sprint08.tdf" line 1729, column 9 +-- Equation name is '_LC8_C22', type is buried +_LC8_C22 = DFFE( _EQ277, CT5, VCC, VCC, VCC); + _EQ277 = !CTV7 & !_LC1_A18 + # !CTV6 & !_LC1_A18 + # !_LC1_A18 & _LC6_C21 + # CTV6 & CTV7 & _LC1_A18 & !_LC6_C21; + +-- Node name is ':2069' from file "sprint08.tdf" line 1875, column 13 +-- Equation name is '_LC6_B21', type is buried +_LC6_B21 = DFFE( V_WE, GLOBAL(!TG42), VCC, VCC, VCC); + +-- Node name is ':2071' from file "sprint08.tdf" line 1883, column 11 +-- Equation name is '_LC1_B23', type is buried +_LC1_B23 = LCELL( V_WE); + +-- Node name is ':2140' from file "sprint08.tdf" line 2479, column 28 +-- Equation name is '_LC8_C1', type is buried +_LC8_C1 = LCELL( _EQ278); + _EQ278 = KB_D1 & KB_D2 & KB_D3 & !KB_D5; + +-- Node name is ':2142' from file "sprint08.tdf" line 2501, column 7 +-- Equation name is '_LC7_C3', type is buried +_LC7_C3 = LCELL( _EQ279); + _EQ279 = KB_CT2 & !RXA0 & !RXA1 + # !KB_CT1 & !RXA0 & !RXA1; + +-- Node name is ':2143' from file "sprint08.tdf" line 2513, column 34 +-- Equation name is '_LC5_C9', type is buried +_LC5_C9 = LCELL( _EQ280); + _EQ280 = KDD6 & KDD7; + +-- Node name is ':2144' from file "sprint08.tdf" line 2513, column 8 +-- Equation name is '_LC4_C6', type is buried +_LC4_C6 = LCELL( _EQ281); + _EQ281 = /IO & !RXA0 & !RXA1; + +-- Node name is ':2149' from file "sprint08.tdf" line 2558, column 21 +-- Equation name is '_LC1_C3', type is buried +_LC1_C3 = LCELL( _EQ282); + _EQ282 = !KB_CT0 & KB_CT1 & !KB_CT2; + +-- Node name is ':2195' from file "sprint08.tdf" line 3103, column 32 +-- Equation name is '_LC2_B16', type is buried +_LC2_B16 = LCELL( _EQ283); + _EQ283 = /IOM1 + # /WR + # _LC1_B16 + # _LC2_B5; + +-- Node name is ':2198' from file "sprint08.tdf" line 3116, column 95 +-- Equation name is '_LC5_A1', type is buried +_LC5_A1 = LCELL( _EQ284); + _EQ284 = AY_D_WR + # !AY_AAX0; + +-- Node name is ':2199' from file "sprint08.tdf" line 3116, column 21 +-- Equation name is '_LC3_A17', type is buried +_LC3_A17 = DFFE( _EQ285, GLOBAL( TG42), VCC, VCC, VCC); + _EQ285 = _LC2_A17 + # !AY_CCC1 + # !_EC8_A; + +-- Node name is ':2200' from file "sprint08.tdf" line 3141, column 14 +-- Equation name is '_LC8_A9', type is buried +_LC8_A9 = LCELL( _EQ286); + _EQ286 = !_EC5_A + # _EC2_A + # !AY_CX & _EC8_A; + +-- Node name is ':2201' from file "sprint08.tdf" line 3157, column 15 +-- Equation name is '_LC4_A9', type is buried +_LC4_A9 = DFFE( _EQ287, GLOBAL( TG42), VCC, VCC, VCC); + _EQ287 = AY_CCC1 & !_EC5_A & !_EC8_A & _LC3_A9; + +-- Node name is ':2202' from file "sprint08.tdf" line 3162, column 14 +-- Equation name is '_LC1_A9', type is buried +_LC1_A9 = DFFE( _EQ288, GLOBAL( TG42), VCC, VCC, VCC); + _EQ288 = AY_CCC1 & _EC2_A & _EC5_A & _EC8_A + # AY_CCC1 & !_EC2_A & _EC5_A & !_EC8_A; + +-- Node name is ':2203' from file "sprint08.tdf" line 3164, column 5 +-- Equation name is '_LC5_A9', type is buried +_LC5_A9 = DFFE( _EQ289, GLOBAL( TG42), VCC, VCC, VCC); + _EQ289 = !_EC2_A & _EC5_A & !_EC8_A; + +-- Node name is ':2204' from file "sprint08.tdf" line 3165, column 11 +-- Equation name is '_LC2_A11', type is buried +_LC2_A11 = LCELL( _EQ290); + _EQ290 = !AY_DAT6 & !AY_DAT7 & !_LC6_A2 & _LC8_A12; + +-- Node name is ':2205' from file "sprint08.tdf" line 3167, column 11 +-- Equation name is '_LC4_A23', type is buried +_LC4_A23 = DFFE( _EQ291, GLOBAL( TG42), VCC, VCC, VCC); + _EQ291 = !AY_F_RES & !_EC1_A + # _EC1_A & !/RESET; + +-- Node name is ':2206' from file "sprint08.tdf" line 3171, column 28 +-- Equation name is '_LC7_A3', type is buried +_LC7_A3 = DFFE(!AY_DAT_WR, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is ':2207' from file "sprint08.tdf" line 3173, column 49 +-- Equation name is '_LC5_A10', type is buried +_LC5_A10 = DFFE( _EQ292, GLOBAL( TG42), VCC, VCC, VCC); + _EQ292 = _LC3_A10 + # AY_C & _LC4_A10; + +-- Node name is ':2208' from file "sprint08.tdf" line 3173, column 54 +-- Equation name is '_LC3_A10', type is buried +_LC3_A10 = DFFE(!_EC2_A, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is ':2209' from file "sprint08.tdf" line 3173, column 86 +-- Equation name is '_LC4_A10', type is buried +_LC4_A10 = DFFE( _EC8_A, GLOBAL( TG42), VCC, VCC, VCC); + +-- Node name is ':2213' from file "sprint08.tdf" line 3203, column 21 +-- Equation name is '_LC1_A5', type is buried +_LC1_A5 = LCELL( _EQ293); + _EQ293 = AY_OUT1 & AY_SH0 + # AY_OUT1 & AY_X_3 + # AY_SH0 & AY_X_0 + # AY_X_0 & AY_X_3; + +-- Node name is ':2214' from file "sprint08.tdf" line 3205, column 18 +-- Equation name is '_LC1_A7', type is buried +_LC1_A7 = LCELL( _EQ294); + _EQ294 = AY_OUT2 & AY_SH0 + # AY_OUT2 & AY_X_4 + # AY_SH0 & AY_X_1 + # AY_X_1 & AY_X_4; + +-- Node name is ':2215' from file "sprint08.tdf" line 3207, column 18 +-- Equation name is '_LC3_A12', type is buried +_LC3_A12 = LCELL( _EQ295); + _EQ295 = AY_OUT3 & AY_SH0 + # AY_OUT3 & AY_X_5 + # AY_SH0 & AY_X_2 + # AY_X_2 & AY_X_5; + +-- Node name is ':2216' from file "sprint08.tdf" line 3211, column 17 +-- Equation name is '_LC5_A24', type is buried +_LC5_A24 = DFFE( _EQ296, GLOBAL( TG42), VCC, VCC, VCC); + _EQ296 = !AY_CCC5 & !AY_CCC6 & !AY_CCC7 & !AY_CCC8; + +-- Node name is ':2217' from file "sprint08.tdf" line 3221, column 29 +-- Equation name is '_LC7_A22', type is buried +_LC7_A22 = DFFE( _EQ297, GLOBAL( TG42), VCC, VCC, VCC); + _EQ297 = AY_CX & !_EC1_A & !_EC7_A & _LC5_A22; + +-- Node name is ':2218' from file "sprint08.tdf" line 3223, column 22 +-- Equation name is '_LC1_A21', type is buried +_LC1_A21 = LCELL( _EQ298); + _EQ298 = AY_SH0 & AY_SH4 & A0 + # AY_SH0 & !AY_SH4 & !A0 + # !AY_SH0 & AY_SH4 & !A0 + # !AY_SH0 & !AY_SH4 & A0; + +-- Node name is ':2219' from file "sprint08.tdf" line 3242, column 29 +-- Equation name is '_LC3_A22', type is buried +_LC3_A22 = DFFE( _EQ299, GLOBAL( TG42), VCC, VCC, VCC); + _EQ299 = !AY_BBLK & _EC1_A & !_EC7_A & _LC5_A22; + +-- Node name is ':2220' from file "sprint08.tdf" line 3246, column 16 +-- Equation name is '_LC2_A22', type is buried +_LC2_A22 = DFFE( _EQ300, GLOBAL( TG42), VCC, VCC, VCC); + _EQ300 = !_EC1_A & _EC7_A & _LC5_A22; + +-- Node name is '~2224~1' from file "sprint08.tdf" line 3273, column 11 +-- Equation name is '~2224~1', location is LC3_A8, type is buried. +-- synthesized logic cell +_LC3_A8 = DFFE( _EQ301, AY_CCC1, VCC, VCC, VCC); + _EQ301 = !AY_XXM5 & _LC7_A24 + # AY_CCC7 & _LC7_A24 + # AY_CCC7 & !AY_XXM5; + +-- Node name is ':2224' from file "sprint08.tdf" line 3273, column 11 +-- Equation name is '_LC6_A8', type is buried +_LC6_A8 = DFFE( _EQ302, AY_CCC1, VCC, VCC, VCC); + _EQ302 = !AY_XXM5 & _LC7_A24 + # AY_CCC7 & _LC7_A24 + # AY_CCC7 & !AY_XXM5; + +-- Node name is ':2292' from file "sprint08.tdf" line 734, column 3 +-- Equation name is '_LC1_B10', type is buried +!_LC1_B10 = _LC1_B10~NOT; +_LC1_B10~NOT = LCELL( _EQ303); + _EQ303 = A14 & A15; + +-- Node name is ':2324' from file "sprint08.tdf" line 749, column 23 +-- Equation name is '_LC8_B2', type is buried +_LC8_B2 = LCELL( _LC4_B10); + +-- Node name is ':2363' from file "sprint08.tdf" line 802, column 18 +-- Equation name is '_LC7_B7', type is buried +!_LC7_B7 = _LC7_B7~NOT; +_LC7_B7~NOT = LCELL( _EQ304); + _EQ304 = DD6 & DD7 & !/IOM1 & !/WR; + +-- Node name is '~2463~1' from file "sprint08.tdf" line 856, column 38 +-- Equation name is '~2463~1', location is LC3_A6, type is buried. +-- synthesized logic cell +_LC3_A6 = LCELL( _EQ305); + _EQ305 = D0 & D4 & D6 & D7; + +-- Node name is '~2463~2' from file "sprint08.tdf" line 856, column 38 +-- Equation name is '~2463~2', location is LC5_A15, type is buried. +-- synthesized logic cell +_LC5_A15 = LCELL( _EQ306); + _EQ306 = D1 & !D2; + +-- Node name is ':3452' from file "sprint08.tdf" line 1290, column 19 +-- Equation name is '_LC5_B3', type is buried +_LC5_B3 = LCELL( _EQ307); + _EQ307 = /IOM1 + # /WR + # !DCP_CX; + +-- Node name is ':3466' from file "sprint08.tdf" line 1297, column 21 +-- Equation name is '_LC3_B22', type is buried +!_LC3_B22 = _LC3_B22~NOT; +_LC3_B22~NOT = LCELL( _EQ308); + _EQ308 = !DD0 & DD1 & !DD2; + +-- Node name is ':3493' from file "sprint08.tdf" line 1303, column 39 +-- Equation name is '_LC8_C15', type is buried +_LC8_C15 = LCELL( _EQ309); + _EQ309 = !DD0 & DD1 & DD2 & !D1; + +-- Node name is ':3497' from file "sprint08.tdf" line 1304, column 19 +-- Equation name is '_LC2_B13', type is buried +!_LC2_B13 = _LC2_B13~NOT; +_LC2_B13~NOT = LCELL( _EQ310); + _EQ310 = !DD0 & DD1 & DD2; + +-- Node name is ':3505' from file "sprint08.tdf" line 1305, column 38 +-- Equation name is '_LC7_C15', type is buried +_LC7_C15 = LCELL( _EQ311); + _EQ311 = !DD0 & DD1 & DD2 & D1; + +-- Node name is ':3511' from file "sprint08.tdf" line 1306, column 41 +-- Equation name is '_LC7_B13', type is buried +_LC7_B13 = LCELL( _EQ312); + _EQ312 = !DD0 & DD1 & DD2 & D2; + +-- Node name is ':3513' from file "sprint08.tdf" line 1307, column 20 +-- Equation name is '_LC1_B16', type is buried +!_LC1_B16 = _LC1_B16~NOT; +_LC1_B16~NOT = LCELL( _EQ313); + _EQ313 = !DD0 & !DD1 & !DD2; + +-- Node name is ':3534' from file "sprint08.tdf" line 1308, column 50 +-- Equation name is '_LC3_B6', type is buried +_LC3_B6 = LCELL( _EQ314); + _EQ314 = DCP3 & !_LC6_C15 + # !_LC6_C15 & !PN5; + +-- Node name is '~3551~1' from file "sprint08.tdf" line 1372, column 31 +-- Equation name is '~3551~1', location is LC3_C8, type is buried. +-- synthesized logic cell +_LC3_C8 = LCELL( _EQ315); + _EQ315 = A8 & !A9 & A10 & A11; + +-- Node name is ':3551' from file "sprint08.tdf" line 1372, column 31 +-- Equation name is '_LC6_C8', type is buried +_LC6_C8 = LCELL( _EQ316); + _EQ316 = A12 & A13 & _LC3_C8 & PN4; + +-- Node name is ':3613' from file "sprint08.tdf" line 1394, column 9 +-- Equation name is '_LC4_A8', type is buried +_LC4_A8 = LCELL( _EQ317); + _EQ317 = DD7 & _EC1_B & !/IO; + +-- Node name is ':3622' from file "sprint08.tdf" line 1394, column 9 +-- Equation name is '_LC6_C7', type is buried +_LC6_C7 = LCELL( _EQ318); + _EQ318 = DD7 & _EC5_B & !/IO; + +-- Node name is ':3626' from file "sprint08.tdf" line 1399, column 5 +-- Equation name is '_LC6_B3', type is buried +_LC6_B3 = LCELL( _EQ319); + _EQ319 = DCP4 & !DD7 & !/IO; + +-- Node name is ':3645' from file "sprint08.tdf" line 1399, column 5 +-- Equation name is '_LC4_B3', type is buried +_LC4_B3 = LCELL( _EQ320); + _EQ320 = !DCP4 & !DD7 & !/IO; + +-- Node name is ':3646' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is '_LC2_C23', type is buried +_LC2_C23 = LCELL( _EQ321); + _EQ321 = KBD0 & _LC4_B3; + +-- Node name is ':3648' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is '_LC2_C20', type is buried +_LC2_C20 = LCELL( _EQ322); + _EQ322 = KBD1 & _LC4_B3; + +-- Node name is ':3650' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is '_LC5_C24', type is buried +_LC5_C24 = LCELL( _EQ323); + _EQ323 = KBD2 & _LC4_B3; + +-- Node name is ':3652' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is '_LC1_C4', type is buried +_LC1_C4 = LCELL( _EQ324); + _EQ324 = KBD3 & _LC4_B3; + +-- Node name is ':3657' from file "sprint08.tdf" line 1406, column 13 +-- Equation name is '_LC7_B2', type is buried +_LC7_B2 = LCELL( _EQ325); + _EQ325 = !DCP4 & !DD7 & !/IO & TAPE_IN; + +-- Node name is ':3661' from file "sprint08.tdf" line 1415, column 31 +-- Equation name is '_LC5_B5', type is buried +_LC5_B5 = LCELL( _EQ326); + _EQ326 = DD7 + # DD6; + +-- Node name is ':3682' from file "sprint08.tdf" line 1456, column 24 +-- Equation name is '_LC5_B24', type is buried +_LC5_B24 = LCELL( _EQ327); + _EQ327 = BRD4 & CT5 + # BRD4 & CT4 + # CT4 & CT5; + +-- Node name is ':3754' from file "sprint08.tdf" line 1612, column 40 +-- Equation name is '_LC5_B18', type is buried +_LC5_B18 = LCELL( _EQ328); + _EQ328 = AY_CCC2 & MC_SYCLE + # CAS & !MC_SYCLE + # AY_CCC2 & CAS + # E_CAS_0 & !MC_SYCLE + # AY_CCC2 & E_CAS_0; + +-- Node name is ':3759' from file "sprint08.tdf" line 1613, column 40 +-- Equation name is '_LC4_B18', type is buried +_LC4_B18 = LCELL( _EQ329); + _EQ329 = AY_CCC2 & MC_SYCLE + # CAS & !MC_SYCLE + # AY_CCC2 & CAS + # E_CAS_1 & !MC_SYCLE + # AY_CCC2 & E_CAS_1; + +-- Node name is ':3764' from file "sprint08.tdf" line 1614, column 40 +-- Equation name is '_LC2_B8', type is buried +_LC2_B8 = LCELL( _EQ330); + _EQ330 = AY_CCC2 & MC_SYCLE + # CAS & !MC_SYCLE + # AY_CCC2 & CAS + # E_CAS_2 & !MC_SYCLE + # AY_CCC2 & E_CAS_2; + +-- Node name is ':3769' from file "sprint08.tdf" line 1615, column 40 +-- Equation name is '_LC7_B18', type is buried +_LC7_B18 = LCELL( _EQ331); + _EQ331 = CAS & !MC_SYCLE + # E_CAS_3 & !MC_SYCLE + # AY_CCC2 & MC_SYCLE + # AY_CCC2 & CAS + # AY_CCC2 & E_CAS_3; + +-- Node name is '~3773~1' from file "sprint08.tdf" line 1617, column 29 +-- Equation name is '~3773~1', location is LC4_B8, type is buried. +-- synthesized logic cell +_LC4_B8 = LCELL( _EQ332); + _EQ332 = AY_CCC2 & !MC_SYCLE + # CAS & MC_SYCLE + # AY_CCC2 & CAS; + +-- Node name is ':3773' from file "sprint08.tdf" line 1617, column 29 +-- Equation name is '_LC5_B8', type is buried +_LC5_B8 = LCELL( _EQ333); + _EQ333 = AY_CCC2 & !MC_SYCLE + # CAS & MC_SYCLE + # AY_CCC2 & CAS; + +-- Node name is ':3864' from file "sprint08.tdf" line 1650, column 36 +-- Equation name is '_LC4_B24', type is buried +_LC4_B24 = LCELL( _EQ334); + _EQ334 = CT2 & CT3; + +-- Node name is ':4028' from file "sprint08.tdf" line 1688, column 16 +-- Equation name is '_LC3_C18', type is buried +_LC3_C18 = LCELL( _EQ335); + _EQ335 = !CTV8 + # !_LC3_C21; + +-- Node name is ':4039' from file "sprint08.tdf" line 1691, column 27 +-- Equation name is '_LC3_C21', type is buried +_LC3_C21 = LCELL( _EQ336); + _EQ336 = CTV3 & CTV4 & CTV5; + +-- Node name is ':4069' from file "sprint08.tdf" line 1695, column 20 +-- Equation name is '_LC3_C19', type is buried +_LC3_C19 = LCELL( _EQ337); + _EQ337 = CTF0 & CTF1; + +-- Node name is '~4089~1' from file "sprint08.tdf" line 1724, column 18 +-- Equation name is '~4089~1', location is LC6_C21, type is buried. +-- synthesized logic cell +!_LC6_C21 = _LC6_C21~NOT; +_LC6_C21~NOT = LCELL( _EQ338); + _EQ338 = !CTV3 & CTV4 & CTV5; + +-- Node name is ':4106' from file "sprint08.tdf" line 1758, column 48 +-- Equation name is '_LC7_B1', type is buried +!_LC7_B1 = _LC7_B1~NOT; +_LC7_B1~NOT = LCELL( _EQ339); + _EQ339 = PN0 & PN2 & !SC4 + # !A15; + +-- Node name is '~4228~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4228~1', location is LC3_C2, type is buried. +-- synthesized logic cell +_LC3_C2 = LCELL( _EQ340); + _EQ340 = AA8 & !VCM0 & VCM1 + # DPIC & !VCM0 & !VCM1; + +-- Node name is '~4231~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4231~1', location is LC8_C19, type is buried. +-- synthesized logic cell +_LC8_C19 = LCELL( _EQ341); + _EQ341 = CTF4 & !VCM0 & !VCM1 + # AA9 & !VCM0 & VCM1; + +-- Node name is '~4234~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4234~1', location is LC6_B23, type is buried. +-- synthesized logic cell +_LC6_B23 = LCELL( _EQ342); + _EQ342 = !VCM0 & !VCM1 + # AA10 & !VCM0; + +-- Node name is '~4246~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4246~1', location is LC3_A18, type is buried. +-- synthesized logic cell +_LC3_A18 = LCELL( _EQ343); + _EQ343 = DCOL0 & !VCM0 & !VCM1 + # CTH0 & VCM0; + +-- Node name is '~4249~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4249~1', location is LC4_B19, type is buried. +-- synthesized logic cell +_LC4_B19 = LCELL( _EQ344); + _EQ344 = DCOL1 & !VCM0 & !VCM1 + # AA1 & !VCM0 & VCM1; + +-- Node name is '~4252~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4252~1', location is LC4_C2, type is buried. +-- synthesized logic cell +_LC4_C2 = LCELL( _EQ345); + _EQ345 = DCOL2 & !VCM0 & !VCM1 + # AA2 & !VCM0 & VCM1; + +-- Node name is '~4255~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4255~1', location is LC1_C17, type is buried. +-- synthesized logic cell +_LC1_C17 = LCELL( _EQ346); + _EQ346 = DCOL3 & !VCM0 & !VCM1 + # AA3 & !VCM0 & VCM1; + +-- Node name is '~4258~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4258~1', location is LC5_B21, type is buried. +-- synthesized logic cell +_LC5_B21 = LCELL( _EQ347); + _EQ347 = DCOL4 & !VCM0 & !VCM1 + # AA4 & !VCM0 & VCM1; + +-- Node name is '~4261~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4261~1', location is LC1_B14, type is buried. +-- synthesized logic cell +_LC1_B14 = LCELL( _EQ348); + _EQ348 = DCOL5 & !VCM0 & !VCM1 + # AA5 & !VCM0 & VCM1; + +-- Node name is '~4264~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4264~1', location is LC6_B13, type is buried. +-- synthesized logic cell +_LC6_B13 = LCELL( _EQ349); + _EQ349 = DCOL6 & !VCM0 & !VCM1 + # AA6 & !VCM0 & VCM1; + +-- Node name is '~4267~1' from file "sprint08.tdf" line 1787, column 11 +-- Equation name is '~4267~1', location is LC8_C17, type is buried. +-- synthesized logic cell +_LC8_C17 = LCELL( _EQ350); + _EQ350 = AA7 & !VCM0 & VCM1 + # DCOL7 & !VCM0 & !VCM1; + +-- Node name is ':4686' from file "sprint08.tdf" line 2436, column 19 +-- Equation name is '_LC4_C3', type is buried +!_LC4_C3 = _LC4_C3~NOT; +_LC4_C3~NOT = LCELL( _EQ351); + _EQ351 = !KB_CT0 & !KB_CT1 & !KB_CT2; + +-- Node name is ':4724' from file "sprint08.tdf" line 2449, column 24 +-- Equation name is '_LC2_C3', type is buried +!_LC2_C3 = _LC2_C3~NOT; +_LC2_C3~NOT = LCELL( _EQ352); + _EQ352 = KB_CT0 & !KB_CT1 & !KB_CT2; + +-- Node name is '~4735~1' from file "sprint08.tdf" line 2450, column 20 +-- Equation name is '~4735~1', location is LC7_C1, type is buried. +-- synthesized logic cell +_LC7_C1 = LCELL( _EQ353); + _EQ353 = !KB_D1 & !KB_D2 & KB_D6 & KB_D7; + +-- Node name is '~4735~2' from file "sprint08.tdf" line 2450, column 20 +-- Equation name is '~4735~2', location is LC3_C1, type is buried. +-- synthesized logic cell +_LC3_C1 = LCELL( _EQ354); + _EQ354 = !KB_D3 & !KB_D4 & KB_D8 & _LC7_C1; + +-- Node name is '~4777~1' from file "sprint08.tdf" line 2483, column 76 +-- Equation name is '~4777~1', location is LC5_C5, type is buried. +-- synthesized logic cell +!_LC5_C5 = _LC5_C5~NOT; +_LC5_C5~NOT = LCELL( _EQ355); + _EQ355 = !KB_D4 & !KB_D8; + +-- Node name is '~4777~2' from file "sprint08.tdf" line 2483, column 76 +-- Equation name is '~4777~2', location is LC8_C5, type is buried. +-- synthesized logic cell +_LC8_C5 = LCELL( _EQ356); + _EQ356 = KB_ALT & KB_CTRL & !KB_OFF & !_LC5_C5; + +-- Node name is '~6697~1' from file "sprint08.tdf" line 3108, column 23 +-- Equation name is '~6697~1', location is LC6_A6, type is buried. +-- synthesized logic cell +_LC6_A6 = LCELL( _EQ357); + _EQ357 = D0 & D3; + +-- Node name is ':6723' from file "sprint08.tdf" line 3125, column 14 +-- Equation name is '_LC7_A4', type is buried +_LC7_A4 = LCELL( _EQ358); + _EQ358 = !AY_ADR3 + # !AY_ADR0 + # AY_ADR1 + # !AY_ADR2; + +-- Node name is ':6740' from file "sprint08.tdf" line 3131, column 3 +-- Equation name is '_LC2_A8', type is buried +!_LC2_A8 = _LC2_A8~NOT; +_LC2_A8~NOT = LCELL( _EQ359); + _EQ359 = !AY_CCC0 & !AY_CCC1; + +-- Node name is ':6811' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is '_LC6_A22', type is buried +_LC6_A22 = LCELL( _EQ360); + _EQ360 = AY_CCC1 & _EC1_A; + +-- Node name is ':6813' from file "sprint08.tdf" line 3140, column 13 +-- Equation name is '_LC5_A7', type is buried +_LC5_A7 = LCELL( _EQ361); + _EQ361 = AY_CCC1 & _EC7_A; + +-- Node name is ':6854' from file "sprint08.tdf" line 3167, column 9 +-- Equation name is '_LC7_A9', type is buried +!_LC7_A9 = _LC7_A9~NOT; +_LC7_A9~NOT = LCELL( _EQ362); + _EQ362 = !_LC2_A11 & _LC5_A9 + # !AY_CX & _LC5_A9 + # !_LC2_A11 & !_LC4_A23 + # !AY_CX & !_LC4_A23 + # !_LC4_A23 & !_LC5_A9; + +-- Node name is ':6859' from file "sprint08.tdf" line 3173, column 34 +-- Equation name is '_LC6_A10', type is buried +!_LC6_A10 = _LC6_A10~NOT; +_LC6_A10~NOT = LCELL( _EQ363); + _EQ363 = !_EC1_A & _LC5_A10; + +-- Node name is ':6875' from file "sprint08.tdf" line 3173, column 34 +-- Equation name is '_LC3_A2', type is buried +_LC3_A2 = LCELL( _EQ364); + _EQ364 = _EC3_A + # _EC7_A + # _LC6_A10; + +-- Node name is ':6881' from file "sprint08.tdf" line 3173, column 34 +-- Equation name is '_LC4_A2', type is buried +!_LC4_A2 = _LC4_A2~NOT; +_LC4_A2~NOT = LCELL( _EQ365); + _EQ365 = !_EC3_A & !_EC4_A & !_EC7_A & !_LC6_A10; + +-- Node name is ':6891' from file "sprint08.tdf" line 3173, column 34 +-- Equation name is '_LC3_A11', type is buried +!_LC3_A11 = _LC3_A11~NOT; +_LC3_A11~NOT = LCELL( _EQ366); + _EQ366 = !_EC2_A & !_EC6_A & !_LC4_A2; + +-- Node name is ':6910' from file "sprint08.tdf" line 3178, column 28 +-- Equation name is '_LC6_A2', type is buried +!_LC6_A2 = _LC6_A2~NOT; +_LC6_A2~NOT = LCELL( _EQ367); + _EQ367 = !AY_DAT3 & !AY_DAT4; + +-- Node name is ':6943' from file "sprint08.tdf" line 3213, column 20 +-- Equation name is '_LC6_A5', type is buried +_LC6_A5 = LCELL( _EQ368); + _EQ368 = AY_AMP0 & AY_XX0; + +-- Node name is ':6959' from file "sprint08.tdf" line 3213, column 20 +-- Equation name is '_LC2_A20', type is buried +_LC2_A20 = LCELL( _EQ369); + _EQ369 = AY_AMP1 & AY_XX1 + # AY_AMP0 & AY_XX0 & AY_XX1 + # AY_AMP0 & AY_AMP1 & AY_XX0; + +-- Node name is ':6969' from file "sprint08.tdf" line 3213, column 20 +-- Equation name is '_LC6_A20', type is buried +_LC6_A20 = LCELL( _EQ370); + _EQ370 = AY_XX2 & _LC2_A20 + # AY_AMP2 & _LC2_A20 + # AY_AMP2 & AY_XX2; + +-- Node name is ':6979' from file "sprint08.tdf" line 3213, column 20 +-- Equation name is '_LC7_A20', type is buried +_LC7_A20 = LCELL( _EQ371); + _EQ371 = AY_XX3 & _LC6_A20 + # AY_AMP3 & _LC6_A20 + # AY_AMP3 & AY_XX3; + +-- Node name is ':6994' from file "sprint08.tdf" line 3243, column 38 +-- Equation name is '_LC2_A23', type is buried +_LC2_A23 = LCELL( _EQ372); + _EQ372 = AY_CX & AY_VAR; + +-- Node name is ':7008' from file "sprint08.tdf" line 3243, column 38 +-- Equation name is '_LC6_A23', type is buried +_LC6_A23 = LCELL( _EQ373); + _EQ373 = AY_CX & AY_VAR & AY_VA0 & AY_VA1; + +-- Node name is ':7357' from file "sprint08.tdf" line 3273, column 31 +-- Equation name is '_LC5_A14', type is buried +_LC5_A14 = LCELL( _EQ374); + _EQ374 = AY_CCC2 & !AY_XXM0 & !AY_XXM1 + # AY_CCC2 & AY_CCC3 & !AY_XXM0 + # AY_CCC3 & !AY_XXM1; + +-- Node name is ':7364' from file "sprint08.tdf" line 3273, column 31 +-- Equation name is '_LC7_A14', type is buried +_LC7_A14 = LCELL( _EQ375); + _EQ375 = !AY_XXM2 & _LC5_A14 + # AY_CCC4 & _LC5_A14 + # AY_CCC4 & !AY_XXM2; + +-- Node name is ':7371' from file "sprint08.tdf" line 3273, column 31 +-- Equation name is '_LC2_A14', type is buried +_LC2_A14 = LCELL( _EQ376); + _EQ376 = !AY_XXM3 & _LC7_A14 + # AY_CCC5 & _LC7_A14 + # AY_CCC5 & !AY_XXM3; + +-- Node name is ':7379' from file "sprint08.tdf" line 3273, column 31 +-- Equation name is '_LC7_A24', type is buried +_LC7_A24 = LCELL( _EQ377); + _EQ377 = !AY_XXM4 & _LC2_A14 + # AY_CCC6 & _LC2_A14 + # AY_CCC6 & !AY_XXM4; + +-- Node name is '~7404~1' from file "sprint08.tdf" line 3246, column 50 +-- Equation name is '~7404~1', location is LC2_A9, type is buried. +-- synthesized logic cell +_LC2_A9 = LCELL( _EQ378); + _EQ378 = _EC2_A & _EC5_A & !_EC8_A; + +-- Node name is '~7404~2' from file "sprint08.tdf" line 3246, column 50 +-- Equation name is '~7404~2', location is LC5_A22, type is buried. +-- synthesized logic cell +_LC5_A22 = LCELL( _EQ379); + _EQ379 = AY_CCC1 & _EC3_A & _LC2_A9; + +-- Node name is '~7491~1' from file "sprint08.tdf" line 3165, column 26 +-- Equation name is '~7491~1', location is LC8_A12, type is buried. +-- synthesized logic cell +_LC8_A12 = LCELL( _EQ380); + _EQ380 = !AY_DAT0 & !AY_DAT1 & !AY_DAT2 & !AY_DAT5; + +-- Node name is ':7513' from file "sprint08.tdf" line 3157, column 67 +-- Equation name is '_LC3_A9', type is buried +_LC3_A9 = LCELL( _EQ381); + _EQ381 = !_EC2_A + # AY_C; + +-- Node name is '~7536~1' from file "sprint08.tdf" line 3116, column 73 +-- Equation name is '~7536~1', location is LC2_A17, type is buried. +-- synthesized logic cell +_LC2_A17 = LCELL( _EQ382); + _EQ382 = !_EC5_A + # !_EC2_A + # _EC1_A + # AY_F_RES; + +-- Node name is '~7548~1' from file "sprint08.tdf" line 3114, column 25 +-- Equation name is '~7548~1', location is LC2_B5, type is buried. +-- synthesized logic cell +_LC2_B5 = LCELL( _EQ383); + _EQ383 = !DD7 + # DD6 + # DCP3 + # !_LC1_B5; + +-- Node name is '~7548~2' from file "sprint08.tdf" line 3114, column 25 +-- Equation name is '~7548~2', location is LC6_C15, type is buried. +-- synthesized logic cell +!_LC6_C15 = _LC6_C15~NOT; +_LC6_C15~NOT = LCELL( _EQ384); + _EQ384 = DD0 & !DD1 & !DD2; + +-- Node name is '~7980~1' from file "sprint08.tdf" line 2526, column 6 +-- Equation name is '~7980~1', location is LC7_C8, type is buried. +-- synthesized logic cell +_LC7_C8 = LCELL( _EQ385); + _EQ385 = A10 & !KB_MA0 & !KB_MA2 + # A14 & !KB_MA0 & KB_MA2; + +-- Node name is '~7980~2' from file "sprint08.tdf" line 2526, column 6 +-- Equation name is '~7980~2', location is LC5_C12, type is buried. +-- synthesized logic cell +_LC5_C12 = LCELL( _EQ386); + _EQ386 = A11 & KB_MA0 & !KB_MA2 + # A15 & KB_MA0 & KB_MA2; + +-- Node name is '~7980~3' from file "sprint08.tdf" line 2526, column 6 +-- Equation name is '~7980~3', location is LC1_C8, type is buried. +-- synthesized logic cell +_LC1_C8 = LCELL( _EQ387); + _EQ387 = A8 & !KB_MA2 + # A12 & KB_MA2; + +-- Node name is '~7980~4' from file "sprint08.tdf" line 2526, column 6 +-- Equation name is '~7980~4', location is LC2_C8, type is buried. +-- synthesized logic cell +_LC2_C8 = LCELL( _EQ388); + _EQ388 = A9 & !KB_MA2 + # A13 & KB_MA2; + +-- Node name is '~7980~5' from file "sprint08.tdf" line 2526, column 6 +-- Equation name is '~7980~5', location is LC8_C8, type is buried. +-- synthesized logic cell +_LC8_C8 = LCELL( _EQ389); + _EQ389 = !KB_MA0 & _LC1_C8 + # KB_MA0 & _LC2_C8; + +-- Node name is '~8352~1' from file "sprint08.tdf" line 1600, column 34 +-- Equation name is '~8352~1', location is LC2_B18, type is buried. +-- synthesized logic cell +_LC2_B18 = LCELL( _EQ390); + _EQ390 = AA11 & /IO + # BLK_R; + +-- Node name is ':8372' from file "sprint08.tdf" line 1554, column 69 +-- Equation name is '_LC2_C13', type is buried +!_LC2_C13 = _LC2_C13~NOT; +_LC2_C13~NOT = LCELL( _EQ391); + _EQ391 = !/IO + # !/MR; + +-- Node name is ':8399' from file "sprint08.tdf" line 1495, column 50 +-- Equation name is '_LC2_C22', type is buried +_LC2_C22 = LCELL( _EQ392); + _EQ392 = CTH5 & /M1 + # CTH5 & /IO; + +-- Node name is ':8459' from file "sprint08.tdf" line 1415, column 66 +-- Equation name is '_LC6_B8', type is buried +!_LC6_B8 = _LC6_B8~NOT; +_LC6_B8~NOT = LCELL( _EQ393); + _EQ393 = !BLK_R & !CAS & !MC_SYCLE; + +-- Node name is ':8464' from file "sprint08.tdf" line 1378, column 25 +-- Equation name is '_LC6_B4', type is buried +!_LC6_B4 = _LC6_B4~NOT; +_LC6_B4~NOT = LCELL( _EQ394); + _EQ394 = !/MR & !/M1; + +-- Node name is ':8472' from file "sprint08.tdf" line 1274, column 27 +-- Equation name is '_LC8_B21', type is buried +!_LC8_B21 = _LC8_B21~NOT; +_LC8_B21~NOT = LCELL( _EQ395); + _EQ395 = !BLK_R & !MC_END; + +-- Node name is '~8621~1' from file "sprint08.tdf" line 859, column 58 +-- Equation name is '~8621~1', location is LC1_B5, type is buried. +-- synthesized logic cell +!_LC1_B5 = _LC1_B5~NOT; +_LC1_B5~NOT = LCELL( _EQ396); + _EQ396 = !DCP4 + # DCP5; + +-- Node name is '~8621~2' from file "sprint08.tdf" line 859, column 58 +-- Equation name is '~8621~2', location is LC1_C15, type is buried. +-- synthesized logic cell +_LC1_C15 = LCELL( _EQ397); + _EQ397 = DD0 & DD1 & DD2; + +-- Node name is '~8621~3' from file "sprint08.tdf" line 859, column 58 +-- Equation name is '~8621~3', location is LC8_B5, type is buried. +-- synthesized logic cell +_LC8_B5 = LCELL( _EQ398); + _EQ398 = DCP3 & IN_OUT_CMD & !/MR & !/RD; + +-- Node name is ':8648' from file "sprint08.tdf" line 809, column 30 +-- Equation name is '_LC4_A16', type is buried +_LC4_A16 = LCELL( _EQ399); + _EQ399 = D1 & !D2 & !D4 & !D5 + # !D1 & D2 & D4 + # !D1 & D2 & D5; + +-- Node name is ':8687' from file "sprint08.tdf" line 746, column 52 +-- Equation name is '_LC2_B4', type is buried +_LC2_B4 = LCELL( _EQ400); + _EQ400 = /IO + # /RD; + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_0' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC4_B', type is memory +_EC4_B = MEMORY_SEGMENT( D0, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_1' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC2_B', type is memory +_EC2_B = MEMORY_SEGMENT( D1, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_2' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC6_B', type is memory +_EC6_B = MEMORY_SEGMENT( D2, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_3' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC7_B', type is memory +_EC7_B = MEMORY_SEGMENT( D3, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_4' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC1_B', type is memory +_EC1_B = MEMORY_SEGMENT( D4, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_5' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC3_B', type is memory +_EC3_B = MEMORY_SEGMENT( D5, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_6' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC8_B', type is memory +_EC8_B = MEMORY_SEGMENT( D6, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:195|altram:sram|segment0_7' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC5_B', type is memory +_EC5_B = MEMORY_SEGMENT( D7, GLOBAL(!TG42), VCC,!_LC7_B7, VCC, PGS0, PGS1, PGS2, PGS3, PGS4, PGS5, PGS6, PGS7, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_0' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC3_C', type is memory +_EC3_C = MEMORY_SEGMENT( KDX0, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_1' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC7_C', type is memory +_EC7_C = MEMORY_SEGMENT( KDX1, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_2' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC6_C', type is memory +_EC6_C = MEMORY_SEGMENT( KDX2, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_3' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC1_C', type is memory +_EC1_C = MEMORY_SEGMENT( KDX3, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_4' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC5_C', type is memory +_EC5_C = MEMORY_SEGMENT( KDX4, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_5' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC4_C', type is memory +_EC4_C = MEMORY_SEGMENT( KDX5, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_6' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC8_C', type is memory +_EC8_C = MEMORY_SEGMENT( VCC, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:291|altram:sram|segment0_7' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC2_C', type is memory +_EC2_C = MEMORY_SEGMENT( VCC, GLOBAL( TG42), VCC,!WR_KBD, VCC, KA8, KA9, KA10, KA11, KA12, KA13, KA14, KA15, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_0' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC1_A', type is memory +_EC1_A = MEMORY_SEGMENT( AY_DI0, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_1' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC7_A', type is memory +_EC7_A = MEMORY_SEGMENT( AY_DI1, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_2' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC3_A', type is memory +_EC3_A = MEMORY_SEGMENT( AY_DI2, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_3' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC4_A', type is memory +_EC4_A = MEMORY_SEGMENT( AY_DI3, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_4' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC6_A', type is memory +_EC6_A = MEMORY_SEGMENT( AY_DI4, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_5' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC2_A', type is memory +_EC2_A = MEMORY_SEGMENT( AY_DI5, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_6' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC5_A', type is memory +_EC5_A = MEMORY_SEGMENT( AY_DI6, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + +-- Node name is '|lpm_ram_dq:386|altram:sram|segment0_7' from file "altram.tdf" line 111, column 12 +-- Equation name is '_EC8_A', type is memory +_EC8_A = MEMORY_SEGMENT( AY_DI7, GLOBAL( TG42), GLOBAL( TG42), AY_WR, VCC, AY_AX0, AY_AX1, AY_AX2, AY_AX3, AY_AX4, AY_AX5, _LC4_B17,!_LC2_A8, VCC, VCC, VCC,); + + + +Project Information c:\prj\sprinter\firmware\97\flex\sprint08.rpt + +** COMPILATION SETTINGS & TIMES ** + +Processing Menu Commands +------------------------ + +Design Doctor = off + +Logic Synthesis: + + Synthesis Type Used = Multi-Level + + Default Synthesis Style = NORMAL + + Logic option settings in 'NORMAL' style for 'FLEX10K' family + + CARRY_CHAIN = ignore + CARRY_CHAIN_LENGTH = 32 + CASCADE_CHAIN = ignore + CASCADE_CHAIN_LENGTH = 2 + DECOMPOSE_GATES = on + DUPLICATE_LOGIC_EXTRACTION = on + MINIMIZATION = full + MULTI_LEVEL_FACTORING = on + NOT_GATE_PUSH_BACK = on + REDUCE_LOGIC = on + REFACTORIZATION = on + REGISTER_OPTIMIZATION = on + RESYNTHESIZE_NETWORK = on + SLOW_SLEW_RATE = off + SUBFACTOR_EXTRACTION = on + IGNORE_SOFT_BUFFERS = on + USE_LPM_FOR_AHDL_OPERATORS = off + + Other logic synthesis settings: + + Automatic Global Clock = on + Automatic Global Clear = on + Automatic Global Preset = on + Automatic Global Output Enable = on + Automatic Fast I/O = off + Automatic Register Packing = off + Automatic Open-Drain Pins = on + Automatic Implement in EAB = off + Optimize = 5 + +Default Timing Specifications: None + +Cut All Bidir Feedback Timing Paths = on +Cut All Clear & Preset Timing Paths = on + +Ignore Timing Assignments = off + +Functional SNF Extractor = off + +Linked SNF Extractor = off +Timing SNF Extractor = on +Optimize Timing SNF = off +Generate AHDL TDO File = off +Fitter Settings = NORMAL +Use Quartus Fitter = on +Smart Recompile = off +Total Recompile = off + +Interfaces Menu Commands +------------------------ + +EDIF Netlist Writer = off +Verilog Netlist Writer = off +VHDL Netlist Writer = off + +Compilation Times +----------------- + + Compiler Netlist Extractor 00:00:01 + Database Builder 00:00:00 + Logic Synthesizer 00:00:00 + Partitioner 00:00:00 + Fitter 00:00:01 + Timing SNF Extractor 00:00:01 + Assembler 00:00:00 + -------------------------- -------- + Total Time 00:00:03 + + +Memory Allocated +----------------- + +Peak memory allocated during compilation = 19,110K diff --git a/fw/src/flex/sprint08.sof b/fw/src/flex/sprint08.sof new file mode 100644 index 0000000..b3812c9 Binary files /dev/null and b/fw/src/flex/sprint08.sof differ diff --git a/fw/src/max/SP037032.ACF b/fw/src/max/SP037032.ACF new file mode 100644 index 0000000..e3df92b --- /dev/null +++ b/fw/src/max/SP037032.ACF @@ -0,0 +1,620 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP sp037032 +BEGIN + |CLK_WG : OUTPUT_PIN = 33; + |HD_CS2 : OUTPUT_PIN = 37; + |/RD : INPUT_PIN = 2; + DEVICE = EPM7064SLC44-10; + |/WRH : OUTPUT_PIN = 24; + |MA7 : INPUT_PIN = 36; + |CLK_PRC : OUTPUT_PIN = 27; + |/DTRB : INPUT_PIN = 34; + |RDAT : OUTPUT_PIN = 16; + |RDATA : INPUT_PIN = 17; + |MA0 : INPUT_PIN = 39; + |TG42_IN : INPUT_PIN = 43; + |TG42_OUT : OUTPUT_PIN = 41; + |/CONFIG : OUTPUT_PIN = 40; + |CLKZZ : OUTPUT_PIN = 31; + |/MR : INPUT_PIN = 28; + |/IO : INPUT_PIN = 29; + |HDD_CS : INPUT_PIN = 26; + |/WR : INPUT_PIN = 25; + |RSTB : INPUT_PIN = 21; + |WSTB : INPUT_PIN = 20; + |STE : INPUT_PIN = 19; + |QDAT : OUTPUT_PIN = 14; + |HD_CSS2 : OUTPUT_PIN = 12; + |HD_CSS1 : OUTPUT_PIN = 11; + |HD_OE1 : OUTPUT_PIN = 8; + |HD_CS1 : OUTPUT_PIN = 9; + |HD_WE1 : OUTPUT_PIN = 6; + |HD_OE2 : OUTPUT_PIN = 5; + |HD_WE2 : OUTPUT_PIN = 4; + |D0 : INPUT_PIN = 18; + |EPM_RES : INPUT_PIN = 1; + |CNF_ON : INPUT_PIN = 44; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EPM7256SQC208-7; + AUTO_DEVICE = EPM7256SRC208-7; + AUTO_DEVICE = EPM7192SQC160-7; + AUTO_DEVICE = EPM7160SQC160-7; + AUTO_DEVICE = EPM7160STC100-7; + AUTO_DEVICE = EPM7160SLC84-7; + AUTO_DEVICE = EPM7128SQC160-6; + AUTO_DEVICE = EPM7128STC100-6; + AUTO_DEVICE = EPM7128SQC100-6; + AUTO_DEVICE = EPM7128SLC84-6; + AUTO_DEVICE = EPM7064STC100-5; + AUTO_DEVICE = EPM7064SLC84-5; + AUTO_DEVICE = EPM7064STC44-5; + AUTO_DEVICE = EPM7064SLC44-5; + AUTO_DEVICE = EPM7032STC44-7; + AUTO_DEVICE = EPM7032SLC44-7; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EPM7064SLC44-10; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +LOGIC_OPTIONS +BEGIN + |/WRH : TURBO_BIT = OFF; + |10K_CLK : TURBO_BIT = OFF; + |10K_D0 : TURBO_BIT = OFF; + |/CONFIG : TURBO_BIT = OFF; + |HD_CSS1 : TURBO_BIT = OFF; + |HD_CSS2 : TURBO_BIT = OFF; + |HD_CS1 : TURBO_BIT = OFF; + |HD_CS2 : TURBO_BIT = OFF; + |HD_OE1 : TURBO_BIT = OFF; + |HD_OE2 : TURBO_BIT = OFF; + |HD_WE1 : TURBO_BIT = OFF; + |HD_WE2 : TURBO_BIT = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + SECURITY_BIT = ON; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MULTIVOLT_IO = OFF; + nCEO = UNRESERVED; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + DEVICE_FAMILY = MAX7000S; + AUTO_GLOBAL_OE = OFF; + AUTO_GLOBAL_PRESET = OFF; + AUTO_GLOBAL_CLEAR = OFF; + AUTO_GLOBAL_CLOCK = OFF; + OPTIMIZE_FOR_SPEED = 0; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + STYLE = NORMAL; + AUTO_FAST_IO = OFF; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + FITTER_SETTINGS = ADVANCED; + SMART_RECOMPILE = ON; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + BIDIR_PIN = STRONG; + END_TIME = 0.0ns; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; + ANALYSIS_MODE = DELAY_MATRIX; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + EXPLICIT_FAMILY = 1; + ORIGINAL_MAXPLUS2_VERSION = 8.0; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + TURBO_BIT = ON; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/fw/src/max/SP037032.TDF b/fw/src/max/SP037032.TDF new file mode 100644 index 0000000..82a342c --- /dev/null +++ b/fw/src/max/SP037032.TDF @@ -0,0 +1,288 @@ +TITLE "SINC_controller"; + +Constant HDD_TYPE = 1; + +SUBDESIGN SP037032 + ( + EPM_RES : INPUT; + HD_WE[2..1] : OUTPUT; + HD_OE[2..1] : OUTPUT; + HD_CS[2..1] : OUTPUT; + HD_CSS[2..1]: OUTPUT; + + CLK_WG : OUTPUT; + RDATA : INPUT; + QDAT : OUTPUT; + RDAT : OUTPUT; + + D0 : INPUT; + MA0 : INPUT; + STE : INPUT; + WSTB,RSTB : INPUT; + + /WR : INPUT; + /RD : INPUT; + HDD_CS : INPUT; + + /MR,/IO : INPUT; + CLKZZ : OUTPUT; + +-- /RTSB, + /DTRB : INPUT; + +-- 10K_D0 : OUTPUT; +-- 10K_CLK : OUTPUT; + /CONFIG : OUTPUT; + CNF_ON : INPUT; + TG42_OUT : OUTPUT; + TG42_IN : INPUT; + + CLK_PRC : OUTPUT; + + MA7 : INPUT; + +-- /WRH : INPUT; + /WRH : OUTPUT; + +-- /RDH : OUTPUT; -> NA HD_CS1 + + ) +VARIABLE + + CT[2..0] : DFF; + CLKZZ1 : NODE; + STWG[2..0] : DFF; + WGR[4..0] : DFF; + CT_WG : NODE; + CT_WG1 : NODE; + TB_WG : NODE; + CODE[4..0] : DFF; + TURBING : NODE; + RDAT_X : NODE; + HD_CS_CLK : NODE; + MXX : NODE; + 10K_D0 : NODE; + 10K_CLK : NODE; +BEGIN + +-- ====== Oscillator ========== + TG42_OUT = EXP(TG42_IN); +-- TG42_OUT = !(TG42_IN); + +-- tG42_OUT = LCELL(EXP(TG42_IN)); +-- ============================ + +-- ====== FLEX Loading ======== + + 10K_CLK = LCELL((/MR or /WR or CNF_ON) & +-- (/IO or /WR or HDD_CS or !CNF_ON) & + (/MR or /RD or HDD_CS or !CNF_ON)); + CODE[].clk = 10K_CLK; + CODE[].clrn = /CONFIG & (/IO or /RD); + +IF !CNF_ON THEN + CODE[].d = (CODE[3..0],(CODE2 xor 10K_D0)); +ELSE + CODE[].d = (CODE[3..0],!CODE0); +END IF; + + 10K_D0 = LCELL(CODE4 xor D0); + +-- ============================ + +-- ======= CP FRQ ============= + + CT[].clk = (TG42_IN xor !CT1); + CT[].d = CT[] + 1; + +-- IF CT[] == 2 THEN +-- CT[].d = GND; +-- ELSE +-- CT[].d = CT[] + 1; +-- END IF; + + CLKZZ = TRI(CT1,!CNF_ON); + +-- ============================ + +-- ======== FDD controller ================== + + TURBING = EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & !/DTRB); +-- TURBING = GND; +-- TB_WG = /DTRB or TURBING; + TB_WG = /DTRB; + +-- CT_WG = TFF(VCC,(CT1 xor (CT_WG & (/DTRB or TURBING))),,); + CT_WG = TFF(VCC,(CT1 xor (CT_WG & TURBING)),,); + + CT_WG1 = TFF(VCC,(CT1 xor (CT_WG1 & /DTRB)),,); +-- STWG[].clk = LCELL(CT_WG xor STWG2); + + STWG[].clk = (CT_WG xor STWG2); + STWG[].d = STWG[] + 1; + CLK_WG = STWG2; + + CLK_PRC = STWG0; +-- CLK_PRC = STWG1; + + WGR[].clk = CT_WG1; + IF !RDAT THEN + TABLE WGR[3..0] => WGR[3..0].d; + 0 => 4; 1 => 5; 2 => 4; 3 => 5; + 4 => 6; 5 => 7; 6 => 8; 7 => 8; + 8 => 9; 9 => 9; 10 => 10; 11 => 11; + 12 => 12; 13 => 13; 14 => 14; 15 => 15; + END TABLE; + WGR4.d = WGR4; + +-- IF WGR[3..0] == 0 THEN +-- WGR[3..0].d = 3; +-- WGR4.d = WGR4; +-- ELSE +-- WGR[].d = WGR[] + 1; +-- END IF; + ELSE + IF WGR[3..0] == 0 THEN + WGR[3..0].d = 3; + WGR4.d = WGR4; + ELSE + WGR[].d = WGR[] + 1; + END IF; + END IF; + + +-- RDAT_X = DFF(RDATA,CT_WG1,,); + RDAT_X = EXP(EXP(RDAT_X & EXP(!RDATA & !CT_WG1)) & EXP(RDATA & !CT_WG1)); + +IF !CNF_ON THEN + QDAT = 10K_CLK; + RDAT = 10K_D0; +ELSE + QDAT = WGR4; + RDAT = DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,); +END IF; + +-- ============================================== + +-- ========= HDD Controller ========= + +IF HDD_TYPE == 0 THEN + + MXX = CODE0; + + HD_CS2 = LCELL(HDD_CS or EXP(!HDD_CS)); + + HD_CS_CLK = HD_CS2 or EXP(EXP(EXP(EXP(EXP(!HD_CS2))))); + + HD_CSS1 = HDD_CS or MA7; + HD_CSS2 = HDD_CS or !MA7; + + + HD_CS1 = (/RD or MA0 or HD_CS_CLK or /IO) & + (/RD or CODE0 or HDD_CS or /MR) ; % /RDH % + + /WRH = (/WR or !MA0 or HD_CS_CLK or /IO); % /WRH % + + + HD_OE1 = (HDD_CS or /RD or !MA0 or /IO) & + (HDD_CS or /RD or !CODE0 or /MR); + + HD_WE1 = HDD_CS or /RD or (/IO & /MR); + + + HD_OE2 = HDD_CS or /WR or !MA0; + + + HD_WE2 = HDD_CS or /WR or MA0 or /IO; + +-- ======= RECONFIG ========= + + /CONFIG = LCELL(EPM_RES & (HDD_CS or /MR or /WR)); + +ELSE + + MXX = CODE0; + + HD_CS2 = LCELL(HDD_CS or EXP(!HDD_CS) or /WRH); + + HD_CS_CLK = HDD_CS or EXP(EXP(EXP(EXP(EXP(!HDD_CS))))); + + HD_CSS1 = HDD_CS or MA7; + HD_CSS2 = HDD_CS or !MA7; + + HD_CS1 = HDD_CS or /WR; + + HD_OE1 = (HD_CS_CLK or /RD or !MA0 or /IO) & + (HD_CS_CLK or /WR or !/WRH or !MA0 or /IO) & + (HDD_CS or /RD or !CODE0 or /MR); + + HD_WE1 = (HDD_CS or (/RD & /WR) or /IO); + + +-- HD_OE1 = (HDD_CS or /RD or !MA0) or (HDD_CS or /RD or ); + +-- HD_WE1 = (HDD_CS or /RD or MA0 or /IO); + + + HD_WE2 = (/WR or !MA0 or HD_CS_CLK or /IO); % /WRH % + + HD_OE2 = (/RD or MA0 or HD_CS_CLK or /IO) & + (/RD or CODE0 or HDD_CS or /MR) ; % /RDH % + + + /WRH = DFF((/WRH or !MA0),(/IO or /WR or HDD_CS),(/IO or /RD),); + +% + HD_CS2 = LCELL(HDD_CS or EXP(!HDD_CS)); + + HD_CS_CLK = EXP(EXP(EXP(EXP(EXP(!HD_CS2))))); + + HD_CS1 = VCC; + + HD_CSS1 = HDD_CS or MA7; + HD_CSS2 = HDD_CS or !MA7; + + HD_OE1 = VCC; + HD_WE1 = VCC; + + HD_OE2 = (/RD or HD_CS_CLK or /IO); + HD_WE2 = (/WR or HD_CS_CLK or /IO); +% + +% + TABLE + + (HDD_CS,/RD,/WR,/IO,/MR,MA7,MXX) => (HD_CS[] ,HD_CSS[] ,HD_OE[], HD_WE[]); + (VCC ,X ,X ,X ,X ,X ,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + (GND ,X ,X ,VCC,VCC,X ,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + (GND ,X ,X ,GND,GND,X ,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + (GND ,VCC,VCC,GND,VCC,X ,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + (GND ,GND,GND,GND,VCC,X ,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + (GND ,VCC,VCC,VCC,GND,X ,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + (GND ,GND,GND,VCC,GND,X ,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + + (GND ,X ,X ,VCC,GND,GND,X ) => (VCC,VCC ,VCC,VCC ,VCC,VCC, VCC,VCC); + + (GND ,GND,VCC,GND,VCC,VCC,X ) => (GND,VCC ,GND,VCC ,GND,VCC, VCC,VCC); + (GND ,VCC,GND,GND,VCC,VCC,X ) => (GND,VCC ,GND,VCC ,VCC,VCC, GND,VCC); + + (GND ,GND,VCC,GND,VCC,GND,X ) => (GND,VCC ,VCC,GND ,GND,VCC, VCC,VCC); + (GND ,VCC,GND,GND,VCC,GND,X ) => (GND,VCC ,VCC,GND ,VCC,VCC, GND,VCC); + + (GND ,GND,VCC,VCC,GND,VCC,GND) => (GND,VCC ,VCC,GND ,GND,VCC, VCC,GND); + (GND ,GND,VCC,VCC,GND,VCC,VCC) => (GND,VCC ,VCC,VCC ,VCC,GND, VCC,VCC); + + (GND ,VCC,GND,VCC,GND,VCC,GND) => (VCC,GND ,VCC,VCC ,VCC,VCC, VCC,GND); + (GND ,VCC,GND,VCC,GND,VCC,VCC) => (VCC,GND ,VCC,GND ,VCC,GND, GND,VCC); + + END TABLE; +% +-- ======= RECONFIG ========= + + /CONFIG = LCELL(EPM_RES & (HDD_CS or /MR or MA7 or /WR)); + +END IF; + + +END; + diff --git a/fw/src/max/SP047032.ACF b/fw/src/max/SP047032.ACF new file mode 100644 index 0000000..aee33c7 --- /dev/null +++ b/fw/src/max/SP047032.ACF @@ -0,0 +1,620 @@ +-- +-- Copyright (C) 1988-2000 Altera Corporation +-- Any megafunction design, and related net list (encrypted or decrypted), +-- support information, device programming or simulation file, and any other +-- associated documentation or information provided by Altera or a partner +-- under Altera's Megafunction Partnership Program may be used only to +-- program PLD devices (but not masked PLD devices) from Altera. Any other +-- use of such megafunction design, net list, support information, device +-- programming or simulation file, or any other related documentation or +-- information is prohibited for any other purpose, including, but not +-- limited to modification, reverse engineering, de-compiling, or use with +-- any other silicon devices, unless such use is explicitly licensed under +-- a separate agreement with Altera or a megafunction partner. Title to +-- the intellectual property, including patents, copyrights, trademarks, +-- trade secrets, or maskworks, embodied in any such megafunction design, +-- net list, support information, device programming or simulation file, or +-- any other related documentation or information provided by Altera or a +-- megafunction partner, remains with Altera, the megafunction partner, or +-- their respective licensors. No other licenses, including any licenses +-- needed under any third party's intellectual property, are provided herein. +-- +CHIP sp047032 +BEGIN + DEVICE = EPM7032LC44-12; + |/WRH : OUTPUT_PIN = 24; + |/RD : PIN = 32; + |MA7 : INPUT_PIN = 36; + |/RTSB : INPUT_PIN = 33; + |CLK_PRC : OUTPUT_PIN = 27; + |/DTRB : INPUT_PIN = 34; + |RDAT : OUTPUT_PIN = 16; + |RDATA : INPUT_PIN = 17; + |MA0 : INPUT_PIN = 39; + |TG42_IN : INPUT_PIN = 43; + |TG42_OUT : OUTPUT_PIN = 41; + |/CONFIG : OUTPUT_PIN = 40; + |10K_CLK : OUTPUT_PIN = 38; + |10K_D0 : OUTPUT_PIN = 37; + |CLKZZ : OUTPUT_PIN = 31; + |/MR : INPUT_PIN = 28; + |/IO : INPUT_PIN = 29; + |HDD_CS : INPUT_PIN = 26; + |/WR : INPUT_PIN = 25; + |RSTB : INPUT_PIN = 21; + |WSTB : INPUT_PIN = 20; + |STE : INPUT_PIN = 19; + |QDAT : OUTPUT_PIN = 14; + |CLK_WG : OUTPUT_PIN = 13; + |HD_CSS2 : OUTPUT_PIN = 12; + |HD_CSS1 : OUTPUT_PIN = 11; + |HD_OE1 : OUTPUT_PIN = 8; + |HD_CS1 : OUTPUT_PIN = 9; + |HD_CS2 : OUTPUT_PIN = 7; + |HD_WE1 : OUTPUT_PIN = 6; + |HD_OE2 : OUTPUT_PIN = 5; + |HD_WE2 : OUTPUT_PIN = 4; + |D0 : INPUT_PIN = 18; + |EPM_RES : INPUT_PIN = 1; + |CNF_ON : INPUT_PIN = 44; +END; + +DEFAULT_DEVICES +BEGIN + AUTO_DEVICE = EPM7096QC100-7; + AUTO_DEVICE = EPM7096LC84-7; + AUTO_DEVICE = EPM7096LC68-7; + AUTO_DEVICE = EPM7064QC100-7; + AUTO_DEVICE = EPM7064LC84-7; + AUTO_DEVICE = EPM7064LC68-7; + AUTO_DEVICE = EPM7064TC44-7; + AUTO_DEVICE = EPM7064LC44-7; + AUTO_DEVICE = EPM7032VTC44-12; + AUTO_DEVICE = EPM7032VLC44-12; + AUTO_DEVICE = EPM7032TC44-6; + AUTO_DEVICE = EPM7032QC44-7; + AUTO_DEVICE = EPM7032LC44-6; + ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; +END; + +TIMING_POINT +BEGIN + DEVICE_FOR_TIMING_SYNTHESIS = EPM7032LC44-12; + MAINTAIN_STABLE_SYNTHESIS = OFF; + CUT_ALL_CLEAR_PRESET = ON; + CUT_ALL_BIDIR = ON; +END; + +IGNORED_ASSIGNMENTS +BEGIN + FIT_IGNORE_TIMING = OFF; + DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; + IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; + IGNORE_DEVICE_ASSIGNMENTS = OFF; + IGNORE_LC_ASSIGNMENTS = OFF; + IGNORE_PIN_ASSIGNMENTS = OFF; + IGNORE_CHIP_ASSIGNMENTS = OFF; + IGNORE_TIMING_ASSIGNMENTS = OFF; + IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; + IGNORE_CLIQUE_ASSIGNMENTS = OFF; +END; + +LOGIC_OPTIONS +BEGIN + |/WRH : TURBO_BIT = OFF; + |10K_CLK : TURBO_BIT = OFF; + |10K_D0 : TURBO_BIT = OFF; + |/CONFIG : TURBO_BIT = OFF; + |HD_CSS1 : TURBO_BIT = OFF; + |HD_CSS2 : TURBO_BIT = OFF; + |HD_CS1 : TURBO_BIT = OFF; + |HD_CS2 : TURBO_BIT = OFF; + |HD_OE1 : TURBO_BIT = OFF; + |HD_OE2 : TURBO_BIT = OFF; + |HD_WE1 : TURBO_BIT = OFF; + |HD_WE2 : TURBO_BIT = OFF; +END; + +GLOBAL_PROJECT_DEVICE_OPTIONS +BEGIN + MAX7000B_ENABLE_VREFB = OFF; + MAX7000B_ENABLE_VREFA = OFF; + MAX7000B_VCCIO_IOBANK2 = 3.3V; + MAX7000B_VCCIO_IOBANK1 = 3.3V; + CONFIG_EPROM_PULLUP_RESISTOR = ON; + CONFIG_EPROM_USER_CODE = FFFFFFFF; + FLEX_CONFIGURATION_EPROM = AUTO; + MAX7000AE_ENABLE_JTAG = ON; + MAX7000AE_USER_CODE = FFFFFFFF; + SECURITY_BIT = ON; + FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; + FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; + FLEX6000_ENABLE_JTAG = OFF; + CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; + MULTIVOLT_IO = OFF; + MAX7000S_ENABLE_JTAG = ON; + FLEX10K_ENABLE_LOCK_OUTPUT = OFF; + MAX7000S_USER_CODE = FFFF; + CONFIG_SCHEME_10K = PASSIVE_SERIAL; + FLEX10K_JTAG_USER_CODE = 7F; + ENABLE_INIT_DONE_OUTPUT = OFF; + ENABLE_CHIP_WIDE_OE = OFF; + ENABLE_CHIP_WIDE_RESET = OFF; + nCEO = UNRESERVED; + CLKUSR = UNRESERVED; + ADD17 = UNRESERVED; + ADD16 = UNRESERVED; + ADD15 = UNRESERVED; + ADD14 = UNRESERVED; + ADD13 = UNRESERVED; + ADD0_TO_ADD12 = UNRESERVED; + SDOUT = RESERVED_DRIVES_OUT; + RDCLK = UNRESERVED; + RDYnBUSY = UNRESERVED; + nWS_nRS_nCS_CS = UNRESERVED; + DATA1_TO_DATA7 = UNRESERVED; + DATA0 = RESERVED_TRI_STATED; + FLEX8000_ENABLE_JTAG = OFF; + CONFIG_SCHEME = ACTIVE_SERIAL; + DISABLE_TIME_OUT = OFF; + ENABLE_DCLK_OUTPUT = OFF; + RELEASE_CLEARS = OFF; + AUTO_RESTART = OFF; + USER_CLOCK = OFF; + RESERVED_PINS_PERCENT = 0; + RESERVED_LCELLS_PERCENT = 0; +END; + +GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS +BEGIN + AUTO_GLOBAL_OE = OFF; + AUTO_GLOBAL_PRESET = OFF; + AUTO_GLOBAL_CLEAR = OFF; + AUTO_GLOBAL_CLOCK = OFF; + OPTIMIZE_FOR_SPEED = 0; + DEVICE_FAMILY = MAX7000; + MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; + AUTO_IMPLEMENT_IN_EAB = OFF; + AUTO_OPEN_DRAIN_PINS = ON; + ONE_HOT_STATE_MACHINE_ENCODING = OFF; + AUTO_REGISTER_PACKING = OFF; + STYLE = NORMAL; + AUTO_FAST_IO = OFF; + MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; +END; + +COMPILER_PROCESSING_CONFIGURATION +BEGIN + FITTER_SETTINGS = ADVANCED; + SMART_RECOMPILE = ON; + PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; + GENERATE_AHDL_TDO_FILE = OFF; + RPT_FILE_USER_ASSIGNMENTS = ON; + RPT_FILE_LCELL_INTERCONNECT = ON; + RPT_FILE_HIERARCHY = ON; + RPT_FILE_EQUATIONS = ON; + LINKED_SNF_EXTRACTOR = OFF; + OPTIMIZE_TIMING_SNF = OFF; + TIMING_SNF_EXTRACTOR = ON; + FUNCTIONAL_SNF_EXTRACTOR = OFF; + DESIGN_DOCTOR_RULES = EPLD; + DESIGN_DOCTOR = OFF; +END; + +COMPILER_INTERFACES_CONFIGURATION +BEGIN + VHDL_FLATTEN_BUS = OFF; + VERILOG_FLATTEN_BUS = OFF; + NETLIST_OUTPUT_TIME_SCALE = 0.1ns; + EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; + EDIF_BUS_DELIMITERS = []; + EDIF_FLATTEN_BUS = OFF; + EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; + EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; + EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; + EDIF_OUTPUT_USE_EDC = OFF; + EDIF_INPUT_USE_LMF2 = OFF; + EDIF_INPUT_USE_LMF1 = OFF; + EDIF_OUTPUT_GND = GND; + EDIF_OUTPUT_VCC = VCC; + EDIF_INPUT_GND = GND; + EDIF_INPUT_VCC = VCC; + EDIF_OUTPUT_EDC_FILE = *.edc; + EDIF_INPUT_LMF2 = *.lmf; + EDIF_INPUT_LMF1 = *.lmf; + VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; + VHDL_OUTPUT_DELAY_CONSTRUCTS = VHO_FILE; + VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; + EDIF_TRUNCATE_HIERARCHY_PATH = OFF; + VHDL_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; + VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; + VHDL_WRITER_VERSION = VHDL87; + VHDL_READER_VERSION = VHDL87; + SYNOPSYS_MAPPING_EFFORT = MEDIUM; + SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; + SYNOPSYS_HIERARCHICAL_COMPILATION = ON; + SYNOPSYS_DESIGNWARE = OFF; + SYNOPSYS_COMPILER = DESIGN; + USE_SYNOPSYS_SYNTHESIS = OFF; + VHDL_NETLIST_WRITER = OFF; + VERILOG_NETLIST_WRITER = OFF; + XNF_GENERATE_AHDL_TDX_FILE = ON; + XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; + XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; + EDIF_OUTPUT_VERSION = 200; + EDIF_NETLIST_WRITER = OFF; +END; + +CUSTOM_DESIGN_DOCTOR_RULES +BEGIN + MASTER_RESET = OFF; + EXPANDER_NETWORKS = ON; + RACE_CONDITIONS = ON; + DELAY_CHAINS = ON; + ASYNCHRONOUS_INPUTS = ON; + PRESET_CLEAR_NETWORKS = ON; + STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; + STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; + MULTI_CLOCK_NETWORKS = ON; + MULTI_LEVEL_CLOCKS = ON; + GATED_CLOCKS = ON; + RIPPLE_CLOCKS = ON; +END; + +SIMULATOR_CONFIGURATION +BEGIN + BIDIR_PIN = STRONG; + END_TIME = 0.0ns; + START_TIME = 0.0ns; + GLITCH_TIME = 0.0ns; + GLITCH = OFF; + OSCILLATION_TIME = 0.0ns; + OSCILLATION = OFF; + CHECK_OUTPUTS = OFF; + SETUP_HOLD = OFF; + USE_DEVICE = OFF; +END; + +TIMING_ANALYZER_CONFIGURATION +BEGIN + CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; + LIST_PATH_FREQUENCY = 10MHz; + LIST_PATH_COUNT = 10; + REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; + INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; + INCLUDE_PATHS_LESS_THAN = OFF; + INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; + INCLUDE_PATHS_GREATER_THAN = OFF; + DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; + CELL_WIDTH = 18; + LIST_ONLY_LONGEST_PATH = ON; + CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; + CUT_OFF_IO_PIN_FEEDBACK = ON; + AUTO_RECALCULATE = OFF; + ANALYSIS_MODE = DELAY_MATRIX; +END; + +OTHER_CONFIGURATION +BEGIN + LAST_MAXPLUS2_VERSION = 10.0; + LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; + ROW_PINS_LCELL_INSERT = ON; + CARRY_OUT_PINS_LCELL_INSERT = OFF; + NORMAL_LCELL_INSERT = ON; + EXPLICIT_FAMILY = 1; + FLEX_10K_52_COLUMNS = 40; + DEFAULT_9K_EXP_PER_LCELL = 1/2; + LCELLS_PER_ROW_PERCENT = 100; + FAN_IN_PER_LCELL_PERCENT = 100; + EXP_PER_LCELL_PERCENT = 100; + ROW_PINS_PERCENT = 50; + ORIGINAL_MAXPLUS2_VERSION = 8.0; + COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 +BEGIN + TURBO_BIT = ON; + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = ON; + REFACTORIZATION = ON; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = ON; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = ON; + TURBO_BIT = ON; + XOR_SYNTHESIS = ON; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = ON; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = ON; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = ON; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = FULL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = AUTO; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = AUTO; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = ON; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = ON; + SOFT_BUFFER_INSERTION = OFF; + FAST_IO = OFF; + IGNORE_SOFT_BUFFERS = OFF; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = ON; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = -1; + CARRY_CHAIN = IGNORE; + CASCADE_CHAIN_LENGTH = -1; + CASCADE_CHAIN = IGNORE; +END; + +DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 +BEGIN + REGISTER_OPTIMIZATION = OFF; + USE_LPM_FOR_AHDL_OPERATORS = OFF; + RESYNTHESIZE_NETWORK = OFF; + MULTI_LEVEL_FACTORING = OFF; + SUBFACTOR_EXTRACTION = OFF; + REFACTORIZATION = OFF; + NOT_GATE_PUSH_BACK = ON; + DUPLICATE_LOGIC_EXTRACTION = OFF; + REDUCE_LOGIC = OFF; + DECOMPOSE_GATES = OFF; + SOFT_BUFFER_INSERTION = ON; + IGNORE_SOFT_BUFFERS = ON; + PARALLEL_EXPANDERS = OFF; + TURBO_BIT = OFF; + XOR_SYNTHESIS = OFF; + SLOW_SLEW_RATE = OFF; + MINIMIZATION = PARTIAL; + CARRY_CHAIN_LENGTH = 32; + CARRY_CHAIN = MANUAL; + CASCADE_CHAIN_LENGTH = 2; + CASCADE_CHAIN = MANUAL; +END; + diff --git a/fw/src/max/SP047032.TDF b/fw/src/max/SP047032.TDF new file mode 100644 index 0000000..e5f5df5 --- /dev/null +++ b/fw/src/max/SP047032.TDF @@ -0,0 +1,233 @@ +TITLE "SINC_controller"; + +Constant HDD_TYPE = 1; + +SUBDESIGN SP047032 + ( + EPM_RES : INPUT; + HD_WE[2..1] : OUTPUT; + HD_OE[2..1] : OUTPUT; + HD_CS[2..1] : OUTPUT; + HD_CSS[2..1]: OUTPUT; + + CLK_WG : OUTPUT; + RDATA : INPUT; + QDAT : OUTPUT; + RDAT : OUTPUT; + + D0 : INPUT; + MA0 : INPUT; + STE : INPUT; + WSTB,RSTB : INPUT; + + /WR : INPUT; + /RD : INPUT; + HDD_CS : INPUT; + + /MR,/IO : INPUT; + CLKZZ : OUTPUT; + + /RTSB,/DTRB : INPUT; + + 10K_D0 : OUTPUT; + 10K_CLK : OUTPUT; + /CONFIG : OUTPUT; + CNF_ON : INPUT; + TG42_OUT : OUTPUT; + TG42_IN : INPUT; + + CLK_PRC : OUTPUT; + + MA7 : INPUT; + +-- /WRH : INPUT; + /WRH : OUTPUT; + +-- /RDH : OUTPUT; -> NA HD_CS1 + + ) +VARIABLE + + CT[2..0] : DFF; + CLKZZ1 : NODE; + STWG[2..0] : DFF; + WGR[4..0] : DFF; + CT_WG : NODE; + CT_WG1 : NODE; + TB_WG : NODE; + CODE[4..0] : DFF; + TURBING : NODE; + RDAT_X : NODE; + HD_CS_CLK : NODE; + MXX : NODE; + +BEGIN + +-- ====== Oscillator ========== + TG42_OUT = EXP(TG42_IN); +-- TG42_OUT = !(TG42_IN); + +-- tG42_OUT = LCELL(EXP(TG42_IN)); +-- ============================ + +-- ====== FLEX Loading ======== + + 10K_CLK = LCELL((/MR or /WR or CNF_ON) & +-- (/IO or /WR or HDD_CS or !CNF_ON) & + (/MR or /RD or HDD_CS or !CNF_ON)); + CODE[].clk = 10K_CLK; + CODE[].clrn = /CONFIG & (/IO or /RD or HDD_CS); + +IF !CNF_ON THEN + CODE[].d = (CODE[3..0],(CODE2 xor 10K_D0)); +ELSE + CODE[].d = (CODE[3..0],!CODE0); +END IF; + 10K_D0 = LCELL(CODE4 xor D0); + +-- ============================ + +-- ======= CP FRQ ============= + + CT[].clk = (TG42_IN xor !CT1); + CT[].d = CT[] + 1; + +-- IF CT[] == 2 THEN +-- CT[].d = GND; +-- ELSE +-- CT[].d = CT[] + 1; +-- END IF; + + CLKZZ = TRI(CT1,!CNF_ON); + +-- ============================ + +-- ======== FDD controller ================== + + TURBING = EXP(EXP(TURBING & !WSTB & !RSTB) & !STE & !/DTRB); +-- TURBING = GND; +-- TB_WG = /DTRB or TURBING; + TB_WG = /DTRB; + +-- CT_WG = TFF(VCC,(CT1 xor (CT_WG & (/DTRB or TURBING))),,); + CT_WG = TFF(VCC,(CT1 xor (CT_WG & TURBING)),,); + + CT_WG1 = TFF(VCC,(CT1 xor (CT_WG1 & /DTRB)),,); +-- STWG[].clk = LCELL(CT_WG xor STWG2); + + STWG[].clk = (CT_WG xor STWG2); + STWG[].d = STWG[] + 1; + CLK_WG = STWG2; + + CLK_PRC = STWG0; +-- CLK_PRC = STWG1; + + WGR[].clk = CT_WG1; + IF !RDAT THEN + TABLE WGR[3..0] => WGR[3..0].d; + 0 => 4; 1 => 5; 2 => 4; 3 => 5; + 4 => 6; 5 => 7; 6 => 8; 7 => 8; + 8 => 9; 9 => 9; 10 => 10; 11 => 11; + 12 => 12; 13 => 13; 14 => 14; 15 => 15; + END TABLE; + WGR4.d = WGR4; + +-- IF WGR[3..0] == 0 THEN +-- WGR[3..0].d = 3; +-- WGR4.d = WGR4; +-- ELSE +-- WGR[].d = WGR[] + 1; +-- END IF; + ELSE + IF WGR[3..0] == 0 THEN + WGR[3..0].d = 3; + WGR4.d = WGR4; + ELSE + WGR[].d = WGR[] + 1; + END IF; + END IF; + + QDAT = WGR4; +-- RDAT_X = DFF(RDATA,CT_WG1,,); + RDAT_X = EXP(EXP(RDAT_X & EXP(!RDATA & !CT_WG1)) & EXP(RDATA & !CT_WG1)); + RDAT = DFF((RDAT_X or !DFF(RDAT_X,CT_WG1,,)),CT_WG1,,); + +-- ============================================== + +-- ========= HDD Controller ========= + +IF HDD_TYPE == 0 THEN + + MXX = CODE0; + + HD_CS2 = LCELL(HDD_CS or EXP(!HDD_CS)); + + HD_CS_CLK = HD_CS2 or EXP(EXP(EXP(EXP(EXP(!HD_CS2))))); + + HD_CSS1 = HDD_CS or MA7; + HD_CSS2 = HDD_CS or !MA7; + + + HD_CS1 = (/RD or MA0 or HD_CS_CLK or /IO) & + (/RD or CODE0 or HDD_CS or /MR) ; % /RDH % + + /WRH = (/WR or !MA0 or HD_CS_CLK or /IO); % /WRH % + + + HD_OE1 = (HDD_CS or /RD or !MA0 or /IO) & + (HDD_CS or /RD or !CODE0 or /MR); + + HD_WE1 = HDD_CS or /RD or (/IO & /MR); + + + HD_OE2 = HDD_CS or /WR or !MA0; + + + HD_WE2 = HDD_CS or /WR or MA0 or /IO; + +-- ======= RECONFIG ========= + + /CONFIG = LCELL(EPM_RES & (HDD_CS or /MR or /WR)); + +ELSE + + MXX = CODE0; + + HD_CS2 = LCELL(HDD_CS or EXP(!HDD_CS) or /WRH); + + HD_CS_CLK = HDD_CS or EXP(EXP(EXP(EXP(EXP(!HDD_CS))))); + + HD_CSS1 = HDD_CS or MA7; + HD_CSS2 = HDD_CS or !MA7; + + HD_CS1 = HDD_CS or /WR; + + HD_OE1 = (HD_CS_CLK or /RD or !MA0 or /IO) & + (HD_CS_CLK or /WR or !/WRH or !MA0 or /IO) & + (HDD_CS or /RD or !CODE0 or /MR); + +-- HD_WE1 = (HDD_CS or (/RD & /WR) or /IO); + + HD_WE1 = DFF(GND,!HDD_CS,,!(/RD & /WR)); + +-- HD_OE1 = (HDD_CS or /RD or !MA0) or (HDD_CS or /RD or ); + +-- HD_WE1 = (HDD_CS or /RD or MA0 or /IO); + + HD_WE2 = (/WR or !MA0 or HD_CS_CLK or /IO); % /WRH % + + HD_OE2 = (/RD or MA0 or HD_CS_CLK or /IO) & + (/RD or CODE0 or HDD_CS or /MR) ; % /RDH % + + + /WRH = DFF((/WRH or !MA0),(/IO or /WR or HDD_CS),(/IO or /RD or HDD_CS),); + +-- ======= RECONFIG ========= + + /CONFIG = LCELL(EPM_RES & (HDD_CS or /MR or MA7 or /WR)); + +END IF; + + +END; + diff --git a/fw/src/max/sp037032.pof b/fw/src/max/sp037032.pof new file mode 100644 index 0000000..062e601 Binary files /dev/null and b/fw/src/max/sp037032.pof differ diff --git a/fw/src/max/sp037032.rpt b/fw/src/max/sp037032.rpt new file mode 100644 index 0000000..12d6463 --- /dev/null +++ b/fw/src/max/sp037032.rpt @@ -0,0 +1,910 @@ +Project Information c:\prj\sprinter\firmware\97\max\sp037032.rpt + +MAX+plus II Compiler Report File +Version 10.0 9/14/2000 +Compiled: 08/05/2024 18:38:47 + +Copyright (C) 1988-2000 Altera Corporation +Any megafunction design, and related net list (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only to +program PLD devices (but not masked PLD devices) from Altera. Any other +use of such megafunction design, net list, support information, device +programming or simulation file, or any other related documentation or +information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to +the intellectual property, including patents, copyrights, trademarks, +trade secrets, or maskworks, embodied in any such megafunction design, +net list, support information, device programming or simulation file, or +any other related documentation or information provided by Altera or a +megafunction partner, remains with Altera, the megafunction partner, or +their respective licensors. No other licenses, including any licenses +needed under any third party's intellectual property, are provided herein. + + + +***** Project compilation was successful + + +SINC_controller + + +** DEVICE SUMMARY ** + +Chip/ Input Output Bidir Shareable +POF Device Pins Pins Pins LCs Expanders % Utilized + +sp037032 EPM7064SLC44-10 16 16 0 35 40 54 % + +User Pins: 16 16 0 + + + +Project Information c:\prj\sprinter\firmware\97\max\sp037032.rpt + +** PROJECT COMPILATION MESSAGES ** + +Warning: Line 63, File c:\prj\sprinter\firmware\97\max\sp037032.tdf: + Symbolic name "MXX" was declared but never used +Warning: Line 53, File c:\prj\sprinter\firmware\97\max\sp037032.tdf: + Symbolic name "CLKZZ1" was declared but never used +Warning: Line 58, File c:\prj\sprinter\firmware\97\max\sp037032.tdf: + Symbolic name "TB_WG" was declared but never used +Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead. + + +Project Information c:\prj\sprinter\firmware\97\max\sp037032.rpt + +** PIN/LOCATION/CHIP ASSIGNMENTS ** + + Actual + User Assignments +Assignments (if different) Node Name + +sp037032@27 CLK_PRC +sp037032@33 CLK_WG +sp037032@31 CLKZZ +sp037032@44 CNF_ON +sp037032@40 /CONFIG +sp037032@34 /DTRB +sp037032@18 D0 +sp037032@1 EPM_RES +sp037032@11 HD_CSS1 +sp037032@12 HD_CSS2 +sp037032@9 HD_CS1 +sp037032@37 HD_CS2 +sp037032@26 HDD_CS +sp037032@8 HD_OE1 +sp037032@5 HD_OE2 +sp037032@6 HD_WE1 +sp037032@4 HD_WE2 +sp037032@29 /IO +sp037032@39 MA0 +sp037032@36 MA7 +sp037032@28 /MR +sp037032@14 QDAT +sp037032@2 /RD +sp037032@16 RDAT +sp037032@17 RDATA +sp037032@21 RSTB +sp037032@19 STE +sp037032@43 TG42_IN +sp037032@41 TG42_OUT +sp037032@25 /WR +sp037032@24 /WRH +sp037032@20 WSTB + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +***** Logic for device 'sp037032' compiled without errors. + + + + +Device: EPM7064SLC44-10 + +Device Options: + Turbo Bit = ON + Security Bit = ON + Enable JTAG Support = ON + User Code = ffff + + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** ERROR SUMMARY ** + +Info: Chip 'sp037032' in device 'EPM7064SLC44-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device + T + E T G / + H H H P C G 4 C + D D D M N 4 2 O + _ _ _ _ F 2 _ N + W O W V / R _ _ G O F + E E E C R E O I N U I + 1 2 2 C D S N N D T G + -----------------------------------_ + / 6 5 4 3 2 1 44 43 42 41 40 | + #TDI | 7 39 | MA0 + HD_OE1 | 8 38 | #TDO + HD_CS1 | 9 37 | HD_CS2 + GND | 10 36 | MA7 + HD_CSS1 | 11 35 | VCC + HD_CSS2 | 12 EPM7064SLC44-10 34 | /DTRB + #TMS | 13 33 | CLK_WG + QDAT | 14 32 | #TCK + VCC | 15 31 | CLKZZ + RDAT | 16 30 | GND + RDATA | 17 29 | /IO + |_ 18 19 20 21 22 23 24 25 26 27 28 _| + ------------------------------------ + D S W R G V / / H C / + 0 T S S N C W W D L M + E T T D C R R D K R + B B H _ _ + C P + S R + C + + + +N.C. = No Connect. This pin has no internal connection to the device. +VCC = Dedicated power pin, which MUST be connected to VCC. +GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. +RESERVED = Unused I/O pin, which MUST be left unconnected. + +^ = Dedicated configuration pin. ++ = Reserved configuration pin, which is tri-stated during user mode. +* = Reserved configuration pin, which drives out in user mode. +PDn = Power Down pin. +@ = Special-purpose pin. +# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. +& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** RESOURCE USAGE ** + + Shareable External +Logic Array Block Logic Cells I/O Pins Expanders Interconnect + +A: LC1 - LC16 16/16(100%) 8/ 8(100%) 13/16( 81%) 22/36( 61%) +B: LC17 - LC32 8/16( 50%) 8/ 8(100%) 16/16(100%) 15/36( 41%) +C: LC33 - LC48 6/16( 37%) 8/ 8(100%) 13/16( 81%) 16/36( 44%) +D: LC49 - LC64 5/16( 31%) 8/ 8(100%) 3/16( 18%) 11/36( 30%) + + +Total dedicated input pins used: 4/4 (100%) +Total I/O pins used: 32/32 (100%) +Total logic cells used: 35/64 ( 54%) +Total shareable expanders used: 40/64 ( 62%) +Total Turbo logic cells used: 23/64 ( 35%) +Total shareable expanders not available (n/a): 5/64 ( 7%) +Average fan-in: 4.65 +Total fan-in: 163 + +Total input pins required: 16 +Total fast input logic cells required: 0 +Total output pins required: 16 +Total bidirectional pins required: 0 +Total reserved pins required 4 +Total logic cells required: 35 +Total flipflops required: 20 +Total product terms required: 126 +Total logic cells lending parallel expanders: 0 +Total shareable expanders in database: 38 + +Synthesized logic cells: 1/ 64 ( 1%) + + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** INPUTS ** + + Shareable + Expanders Fan-In Fan-Out + Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name + 44 - - INPUT 0 0 0 0 0 2 8 CNF_ON + 34 (51) (D) INPUT 0 0 0 0 0 0 2 /DTRB + 18 (21) (B) INPUT 0 0 0 0 0 0 1 D0 + 1 - - INPUT 0 0 0 0 0 1 0 EPM_RES + 26 (36) (C) INPUT 0 0 0 0 0 10 1 HDD_CS + 29 (41) (C) INPUT 0 0 0 0 0 5 5 /IO + 39 (57) (D) INPUT 0 0 0 0 0 4 0 MA0 + 36 (52) (D) INPUT 0 0 0 0 0 3 0 MA7 + 28 (40) (C) INPUT 0 0 0 0 0 3 1 /MR + 2 - - INPUT 0 0 0 0 0 4 6 /RD + 17 (24) (B) INPUT 0 0 0 0 0 0 2 RDATA + 21 (17) (B) INPUT 0 0 0 0 0 0 1 RSTB + 19 (20) (B) INPUT 0 0 0 0 0 0 1 STE + 43 - - INPUT 0 0 0 0 0 2 1 TG42_IN + 25 (35) (C) INPUT 0 0 0 0 0 6 1 /WR + 20 (19) (B) INPUT 0 0 0 0 0 0 1 WSTB + + +Code: + +s = Synthesized pin or logic cell +t = Turbo logic cell ++ = Synchronous flipflop +/ = Slow slew-rate output +! = NOT gate push-back +r = Fitter-inserted logic cell + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** OUTPUTS ** + + Shareable + Expanders Fan-In Fan-Out + Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name + 27 37 C FF t 2 2 0 0 2 1 1 CLK_PRC + 33 49 D FF t 2 2 0 0 4 2 1 CLK_WG + 31 46 C TRI/FF t 2 2 0 1 2 1 3 CLKZZ + 40 62 D OUTPUT 0 0 0 5 0 0 5 /CONFIG + 11 3 A OUTPUT 0 0 0 2 0 0 0 HD_CSS1 + 12 1 A OUTPUT 0 0 0 2 0 0 0 HD_CSS2 + 9 4 A OUTPUT 0 0 0 2 0 0 0 HD_CS1 + 37 53 D OUTPUT 0 0 0 1 1 0 0 HD_CS2 + 8 5 A OUTPUT 4 4 0 6 2 0 0 HD_OE1 + 5 14 A OUTPUT 4 4 0 5 1 0 0 HD_OE2 + 6 11 A OUTPUT 0 0 0 4 0 0 0 HD_WE1 + 4 16 A OUTPUT 4 4 0 4 0 0 0 HD_WE2 + 14 30 B OUTPUT t 0 0 0 1 2 0 0 QDAT + 16 25 B OUTPUT t 0 0 0 1 2 0 0 RDAT + 41 64 D OUTPUT t 1 0 0 1 0 0 0 TG42_OUT + 24 33 C FF 1 0 0 5 1 3 0 /WRH + + +Code: + +s = Synthesized pin or logic cell +t = Turbo logic cell ++ = Synchronous flipflop +/ = Slow slew-rate output +! = NOT gate push-back +r = Fitter-inserted logic cell + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** BURIED LOGIC ** + + Shareable + Expanders Fan-In Fan-Out + Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name + - 12 A DFFE t 3 2 1 3 5 2 2 CODE0 + - 9 A DFFE t 2 2 0 2 3 0 1 CODE1 + (7) 8 A DFFE t 2 2 0 2 3 0 2 CODE2 + - 13 A DFFE t 2 2 0 2 3 0 1 CODE3 + - 15 A DFFE t 2 2 0 2 3 0 1 CODE4 + (26) 36 C TFFE t 5 0 0 4 2 2 2 CT_WG + - 34 C TFFE t 3 0 0 1 2 0 8 CT_WG1 + (25) 35 C TFFE t 2 2 0 1 1 1 0 CT0 + (36) 52 D TFFE t 2 2 0 0 3 1 0 STWG1 + - 7 A TFFE t 1 0 1 1 7 0 5 WGR0 + (20) 19 B DFFE t 5 1 1 1 8 0 6 WGR1 + - 22 B TFFE t 8 1 0 1 7 0 6 WGR2 + - 6 A DFFE t 4 0 1 1 7 0 6 WGR3 + (21) 17 B TFFE t 0 0 0 1 7 1 0 WGR4 + - 2 A LCELL 0 0 0 5 0 1 5 10K_CLK + - 18 B LCELL 0 0 0 1 1 1 7 10K_D0 + - 23 B DFFE t 4 4 0 1 2 1 6 :97 + (17) 24 B DFFE t 4 4 0 1 1 0 1 :98 + - 10 A SOFT s t 1 0 1 1 5 0 1 ~389~1 + + +Code: + +s = Synthesized pin or logic cell +t = Turbo logic cell ++ = Synchronous flipflop +/ = Slow slew-rate output +! = NOT gate push-back +r = Fitter-inserted logic cell + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** LOGIC CELL INTERCONNECTIONS ** + +Logic Array Block 'A': + + Logic cells placed in LAB 'A' + +------------------------------- LC12 CODE0 + | +----------------------------- LC9 CODE1 + | | +--------------------------- LC8 CODE2 + | | | +------------------------- LC13 CODE3 + | | | | +----------------------- LC15 CODE4 + | | | | | +--------------------- LC3 HD_CSS1 + | | | | | | +------------------- LC1 HD_CSS2 + | | | | | | | +----------------- LC4 HD_CS1 + | | | | | | | | +--------------- LC5 HD_OE1 + | | | | | | | | | +------------- LC14 HD_OE2 + | | | | | | | | | | +----------- LC11 HD_WE1 + | | | | | | | | | | | +--------- LC16 HD_WE2 + | | | | | | | | | | | | +------- LC7 WGR0 + | | | | | | | | | | | | | +----- LC6 WGR3 + | | | | | | | | | | | | | | +--- LC2 10K_CLK + | | | | | | | | | | | | | | | +- LC10 ~389~1 + | | | | | | | | | | | | | | | | + | | | | | | | | | | | | | | | | Other LABs fed by signals + | | | | | | | | | | | | | | | | that feed LAB 'A' +LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A': +LC12 -> * * - - - - - - * * - - - - - - | * - - - | <-- CODE0 +LC9 -> - - * - - - - - - - - - - - - - | * - - - | <-- CODE1 +LC8 -> * - - * - - - - - - - - - - - - | * - - - | <-- CODE2 +LC13 -> - - - - * - - - - - - - - - - - | * - - - | <-- CODE3 +LC7 -> - - - - - - - - - - - - * * - - | * * - - | <-- WGR0 +LC6 -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR3 +LC2 -> * * * * * - - - - - - - - - - - | * * - - | <-- 10K_CLK + +Pin +44 -> * - - - - - - - - - - - * * * * | * * - - | <-- CNF_ON +1 -> - - - - - - - - - - - - - - - - | - - - * | <-- EPM_RES +26 -> - - - - - * * * * * * * - - * - | * - * * | <-- HDD_CS +29 -> * * * * * - - - * * * * - - - - | * - * - | <-- /IO +39 -> - - - - - - - - * * - * - - - - | * - * - | <-- MA0 +36 -> - - - - - * * - - - - - - - - - | * - - * | <-- MA7 +28 -> - - - - - - - - * * - - - - * - | * - - * | <-- /MR +2 -> * * * * * - - - * * * - - - * - | * - * - | <-- /RD +43 -> - - - - - - - - - - - - - - - - | - - * * | <-- TG42_IN +25 -> - - - - - - - * * - * * - - * - | * - * * | <-- /WR +LC62 -> * * * * * - - - - - - - - - - - | * - - - | <-- /CONFIG +LC34 -> - - - - - - - - - - - - * * - - | * * * - | <-- CT_WG1 +LC19 -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR1 +LC22 -> - - - - - - - - - - - - * * - * | * * - - | <-- WGR2 +LC33 -> - - - - - - - - * - - - - - - - | * - * * | <-- /WRH +LC18 -> * - - - - - - - - - - - * * - * | * * - - | <-- 10K_D0 +LC23 -> - - - - - - - - - - - - * * - * | * * - - | <-- :97 + + +* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. +- = The logic cell or pin is not an input to the logic cell (or LAB). + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** LOGIC CELL INTERCONNECTIONS ** + +Logic Array Block 'B': + + Logic cells placed in LAB 'B' + +--------------- LC30 QDAT + | +------------- LC25 RDAT + | | +----------- LC19 WGR1 + | | | +--------- LC22 WGR2 + | | | | +------- LC17 WGR4 + | | | | | +----- LC18 10K_D0 + | | | | | | +--- LC23 :97 + | | | | | | | +- LC24 :98 + | | | | | | | | + | | | | | | | | Other LABs fed by signals + | | | | | | | | that feed LAB 'B' +LC | | | | | | | | | A B C D | Logic cells that feed LAB 'B': +LC19 -> - - * * * - - - | * * - - | <-- WGR1 +LC22 -> - - * * * - - - | * * - - | <-- WGR2 +LC17 -> * - - - * - - - | - * - - | <-- WGR4 +LC18 -> - * * * * - - - | * * - - | <-- 10K_D0 +LC23 -> - * * * * - - - | * * - - | <-- :97 +LC24 -> - - - - - - * - | - * - - | <-- :98 + +Pin +44 -> * * * * * - - - | * * - - | <-- CNF_ON +18 -> - - - - - * - - | - * - - | <-- D0 +1 -> - - - - - - - - | - - - * | <-- EPM_RES +2 -> - - - - - - - - | * - * - | <-- /RD +17 -> - - - - - - * * | - * - - | <-- RDATA +43 -> - - - - - - - - | - - * * | <-- TG42_IN +LC15 -> - - - - - * - - | - * - - | <-- CODE4 +LC34 -> - - * * * - * * | * * * - | <-- CT_WG1 +LC7 -> - - * * * - - - | * * - - | <-- WGR0 +LC6 -> - - * * * - - - | * * - - | <-- WGR3 +LC2 -> * - - - - - - - | * * - - | <-- 10K_CLK +LC10 -> - - * - - - - - | - * - - | <-- ~389~1 + + +* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. +- = The logic cell or pin is not an input to the logic cell (or LAB). + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** LOGIC CELL INTERCONNECTIONS ** + +Logic Array Block 'C': + + Logic cells placed in LAB 'C' + +----------- LC37 CLK_PRC + | +--------- LC46 CLKZZ + | | +------- LC36 CT_WG + | | | +----- LC34 CT_WG1 + | | | | +--- LC35 CT0 + | | | | | +- LC33 /WRH + | | | | | | + | | | | | | Other LABs fed by signals + | | | | | | that feed LAB 'C' +LC | | | | | | | A B C D | Logic cells that feed LAB 'C': +LC46 -> - * * * * - | - - * - | <-- CLKZZ +LC36 -> * - * - - - | - - * * | <-- CT_WG +LC34 -> - - - * - - | * * * - | <-- CT_WG1 +LC35 -> - * - - * - | - - * - | <-- CT0 +LC33 -> - - - - - * | * - * * | <-- /WRH + +Pin +44 -> - - - - - - | * * - - | <-- CNF_ON +34 -> - - * * - - | - - * - | <-- /DTRB +1 -> - - - - - - | - - - * | <-- EPM_RES +26 -> - - - - - * | * - * * | <-- HDD_CS +29 -> - - - - - * | * - * - | <-- /IO +39 -> - - - - - * | * - * - | <-- MA0 +2 -> - - - - - * | * - * - | <-- /RD +21 -> - - * - - - | - - * - | <-- RSTB +19 -> - - * - - - | - - * - | <-- STE +43 -> - * - - * - | - - * * | <-- TG42_IN +25 -> - - - - - * | * - * * | <-- /WR +20 -> - - * - - - | - - * - | <-- WSTB +LC49 -> * - - - - - | - - * * | <-- CLK_WG + + +* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. +- = The logic cell or pin is not an input to the logic cell (or LAB). + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** LOGIC CELL INTERCONNECTIONS ** + +Logic Array Block 'D': + + Logic cells placed in LAB 'D' + +--------- LC49 CLK_WG + | +------- LC62 /CONFIG + | | +----- LC53 HD_CS2 + | | | +--- LC52 STWG1 + | | | | +- LC64 TG42_OUT + | | | | | + | | | | | Other LABs fed by signals + | | | | | that feed LAB 'D' +LC | | | | | | A B C D | Logic cells that feed LAB 'D': +LC49 -> * - - * - | - - * * | <-- CLK_WG +LC52 -> * - - * - | - - - * | <-- STWG1 + +Pin +44 -> - - - - - | * * - - | <-- CNF_ON +1 -> - * - - - | - - - * | <-- EPM_RES +26 -> - * * - - | * - * * | <-- HDD_CS +36 -> - * - - - | * - - * | <-- MA7 +28 -> - * - - - | * - - * | <-- /MR +2 -> - - - - - | * - * - | <-- /RD +43 -> - - - - * | - - * * | <-- TG42_IN +25 -> - * - - - | * - * * | <-- /WR +LC37 -> * - - * - | - - - * | <-- CLK_PRC +LC36 -> * - - * - | - - * * | <-- CT_WG +LC33 -> - - * - - | * - * * | <-- /WRH + + +* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. +- = The logic cell or pin is not an input to the logic cell (or LAB). + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp037032.rpt +sp037032 + +** EQUATIONS ** + +CNF_ON : INPUT; +D0 : INPUT; +EPM_RES : INPUT; +HDD_CS : INPUT; +MA0 : INPUT; +MA7 : INPUT; +RDATA : INPUT; +RSTB : INPUT; +STE : INPUT; +TG42_IN : INPUT; +WSTB : INPUT; +/DTRB : INPUT; +/IO : INPUT; +/MR : INPUT; +/RD : INPUT; +/WR : INPUT; + +-- Node name is 'CLK_PRC' = 'STWG0' from file "sp037032.tdf" line 54, column 6 +-- Equation name is 'CLK_PRC', location is LC037, type is output. + CLK_PRC = TFFE( VCC, _EQ001, VCC, VCC, VCC); + _EQ001 = _X001 & _X002; + _X001 = EXP(!CLK_WG & !CT_WG); + _X002 = EXP( CLK_WG & CT_WG); + +-- Node name is 'CLK_WG' = 'STWG2' from file "sp037032.tdf" line 54, column 6 +-- Equation name is 'CLK_WG', location is LC049, type is output. + CLK_WG = TFFE( _EQ002, _EQ003, VCC, VCC, VCC); + _EQ002 = CLK_PRC & STWG1; + _EQ003 = _X001 & _X002; + _X001 = EXP(!CLK_WG & !CT_WG); + _X002 = EXP( CLK_WG & CT_WG); + +-- Node name is 'CLKZZ' = 'CT1' from file "sp037032.tdf" line 52, column 4 +-- Equation name is 'CLKZZ', location is LC046, type is output. +CLKZZ = TRI(CT1, !CNF_ON); +CT1 = TFFE( CT0, _EQ004, VCC, VCC, VCC); + _EQ004 = _X003 & _X004; + _X003 = EXP( CT1 & !TG42_IN); + _X004 = EXP(!CT1 & TG42_IN); + +-- Node name is 'CODE0' from file "sp037032.tdf" line 59, column 6 +-- Equation name is 'CODE0', location is LC012, type is buried. +CODE0 = DFFE( _EQ005 $ GND, 10K_CLK, !_EQ006, VCC, VCC); + _EQ005 = !CNF_ON & CODE2 & !10K_D0 + # !CNF_ON & !CODE2 & 10K_D0 + # CNF_ON & !CODE0; + _EQ006 = _X005 & _X006; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + +-- Node name is 'CODE1' from file "sp037032.tdf" line 59, column 6 +-- Equation name is 'CODE1', location is LC009, type is buried. +CODE1 = DFFE( CODE0 $ GND, 10K_CLK, !_EQ007, VCC, VCC); + _EQ007 = _X005 & _X006; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + +-- Node name is 'CODE2' from file "sp037032.tdf" line 59, column 6 +-- Equation name is 'CODE2', location is LC008, type is buried. +CODE2 = DFFE( CODE1 $ GND, 10K_CLK, !_EQ008, VCC, VCC); + _EQ008 = _X005 & _X006; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + +-- Node name is 'CODE3' from file "sp037032.tdf" line 59, column 6 +-- Equation name is 'CODE3', location is LC013, type is buried. +CODE3 = DFFE( CODE2 $ GND, 10K_CLK, !_EQ009, VCC, VCC); + _EQ009 = _X005 & _X006; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + +-- Node name is 'CODE4' from file "sp037032.tdf" line 59, column 6 +-- Equation name is 'CODE4', location is LC015, type is buried. +CODE4 = DFFE( CODE3 $ GND, 10K_CLK, !_EQ010, VCC, VCC); + _EQ010 = _X005 & _X006; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + +-- Node name is 'CT_WG' from file "sp037032.tdf" line 116, column 11 +-- Equation name is 'CT_WG', location is LC036, type is buried. +CT_WG = TFFE( VCC, _EQ011, VCC, VCC, VCC); + _EQ011 = _X007 & _X008 & _X009; + _X007 = EXP(!CT_WG & !CT1); + _X008 = EXP( CT_WG & CT1 & _X010); + _X009 = EXP(!CT1 & !/DTRB & !STE & _X011); + _X010 = EXP(!/DTRB & !STE & _X011); + _X011 = EXP(!RSTB & !WSTB & _X010); + +-- Node name is 'CT_WG1' from file "sp037032.tdf" line 118, column 12 +-- Equation name is 'CT_WG1', location is LC034, type is buried. +CT_WG1 = TFFE( VCC, _EQ012, VCC, VCC, VCC); + _EQ012 = _X012 & _X013 & _X014; + _X012 = EXP(!CT_WG1 & !CT1); + _X013 = EXP( CT_WG1 & CT1 & /DTRB); + _X014 = EXP(!CT1 & !/DTRB); + +-- Node name is 'CT0' from file "sp037032.tdf" line 52, column 4 +-- Equation name is 'CT0', location is LC035, type is buried. +CT0 = TFFE( VCC, _EQ013, VCC, VCC, VCC); + _EQ013 = _X003 & _X004; + _X003 = EXP( CT1 & !TG42_IN); + _X004 = EXP(!CT1 & TG42_IN); + +-- Node name is 'HD_CSS1' +-- Equation name is 'HD_CSS1', location is LC003, type is output. + HD_CSS1 = LCELL( _EQ014 $ VCC); + _EQ014 = !HDD_CS & !MA7; + +-- Node name is 'HD_CSS2' +-- Equation name is 'HD_CSS2', location is LC001, type is output. + HD_CSS2 = LCELL( _EQ015 $ VCC); + _EQ015 = !HDD_CS & MA7; + +-- Node name is 'HD_CS1' +-- Equation name is 'HD_CS1', location is LC004, type is output. + HD_CS1 = LCELL( _EQ016 $ VCC); + _EQ016 = !HDD_CS & !/WR; + +-- Node name is 'HD_CS2' = ':107' from file "sp037032.tdf" line 206, column 12 +-- Equation name is 'HD_CS2', type is output + HD_CS2 = LCELL( _EQ017 $ VCC); + _EQ017 = !HDD_CS & !/WRH; + +-- Node name is 'HD_OE1' +-- Equation name is 'HD_OE1', location is LC005, type is output. + HD_OE1 = LCELL( _EQ018 $ VCC); + _EQ018 = !HDD_CS & !/IO & MA0 & !/WR & /WRH & _X015 + # !HDD_CS & !/IO & MA0 & !/RD & _X015 + # CODE0 & !HDD_CS & !/MR & !/RD; + _X015 = EXP( _X016); + _X016 = EXP( _X017); + _X017 = EXP( _X018); + _X018 = EXP(!HDD_CS); + +-- Node name is 'HD_OE2' +-- Equation name is 'HD_OE2', location is LC014, type is output. + HD_OE2 = LCELL( _EQ019 $ VCC); + _EQ019 = !HDD_CS & !/IO & !MA0 & !/RD & _X015 + # !CODE0 & !HDD_CS & !/MR & !/RD; + _X015 = EXP( _X016); + _X016 = EXP( _X017); + _X017 = EXP( _X018); + _X018 = EXP(!HDD_CS); + +-- Node name is 'HD_WE1' +-- Equation name is 'HD_WE1', location is LC011, type is output. + HD_WE1 = LCELL( _EQ020 $ VCC); + _EQ020 = !HDD_CS & !/IO & !/WR + # !HDD_CS & !/IO & !/RD; + +-- Node name is 'HD_WE2' +-- Equation name is 'HD_WE2', location is LC016, type is output. + HD_WE2 = LCELL( _EQ021 $ VCC); + _EQ021 = !HDD_CS & !/IO & MA0 & !/WR & _X015; + _X015 = EXP( _X016); + _X016 = EXP( _X017); + _X017 = EXP( _X018); + _X018 = EXP(!HDD_CS); + +-- Node name is 'QDAT' +-- Equation name is 'QDAT', location is LC030, type is output. + QDAT = LCELL( _EQ022 $ GND); + _EQ022 = CNF_ON & WGR4 + # !CNF_ON & 10K_CLK; + +-- Node name is 'RDAT' +-- Equation name is 'RDAT', location is LC025, type is output. + RDAT = LCELL( _EQ023 $ GND); + _EQ023 = CNF_ON & _LC023 + # !CNF_ON & 10K_D0; + +-- Node name is 'STWG1' from file "sp037032.tdf" line 54, column 6 +-- Equation name is 'STWG1', location is LC052, type is buried. +STWG1 = TFFE( CLK_PRC, _EQ024, VCC, VCC, VCC); + _EQ024 = _X001 & _X002; + _X001 = EXP(!CLK_WG & !CT_WG); + _X002 = EXP( CLK_WG & CT_WG); + +-- Node name is 'TG42_OUT' +-- Equation name is 'TG42_OUT', location is LC064, type is output. + TG42_OUT = LCELL( _EQ025 $ GND); + _EQ025 = _X019; + _X019 = EXP( TG42_IN); + +-- Node name is 'WGR0' from file "sp037032.tdf" line 55, column 5 +-- Equation name is 'WGR0', location is LC007, type is buried. +WGR0 = TFFE( _EQ026, CT_WG1, VCC, VCC, VCC); + _EQ026 = WGR0 & WGR1 & WGR2 & !WGR3 + # !WGR0 & !WGR1 & !WGR2 & WGR3 + # CNF_ON & _LC023 + # !CNF_ON & 10K_D0; + +-- Node name is 'WGR1' from file "sp037032.tdf" line 55, column 5 +-- Equation name is 'WGR1', location is LC019, type is buried. +WGR1 = DFFE( _EQ027 $ _EQ028, CT_WG1, VCC, VCC, VCC); + _EQ027 = CNF_ON & !_LC010 & _LC023 & !WGR0 & !WGR1 & WGR2 & _X020 & + _X021 & _X022 & _X023 + # !CNF_ON & !_LC010 & !WGR0 & !WGR1 & WGR2 & _X020 & _X021 & + _X022 & _X023 & 10K_D0 + # CNF_ON & !_LC010 & _LC023 & WGR0 & WGR1 & _X020 & _X021 & + _X022 & _X023; + _X020 = EXP(!CNF_ON & WGR0 & WGR1 & 10K_D0); + _X021 = EXP(!CNF_ON & !WGR1 & !WGR2 & !10K_D0); + _X022 = EXP( WGR0 & WGR1 & !WGR3); + _X023 = EXP(!WGR0 & !WGR1 & WGR3); + _EQ028 = !_LC010 & _X020 & _X021 & _X022 & _X023; + _X020 = EXP(!CNF_ON & WGR0 & WGR1 & 10K_D0); + _X021 = EXP(!CNF_ON & !WGR1 & !WGR2 & !10K_D0); + _X022 = EXP( WGR0 & WGR1 & !WGR3); + _X023 = EXP(!WGR0 & !WGR1 & WGR3); + +-- Node name is 'WGR2' from file "sp037032.tdf" line 55, column 5 +-- Equation name is 'WGR2', location is LC022, type is buried. +WGR2 = TFFE(!_EQ029, CT_WG1, VCC, VCC, VCC); + _EQ029 = _X020 & _X024 & _X025 & _X026 & _X027 & _X028 & _X029 & + _X030; + _X020 = EXP(!CNF_ON & WGR0 & WGR1 & 10K_D0); + _X024 = EXP(!CNF_ON & WGR1 & WGR2 & !WGR3 & !10K_D0); + _X025 = EXP( CNF_ON & !_LC023 & WGR1 & WGR2 & !WGR3); + _X026 = EXP( CNF_ON & _LC023 & WGR0 & WGR1); + _X027 = EXP( WGR0 & WGR1 & WGR2 & !WGR3); + _X028 = EXP( CNF_ON & !_LC023 & !WGR2 & !WGR3); + _X029 = EXP(!_LC023 & !WGR2 & !WGR3 & !10K_D0); + _X030 = EXP(!CNF_ON & !WGR2 & !WGR3 & !10K_D0); + +-- Node name is 'WGR3' from file "sp037032.tdf" line 55, column 5 +-- Equation name is 'WGR3', location is LC006, type is buried. +WGR3 = DFFE( _EQ030 $ _EQ031, CT_WG1, VCC, VCC, VCC); + _EQ030 = CNF_ON & _LC023 & WGR0 & WGR1 & WGR2 & WGR3 & _X031 & + _X032 & _X033 + # !CNF_ON & WGR0 & WGR1 & WGR2 & WGR3 & _X031 & _X032 & _X033 & + 10K_D0 + # CNF_ON & _LC023 & !WGR0 & !WGR3 & _X031 & _X032 & _X033; + _X031 = EXP(!WGR1 & !WGR3); + _X032 = EXP(!CNF_ON & !WGR0 & !WGR3 & 10K_D0); + _X033 = EXP(!WGR2 & !WGR3); + _EQ031 = _X031 & _X032 & _X033; + _X031 = EXP(!WGR1 & !WGR3); + _X032 = EXP(!CNF_ON & !WGR0 & !WGR3 & 10K_D0); + _X033 = EXP(!WGR2 & !WGR3); + +-- Node name is 'WGR4' from file "sp037032.tdf" line 55, column 5 +-- Equation name is 'WGR4', location is LC017, type is buried. +WGR4 = TFFE( _EQ032, CT_WG1, VCC, VCC, VCC); + _EQ032 = CNF_ON & _LC023 & WGR0 & WGR1 & WGR2 & WGR3 + # !CNF_ON & WGR0 & WGR1 & WGR2 & WGR3 & 10K_D0; + +-- Node name is '10K_CLK' from file "sp037032.tdf" line 77, column 13 +-- Equation name is '10K_CLK', location is LC002, type is buried. +10K_CLK = LCELL( _EQ033 $ VCC); + _EQ033 = CNF_ON & !HDD_CS & !/MR & !/RD + # !CNF_ON & !/MR & !/WR; + +-- Node name is '10K_D0' from file "sp037032.tdf" line 89, column 12 +-- Equation name is '10K_D0', location is LC018, type is buried. +10K_D0 = LCELL( CODE4 $ D0); + +-- Node name is '/CONFIG' = ':115' from file "sp037032.tdf" line 282, column 12 +-- Equation name is '/CONFIG', type is output + /CONFIG = LCELL( _EQ034 $ EPM_RES); + _EQ034 = EPM_RES & !HDD_CS & !MA7 & !/MR & !/WR; + +-- Node name is '/WRH' = ':114' from file "sp037032.tdf" line 233, column 9 +-- Equation name is '/WRH', type is output + /WRH = DFFE( _EQ035 $ VCC, _EQ036, !_EQ037, VCC, VCC); + _EQ035 = MA0 & !/WRH; + _EQ036 = _X034; + _X034 = EXP(!HDD_CS & !/IO & !/WR); + _EQ037 = !/IO & !/RD; + +-- Node name is ':97' from file "sp037032.tdf" line 162, column 9 +-- Equation name is '_LC023', type is buried +_LC023 = DFFE( _EQ038 $ VCC, CT_WG1, VCC, VCC, VCC); + _EQ038 = _LC024 & _X035 & _X036; + _X035 = EXP(!CT_WG1 & RDATA); + _X036 = EXP( _X037 & _X038); + _X037 = EXP(!CT_WG1 & !RDATA); + _X038 = EXP( _X035 & _X036); + +-- Node name is ':98' from file "sp037032.tdf" line 162, column 25 +-- Equation name is '_LC024', type is buried +_LC024 = DFFE( _EQ039 $ GND, CT_WG1, VCC, VCC, VCC); + _EQ039 = _X038; + _X038 = EXP( _X035 & _X036); + _X035 = EXP(!CT_WG1 & RDATA); + _X036 = EXP( _X037 & _X038); + _X037 = EXP(!CT_WG1 & !RDATA); + +-- Node name is '~389~1' from file "sp037032.tdf" line 149, column 14 +-- Equation name is '~389~1', location is LC010, type is buried. +-- synthesized logic cell +_LC010 = LCELL( _EQ040 $ GND); + _EQ040 = CNF_ON & !_LC023 & WGR1 & !WGR3 + # CNF_ON & !_LC023 & !WGR1 & WGR3 + # !CNF_ON & WGR1 & !WGR3 & !10K_D0 + # CNF_ON & !_LC023 & !WGR1 & !WGR2 + # !CNF_ON & !WGR1 & WGR3 & !10K_D0; + + + +-- Shareable expanders that are duplicated in multiple LABs: +-- _X001 occurs in LABs C, D +-- _X002 occurs in LABs C, D + + + + +Project Information c:\prj\sprinter\firmware\97\max\sp037032.rpt + +** COMPILATION SETTINGS & TIMES ** + +Processing Menu Commands +------------------------ + +Design Doctor = off + +Logic Synthesis: + + Synthesis Type Used = Standard + + Default Synthesis Style = NORMAL + + Logic option settings in 'NORMAL' style for 'MAX7000S' family + + DECOMPOSE_GATES = on + DUPLICATE_LOGIC_EXTRACTION = on + MINIMIZATION = full + MULTI_LEVEL_FACTORING = on + NOT_GATE_PUSH_BACK = on + PARALLEL_EXPANDERS = off + REDUCE_LOGIC = on + REFACTORIZATION = on + REGISTER_OPTIMIZATION = on + RESYNTHESIZE_NETWORK = on + SLOW_SLEW_RATE = off + SOFT_BUFFER_INSERTION = on + SUBFACTOR_EXTRACTION = on + TURBO_BIT = on + XOR_SYNTHESIS = on + IGNORE_SOFT_BUFFERS = off + USE_LPM_FOR_AHDL_OPERATORS = off + + Other logic synthesis settings: + + Automatic Global Clock = off + Automatic Global Clear = off + Automatic Global Preset = off + Automatic Global Output Enable = off + Automatic Fast I/O = off + Automatic Register Packing = off + Automatic Open-Drain Pins = on + Automatic Implement in EAB = off + One-Hot State Machine Encoding = off + Optimize = 0 + +Default Timing Specifications: None + +Cut All Bidir Feedback Timing Paths = on +Cut All Clear & Preset Timing Paths = on + +Ignore Timing Assignments = off + +Functional SNF Extractor = off + +Linked SNF Extractor = off +Timing SNF Extractor = on +Optimize Timing SNF = off +Generate AHDL TDO File = off +Fitter Settings = ADVANCED +Smart Recompile = on +Total Recompile = off + +Interfaces Menu Commands +------------------------ + +EDIF Netlist Writer = off +Verilog Netlist Writer = off +VHDL Netlist Writer = off + +Compilation Times +----------------- + + Compiler Netlist Extractor 00:00:00 + Database Builder 00:00:00 + Logic Synthesizer 00:00:00 + Partitioner 00:00:00 + Fitter 00:00:00 + Timing SNF Extractor 00:00:00 + Assembler 00:00:01 + -------------------------- -------- + Total Time 00:00:01 + + +Memory Allocated +----------------- + +Peak memory allocated during compilation = 3,985K diff --git a/fw/src/max/sp047032.pof b/fw/src/max/sp047032.pof new file mode 100644 index 0000000..13c9548 Binary files /dev/null and b/fw/src/max/sp047032.pof differ diff --git a/fw/src/max/sp047032.rpt b/fw/src/max/sp047032.rpt new file mode 100644 index 0000000..8fab0a3 --- /dev/null +++ b/fw/src/max/sp047032.rpt @@ -0,0 +1,811 @@ +Project Information c:\prj\sprinter\firmware\97\max\sp047032.rpt + +MAX+plus II Compiler Report File +Version 10.0 9/14/2000 +Compiled: 08/05/2024 18:38:05 + +Copyright (C) 1988-2000 Altera Corporation +Any megafunction design, and related net list (encrypted or decrypted), +support information, device programming or simulation file, and any other +associated documentation or information provided by Altera or a partner +under Altera's Megafunction Partnership Program may be used only to +program PLD devices (but not masked PLD devices) from Altera. Any other +use of such megafunction design, net list, support information, device +programming or simulation file, or any other related documentation or +information is prohibited for any other purpose, including, but not +limited to modification, reverse engineering, de-compiling, or use with +any other silicon devices, unless such use is explicitly licensed under +a separate agreement with Altera or a megafunction partner. Title to +the intellectual property, including patents, copyrights, trademarks, +trade secrets, or maskworks, embodied in any such megafunction design, +net list, support information, device programming or simulation file, or +any other related documentation or information provided by Altera or a +megafunction partner, remains with Altera, the megafunction partner, or +their respective licensors. No other licenses, including any licenses +needed under any third party's intellectual property, are provided herein. + + + +***** Project compilation was successful + + +SINC_controller + + +** DEVICE SUMMARY ** + +Chip/ Input Output Bidir Shareable +POF Device Pins Pins Pins LCs Expanders % Utilized + +sp047032 EPM7032LC44-12 17 18 0 32 27 100% + +User Pins: 17 18 0 + + + +Project Information c:\prj\sprinter\firmware\97\max\sp047032.rpt + +** PROJECT COMPILATION MESSAGES ** + +Warning: Line 62, File c:\prj\sprinter\firmware\97\max\sp047032.tdf: + Symbolic name "MXX" was declared but never used +Warning: Line 30, File c:\prj\sprinter\firmware\97\max\sp047032.tdf: + Symbolic name "/RTSB" was declared but never used +Warning: Line 52, File c:\prj\sprinter\firmware\97\max\sp047032.tdf: + Symbolic name "CLKZZ1" was declared but never used +Warning: Line 57, File c:\prj\sprinter\firmware\97\max\sp047032.tdf: + Symbolic name "TB_WG" was declared but never used +Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead. +Info: Reserved unused input pin '/RTSB' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board + + +Project Information c:\prj\sprinter\firmware\97\max\sp047032.rpt + +** AUTO GLOBAL SIGNALS ** + + + +INFO: Signal 'CNF_ON' chosen for auto global Output Enable + + +Project Information c:\prj\sprinter\firmware\97\max\sp047032.rpt + +** PIN/LOCATION/CHIP ASSIGNMENTS ** + + Actual + User Assignments +Assignments (if different) Node Name + +sp047032@27 CLK_PRC +sp047032@13 CLK_WG +sp047032@31 CLKZZ +sp047032@44 CNF_ON +sp047032@40 /CONFIG +sp047032@34 /DTRB +sp047032@18 D0 +sp047032@1 EPM_RES +sp047032@11 HD_CSS1 +sp047032@12 HD_CSS2 +sp047032@9 HD_CS1 +sp047032@7 HD_CS2 +sp047032@26 HDD_CS +sp047032@8 HD_OE1 +sp047032@5 HD_OE2 +sp047032@6 HD_WE1 +sp047032@4 HD_WE2 +sp047032@29 /IO +sp047032@39 MA0 +sp047032@36 MA7 +sp047032@28 /MR +sp047032@14 QDAT +sp047032@32 /RD +sp047032@16 RDAT +sp047032@17 RDATA +sp047032@21 RSTB +sp047032@33 /RTSB +sp047032@19 STE +sp047032@43 TG42_IN +sp047032@41 TG42_OUT +sp047032@25 /WR +sp047032@24 /WRH +sp047032@20 WSTB +sp047032@38 10K_CLK +sp047032@37 10K_D0 + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +***** Logic for device 'sp047032' compiled without errors. + + + + +Device: EPM7032LC44-12 + +Device Options: + Turbo Bit = ON + Security Bit = ON + + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** ERROR SUMMARY ** + +Info: Chip 'sp047032' in device 'EPM7032LC44-12' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device +Info: Chip 'sp047032' in device 'EPM7032LC44-12' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device + T + E T G / + H H H P C G 4 C + D D D M N 4 2 O + _ _ _ _ F 2 _ N + W O W V G R _ _ G O F + E E E C N E O I N U I + 1 2 2 C D S N N D T G + -----------------------------------_ + / 6 5 4 3 2 1 44 43 42 41 40 | + HD_CS2 | 7 39 | MA0 + HD_OE1 | 8 38 | 10K_CLK + HD_CS1 | 9 37 | 10K_D0 + GND | 10 36 | MA7 + HD_CSS1 | 11 35 | VCC + HD_CSS2 | 12 EPM7032LC44-12 34 | /DTRB + CLK_WG | 13 33 | /RTSB + QDAT | 14 32 | /RD + VCC | 15 31 | CLKZZ + RDAT | 16 30 | GND + RDATA | 17 29 | /IO + |_ 18 19 20 21 22 23 24 25 26 27 28 _| + ------------------------------------ + D S W R G V / / H C / + 0 T S S N C W W D L M + E T T D C R R D K R + B B H _ _ + C P + S R + C + + + +N.C. = No Connect. This pin has no internal connection to the device. +VCC = Dedicated power pin, which MUST be connected to VCC. +GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. +RESERVED = Unused I/O pin, which MUST be left unconnected. + + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** RESOURCE USAGE ** + + Shareable External +Logic Array Block Logic Cells I/O Pins Expanders Interconnect + +A: LC1 - LC16 16/16(100%) 16/16(100%) 15/16( 93%) 26/36( 72%) +B: LC17 - LC32 16/16(100%) 16/16(100%) 14/16( 87%) 31/36( 86%) + + +Total dedicated input pins used: 3/4 ( 75%) +Total I/O pins used: 32/32 (100%) +Total logic cells used: 32/32 (100%) +Total shareable expanders used: 27/32 ( 84%) +Total Turbo logic cells used: 20/32 ( 62%) +Total shareable expanders not available (n/a): 2/32 ( 6%) +Average fan-in: 4.50 +Total fan-in: 144 + +Total input pins required: 17 +Total output pins required: 18 +Total bidirectional pins required: 0 +Total logic cells required: 32 +Total flipflops required: 21 +Total product terms required: 104 +Total logic cells lending parallel expanders: 0 +Total shareable expanders in database: 25 + +Synthesized logic cells: 0/ 32 ( 0%) + + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** INPUTS ** + + Shareable + Expanders Fan-In Fan-Out + Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name + 44 - - INPUT G 0 0 0 0 0 1 1 CNF_ON + 34 (23) (B) INPUT 0 0 0 0 0 0 2 /DTRB + 18 (13) (A) INPUT 0 0 0 0 0 1 0 D0 + 1 - - INPUT 0 0 0 0 0 1 0 EPM_RES + 26 (30) (B) INPUT 0 0 0 0 0 11 5 HDD_CS + 29 (27) (B) INPUT 0 0 0 0 0 4 5 /IO + 39 (19) (B) INPUT 0 0 0 0 0 4 0 MA0 + 36 (22) (B) INPUT 0 0 0 0 0 3 0 MA7 + 28 (28) (B) INPUT 0 0 0 0 0 4 0 /MR + 32 (25) (B) INPUT 0 0 0 0 0 5 5 /RD + 17 (12) (A) INPUT 0 0 0 0 0 1 1 RDATA + 21 (16) (A) INPUT 0 0 0 0 0 0 1 RSTB + 33 (24) (B) INPUT 0 0 0 0 0 0 0 /RTSB + 19 (14) (A) INPUT 0 0 0 0 0 0 1 STE + 43 - - INPUT 0 0 0 0 0 2 1 TG42_IN + 25 (31) (B) INPUT 0 0 0 0 0 7 0 /WR + 20 (15) (A) INPUT 0 0 0 0 0 0 1 WSTB + + +Code: + +s = Synthesized pin or logic cell +t = Turbo logic cell ++ = Synchronous flipflop +! = NOT gate push-back +r = Fitter-inserted logic cell +G = Global Source. Fan-out destinations counted here do not include destinations +that are driven using global routing resources. Refer to the Auto Global Signals, +Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals +Sections of this Report File for information on which signals' fan-outs are used as +Clock, Clear, Preset, Output Enable, and synchronous Load signals. + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** OUTPUTS ** + + Shareable + Expanders Fan-In Fan-Out + Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name + 27 29 B FF t 2 2 0 0 2 1 1 CLK_PRC + 13 9 A FF t 2 2 0 0 4 2 1 CLK_WG + 31 26 B TRI/FF t 2 2 0 1 2 1 3 CLKZZ + 40 18 B OUTPUT 0 0 0 5 0 0 5 /CONFIG + 11 7 A OUTPUT 0 0 0 2 0 0 0 HD_CSS1 + 12 8 A OUTPUT 0 0 0 2 0 0 0 HD_CSS2 + 9 6 A OUTPUT 0 0 0 2 0 0 0 HD_CS1 + 7 4 A OUTPUT 0 0 0 1 1 0 0 HD_CS2 + 8 5 A OUTPUT 4 4 0 6 2 0 0 HD_OE1 + 5 2 A OUTPUT 4 4 0 5 1 0 0 HD_OE2 + 6 3 A FF 0 0 0 3 0 0 0 HD_WE1 + 4 1 A OUTPUT 4 4 0 4 0 0 0 HD_WE2 + 14 10 A FF t 0 0 0 0 6 0 0 QDAT + 16 11 A FF t 4 4 0 1 2 1 4 RDAT + 41 17 B OUTPUT t 1 0 0 1 0 0 0 TG42_OUT + 24 32 B FF 1 0 0 5 1 3 0 /WRH + 38 20 B OUTPUT 0 0 0 5 0 0 5 10K_CLK + 37 21 B OUTPUT 0 0 0 1 1 0 1 10K_D0 + + +Code: + +s = Synthesized pin or logic cell +t = Turbo logic cell ++ = Synchronous flipflop +! = NOT gate push-back +r = Fitter-inserted logic cell + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** BURIED LOGIC ** + + Shareable + Expanders Fan-In Fan-Out + Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name + (26) 30 B DFFE t 4 3 1 4 5 2 2 CODE0 + (34) 23 B DFFE t 3 3 0 3 3 0 1 CODE1 + (36) 22 B DFFE t 3 3 0 3 3 0 2 CODE2 + (25) 31 B DFFE t 3 3 0 3 3 0 1 CODE3 + (29) 27 B DFFE t 3 3 0 3 3 1 0 CODE4 + (18) 13 A TFFE t 5 0 0 4 2 2 2 CT_WG + (32) 25 B TFFE t 3 0 0 1 2 2 6 CT_WG1 + (28) 28 B TFFE t 2 2 0 1 1 1 0 CT0 + (19) 14 A TFFE t 2 2 0 0 3 1 0 STWG1 + (33) 24 B TFFE t 0 0 0 0 6 1 4 WGR0 + (39) 19 B TFFE t 1 0 1 0 6 1 4 WGR1 + (17) 12 A TFFE t 0 0 0 0 6 1 4 WGR2 + (20) 15 A TFFE t 0 0 0 0 6 1 4 WGR3 + (21) 16 A DFFE t 4 4 0 1 1 1 0 :99 + + +Code: + +s = Synthesized pin or logic cell +t = Turbo logic cell ++ = Synchronous flipflop +! = NOT gate push-back +r = Fitter-inserted logic cell + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** LOGIC CELL INTERCONNECTIONS ** + +Logic Array Block 'A': + + Logic cells placed in LAB 'A' + +------------------------------- LC9 CLK_WG + | +----------------------------- LC13 CT_WG + | | +--------------------------- LC7 HD_CSS1 + | | | +------------------------- LC8 HD_CSS2 + | | | | +----------------------- LC6 HD_CS1 + | | | | | +--------------------- LC4 HD_CS2 + | | | | | | +------------------- LC5 HD_OE1 + | | | | | | | +----------------- LC2 HD_OE2 + | | | | | | | | +--------------- LC3 HD_WE1 + | | | | | | | | | +------------- LC1 HD_WE2 + | | | | | | | | | | +----------- LC10 QDAT + | | | | | | | | | | | +--------- LC11 RDAT + | | | | | | | | | | | | +------- LC14 STWG1 + | | | | | | | | | | | | | +----- LC12 WGR2 + | | | | | | | | | | | | | | +--- LC15 WGR3 + | | | | | | | | | | | | | | | +- LC16 :99 + | | | | | | | | | | | | | | | | + | | | | | | | | | | | | | | | | Other LABs fed by signals + | | | | | | | | | | | | | | | | that feed LAB 'A' +LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A': +LC9 -> * - - - - - - - - - - - * - - - | * * | <-- CLK_WG +LC13 -> * * - - - - - - - - - - * - - - | * * | <-- CT_WG +LC11 -> - - - - - - - - - - * - - * * - | * * | <-- RDAT +LC14 -> * - - - - - - - - - - - * - - - | * - | <-- STWG1 +LC12 -> - - - - - - - - - - * - - * * - | * * | <-- WGR2 +LC15 -> - - - - - - - - - - * - - * * - | * * | <-- WGR3 +LC16 -> - - - - - - - - - - - * - - - - | * - | <-- :99 + +Pin +44 -> - - - - - - - - - - - - - - - - | - * | <-- CNF_ON +34 -> - * - - - - - - - - - - - - - - | * * | <-- /DTRB +1 -> - - - - - - - - - - - - - - - - | - * | <-- EPM_RES +26 -> - - * * * * * * * * - - - - - - | * * | <-- HDD_CS +29 -> - - - - - - * * - * - - - - - - | * * | <-- /IO +39 -> - - - - - - * * - * - - - - - - | * * | <-- MA0 +36 -> - - * * - - - - - - - - - - - - | * * | <-- MA7 +28 -> - - - - - - * * - - - - - - - - | * * | <-- /MR +32 -> - - - - - - * * * - - - - - - - | * * | <-- /RD +17 -> - - - - - - - - - - - * - - - * | * - | <-- RDATA +21 -> - * - - - - - - - - - - - - - - | * - | <-- RSTB +19 -> - * - - - - - - - - - - - - - - | * - | <-- STE +43 -> - - - - - - - - - - - - - - - - | - * | <-- TG42_IN +25 -> - - - - * - * - * * - - - - - - | * * | <-- /WR +20 -> - * - - - - - - - - - - - - - - | * - | <-- WSTB +LC29 -> * - - - - - - - - - - - * - - - | * - | <-- CLK_PRC +LC26 -> - * - - - - - - - - - - - - - - | * * | <-- CLKZZ +LC30 -> - - - - - - * * - - - - - - - - | * * | <-- CODE0 +LC25 -> - - - - - - - - - - * * - * * * | * * | <-- CT_WG1 +LC24 -> - - - - - - - - - - * - - * * - | * * | <-- WGR0 +LC19 -> - - - - - - - - - - * - - * * - | * * | <-- WGR1 +LC32 -> - - - - - * * - - - - - - - - - | * * | <-- /WRH + + +* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. +- = The logic cell or pin is not an input to the logic cell (or LAB). + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** LOGIC CELL INTERCONNECTIONS ** + +Logic Array Block 'B': + + Logic cells placed in LAB 'B' + +------------------------------- LC29 CLK_PRC + | +----------------------------- LC26 CLKZZ + | | +--------------------------- LC30 CODE0 + | | | +------------------------- LC23 CODE1 + | | | | +----------------------- LC22 CODE2 + | | | | | +--------------------- LC31 CODE3 + | | | | | | +------------------- LC27 CODE4 + | | | | | | | +----------------- LC18 /CONFIG + | | | | | | | | +--------------- LC25 CT_WG1 + | | | | | | | | | +------------- LC28 CT0 + | | | | | | | | | | +----------- LC17 TG42_OUT + | | | | | | | | | | | +--------- LC24 WGR0 + | | | | | | | | | | | | +------- LC19 WGR1 + | | | | | | | | | | | | | +----- LC32 /WRH + | | | | | | | | | | | | | | +--- LC20 10K_CLK + | | | | | | | | | | | | | | | +- LC21 10K_D0 + | | | | | | | | | | | | | | | | + | | | | | | | | | | | | | | | | Other LABs fed by signals + | | | | | | | | | | | | | | | | that feed LAB 'B' +LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B': +LC26 -> - * - - - - - - * * - - - - - - | * * | <-- CLKZZ +LC30 -> - - * * - - - - - - - - - - - - | * * | <-- CODE0 +LC23 -> - - - - * - - - - - - - - - - - | - * | <-- CODE1 +LC22 -> - - * - - * - - - - - - - - - - | - * | <-- CODE2 +LC31 -> - - - - - - * - - - - - - - - - | - * | <-- CODE3 +LC27 -> - - - - - - - - - - - - - - - * | - * | <-- CODE4 +LC18 -> - - * * * * * - - - - - - - - - | - * | <-- /CONFIG +LC25 -> - - - - - - - - * - - * * - - - | * * | <-- CT_WG1 +LC28 -> - * - - - - - - - * - - - - - - | - * | <-- CT0 +LC24 -> - - - - - - - - - - - * * - - - | * * | <-- WGR0 +LC19 -> - - - - - - - - - - - * * - - - | * * | <-- WGR1 +LC32 -> - - - - - - - - - - - - - * - - | * * | <-- /WRH +LC20 -> - - * * * * * - - - - - - - - - | - * | <-- 10K_CLK +LC21 -> - - * - - - - - - - - - - - - - | - * | <-- 10K_D0 + +Pin +44 -> - - * - - - - - - - - - - - * - | - * | <-- CNF_ON +34 -> - - - - - - - - * - - - - - - - | * * | <-- /DTRB +18 -> - - - - - - - - - - - - - - - * | - * | <-- D0 +1 -> - - - - - - - * - - - - - - - - | - * | <-- EPM_RES +26 -> - - * * * * * * - - - - - * * - | * * | <-- HDD_CS +29 -> - - * * * * * - - - - - - * - - | * * | <-- /IO +39 -> - - - - - - - - - - - - - * - - | * * | <-- MA0 +36 -> - - - - - - - * - - - - - - - - | * * | <-- MA7 +28 -> - - - - - - - * - - - - - - * - | * * | <-- /MR +32 -> - - * * * * * - - - - - - * * - | * * | <-- /RD +43 -> - * - - - - - - - * * - - - - - | - * | <-- TG42_IN +25 -> - - - - - - - * - - - - - * * - | * * | <-- /WR +LC9 -> * - - - - - - - - - - - - - - - | * * | <-- CLK_WG +LC13 -> * - - - - - - - - - - - - - - - | * * | <-- CT_WG +LC11 -> - - - - - - - - - - - * * - - - | * * | <-- RDAT +LC12 -> - - - - - - - - - - - * * - - - | * * | <-- WGR2 +LC15 -> - - - - - - - - - - - * * - - - | * * | <-- WGR3 + + +* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. +- = The logic cell or pin is not an input to the logic cell (or LAB). + + +Device-Specific Information: c:\prj\sprinter\firmware\97\max\sp047032.rpt +sp047032 + +** EQUATIONS ** + +CNF_ON : INPUT; +D0 : INPUT; +EPM_RES : INPUT; +HDD_CS : INPUT; +MA0 : INPUT; +MA7 : INPUT; +RDATA : INPUT; +RSTB : INPUT; +STE : INPUT; +TG42_IN : INPUT; +WSTB : INPUT; +/DTRB : INPUT; +/IO : INPUT; +/MR : INPUT; +/RD : INPUT; +/RTSB : INPUT; +/WR : INPUT; + +-- Node name is 'CLK_PRC' = 'STWG0' from file "sp047032.tdf" line 53, column 6 +-- Equation name is 'CLK_PRC', location is LC029, type is output. + CLK_PRC = TFFE( VCC, _EQ001, VCC, VCC, VCC); + _EQ001 = _X001 & _X002; + _X001 = EXP(!CLK_WG & !CT_WG); + _X002 = EXP( CLK_WG & CT_WG); + +-- Node name is 'CLK_WG' = 'STWG2' from file "sp047032.tdf" line 53, column 6 +-- Equation name is 'CLK_WG', location is LC009, type is output. + CLK_WG = TFFE( _EQ002, _EQ003, VCC, VCC, VCC); + _EQ002 = CLK_PRC & STWG1; + _EQ003 = _X001 & _X002; + _X001 = EXP(!CLK_WG & !CT_WG); + _X002 = EXP( CLK_WG & CT_WG); + +-- Node name is 'CLKZZ' = 'CT1' from file "sp047032.tdf" line 51, column 4 +-- Equation name is 'CLKZZ', location is LC026, type is output. +CLKZZ = TRI(CT1, GLOBAL(!CNF_ON)); +CT1 = TFFE( CT0, _EQ004, VCC, VCC, VCC); + _EQ004 = _X003 & _X004; + _X003 = EXP( CT1 & !TG42_IN); + _X004 = EXP(!CT1 & TG42_IN); + +-- Node name is 'CODE0' from file "sp047032.tdf" line 58, column 6 +-- Equation name is 'CODE0', location is LC030, type is buried. +CODE0 = DFFE( _EQ005 $ GND, 10K_CLK, !_EQ006, VCC, VCC); + _EQ005 = !CNF_ON & CODE2 & !10K_D0 + # !CNF_ON & !CODE2 & 10K_D0 + # CNF_ON & !CODE0; + _EQ006 = _X005 & _X006 & _X007; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + _X007 = EXP( /CONFIG & HDD_CS); + +-- Node name is 'CODE1' from file "sp047032.tdf" line 58, column 6 +-- Equation name is 'CODE1', location is LC023, type is buried. +CODE1 = DFFE( CODE0 $ GND, 10K_CLK, !_EQ007, VCC, VCC); + _EQ007 = _X005 & _X006 & _X007; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + _X007 = EXP( /CONFIG & HDD_CS); + +-- Node name is 'CODE2' from file "sp047032.tdf" line 58, column 6 +-- Equation name is 'CODE2', location is LC022, type is buried. +CODE2 = DFFE( CODE1 $ GND, 10K_CLK, !_EQ008, VCC, VCC); + _EQ008 = _X005 & _X006 & _X007; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + _X007 = EXP( /CONFIG & HDD_CS); + +-- Node name is 'CODE3' from file "sp047032.tdf" line 58, column 6 +-- Equation name is 'CODE3', location is LC031, type is buried. +CODE3 = DFFE( CODE2 $ GND, 10K_CLK, !_EQ009, VCC, VCC); + _EQ009 = _X005 & _X006 & _X007; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + _X007 = EXP( /CONFIG & HDD_CS); + +-- Node name is 'CODE4' from file "sp047032.tdf" line 58, column 6 +-- Equation name is 'CODE4', location is LC027, type is buried. +CODE4 = DFFE( CODE3 $ GND, 10K_CLK, !_EQ010, VCC, VCC); + _EQ010 = _X005 & _X006 & _X007; + _X005 = EXP( /CONFIG & /RD); + _X006 = EXP( /CONFIG & /IO); + _X007 = EXP( /CONFIG & HDD_CS); + +-- Node name is 'CT_WG' from file "sp047032.tdf" line 113, column 11 +-- Equation name is 'CT_WG', location is LC013, type is buried. +CT_WG = TFFE( VCC, _EQ011, VCC, VCC, VCC); + _EQ011 = _X008 & _X009 & _X010; + _X008 = EXP(!CT_WG & !CT1); + _X009 = EXP( CT_WG & CT1 & _X011); + _X010 = EXP(!CT1 & !/DTRB & !STE & _X012); + _X011 = EXP(!/DTRB & !STE & _X012); + _X012 = EXP(!RSTB & !WSTB & _X011); + +-- Node name is 'CT_WG1' from file "sp047032.tdf" line 115, column 12 +-- Equation name is 'CT_WG1', location is LC025, type is buried. +CT_WG1 = TFFE( VCC, _EQ012, VCC, VCC, VCC); + _EQ012 = _X013 & _X014 & _X015; + _X013 = EXP(!CT_WG1 & !CT1); + _X014 = EXP( CT_WG1 & CT1 & /DTRB); + _X015 = EXP(!CT1 & !/DTRB); + +-- Node name is 'CT0' from file "sp047032.tdf" line 51, column 4 +-- Equation name is 'CT0', location is LC028, type is buried. +CT0 = TFFE( VCC, _EQ013, VCC, VCC, VCC); + _EQ013 = _X003 & _X004; + _X003 = EXP( CT1 & !TG42_IN); + _X004 = EXP(!CT1 & TG42_IN); + +-- Node name is 'HD_CSS1' +-- Equation name is 'HD_CSS1', location is LC007, type is output. + HD_CSS1 = LCELL( _EQ014 $ VCC); + _EQ014 = !HDD_CS & !MA7; + +-- Node name is 'HD_CSS2' +-- Equation name is 'HD_CSS2', location is LC008, type is output. + HD_CSS2 = LCELL( _EQ015 $ VCC); + _EQ015 = !HDD_CS & MA7; + +-- Node name is 'HD_CS1' +-- Equation name is 'HD_CS1', location is LC006, type is output. + HD_CS1 = LCELL( _EQ016 $ VCC); + _EQ016 = !HDD_CS & !/WR; + +-- Node name is 'HD_CS2' = ':108' from file "sp047032.tdf" line 196, column 12 +-- Equation name is 'HD_CS2', type is output + HD_CS2 = LCELL( _EQ017 $ VCC); + _EQ017 = !HDD_CS & !/WRH; + +-- Node name is 'HD_OE1' +-- Equation name is 'HD_OE1', location is LC005, type is output. + HD_OE1 = LCELL( _EQ018 $ VCC); + _EQ018 = !HDD_CS & !/IO & MA0 & !/WR & /WRH & _X016 + # !HDD_CS & !/IO & MA0 & !/RD & _X016 + # CODE0 & !HDD_CS & !/MR & !/RD; + _X016 = EXP( _X017); + _X017 = EXP( _X018); + _X018 = EXP( _X019); + _X019 = EXP(!HDD_CS); + +-- Node name is 'HD_OE2' +-- Equation name is 'HD_OE2', location is LC002, type is output. + HD_OE2 = LCELL( _EQ019 $ VCC); + _EQ019 = !HDD_CS & !/IO & !MA0 & !/RD & _X016 + # !CODE0 & !HDD_CS & !/MR & !/RD; + _X016 = EXP( _X017); + _X017 = EXP( _X018); + _X018 = EXP( _X019); + _X019 = EXP(!HDD_CS); + +-- Node name is 'HD_WE1' = ':115' from file "sp047032.tdf" line 211, column 12 +-- Equation name is 'HD_WE1', type is output + HD_WE1 = DFFE( GND $ GND, !HDD_CS, VCC, !_EQ020, VCC); + _EQ020 = /RD & /WR; + +-- Node name is 'HD_WE2' +-- Equation name is 'HD_WE2', location is LC001, type is output. + HD_WE2 = LCELL( _EQ021 $ VCC); + _EQ021 = !HDD_CS & !/IO & MA0 & !/WR & _X016; + _X016 = EXP( _X017); + _X017 = EXP( _X018); + _X018 = EXP( _X019); + _X019 = EXP(!HDD_CS); + +-- Node name is 'QDAT' = 'WGR4' from file "sp047032.tdf" line 54, column 5 +-- Equation name is 'QDAT', location is LC010, type is output. + QDAT = TFFE( _EQ022, CT_WG1, VCC, VCC, VCC); + _EQ022 = RDAT & WGR0 & WGR1 & WGR2 & WGR3; + +-- Node name is 'RDAT' = ':98' from file "sp047032.tdf" line 153, column 9 +-- Equation name is 'RDAT', type is output + RDAT = DFFE( _EQ023 $ VCC, CT_WG1, VCC, VCC, VCC); + _EQ023 = _LC016 & _X020 & _X021; + _X020 = EXP(!CT_WG1 & RDATA); + _X021 = EXP( _X022 & _X023); + _X022 = EXP(!CT_WG1 & !RDATA); + _X023 = EXP( _X020 & _X021); + +-- Node name is 'STWG1' from file "sp047032.tdf" line 53, column 6 +-- Equation name is 'STWG1', location is LC014, type is buried. +STWG1 = TFFE( CLK_PRC, _EQ024, VCC, VCC, VCC); + _EQ024 = _X001 & _X002; + _X001 = EXP(!CLK_WG & !CT_WG); + _X002 = EXP( CLK_WG & CT_WG); + +-- Node name is 'TG42_OUT' +-- Equation name is 'TG42_OUT', location is LC017, type is output. + TG42_OUT = LCELL( _EQ025 $ GND); + _EQ025 = _X024; + _X024 = EXP( TG42_IN); + +-- Node name is 'WGR0' from file "sp047032.tdf" line 54, column 5 +-- Equation name is 'WGR0', location is LC024, type is buried. +WGR0 = TFFE( _EQ026, CT_WG1, VCC, VCC, VCC); + _EQ026 = WGR0 & WGR1 & WGR2 & !WGR3 + # !WGR0 & !WGR1 & !WGR2 & WGR3 + # RDAT; + +-- Node name is 'WGR1' from file "sp047032.tdf" line 54, column 5 +-- Equation name is 'WGR1', location is LC019, type is buried. +WGR1 = TFFE( _EQ027, CT_WG1, VCC, VCC, VCC); + _EQ027 = RDAT & !WGR0 & !WGR1 & !WGR2 & !WGR3 + # !RDAT & !WGR1 & WGR2 & !WGR3 + # !RDAT & WGR1 & !WGR3 + # RDAT & WGR0; + +-- Node name is 'WGR2' from file "sp047032.tdf" line 54, column 5 +-- Equation name is 'WGR2', location is LC012, type is buried. +WGR2 = TFFE( _EQ028, CT_WG1, VCC, VCC, VCC); + _EQ028 = !RDAT & WGR1 & WGR2 & !WGR3 + # RDAT & WGR0 & WGR1 + # !RDAT & !WGR2 & !WGR3; + +-- Node name is 'WGR3' from file "sp047032.tdf" line 54, column 5 +-- Equation name is 'WGR3', location is LC015, type is buried. +WGR3 = TFFE( _EQ029, CT_WG1, VCC, VCC, VCC); + _EQ029 = RDAT & WGR0 & WGR1 & WGR2 & WGR3 + # WGR0 & WGR1 & WGR2 & !WGR3 + # !RDAT & WGR1 & WGR2 & !WGR3; + +-- Node name is '10K_CLK' = ':87' from file "sp047032.tdf" line 75, column 13 +-- Equation name is '10K_CLK', type is output + 10K_CLK = LCELL( _EQ030 $ VCC); + _EQ030 = CNF_ON & !HDD_CS & !/MR & !/RD + # !CNF_ON & !/MR & !/WR; + +-- Node name is '10K_D0' = ':88' from file "sp047032.tdf" line 86, column 12 +-- Equation name is '10K_D0', type is output + 10K_D0 = LCELL( CODE4 $ D0); + +-- Node name is '/CONFIG' = ':117' from file "sp047032.tdf" line 227, column 12 +-- Equation name is '/CONFIG', type is output + /CONFIG = LCELL( _EQ031 $ EPM_RES); + _EQ031 = EPM_RES & !HDD_CS & !MA7 & !/MR & !/WR; + +-- Node name is '/WRH' = ':116' from file "sp047032.tdf" line 223, column 9 +-- Equation name is '/WRH', type is output + /WRH = DFFE( _EQ032 $ VCC, _EQ033, !_EQ034, VCC, VCC); + _EQ032 = MA0 & !/WRH; + _EQ033 = _X025; + _X025 = EXP(!HDD_CS & !/IO & !/WR); + _EQ034 = !HDD_CS & !/IO & !/RD; + +-- Node name is ':99' from file "sp047032.tdf" line 153, column 25 +-- Equation name is '_LC016', type is buried +_LC016 = DFFE( _EQ035 $ GND, CT_WG1, VCC, VCC, VCC); + _EQ035 = _X023; + _X023 = EXP( _X020 & _X021); + _X020 = EXP(!CT_WG1 & RDATA); + _X021 = EXP( _X022 & _X023); + _X022 = EXP(!CT_WG1 & !RDATA); + + + +-- Shareable expanders that are duplicated in multiple LABs: +-- _X001 occurs in LABs A, B +-- _X002 occurs in LABs A, B + + + + +Project Information c:\prj\sprinter\firmware\97\max\sp047032.rpt + +** COMPILATION SETTINGS & TIMES ** + +Processing Menu Commands +------------------------ + +Design Doctor = off + +Logic Synthesis: + + Synthesis Type Used = Standard + + Default Synthesis Style = NORMAL + + Logic option settings in 'NORMAL' style for 'MAX7000' family + + DECOMPOSE_GATES = on + DUPLICATE_LOGIC_EXTRACTION = on + MINIMIZATION = full + MULTI_LEVEL_FACTORING = on + NOT_GATE_PUSH_BACK = on + PARALLEL_EXPANDERS = off + REDUCE_LOGIC = on + REFACTORIZATION = on + REGISTER_OPTIMIZATION = on + RESYNTHESIZE_NETWORK = on + SLOW_SLEW_RATE = off + SOFT_BUFFER_INSERTION = on + SUBFACTOR_EXTRACTION = on + TURBO_BIT = on + XOR_SYNTHESIS = on + IGNORE_SOFT_BUFFERS = off + USE_LPM_FOR_AHDL_OPERATORS = off + + Other logic synthesis settings: + + Automatic Global Clock = off + Automatic Global Clear = off + Automatic Global Preset = off + Automatic Global Output Enable = off + Automatic Fast I/O = off + Automatic Register Packing = off + Automatic Open-Drain Pins = on + Automatic Implement in EAB = off + One-Hot State Machine Encoding = off + Optimize = 0 + +Default Timing Specifications: None + +Cut All Bidir Feedback Timing Paths = on +Cut All Clear & Preset Timing Paths = on + +Ignore Timing Assignments = off + +Functional SNF Extractor = off + +Linked SNF Extractor = off +Timing SNF Extractor = on +Optimize Timing SNF = off +Generate AHDL TDO File = off +Fitter Settings = ADVANCED +Smart Recompile = on +Total Recompile = off + +Interfaces Menu Commands +------------------------ + +EDIF Netlist Writer = off +Verilog Netlist Writer = off +VHDL Netlist Writer = off + +Compilation Times +----------------- + + Compiler Netlist Extractor 00:00:00 + Database Builder 00:00:00 + Logic Synthesizer 00:00:00 + Partitioner 00:00:00 + Fitter 00:00:00 + Timing SNF Extractor 00:00:00 + Assembler 00:00:00 + -------------------------- -------- + Total Time 00:00:00 + + +Memory Allocated +----------------- + +Peak memory allocated during compilation = 3,646K diff --git a/gerber/SPRINT05.GBR.ZIP b/gerber/SPRINT05.GBR.ZIP new file mode 100644 index 0000000..29bf3c3 Binary files /dev/null and b/gerber/SPRINT05.GBR.ZIP differ diff --git a/master/sp97-bios-master.zip b/master/sp97-bios-master.zip new file mode 100644 index 0000000..34fca61 Binary files /dev/null and b/master/sp97-bios-master.zip differ diff --git a/master/sp97-fw-master.zip b/master/sp97-fw-master.zip new file mode 100644 index 0000000..427c742 Binary files /dev/null and b/master/sp97-fw-master.zip differ diff --git a/master/sp97-pcb-master.zip b/master/sp97-pcb-master.zip new file mode 100644 index 0000000..42a042c Binary files /dev/null and b/master/sp97-pcb-master.zip differ diff --git a/pcb/SPRIN02.BMP b/pcb/SPRIN02.BMP new file mode 100644 index 0000000..f6bf114 Binary files /dev/null and b/pcb/SPRIN02.BMP differ diff --git a/pcb/converted/SPRINT05.BD1 b/pcb/converted/SPRINT05.BD1 new file mode 100644 index 0000000..8a79091 Binary files /dev/null and b/pcb/converted/SPRINT05.BD1 differ diff --git a/pcb/converted/SPRINT05.MIN b/pcb/converted/SPRINT05.MIN new file mode 100644 index 0000000..922c5c7 --- /dev/null +++ b/pcb/converted/SPRINT05.MIN @@ -0,0 +1,27002 @@ +(MIN +(Version 9100) +(MajorRev 9)(MinorRev 1) +(L 28)(V 16) +(Begin +(Header + (Grid 1500) + (ViaGrid 0) + (UserDiv 60) + (DisplayGrid 0) + (PlaceGrid 6000 6000) + (DetailGrid 1500 1500) + (DotGrid 0 0) + (DisplayPrecision 60) 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Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 5(N "VIA5")(Uid 2501)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 6(N "VIA6")(Uid 2502)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 7(N "VIA7")(Uid 2503)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 8(N "VIA8")(Uid 2504)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 9(N "VIA9")(Uid 2505)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 10(N "VIA10")(Uid 2506)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 11(N "VIA11")(Uid 2507)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 12(N "VIA12")(Uid 2508)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 13(N "VIA13")(Uid 2509)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 14(N "VIA14")(Uid 2510)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 15(N "VIA15")(Uid 2511)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 16(N "VIA16")(Uid 2512)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(UNDEF)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(UNDEF)) + (L 18(UNDEF)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(UNDEF)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 17(N "pad1")(Uid 2513)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)(R 16200)) + (L 2(Round 1650)(R 16200)) + (L 3(Round 2550)(R 16200)) + (L 4(Round 2550)(R 16200)) + (L 5(Round 1650)(R 16200)) + (L 6(Round 1650)(R 16200)) + (L 7(Round 1650)(R 16200)) + (L 8(Round 1650)(R 16200)) + (L 9(Round 1650)(R 16200)) + (L 10(Round 1650)(R 16200)) + (L 11(Round 1650)(R 16200)) + (L 12(Round 1650)(R 16200)) + (L 13(Round 1650)(R 16200)) + (L 14(Round 1650)(R 16200)) + (L 15(Round 1650)(R 16200)) + (L 16(Round 1650)(R 16200)) + (L 17(Round 1650)(R 16200)) + (L 18(Round 1650)(R 16200)) + (L 19(UNDEF)(R 16200)) + (L 20(UNDEF)(R 16200)) + (L 21(UNDEF)(R 16200)) + (L 22(UNDEF)(R 16200)) + (L 23(Round 1650)(R 16200)) + (L 24(Round 1650)(R 16200)) + (L 25(Round 1050)(R 16200)) + (L 26(Round 1050)(R 16200)) + (L 27(UNDEF)(R 16200)) + (L 28(UNDEF)(R 16200)) + ) +(THRU 18(N "pad2")(Uid 2514)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Square 1650)(R 16200)) + (L 2(Square 1650)(R 16200)) + (L 3(Square 2550)(R 16200)) + (L 4(Square 2550)(R 16200)) + (L 5(Square 1650)(R 16200)) + (L 6(Square 1650)(R 16200)) + (L 7(Square 1650)(R 16200)) + (L 8(Square 1650)(R 16200)) + (L 9(Square 1650)(R 16200)) + (L 10(Square 1650)(R 16200)) + (L 11(Square 1650)(R 16200)) + (L 12(Square 1650)(R 16200)) + (L 13(Square 1650)(R 16200)) + (L 14(Square 1650)(R 16200)) + (L 15(Square 1650)(R 16200)) + (L 16(Square 1650)(R 16200)) + (L 17(Square 1650)(R 16200)) + (L 18(Square 1650)(R 16200)) + (L 19(UNDEF)(R 16200)) + (L 20(UNDEF)(R 16200)) + (L 21(UNDEF)(R 16200)) + (L 22(UNDEF)(R 16200)) + (L 23(Square 1650)(R 16200)) + (L 24(Square 1650)(R 16200)) + (L 25(Round 1050)(R 16200)) + (L 26(Round 1050)(R 16200)) + (L 27(UNDEF)(R 16200)) + (L 28(UNDEF)(R 16200)) + ) +(THRU 19(N "pad3")(Uid 2515)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)) + (L 2(Round 1650)) + (L 3(Round 2550)) + (L 4(Round 2550)) + (L 5(Round 1650)) + (L 6(Round 1650)) + (L 7(Round 1650)) + (L 8(Round 1650)) + (L 9(Round 1650)) + (L 10(Round 1650)) + (L 11(Round 1650)) + (L 12(Round 1650)) + (L 13(Round 1650)) + (L 14(Round 1650)) + (L 15(Round 1650)) + (L 16(Round 1650)) + (L 17(Round 1650)) + (L 18(Round 1650)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Round 1650)) + (L 24(Round 1650)) + (L 25(Round 1050)) + (L 26(Round 1050)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 20(N "pad4")(Uid 2516)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Square 1650)(R 10800)) + (L 2(Square 1650)(R 10800)) + (L 3(Square 2550)(R 10800)) + (L 4(Square 2550)(R 10800)) + (L 5(Square 1650)(R 10800)) + (L 6(Square 1650)(R 10800)) + (L 7(Square 1650)(R 10800)) + (L 8(Square 1650)(R 10800)) + (L 9(Square 1650)(R 10800)) + (L 10(Square 1650)(R 10800)) + (L 11(Square 1650)(R 10800)) + (L 12(Square 1650)(R 10800)) + (L 13(Square 1650)(R 10800)) + (L 14(Square 1650)(R 10800)) + (L 15(Square 1650)(R 10800)) + (L 16(Square 1650)(R 10800)) + (L 17(Square 1650)(R 10800)) + (L 18(Square 1650)(R 10800)) + (L 19(UNDEF)(R 10800)) + (L 20(UNDEF)(R 10800)) + (L 21(UNDEF)(R 10800)) + (L 22(UNDEF)(R 10800)) + (L 23(Square 1650)(R 10800)) + (L 24(Square 1650)(R 10800)) + (L 25(Round 1050)(R 10800)) + (L 26(Round 1050)(R 10800)) + (L 27(UNDEF)(R 10800)) + (L 28(UNDEF)(R 10800)) + ) +(THRU 21(N "pad5")(Uid 2517)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)(R 10800)) + (L 2(Round 1650)(R 10800)) + (L 3(Round 2550)(R 10800)) + (L 4(Round 2550)(R 10800)) + (L 5(Round 1650)(R 10800)) + (L 6(Round 1650)(R 10800)) + (L 7(Round 1650)(R 10800)) + (L 8(Round 1650)(R 10800)) + (L 9(Round 1650)(R 10800)) + (L 10(Round 1650)(R 10800)) + (L 11(Round 1650)(R 10800)) + (L 12(Round 1650)(R 10800)) + (L 13(Round 1650)(R 10800)) + (L 14(Round 1650)(R 10800)) + (L 15(Round 1650)(R 10800)) + (L 16(Round 1650)(R 10800)) + (L 17(Round 1650)(R 10800)) + (L 18(Round 1650)(R 10800)) + (L 19(UNDEF)(R 10800)) + (L 20(UNDEF)(R 10800)) + (L 21(UNDEF)(R 10800)) + (L 22(UNDEF)(R 10800)) + (L 23(Round 1650)(R 10800)) + (L 24(Round 1650)(R 10800)) + (L 25(Round 1050)(R 10800)) + (L 26(Round 1050)(R 10800)) + (L 27(UNDEF)(R 10800)) + (L 28(UNDEF)(R 10800)) + ) +(THRU 22(N "pad6")(Uid 2518)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Rect 450 1500 450 1500)(R 5400)) + (L 2(UNDEF)(R 5400)) + (L 3(UNDEF)(R 5400)) + (L 4(UNDEF)(R 5400)) + (L 5(UNDEF)(R 5400)) + (L 6(UNDEF)(R 5400)) + (L 7(UNDEF)(R 5400)) + (L 8(UNDEF)(R 5400)) + (L 9(UNDEF)(R 5400)) + (L 10(UNDEF)(R 5400)) + (L 11(UNDEF)(R 5400)) + (L 12(UNDEF)(R 5400)) + (L 13(UNDEF)(R 5400)) + (L 14(UNDEF)(R 5400)) + (L 15(UNDEF)(R 5400)) + (L 16(UNDEF)(R 5400)) + (L 17(Rect 450 1500 450 1500)(R 5400)) + (L 18(UNDEF)(R 5400)) + (L 19(Rect 1431 2481 1431 2481)(R 5400)) + (L 20(UNDEF)(R 5400)) + (L 21(UNDEF)(R 5400)) + (L 22(UNDEF)(R 5400)) + (L 23(Rect 450 1500 450 1500)(R 5400)) + (L 24(UNDEF)(R 5400)) + (L 25(UNDEF)(R 5400)) + (L 26(UNDEF)(R 5400)) + (L 27(UNDEF)(R 5400)) + (L 28(UNDEF)(R 5400)) + ) +(THRU 23(N "pad7")(Uid 2519)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Rect 450 1500 450 1500)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(Rect 450 1500 450 1500)) + (L 18(UNDEF)) + (L 19(Rect 1431 2481 1431 2481)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Rect 450 1500 450 1500)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 24(N "pad8")(Uid 2520)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Square 1650)) + (L 2(Square 1650)) + (L 3(Square 2550)) + (L 4(Square 2550)) + (L 5(Square 1650)) + (L 6(Square 1650)) + (L 7(Square 1650)) + (L 8(Square 1650)) + (L 9(Square 1650)) + (L 10(Square 1650)) + (L 11(Square 1650)) + (L 12(Square 1650)) + (L 13(Square 1650)) + (L 14(Square 1650)) + (L 15(Square 1650)) + (L 16(Square 1650)) + (L 17(Square 1650)) + (L 18(Square 1650)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Square 1650)) + (L 24(Square 1650)) + (L 25(Round 1050)) + (L 26(Round 1050)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 25(N "pad9")(Uid 2521)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 2100)(R 16200)) + (L 2(Round 2100)(R 16200)) + (L 3(Round 3000)(R 16200)) + (L 4(Round 3000)(R 16200)) + (L 5(Round 2100)(R 16200)) + (L 6(Round 2100)(R 16200)) + (L 7(Round 2100)(R 16200)) + (L 8(Round 2100)(R 16200)) + (L 9(Round 2100)(R 16200)) + (L 10(Round 2100)(R 16200)) + (L 11(Round 2100)(R 16200)) + (L 12(Round 2100)(R 16200)) + (L 13(Round 2100)(R 16200)) + (L 14(Round 2100)(R 16200)) + (L 15(Round 2100)(R 16200)) + (L 16(Round 2100)(R 16200)) + (L 17(Round 2100)(R 16200)) + (L 18(Round 2100)(R 16200)) + (L 19(UNDEF)(R 16200)) + (L 20(UNDEF)(R 16200)) + (L 21(UNDEF)(R 16200)) + (L 22(UNDEF)(R 16200)) + (L 23(Round 2100)(R 16200)) + (L 24(Round 2100)(R 16200)) + (L 25(Round 1800)(R 16200)) + (L 26(Round 1800)(R 16200)) + (L 27(UNDEF)(R 16200)) + (L 28(UNDEF)(R 16200)) + ) +(THRU 26(N "pad10")(Uid 2522)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 2100)(R 16200)) + (L 2(Round 2100)(R 16200)) + (L 3(Round 3000)(R 16200)) + (L 4(Round 3000)(R 16200)) + (L 5(Round 2100)(R 16200)) + (L 6(Round 2100)(R 16200)) + (L 7(Round 2100)(R 16200)) + (L 8(Round 2100)(R 16200)) + (L 9(Round 2100)(R 16200)) + (L 10(Round 2100)(R 16200)) + (L 11(Round 2100)(R 16200)) + (L 12(Round 2100)(R 16200)) + (L 13(Round 2100)(R 16200)) + (L 14(Round 2100)(R 16200)) + (L 15(Round 2100)(R 16200)) + (L 16(Round 2100)(R 16200)) + (L 17(Round 2100)(R 16200)) + (L 18(Round 2100)(R 16200)) + (L 19(UNDEF)(R 16200)) + (L 20(UNDEF)(R 16200)) + (L 21(UNDEF)(R 16200)) + (L 22(UNDEF)(R 16200)) + (L 23(Round 2100)(R 16200)) + (L 24(Round 2100)(R 16200)) + (L 25(Round 1500)(R 16200)) + (L 26(Round 1500)(R 16200)) + (L 27(UNDEF)(R 16200)) + (L 28(UNDEF)(R 16200)) + ) +(THRU 27(N "pad11")(Uid 2523)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Square 1650)(R 5400)) + (L 2(Square 1650)(R 5400)) + (L 3(Square 2550)(R 5400)) + (L 4(Square 2550)(R 5400)) + (L 5(Square 1650)(R 5400)) + (L 6(Square 1650)(R 5400)) + (L 7(Square 1650)(R 5400)) + (L 8(Square 1650)(R 5400)) + (L 9(Square 1650)(R 5400)) + (L 10(Square 1650)(R 5400)) + (L 11(Square 1650)(R 5400)) + (L 12(Square 1650)(R 5400)) + (L 13(Square 1650)(R 5400)) + (L 14(Square 1650)(R 5400)) + (L 15(Square 1650)(R 5400)) + (L 16(Square 1650)(R 5400)) + (L 17(Square 1650)(R 5400)) + (L 18(Square 1650)(R 5400)) + (L 19(UNDEF)(R 5400)) + (L 20(UNDEF)(R 5400)) + (L 21(UNDEF)(R 5400)) + (L 22(UNDEF)(R 5400)) + (L 23(Square 1650)(R 5400)) + (L 24(Square 1650)(R 5400)) + (L 25(Round 1050)(R 5400)) + (L 26(Round 1050)(R 5400)) + (L 27(UNDEF)(R 5400)) + (L 28(UNDEF)(R 5400)) + ) +(THRU 28(N "pad12")(Uid 2524)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)(R 5400)) + (L 2(Round 1650)(R 5400)) + (L 3(Round 2550)(R 5400)) + (L 4(Round 2550)(R 5400)) + (L 5(Round 1650)(R 5400)) + (L 6(Round 1650)(R 5400)) + (L 7(Round 1650)(R 5400)) + (L 8(Round 1650)(R 5400)) + (L 9(Round 1650)(R 5400)) + (L 10(Round 1650)(R 5400)) + (L 11(Round 1650)(R 5400)) + (L 12(Round 1650)(R 5400)) + (L 13(Round 1650)(R 5400)) + (L 14(Round 1650)(R 5400)) + (L 15(Round 1650)(R 5400)) + (L 16(Round 1650)(R 5400)) + (L 17(Round 1650)(R 5400)) + (L 18(Round 1650)(R 5400)) + (L 19(UNDEF)(R 5400)) + (L 20(UNDEF)(R 5400)) + (L 21(UNDEF)(R 5400)) + (L 22(UNDEF)(R 5400)) + (L 23(Round 1650)(R 5400)) + (L 24(Round 1650)(R 5400)) + (L 25(Round 1050)(R 5400)) + (L 26(Round 1050)(R 5400)) + (L 27(UNDEF)(R 5400)) + (L 28(UNDEF)(R 5400)) + ) +(THRU 29(N "hole1")(Uid 2525)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 2400)) + (L 2(Round 2400)) + (L 3(Round 3300)) + (L 4(Round 3300)) + (L 5(Round 2400)) + (L 6(Round 2400)) + (L 7(Round 2400)) + (L 8(Round 2400)) + (L 9(Round 2400)) + (L 10(Round 2400)) + (L 11(Round 2400)) + (L 12(Round 2400)) + (L 13(Round 2400)) + (L 14(Round 2400)) + (L 15(Round 2400)) + (L 16(Round 2400)) + (L 17(Round 2400)) + (L 18(Round 2400)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Round 2400)) + (L 24(Round 2400)) + (L 25(Round 2400)) + (L 26(Round 2400)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 30(N "pad13")(Uid 2526)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 2400)(R 10800)) + (L 2(Round 2400)(R 10800)) + (L 3(Round 3300)(R 10800)) + (L 4(Round 3300)(R 10800)) + (L 5(Round 2400)(R 10800)) + (L 6(Round 2400)(R 10800)) + (L 7(Round 2400)(R 10800)) + (L 8(Round 2400)(R 10800)) + (L 9(Round 2400)(R 10800)) + (L 10(Round 2400)(R 10800)) + (L 11(Round 2400)(R 10800)) + (L 12(Round 2400)(R 10800)) + (L 13(Round 2400)(R 10800)) + (L 14(Round 2400)(R 10800)) + (L 15(Round 2400)(R 10800)) + (L 16(Round 2400)(R 10800)) + (L 17(Round 2400)(R 10800)) + (L 18(Round 2400)(R 10800)) + (L 19(UNDEF)(R 10800)) + (L 20(UNDEF)(R 10800)) + (L 21(UNDEF)(R 10800)) + (L 22(UNDEF)(R 10800)) + (L 23(Round 2400)(R 10800)) + (L 24(Round 2400)(R 10800)) + (L 25(Round 2400)(R 10800)) + (L 26(Round 2400)(R 10800)) + (L 27(UNDEF)(R 10800)) + (L 28(UNDEF)(R 10800)) + ) +(THRU 31(N "hole2")(Uid 2527)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 4800)) + (L 2(Round 4800)) + (L 3(Round 5700)) + (L 4(Round 5700)) + (L 5(Round 4800)) + (L 6(Round 4800)) + (L 7(Round 4800)) + (L 8(Round 4800)) + (L 9(Round 4800)) + (L 10(Round 4800)) + (L 11(Round 4800)) + (L 12(Round 4800)) + (L 13(Round 4800)) + (L 14(Round 4800)) + (L 15(Round 4800)) + (L 16(Round 4800)) + (L 17(Round 4800)) + (L 18(Round 4800)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Round 4800)) + (L 24(Round 4800)) + (L 25(Round 4800)) + (L 26(Round 4800)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 32(N "pad14")(Uid 2528)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1980)(R 10800)) + (L 2(Round 1980)(R 10800)) + (L 3(Round 2880)(R 10800)) + (L 4(Round 2880)(R 10800)) + (L 5(Round 1980)(R 10800)) + (L 6(Round 1980)(R 10800)) + (L 7(Round 1980)(R 10800)) + (L 8(Round 1980)(R 10800)) + (L 9(Round 1980)(R 10800)) + (L 10(Round 1980)(R 10800)) + (L 11(Round 1980)(R 10800)) + (L 12(Round 1980)(R 10800)) + (L 13(Round 1980)(R 10800)) + (L 14(Round 1980)(R 10800)) + (L 15(Round 1980)(R 10800)) + (L 16(Round 1980)(R 10800)) + (L 17(Round 1980)(R 10800)) + (L 18(Round 1980)(R 10800)) + (L 19(UNDEF)(R 10800)) + (L 20(UNDEF)(R 10800)) + (L 21(UNDEF)(R 10800)) + (L 22(UNDEF)(R 10800)) + (L 23(Round 1980)(R 10800)) + (L 24(Round 1980)(R 10800)) + (L 25(Round 1350)(R 10800)) + (L 26(Round 1350)(R 10800)) + (L 27(UNDEF)(R 10800)) + (L 28(UNDEF)(R 10800)) + ) +(THRU 33(N "pad15")(Uid 2529)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1980)(R 5400)) + (L 2(Round 1980)(R 5400)) + (L 3(Round 2880)(R 5400)) + (L 4(Round 2880)(R 5400)) + (L 5(Round 1980)(R 5400)) + (L 6(Round 1980)(R 5400)) + (L 7(Round 1980)(R 5400)) + (L 8(Round 1980)(R 5400)) + (L 9(Round 1980)(R 5400)) + (L 10(Round 1980)(R 5400)) + (L 11(Round 1980)(R 5400)) + (L 12(Round 1980)(R 5400)) + (L 13(Round 1980)(R 5400)) + (L 14(Round 1980)(R 5400)) + (L 15(Round 1980)(R 5400)) + (L 16(Round 1980)(R 5400)) + (L 17(Round 1980)(R 5400)) + (L 18(Round 1980)(R 5400)) + (L 19(UNDEF)(R 5400)) + (L 20(UNDEF)(R 5400)) + (L 21(UNDEF)(R 5400)) + (L 22(UNDEF)(R 5400)) + (L 23(Round 1980)(R 5400)) + (L 24(Round 1980)(R 5400)) + (L 25(Round 1350)(R 5400)) + (L 26(Round 1350)(R 5400)) + (L 27(UNDEF)(R 5400)) + (L 28(UNDEF)(R 5400)) + ) +(THRU 34(N "pad16")(Uid 2530)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1980)(R 16200)) + (L 2(Round 1980)(R 16200)) + (L 3(Round 2880)(R 16200)) + (L 4(Round 2880)(R 16200)) + (L 5(Round 1980)(R 16200)) + (L 6(Round 1980)(R 16200)) + (L 7(Round 1980)(R 16200)) + (L 8(Round 1980)(R 16200)) + (L 9(Round 1980)(R 16200)) + (L 10(Round 1980)(R 16200)) + (L 11(Round 1980)(R 16200)) + (L 12(Round 1980)(R 16200)) + (L 13(Round 1980)(R 16200)) + (L 14(Round 1980)(R 16200)) + (L 15(Round 1980)(R 16200)) + (L 16(Round 1980)(R 16200)) + (L 17(Round 1980)(R 16200)) + (L 18(Round 1980)(R 16200)) + (L 19(UNDEF)(R 16200)) + (L 20(UNDEF)(R 16200)) + (L 21(UNDEF)(R 16200)) + (L 22(UNDEF)(R 16200)) + (L 23(Round 1980)(R 16200)) + (L 24(Round 1980)(R 16200)) + (L 25(Round 1350)(R 16200)) + (L 26(Round 1350)(R 16200)) + (L 27(UNDEF)(R 16200)) + (L 28(UNDEF)(R 16200)) + ) +(THRU 35(N "pad17")(Uid 2531)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 2400)(R 5400)) + (L 2(Round 2400)(R 5400)) + (L 3(Round 3300)(R 5400)) + (L 4(Round 3300)(R 5400)) + (L 5(Round 2400)(R 5400)) + (L 6(Round 2400)(R 5400)) + (L 7(Round 2400)(R 5400)) + (L 8(Round 2400)(R 5400)) + (L 9(Round 2400)(R 5400)) + (L 10(Round 2400)(R 5400)) + (L 11(Round 2400)(R 5400)) + (L 12(Round 2400)(R 5400)) + (L 13(Round 2400)(R 5400)) + (L 14(Round 2400)(R 5400)) + (L 15(Round 2400)(R 5400)) + (L 16(Round 2400)(R 5400)) + (L 17(Round 2400)(R 5400)) + (L 18(Round 2400)(R 5400)) + (L 19(UNDEF)(R 5400)) + (L 20(UNDEF)(R 5400)) + (L 21(UNDEF)(R 5400)) + (L 22(UNDEF)(R 5400)) + (L 23(Round 2400)(R 5400)) + (L 24(Round 2400)(R 5400)) + (L 25(Round 1200)(R 5400)) + (L 26(Round 1200)(R 5400)) + (L 27(UNDEF)(R 5400)) + (L 28(UNDEF)(R 5400)) + ) +(THRU 36(N "pad18")(Uid 2532)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)(R 5400)) + (L 2(Round 1650)(R 5400)) + (L 3(Round 2550)(R 5400)) + (L 4(Round 2550)(R 5400)) + (L 5(Round 1650)(R 5400)) + (L 6(Round 1650)(R 5400)) + (L 7(Round 1650)(R 5400)) + (L 8(Round 1650)(R 5400)) + (L 9(Round 1650)(R 5400)) + (L 10(Round 1650)(R 5400)) + (L 11(Round 1650)(R 5400)) + (L 12(Round 1650)(R 5400)) + (L 13(Round 1650)(R 5400)) + (L 14(Round 1650)(R 5400)) + (L 15(Round 1650)(R 5400)) + (L 16(Round 1650)(R 5400)) + (L 17(Round 1650)(R 5400)) + (L 18(Round 1650)(R 5400)) + (L 19(UNDEF)(R 5400)) + (L 20(UNDEF)(R 5400)) + (L 21(UNDEF)(R 5400)) + (L 22(UNDEF)(R 5400)) + (L 23(Round 1650)(R 5400)) + (L 24(Round 1650)(R 5400)) + (L 25(Round 1200)(R 5400)) + (L 26(Round 1200)(R 5400)) + (L 27(UNDEF)(R 5400)) + (L 28(UNDEF)(R 5400)) + ) +(THRU 37(N "pad19")(Uid 2533)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Rect 300 3000 300 3000)) + (L 2(UNDEF)) + (L 3(UNDEF)) + (L 4(UNDEF)) + (L 5(UNDEF)) + (L 6(UNDEF)) + (L 7(UNDEF)) + (L 8(UNDEF)) + (L 9(UNDEF)) + (L 10(UNDEF)) + (L 11(UNDEF)) + (L 12(UNDEF)) + (L 13(UNDEF)) + (L 14(UNDEF)) + (L 15(UNDEF)) + (L 16(UNDEF)) + (L 17(Rect 300 3000 300 3000)) + (L 18(UNDEF)) + (L 19(Rect 1281 3981 1281 3981)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Rect 300 3000 300 3000)) + (L 24(UNDEF)) + (L 25(UNDEF)) + (L 26(UNDEF)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 38(N "pad20")(Uid 2534)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Rect 300 3000 300 3000)(R 16200)) + (L 2(UNDEF)(R 16200)) + (L 3(UNDEF)(R 16200)) + (L 4(UNDEF)(R 16200)) + (L 5(UNDEF)(R 16200)) + (L 6(UNDEF)(R 16200)) + (L 7(UNDEF)(R 16200)) + (L 8(UNDEF)(R 16200)) + (L 9(UNDEF)(R 16200)) + (L 10(UNDEF)(R 16200)) + (L 11(UNDEF)(R 16200)) + (L 12(UNDEF)(R 16200)) + (L 13(UNDEF)(R 16200)) + (L 14(UNDEF)(R 16200)) + (L 15(UNDEF)(R 16200)) + (L 16(UNDEF)(R 16200)) + (L 17(Rect 300 3000 300 3000)(R 16200)) + (L 18(UNDEF)(R 16200)) + (L 19(Rect 1281 3981 1281 3981)(R 16200)) + (L 20(UNDEF)(R 16200)) + (L 21(UNDEF)(R 16200)) + (L 22(UNDEF)(R 16200)) + (L 23(Rect 300 3000 300 3000)(R 16200)) + (L 24(UNDEF)(R 16200)) + (L 25(UNDEF)(R 16200)) + (L 26(UNDEF)(R 16200)) + (L 27(UNDEF)(R 16200)) + (L 28(UNDEF)(R 16200)) + ) +(THRU 39(N "pad21")(Uid 2535)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)(R 16200)) + (L 2(Round 1650)(R 16200)) + (L 3(Round 2550)(R 16200)) + (L 4(Round 2550)(R 16200)) + (L 5(Round 1650)(R 16200)) + (L 6(Round 1650)(R 16200)) + (L 7(Round 1650)(R 16200)) + (L 8(Round 1650)(R 16200)) + (L 9(Round 1650)(R 16200)) + (L 10(Round 1650)(R 16200)) + (L 11(Round 1650)(R 16200)) + (L 12(Round 1650)(R 16200)) + (L 13(Round 1650)(R 16200)) + (L 14(Round 1650)(R 16200)) + (L 15(Round 1650)(R 16200)) + (L 16(Round 1650)(R 16200)) + (L 17(Round 1650)(R 16200)) + (L 18(Round 1650)(R 16200)) + (L 19(UNDEF)(R 16200)) + (L 20(UNDEF)(R 16200)) + (L 21(UNDEF)(R 16200)) + (L 22(UNDEF)(R 16200)) + (L 23(Round 1650)(R 16200)) + (L 24(Round 1650)(R 16200)) + (L 25(Round 1200)(R 16200)) + (L 26(Round 1200)(R 16200)) + (L 27(UNDEF)(R 16200)) + (L 28(UNDEF)(R 16200)) + ) +(THRU 40(N "pad22")(Uid 2536)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Square 1650)) + (L 2(Square 1650)) + (L 3(Square 2550)) + (L 4(Square 2550)) + (L 5(Square 1650)) + (L 6(Square 1650)) + (L 7(Square 1650)) + (L 8(Square 1650)) + (L 9(Square 1650)) + (L 10(Square 1650)) + (L 11(Square 1650)) + (L 12(Square 1650)) + (L 13(Square 1650)) + (L 14(Square 1650)) + (L 15(Square 1650)) + (L 16(Square 1650)) + (L 17(Square 1650)) + (L 18(Square 1650)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Square 1650)) + (L 24(Square 1650)) + (L 25(Round 1200)) + (L 26(Round 1200)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 41(N "pad23")(Uid 2537)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)) + (L 2(Round 1650)) + (L 3(Round 2550)) + (L 4(Round 2550)) + (L 5(Round 1650)) + (L 6(Round 1650)) + (L 7(Round 1650)) + (L 8(Round 1650)) + (L 9(Round 1650)) + (L 10(Round 1650)) + (L 11(Round 1650)) + (L 12(Round 1650)) + (L 13(Round 1650)) + (L 14(Round 1650)) + (L 15(Round 1650)) + (L 16(Round 1650)) + (L 17(Round 1650)) + (L 18(Round 1650)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Round 1650)) + (L 24(Round 1650)) + (L 25(Round 1200)) + (L 26(Round 1200)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(THRU 42(N "pad24")(Uid 2538)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Square 1650)(R 10800)) + (L 2(Square 1650)(R 10800)) + (L 3(Square 2550)(R 10800)) + (L 4(Square 2550)(R 10800)) + (L 5(Square 1650)(R 10800)) + (L 6(Square 1650)(R 10800)) + (L 7(Square 1650)(R 10800)) + (L 8(Square 1650)(R 10800)) + (L 9(Square 1650)(R 10800)) + (L 10(Square 1650)(R 10800)) + (L 11(Square 1650)(R 10800)) + (L 12(Square 1650)(R 10800)) + (L 13(Square 1650)(R 10800)) + (L 14(Square 1650)(R 10800)) + (L 15(Square 1650)(R 10800)) + (L 16(Square 1650)(R 10800)) + (L 17(Square 1650)(R 10800)) + (L 18(Square 1650)(R 10800)) + (L 19(UNDEF)(R 10800)) + (L 20(UNDEF)(R 10800)) + (L 21(UNDEF)(R 10800)) + (L 22(UNDEF)(R 10800)) + (L 23(Square 1650)(R 10800)) + (L 24(Square 1650)(R 10800)) + (L 25(Round 1200)(R 10800)) + (L 26(Round 1200)(R 10800)) + (L 27(UNDEF)(R 10800)) + (L 28(UNDEF)(R 10800)) + ) +(THRU 43(N "pad25")(Uid 2539)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 1650)(R 10800)) + (L 2(Round 1650)(R 10800)) + (L 3(Round 2550)(R 10800)) + (L 4(Round 2550)(R 10800)) + (L 5(Round 1650)(R 10800)) + (L 6(Round 1650)(R 10800)) + (L 7(Round 1650)(R 10800)) + (L 8(Round 1650)(R 10800)) + (L 9(Round 1650)(R 10800)) + (L 10(Round 1650)(R 10800)) + (L 11(Round 1650)(R 10800)) + (L 12(Round 1650)(R 10800)) + (L 13(Round 1650)(R 10800)) + (L 14(Round 1650)(R 10800)) + (L 15(Round 1650)(R 10800)) + (L 16(Round 1650)(R 10800)) + (L 17(Round 1650)(R 10800)) + (L 18(Round 1650)(R 10800)) + (L 19(UNDEF)(R 10800)) + (L 20(UNDEF)(R 10800)) + (L 21(UNDEF)(R 10800)) + (L 22(UNDEF)(R 10800)) + (L 23(Round 1650)(R 10800)) + (L 24(Round 1650)(R 10800)) + (L 25(Round 1200)(R 10800)) + (L 26(Round 1200)(R 10800)) + (L 27(UNDEF)(R 10800)) + (L 28(UNDEF)(R 10800)) + ) +(THRU 44(N "pad26")(Uid 2540)(TestPt Off)(NonPlated Off) + (LgThermal Off)(DirectHit Off) + (L 1(Round 2100)) + (L 2(Round 2100)) + (L 3(Round 3000)) + (L 4(Round 3000)) + (L 5(Round 2100)) + (L 6(Round 2100)) + (L 7(Round 2100)) + (L 8(Round 2100)) + (L 9(Round 2100)) + (L 10(Round 2100)) + (L 11(Round 2100)) + (L 12(Round 2100)) + (L 13(Round 2100)) + (L 14(Round 2100)) + (L 15(Round 2100)) + (L 16(Round 2100)) + (L 17(Round 2100)) + (L 18(Round 2100)) + (L 19(UNDEF)) + (L 20(UNDEF)) + (L 21(UNDEF)) + (L 22(UNDEF)) + (L 23(Round 2100)) + (L 24(Round 2100)) + (L 25(Round 1500)) + (L 26(Round 1500)) + (L 27(UNDEF)) + (L 28(UNDEF)) + ) +(SYM 1(N "PLCC44_DD1")(Uid 427 3000 15000 0 0)(Derived 256) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -6000 17(ExitRule "Std")) + (P 4(N "4") -6000 -12000 17(ExitRule "Std")) + (P 5(N "5") 0 -12000 17(ExitRule "Std")) + (P 6(N "6") -6000 -18000 17(ExitRule "Std")) + (P 7(N "7") 0 -24000 17(ExitRule "Std")) + (P 8(N "8") 0 -18000 17(ExitRule "Std")) + (P 9(N "9") 6000 -24000 17(ExitRule "Std")) + (P 10(N "10") 6000 -18000 17(ExitRule "Std")) + (P 11(N "11") 12000 -24000 17(ExitRule "Std")) + (P 12(N "12") 12000 -18000 17(ExitRule "Std")) + (P 13(N "13") 18000 -24000 17(ExitRule "Std")) + (P 14(N "14") 18000 -18000 17(ExitRule "Std")) + (P 15(N "15") 24000 -24000 17(ExitRule "Std")) + (P 16(N "16") 24000 -18000 17(ExitRule "Std")) + (P 17(N "17") 30000 -24000 17(ExitRule "Std")) + (P 18(N "18") 36000 -18000 17(ExitRule "Std")) + (P 19(N "19") 30000 -18000 17(ExitRule "Std")) + (P 20(N "20") 36000 -12000 17(ExitRule "Std")) + (P 21(N "21") 30000 -12000 17(ExitRule "Std")) + (P 22(N "22") 36000 -6000 17(ExitRule "Std")) + (P 23(N "23") 30000 -6000 17(ExitRule "Std")) + (P 24(N "24") 36000 0 17(ExitRule "Std")) + (P 25(N "25") 30000 0 17(ExitRule "Std")) + (P 26(N "26") 36000 6000 17(ExitRule "Std")) + (P 27(N "27") 30000 6000 17(ExitRule "Std")) + (P 28(N "28") 36000 12000 17(ExitRule "Std")) + (P 29(N "29") 30000 18000 17(ExitRule "Std")) + (P 30(N "30") 30000 12000 17(ExitRule "Std")) + (P 31(N "31") 24000 18000 17(ExitRule "Std")) + (P 32(N "32") 24000 12000 17(ExitRule "Std")) + (P 33(N "33") 18000 18000 17(ExitRule "Std")) + (P 34(N "34") 18000 12000 17(ExitRule "Std")) + (P 35(N "35") 12000 18000 17(ExitRule "Std")) + (P 36(N "36") 12000 12000 17(ExitRule "Std")) + (P 37(N "37") 6000 18000 17(ExitRule "Std")) + (P 38(N "38") 6000 12000 17(ExitRule "Std")) + (P 39(N "39") 0 18000 17(ExitRule "Std")) + (P 40(N "40") -6000 12000 17(ExitRule "Std")) + (P 41(N "41") 0 12000 17(ExitRule "Std")) + (P 42(N "42") -6000 6000 17(ExitRule "Std")) + (P 43(N "43") 0 6000 17(ExitRule "Std")) + (P 44(N "44") -6000 0 17(ExitRule "Std")) + ) +(SYM 2(N "32dip300_DD2")(Uid 513 45000 9000 0 0)(Derived 257) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 3(N "32dip300_DD3")(Uid 544 45000 9000 0 0)(Derived 258) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 4(N "32dip300_DD4")(Uid 556 45000 9000 0 0)(Derived 259) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 5(N "20DIP300_DD5")(Uid 568 27000 9000 0 0)(Derived 260) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 18000 -54000 17(ExitRule "Std")) + (P 12(N "12") 18000 -48000 17(ExitRule "Std")) + (P 13(N "13") 18000 -42000 17(ExitRule "Std")) + (P 14(N "14") 18000 -36000 17(ExitRule "Std")) + (P 15(N "15") 18000 -30000 17(ExitRule "Std")) + (P 16(N "16") 18000 -24000 17(ExitRule "Std")) + (P 17(N "17") 18000 -18000 17(ExitRule "Std")) + (P 18(N "18") 18000 -12000 17(ExitRule "Std")) + (P 19(N "19") 18000 -6000 17(ExitRule "Std")) + (P 20(N "20") 18000 0 17(ExitRule "Std")) + ) +(SYM 6(N "20DIP300_DD6")(Uid 582 27000 9000 0 0)(Derived 261) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 18000 -54000 17(ExitRule "Std")) + (P 12(N "12") 18000 -48000 17(ExitRule "Std")) + (P 13(N "13") 18000 -42000 17(ExitRule "Std")) + (P 14(N "14") 18000 -36000 17(ExitRule "Std")) + (P 15(N "15") 18000 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18000 19(ExitRule "Std")) + (P 17(N "17") 24000 0 19(ExitRule "Std")) + (P 18(N "18") 24000 6000 19(ExitRule "Std")) + (P 19(N "19") 24000 12000 19(ExitRule "Std")) + (P 20(N "20") 24000 18000 19(ExitRule "Std")) + (P 21(N "21") 30000 0 19(ExitRule "Std")) + (P 22(N "22") 30000 6000 19(ExitRule "Std")) + (P 23(N "23") 30000 12000 19(ExitRule "Std")) + (P 24(N "24") 30000 18000 19(ExitRule "Std")) + (P 25(N "25") 36000 0 19(ExitRule "Std")) + (P 26(N "26") 36000 6000 19(ExitRule "Std")) + (P 27(N "27") 36000 12000 19(ExitRule "Std")) + (P 28(N "28") 36000 18000 19(ExitRule "Std")) + (P 29(N "29") 42000 0 19(ExitRule "Std")) + (P 30(N "30") 42000 6000 19(ExitRule "Std")) + (P 31(N "31") 42000 12000 19(ExitRule "Std")) + (P 32(N "32") 42000 18000 19(ExitRule "Std")) + ) +(SYM 9(N "PLATA_R17-R32")(Uid 622 21000 9000 0 0)(Derived 264) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule 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19(ExitRule "Std")) + (P 27(N "27") 36000 12000 19(ExitRule "Std")) + (P 28(N "28") 36000 18000 19(ExitRule "Std")) + (P 29(N "29") 42000 0 19(ExitRule "Std")) + (P 30(N "30") 42000 6000 19(ExitRule "Std")) + (P 31(N "31") 42000 12000 19(ExitRule "Std")) + (P 32(N "32") 42000 18000 19(ExitRule "Std")) + ) +(SYM 10(N "PLATA_R33-R48")(Uid 632 21000 9000 0 0)(Derived 265) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") 6000 0 19(ExitRule "Std")) + (P 6(N "6") 6000 6000 19(ExitRule "Std")) + (P 7(N "7") 6000 12000 19(ExitRule "Std")) + (P 8(N "8") 6000 18000 19(ExitRule "Std")) + (P 9(N "9") 12000 0 19(ExitRule "Std")) + (P 10(N "10") 12000 6000 19(ExitRule "Std")) + (P 11(N "11") 12000 12000 19(ExitRule "Std")) + (P 12(N "12") 12000 18000 19(ExitRule "Std")) + (P 13(N "13") 18000 0 19(ExitRule "Std")) + (P 14(N "14") 18000 6000 19(ExitRule "Std")) + (P 15(N "15") 18000 12000 19(ExitRule "Std")) + (P 16(N "16") 18000 18000 19(ExitRule "Std")) + (P 17(N "17") 24000 0 19(ExitRule "Std")) + (P 18(N "18") 24000 6000 19(ExitRule "Std")) + (P 19(N "19") 24000 12000 19(ExitRule "Std")) + (P 20(N "20") 24000 18000 19(ExitRule "Std")) + (P 21(N "21") 30000 0 19(ExitRule "Std")) + (P 22(N "22") 30000 6000 19(ExitRule "Std")) + (P 23(N "23") 30000 12000 19(ExitRule "Std")) + (P 24(N "24") 30000 18000 19(ExitRule "Std")) + (P 25(N "25") 36000 0 19(ExitRule "Std")) + (P 26(N "26") 36000 6000 19(ExitRule "Std")) + (P 27(N "27") 36000 12000 19(ExitRule "Std")) + (P 28(N "28") 36000 18000 19(ExitRule "Std")) + (P 29(N "29") 42000 0 19(ExitRule "Std")) + (P 30(N "30") 42000 6000 19(ExitRule "Std")) + (P 31(N "31") 42000 12000 19(ExitRule "Std")) + (P 32(N "32") 42000 18000 19(ExitRule "Std")) + ) +(SYM 11(N "16DIP300_DD8")(Uid 642 9000 -21000 0 0)(Derived 266) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 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21(ExitRule "Std")) + (P 9(N "9") 0 48000 21(ExitRule "Std")) + (P 10(N "10") 0 54000 21(ExitRule "Std")) + (P 11(N "11") -18000 54000 21(ExitRule "Std")) + (P 12(N "12") -18000 48000 21(ExitRule "Std")) + (P 13(N "13") -18000 42000 21(ExitRule "Std")) + (P 14(N "14") -18000 36000 21(ExitRule "Std")) + (P 15(N "15") -18000 30000 21(ExitRule "Std")) + (P 16(N "16") -18000 24000 21(ExitRule "Std")) + (P 17(N "17") -18000 18000 21(ExitRule "Std")) + (P 18(N "18") -18000 12000 21(ExitRule "Std")) + (P 19(N "19") -18000 6000 21(ExitRule "Std")) + (P 20(N "20") -18000 0 21(ExitRule "Std")) + ) +(SYM 13(N "QFP100_DD10")(Uid 672 -21000 22500 0 0)(Derived 268) + (P 1(N "1") 0 0 22(ExitRule "Std")) + (P 2(N "2") 0 1500 22(ExitRule "Std")) + (P 3(N "3") 0 3000 22(ExitRule "Std")) + (P 4(N "4") 0 4500 22(ExitRule "Std")) + (P 5(N "5") 0 6000 22(ExitRule "Std")) + (P 6(N "6") 0 7500 22(ExitRule "Std")) + (P 7(N "7") 0 9000 22(ExitRule "Std")) + (P 8(N "8") 0 10500 22(ExitRule "Std")) + (P 9(N "9") 0 12000 22(ExitRule "Std")) + (P 10(N "10") 0 13500 22(ExitRule "Std")) + (P 11(N "11") 0 15000 22(ExitRule "Std")) + (P 12(N "12") 0 16500 22(ExitRule "Std")) + (P 13(N "13") 0 18000 22(ExitRule "Std")) + (P 14(N "14") 0 19500 22(ExitRule "Std")) + (P 15(N "15") 0 21000 22(ExitRule "Std")) + (P 16(N "16") 0 22500 22(ExitRule "Std")) + (P 17(N "17") 0 24000 22(ExitRule "Std")) + (P 18(N "18") 0 25500 22(ExitRule "Std")) + (P 19(N "19") 0 27000 22(ExitRule "Std")) + (P 20(N "20") 0 28500 22(ExitRule "Std")) + (P 21(N "21") 0 30000 22(ExitRule "Std")) + (P 22(N "22") 0 31500 22(ExitRule "Std")) + (P 23(N "23") 0 33000 22(ExitRule "Std")) + (P 24(N "24") 0 34500 22(ExitRule "Std")) + (P 25(N "25") 0 36000 22(ExitRule "Std")) + (P 26(N "26") 0 37500 22(ExitRule "Std")) + (P 27(N "27") 0 39000 22(ExitRule "Std")) + (P 28(N "28") 0 40500 22(ExitRule "Std")) + (P 29(N "29") 0 42000 22(ExitRule "Std")) + (P 30(N "30") 0 43500 22(ExitRule "Std")) + (P 31(N "31") -6000 49500 23(ExitRule "Std")) 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42000 22(ExitRule "Std")) + (P 53(N "53") -40500 40500 22(ExitRule "Std")) + (P 54(N "54") -40500 39000 22(ExitRule "Std")) + (P 55(N "55") -40500 37500 22(ExitRule "Std")) + (P 56(N "56") -40500 36000 22(ExitRule "Std")) + (P 57(N "57") -40500 34500 22(ExitRule "Std")) + (P 58(N "58") -40500 33000 22(ExitRule "Std")) + (P 59(N "59") -40500 31500 22(ExitRule "Std")) + (P 60(N "60") -40500 30000 22(ExitRule "Std")) + (P 61(N "61") -40500 28500 22(ExitRule "Std")) + (P 62(N "62") -40500 27000 22(ExitRule "Std")) + (P 63(N "63") -40500 25500 22(ExitRule "Std")) + (P 64(N "64") -40500 24000 22(ExitRule "Std")) + (P 65(N "65") -40500 22500 22(ExitRule "Std")) + (P 66(N "66") -40500 21000 22(ExitRule "Std")) + (P 67(N "67") -40500 19500 22(ExitRule "Std")) + (P 68(N "68") -40500 18000 22(ExitRule "Std")) + (P 69(N "69") -40500 16500 22(ExitRule "Std")) + (P 70(N "70") -40500 15000 22(ExitRule "Std")) + (P 71(N "71") -40500 13500 22(ExitRule "Std")) + (P 72(N "72") -40500 12000 22(ExitRule "Std")) + (P 73(N "73") -40500 10500 22(ExitRule "Std")) + (P 74(N "74") -40500 9000 22(ExitRule "Std")) + (P 75(N "75") -40500 7500 22(ExitRule "Std")) + (P 76(N "76") -40500 6000 22(ExitRule "Std")) + (P 77(N "77") -40500 4500 22(ExitRule "Std")) + (P 78(N "78") -40500 3000 22(ExitRule "Std")) + (P 79(N "79") -40500 1500 22(ExitRule "Std")) + (P 80(N "80") -40500 0 22(ExitRule "Std")) + (P 81(N "81") -34500 -6000 23(ExitRule "Std")) + (P 82(N "82") -33000 -6000 23(ExitRule "Std")) + (P 83(N "83") -31500 -6000 23(ExitRule "Std")) + (P 84(N "84") -30000 -6000 23(ExitRule "Std")) + (P 85(N "85") -28500 -6000 23(ExitRule "Std")) + (P 86(N "86") -27000 -6000 23(ExitRule "Std")) + (P 87(N "87") -25500 -6000 23(ExitRule "Std")) + (P 88(N "88") -24000 -6000 23(ExitRule "Std")) + (P 89(N "89") -22500 -6000 23(ExitRule "Std")) + (P 90(N "90") -21000 -6000 23(ExitRule "Std")) + (P 91(N "91") -19500 -6000 23(ExitRule "Std")) + (P 92(N "92") -18000 -6000 23(ExitRule "Std")) + (P 93(N "93") -16500 -6000 23(ExitRule "Std")) + (P 94(N "94") -15000 -6000 23(ExitRule "Std")) + (P 95(N "95") -13500 -6000 23(ExitRule "Std")) + (P 96(N "96") -12000 -6000 23(ExitRule "Std")) + (P 97(N "97") -10500 -6000 23(ExitRule "Std")) + (P 98(N "98") -9000 -6000 23(ExitRule "Std")) + (P 99(N "99") -7500 -6000 23(ExitRule "Std")) + (P 100(N "100") -6000 -6000 23(ExitRule "Std")) + ) +(SYM 14(N "20DIP300_DD12")(Uid 806 -9000 27000 0 0)(Derived 269) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") 0 24000 19(ExitRule "Std")) + (P 6(N "6") 0 30000 19(ExitRule "Std")) + (P 7(N "7") 0 36000 19(ExitRule "Std")) + (P 8(N "8") 0 42000 19(ExitRule "Std")) + (P 9(N "9") 0 48000 19(ExitRule "Std")) + (P 10(N "10") 0 54000 19(ExitRule "Std")) + (P 11(N "11") -18000 54000 19(ExitRule "Std")) + (P 12(N "12") -18000 48000 19(ExitRule "Std")) + (P 13(N "13") -18000 42000 19(ExitRule "Std")) + (P 14(N "14") -18000 36000 19(ExitRule "Std")) + (P 15(N "15") -18000 30000 19(ExitRule "Std")) + (P 16(N "16") -18000 24000 19(ExitRule "Std")) + (P 17(N "17") -18000 18000 19(ExitRule "Std")) + (P 18(N "18") -18000 12000 19(ExitRule "Std")) + (P 19(N "19") -18000 6000 19(ExitRule "Std")) + (P 20(N "20") -18000 0 19(ExitRule "Std")) + ) +(SYM 15(N "20DIP300_DD13")(Uid 817 -9000 27000 0 0)(Derived 270) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") 0 24000 19(ExitRule "Std")) + (P 6(N "6") 0 30000 19(ExitRule "Std")) + (P 7(N "7") 0 36000 19(ExitRule "Std")) + (P 8(N "8") 0 42000 19(ExitRule "Std")) + (P 9(N "9") 0 48000 19(ExitRule "Std")) + (P 10(N "10") 0 54000 19(ExitRule "Std")) + (P 11(N "11") -18000 54000 19(ExitRule "Std")) + (P 12(N "12") -18000 48000 19(ExitRule "Std")) + (P 13(N "13") -18000 42000 19(ExitRule "Std")) + (P 14(N "14") -18000 36000 19(ExitRule "Std")) + (P 15(N "15") -18000 30000 19(ExitRule "Std")) + (P 16(N "16") -18000 24000 19(ExitRule "Std")) + (P 17(N "17") -18000 18000 19(ExitRule "Std")) + (P 18(N "18") -18000 12000 19(ExitRule "Std")) + (P 19(N "19") -18000 6000 19(ExitRule "Std")) + (P 20(N "20") -18000 0 19(ExitRule "Std")) + ) +(SYM 16(N "ONC5_XR1")(Uid 827 18000 12000 0 0)(Derived 271) + (P 1(N "1") 0 0 25(ExitRule "Std")) + (P 2(N "2") 0 -18000 25(ExitRule "Std")) + (P 3(N "3") 0 -36000 25(ExitRule "Std")) + (P 4(N "4") -6000 -6000 25(ExitRule "Std")) + (P 5(N "5") -6000 -30000 25(ExitRule "Std")) + (P 6(N "X1") 24000 -6000 26(ExitRule "Std")) + (P 7(N "X2") 24000 -12000 26(ExitRule "Std")) + (P 8(N "X3") 24000 -24000 26(ExitRule "Std")) + (P 9(N "X4") 24000 -30000 26(ExitRule "Std")) + ) +(SYM 17(N "XPOWER_XR2")(Uid 840 18000 0 0 0)(Derived 272) + (P 1(N "1") 0 0 25(ExitRule "Std")) + (P 2(N "2") 0 -9000 25(ExitRule "Std")) + (P 3(N "3") 0 -18000 25(ExitRule "Std")) + (P 4(N "4") 0 -27000 25(ExitRule "Std")) + (P 5(N "5") 0 -36000 25(ExitRule "Std")) + (P 6(N "6") 0 -45000 25(ExitRule "Std")) + ) +(SYM 18(N "20DIP300_DD14")(Uid 847 -27000 -9000 0 0)(Derived 273) + (P 1(N "1") 0 0 27(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + (P 3(N "3") 0 -12000 28(ExitRule "Std")) + (P 4(N "4") 0 -18000 28(ExitRule "Std")) + (P 5(N "5") 0 -24000 28(ExitRule "Std")) + (P 6(N "6") 0 -30000 28(ExitRule "Std")) + (P 7(N "7") 0 -36000 28(ExitRule "Std")) + (P 8(N "8") 0 -42000 28(ExitRule "Std")) + (P 9(N "9") 0 -48000 28(ExitRule "Std")) + (P 10(N "10") 0 -54000 28(ExitRule "Std")) + (P 11(N "11") 18000 -54000 28(ExitRule "Std")) + (P 12(N "12") 18000 -48000 28(ExitRule "Std")) + (P 13(N "13") 18000 -42000 28(ExitRule "Std")) + (P 14(N "14") 18000 -36000 28(ExitRule "Std")) + (P 15(N "15") 18000 -30000 28(ExitRule "Std")) + (P 16(N "16") 18000 -24000 28(ExitRule "Std")) + (P 17(N "17") 18000 -18000 28(ExitRule "Std")) + (P 18(N "18") 18000 -12000 28(ExitRule "Std")) + (P 19(N "19") 18000 -6000 28(ExitRule "Std")) + (P 20(N "20") 18000 0 28(ExitRule "Std")) + ) +(SYM 19(N "20DIP300_DD15")(Uid 857 -27000 -9000 0 0)(Derived 274) + (P 1(N "1") 0 0 27(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + (P 3(N "3") 0 -12000 28(ExitRule "Std")) + (P 4(N "4") 0 -18000 28(ExitRule "Std")) + (P 5(N "5") 0 -24000 28(ExitRule "Std")) + (P 6(N "6") 0 -30000 28(ExitRule "Std")) + (P 7(N "7") 0 -36000 28(ExitRule "Std")) + (P 8(N "8") 0 -42000 28(ExitRule "Std")) + (P 9(N "9") 0 -48000 28(ExitRule "Std")) + (P 10(N "10") 0 -54000 28(ExitRule "Std")) + (P 11(N "11") 18000 -54000 28(ExitRule "Std")) + (P 12(N "12") 18000 -48000 28(ExitRule "Std")) + (P 13(N "13") 18000 -42000 28(ExitRule "Std")) + (P 14(N "14") 18000 -36000 28(ExitRule "Std")) + (P 15(N "15") 18000 -30000 28(ExitRule "Std")) + (P 16(N "16") 18000 -24000 28(ExitRule "Std")) + (P 17(N "17") 18000 -18000 28(ExitRule "Std")) + (P 18(N "18") 18000 -12000 28(ExitRule "Std")) + (P 19(N "19") 18000 -6000 28(ExitRule "Std")) + (P 20(N "20") 18000 0 28(ExitRule "Std")) + ) +(SYM 20(N "SIMM72_SIMM")(Uid 867 3000 112500 0 0)(Derived 275) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") -6000 -3000 21(ExitRule "Std")) + (P 3(N "3") 0 -6000 21(ExitRule "Std")) + (P 4(N "4") -6000 -9000 21(ExitRule "Std")) + (P 5(N "5") 0 -12000 21(ExitRule "Std")) + (P 6(N "6") -6000 -15000 21(ExitRule "Std")) + (P 7(N "7") 0 -18000 21(ExitRule "Std")) + (P 8(N "8") -6000 -21000 21(ExitRule "Std")) + (P 9(N "9") 0 -24000 21(ExitRule "Std")) + (P 10(N "10") -6000 -27000 21(ExitRule "Std")) + (P 11(N "11") 0 -30000 21(ExitRule "Std")) + (P 12(N "12") -6000 -33000 21(ExitRule "Std")) + (P 13(N "13") 0 -36000 21(ExitRule "Std")) + (P 14(N "14") -6000 -39000 21(ExitRule "Std")) + (P 15(N "15") 0 -42000 21(ExitRule "Std")) + (P 16(N "16") -6000 -45000 21(ExitRule "Std")) + (P 17(N "17") 0 -48000 21(ExitRule "Std")) + (P 18(N "18") -6000 -51000 21(ExitRule "Std")) + (P 19(N "19") 0 -54000 21(ExitRule "Std")) + (P 20(N "20") -6000 -57000 21(ExitRule "Std")) + (P 21(N "21") 0 -60000 21(ExitRule "Std")) + (P 22(N "22") -6000 -63000 21(ExitRule "Std")) + (P 23(N "23") 0 -66000 21(ExitRule "Std")) + (P 24(N "24") -6000 -69000 21(ExitRule "Std")) + (P 25(N "25") 0 -72000 21(ExitRule "Std")) + (P 26(N "26") -6000 -75000 21(ExitRule "Std")) + (P 27(N "27") 0 -78000 21(ExitRule "Std")) + (P 28(N "28") -6000 -81000 21(ExitRule "Std")) + (P 29(N "29") 0 -84000 21(ExitRule "Std")) + (P 30(N "30") -6000 -87000 21(ExitRule "Std")) + (P 31(N "31") 0 -90000 21(ExitRule "Std")) + (P 32(N "32") -6000 -93000 21(ExitRule "Std")) + (P 33(N "33") 0 -96000 21(ExitRule "Std")) + (P 34(N "34") -6000 -99000 21(ExitRule "Std")) + (P 35(N "35") 0 -102000 21(ExitRule "Std")) + (P 36(N "36") -6000 -105000 21(ExitRule "Std")) + (P 37(N "37") 0 -120000 21(ExitRule "Std")) + (P 38(N "38") -6000 -123000 21(ExitRule "Std")) + (P 39(N "39") 0 -126000 21(ExitRule "Std")) + (P 40(N "40") -6000 -129000 21(ExitRule "Std")) + (P 41(N "41") 0 -132000 21(ExitRule "Std")) + (P 42(N "42") -6000 -135000 21(ExitRule "Std")) + (P 43(N "43") 0 -138000 21(ExitRule "Std")) + (P 44(N "44") -6000 -141000 21(ExitRule "Std")) + (P 45(N "45") 0 -144000 21(ExitRule "Std")) + (P 46(N "46") -6000 -147000 21(ExitRule "Std")) + (P 47(N "47") 0 -150000 21(ExitRule "Std")) + (P 48(N "48") -6000 -153000 21(ExitRule "Std")) + (P 49(N "49") 0 -156000 21(ExitRule "Std")) + (P 50(N "50") -6000 -159000 21(ExitRule "Std")) + (P 51(N "51") 0 -162000 21(ExitRule "Std")) + (P 52(N "52") -6000 -165000 21(ExitRule "Std")) + (P 53(N "53") 0 -168000 21(ExitRule "Std")) + (P 54(N "54") -6000 -171000 21(ExitRule "Std")) + (P 55(N "55") 0 -174000 21(ExitRule "Std")) + (P 56(N "56") -6000 -177000 21(ExitRule "Std")) + (P 57(N "57") 0 -180000 21(ExitRule "Std")) + (P 58(N "58") -6000 -183000 21(ExitRule "Std")) + (P 59(N "59") 0 -186000 21(ExitRule "Std")) + (P 60(N "60") -6000 -189000 21(ExitRule "Std")) + (P 61(N "61") 0 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"Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 23(N "32dip300_DD17")(Uid 910 45000 9000 0 0)(Derived 278) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 24(N "32dip300_DD18")(Uid 912 45000 9000 0 0)(Derived 279) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 25(N "VT1_VT1-2")(Uid 914 0 -6000 0 0)(Derived 280) + (P 1(N "1") 0 0 32(ExitRule "Std")) + (P 2(N "2") 0 6000 32(ExitRule "Std")) + (P 3(N "3") 0 12000 32(ExitRule "Std")) + ) +(SYM 26(N "VT1_VT2")(Uid 919 0 -6000 0 0)(Derived 281) + (P 1(N "1") 0 0 32(ExitRule "Std")) + (P 2(N "2") 0 6000 32(ExitRule "Std")) + (P 3(N "3") 0 12000 32(ExitRule "Std")) + ) +(SYM 27(N "VT1_VT3")(Uid 922 0 -6000 0 0)(Derived 282) + (P 1(N "1") 0 0 32(ExitRule "Std")) + (P 2(N "2") 0 6000 32(ExitRule "Std")) + (P 3(N "3") 0 12000 32(ExitRule "Std")) + ) +(SYM 28(N "VT1_VT4")(Uid 925 0 -6000 0 0)(Derived 283) + (P 1(N "1") 0 0 32(ExitRule "Std")) + (P 2(N "2") 0 6000 32(ExitRule "Std")) + (P 3(N "3") 0 12000 32(ExitRule "Std")) + ) +(SYM 29(N "pin_PIN-2")(Uid 929 0 0 0 0)(Derived 284) + (P 1(N "Hole4") 0 0 31(ExitRule "Std")) + ) +(SYM 30(N "pin_PIN-3")(Uid 931 0 0 0 0)(Derived 285) + (P 1(N "Hole5") 0 0 31(ExitRule "Std")) + ) +(SYM 31(N "pin_PIN-4")(Uid 933 0 0 0 0)(Derived 286) + (P 1(N "Hole6") 0 0 31(ExitRule "Std")) + ) +(SYM 32(N "RC02_R49")(Uid 935 3000 0 0 0)(Derived 287) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 33(N "RC02_R50")(Uid 940 3000 0 0 0)(Derived 288) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 34(N "RC02_R51")(Uid 943 -3000 0 0 0)(Derived 289) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 35(N "RC02_R52")(Uid 946 3000 0 0 0)(Derived 290) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 36(N "RC02_R53")(Uid 948 3000 0 0 0)(Derived 291) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 37(N "RC02_R54")(Uid 951 -3000 0 0 0)(Derived 292) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 38(N "RC02_R55")(Uid 953 3000 0 0 0)(Derived 293) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 39(N "RC02_R56")(Uid 956 3000 0 0 0)(Derived 294) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 40(N "RC02_R57")(Uid 959 -3000 0 0 0)(Derived 295) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 41(N "RC02_R58")(Uid 961 3000 0 0 0)(Derived 296) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 42(N "RC02_R59")(Uid 963 3000 0 0 0)(Derived 297) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 43(N "RC02_R60")(Uid 966 -3000 0 0 0)(Derived 298) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 44(N "40DIP600_DD19")(Uid 968 18000 -57000 0 0)(Derived 299) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") 0 42000 21(ExitRule "Std")) + (P 9(N "9") 0 48000 21(ExitRule "Std")) + (P 10(N "10") 0 54000 21(ExitRule "Std")) + (P 11(N "11") 0 60000 21(ExitRule "Std")) + (P 12(N "12") 0 66000 21(ExitRule "Std")) + (P 13(N "13") 0 72000 21(ExitRule "Std")) + (P 14(N "14") 0 78000 21(ExitRule "Std")) + (P 15(N "15") 0 84000 21(ExitRule "Std")) + (P 16(N "16") 0 90000 21(ExitRule "Std")) + (P 17(N "17") 0 96000 21(ExitRule "Std")) + (P 18(N "18") 0 102000 21(ExitRule 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-36000 6000 21(ExitRule "Std")) + (P 40(N "40") -36000 0 21(ExitRule "Std")) + ) +(SYM 45(N "HD10_R61-R70")(Uid 985 21000 0 0 0)(Derived 300) + (P 1(N "2") 0 0 19(ExitRule "Std")) + (P 2(N "3") 6000 0 19(ExitRule "Std")) + (P 3(N "4") 12000 0 19(ExitRule "Std")) + (P 4(N "5") 18000 0 19(ExitRule "Std")) + (P 5(N "6") 24000 0 19(ExitRule "Std")) + (P 6(N "7") 30000 0 19(ExitRule "Std")) + (P 7(N "8") 36000 0 19(ExitRule "Std")) + (P 8(N "9") 42000 0 19(ExitRule "Std")) + (P 9(N "10") 48000 0 19(ExitRule "Std")) + (P 10(N "1") -6000 0 19(ExitRule "Std")) + ) +(SYM 46(N "VT1_VT5")(Uid 990 -6000 0 0 0)(Derived 301) + (P 1(N "1") 0 0 33(ExitRule "Std")) + (P 2(N "2") 0 -6000 33(ExitRule "Std")) + (P 3(N "3") 0 -12000 33(ExitRule "Std")) + ) +(SYM 47(N "VT1_VT6")(Uid 994 6000 0 0 0)(Derived 302) + (P 1(N "1") 0 0 34(ExitRule "Std")) + (P 2(N "2") 0 -6000 34(ExitRule "Std")) + (P 3(N "3") 0 -12000 34(ExitRule "Std")) + ) +(SYM 48(N "RC02_R71")(Uid 996 -3000 0 0 0)(Derived 303) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 49(N "RC05_R72")(Uid 999 -12000 0 0 0)(Derived 304) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -24000 28(ExitRule "Std")) + ) +(SYM 50(N "RC05_R73")(Uid 1002 -12000 0 0 0)(Derived 305) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -24000 28(ExitRule "Std")) + ) +(SYM 51(N "RC02_R74")(Uid 1004 0 -3000 0 0)(Derived 306) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 52(N "14DIP300_DD20")(Uid 1007 -18000 -9000 0 0) + (Derived 307) + (P 1(N "1") 0 0 27(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + (P 3(N "3") 0 -12000 28(ExitRule "Std")) + (P 4(N "4") 0 -18000 28(ExitRule "Std")) + (P 5(N "5") 0 -24000 28(ExitRule "Std")) + (P 6(N "6") 0 -30000 28(ExitRule "Std")) + (P 7(N "7") 0 -36000 28(ExitRule "Std")) + (P 8(N "8") 18000 -36000 28(ExitRule "Std")) + (P 9(N "9") 18000 -30000 28(ExitRule "Std")) + (P 10(N "10") 18000 -24000 28(ExitRule "Std")) + (P 11(N "11") 18000 -18000 28(ExitRule "Std")) + (P 12(N "12") 18000 -12000 28(ExitRule "Std")) + (P 13(N "13") 18000 -6000 28(ExitRule "Std")) + (P 14(N "14") 18000 0 28(ExitRule "Std")) + ) +(SYM 53(N "RC02_R75")(Uid 1018 -3000 0 0 0)(Derived 308) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 54(N "RC02_R76")(Uid 1021 -3000 0 0 0)(Derived 309) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 55(N "CAP1_C1")(Uid 1023 0 12000 0 0)(Derived 310) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 24000 19(ExitRule "Std")) + ) +(SYM 56(N "pin_PIN-5")(Uid 1027 0 0 0 0)(Derived 311) + (P 1(N "Hole7") 0 0 31(ExitRule "Std")) + ) +(SYM 57(N "2200mkf_C2")(Uid 1029 0 12000 0 0)(Derived 312) + (P 1(N "1") 0 0 35(ExitRule "Std")) + (P 2(N "2") -24000 0 35(ExitRule "Std")) + ) +(SYM 58(N "20dip300_DD21")(Uid 1033 -9000 27000 0 0)(Derived 313) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") 0 24000 19(ExitRule "Std")) + (P 6(N "6") 0 30000 19(ExitRule "Std")) + (P 7(N "7") 0 36000 19(ExitRule "Std")) + (P 8(N "8") 0 42000 19(ExitRule "Std")) + (P 9(N "9") 0 48000 19(ExitRule "Std")) + (P 10(N "10") 0 54000 19(ExitRule "Std")) + (P 11(N "11") -18000 54000 19(ExitRule "Std")) + (P 12(N "12") -18000 48000 19(ExitRule "Std")) + (P 13(N "13") -18000 42000 19(ExitRule "Std")) + (P 14(N "14") -18000 36000 19(ExitRule "Std")) + (P 15(N "15") -18000 30000 19(ExitRule "Std")) + (P 16(N "16") -18000 24000 19(ExitRule "Std")) + (P 17(N "17") -18000 18000 19(ExitRule "Std")) + (P 18(N "18") -18000 12000 19(ExitRule "Std")) + (P 19(N "19") -18000 6000 19(ExitRule "Std")) + (P 20(N "20") -18000 0 19(ExitRule "Std")) + ) +(SYM 59(N "32dip300_DD22")(Uid 1045 9000 -45000 0 0)(Derived 314) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") 0 42000 21(ExitRule "Std")) + (P 9(N "9") 0 48000 21(ExitRule "Std")) + (P 10(N "10") 0 54000 21(ExitRule "Std")) + (P 11(N "11") 0 60000 21(ExitRule "Std")) + (P 12(N "12") 0 66000 21(ExitRule "Std")) + (P 13(N "13") 0 72000 21(ExitRule "Std")) + (P 14(N "14") 0 78000 21(ExitRule "Std")) + (P 15(N "15") 0 84000 21(ExitRule "Std")) + (P 16(N "16") 0 90000 21(ExitRule "Std")) + (P 17(N "17") -18000 90000 21(ExitRule "Std")) + (P 18(N "18") -18000 84000 21(ExitRule "Std")) + (P 19(N "19") -18000 78000 21(ExitRule "Std")) + (P 20(N "20") -18000 72000 21(ExitRule "Std")) + (P 21(N "21") -18000 66000 21(ExitRule "Std")) + (P 22(N "22") -18000 60000 21(ExitRule "Std")) + (P 23(N "23") -18000 54000 21(ExitRule "Std")) + (P 24(N "24") -18000 48000 21(ExitRule "Std")) + (P 25(N "25") -18000 42000 21(ExitRule "Std")) + (P 26(N "26") -18000 36000 21(ExitRule "Std")) + (P 27(N "27") -18000 30000 21(ExitRule "Std")) + (P 28(N "28") -18000 24000 21(ExitRule "Std")) + (P 29(N "29") -18000 18000 21(ExitRule "Std")) + (P 30(N "30") -18000 12000 21(ExitRule "Std")) + (P 31(N "31") -18000 6000 21(ExitRule "Std")) + (P 32(N "32") -18000 0 21(ExitRule "Std")) + ) +(SYM 60(N "16DIP300_DD23")(Uid 1049 21000 9000 0 0)(Derived 315) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 18000 -42000 17(ExitRule "Std")) + (P 10(N "10") 18000 -36000 17(ExitRule "Std")) + (P 11(N "11") 18000 -30000 17(ExitRule "Std")) + (P 12(N "12") 18000 -24000 17(ExitRule "Std")) + (P 13(N "13") 18000 -18000 17(ExitRule "Std")) + (P 14(N "14") 18000 -12000 17(ExitRule "Std")) + (P 15(N "15") 18000 -6000 17(ExitRule "Std")) + (P 16(N "16") 18000 0 17(ExitRule "Std")) + ) +(SYM 61(N "RC02_XR3")(Uid 1060 -3000 0 0 0)(Derived 316) + (P 1(N "1") 0 0 36(ExitRule "Std")) + (P 2(N "2") 0 -6000 36(ExitRule "Std")) + ) +(SYM 62(N "RC02_R77")(Uid 1066 0 3000 0 0)(Derived 317) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 63(N "RC02_R78")(Uid 1069 0 3000 0 0)(Derived 318) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 64(N "RC02_R79")(Uid 1072 0 3000 0 0)(Derived 319) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 65(N "RC02_R80")(Uid 1075 0 -3000 0 0)(Derived 320) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 66(N "RC02_XR5")(Uid 1078 -3000 0 0 0)(Derived 321) + (P 1(N "1") 0 0 36(ExitRule "Std")) + (P 2(N "2") 0 -6000 36(ExitRule "Std")) + ) +(SYM 67(N "2200MKF_C3")(Uid 1081 0 12000 0 0)(Derived 322) + (P 1(N "1") 0 0 35(ExitRule "Std")) + (P 2(N "2") -24000 0 35(ExitRule "Std")) + ) +(SYM 68(N "CAP1_C4")(Uid 1084 -12000 0 0 0)(Derived 323) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -24000 28(ExitRule "Std")) + ) +(SYM 69(N "CAP1_C5")(Uid 1086 12000 0 0 0)(Derived 324) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -24000 17(ExitRule "Std")) + ) +(SYM 70(N "CAP1_C6")(Uid 1088 12000 0 0 0)(Derived 325) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -24000 17(ExitRule "Std")) + ) +(SYM 71(N "CAP1_C7")(Uid 1090 12000 0 0 0)(Derived 326) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -24000 17(ExitRule "Std")) + ) +(SYM 72(N "CAP1_C8")(Uid 1092 12000 0 0 0)(Derived 327) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -24000 17(ExitRule "Std")) + ) +(SYM 73(N "CAP1_C9")(Uid 1094 0 -12000 0 0)(Derived 328) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 24000 21(ExitRule "Std")) + ) +(SYM 74(N "RC02_R81")(Uid 1096 -3000 0 0 0)(Derived 329) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 75(N "RC02_R82")(Uid 1099 -3000 0 0 0)(Derived 330) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 76(N "RC02_R83")(Uid 1103 -3000 0 0 0)(Derived 331) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 77(N "RC02_R84")(Uid 1107 0 -3000 0 0)(Derived 332) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 78(N "RC02_R85")(Uid 1110 0 -3000 0 0)(Derived 333) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 79(N "20DIP300_DD34")(Uid 1113 -9000 27000 0 0)(Derived 334) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") 0 24000 19(ExitRule "Std")) + (P 6(N "6") 0 30000 19(ExitRule "Std")) + (P 7(N "7") 0 36000 19(ExitRule "Std")) + (P 8(N "8") 0 42000 19(ExitRule "Std")) + (P 9(N "9") 0 48000 19(ExitRule "Std")) + (P 10(N "10") 0 54000 19(ExitRule "Std")) + (P 11(N "11") -18000 54000 19(ExitRule "Std")) + (P 12(N "12") -18000 48000 19(ExitRule "Std")) + (P 13(N "13") -18000 42000 19(ExitRule "Std")) + (P 14(N "14") -18000 36000 19(ExitRule "Std")) + (P 15(N "15") -18000 30000 19(ExitRule "Std")) + (P 16(N "16") -18000 24000 19(ExitRule "Std")) + (P 17(N "17") -18000 18000 19(ExitRule "Std")) + (P 18(N "18") -18000 12000 19(ExitRule "Std")) + (P 19(N "19") -18000 6000 19(ExitRule "Std")) + (P 20(N "20") -18000 0 19(ExitRule "Std")) + ) +(SYM 80(N "RC02_R86")(Uid 1124 -3000 0 0 0)(Derived 335) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 81(N "RC02_R87")(Uid 1127 -3000 0 0 0)(Derived 336) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 82(N "32dip300_DD25")(Uid 1129 45000 9000 0 0)(Derived 337) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 83(N "32dip300_DD26")(Uid 1131 45000 9000 0 0)(Derived 338) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 19(N "19") 18000 -78000 17(ExitRule "Std")) + (P 20(N "20") 18000 -72000 17(ExitRule "Std")) + (P 21(N "21") 18000 -66000 17(ExitRule "Std")) + (P 22(N "22") 18000 -60000 17(ExitRule "Std")) + (P 23(N "23") 18000 -54000 17(ExitRule "Std")) + (P 24(N "24") 18000 -48000 17(ExitRule "Std")) + (P 25(N "25") 18000 -42000 17(ExitRule "Std")) + (P 26(N "26") 18000 -36000 17(ExitRule "Std")) + (P 27(N "27") 18000 -30000 17(ExitRule "Std")) + (P 28(N "28") 18000 -24000 17(ExitRule "Std")) + (P 29(N "29") 18000 -18000 17(ExitRule "Std")) + (P 30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 84(N "32dip600_DD27")(Uid 1133 18000 -45000 0 0) + (Derived 339) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") 0 42000 21(ExitRule "Std")) + (P 9(N "9") 0 48000 21(ExitRule "Std")) + (P 10(N "10") 0 54000 21(ExitRule "Std")) + (P 11(N "11") 0 60000 21(ExitRule "Std")) + (P 12(N "12") 0 66000 21(ExitRule "Std")) + (P 13(N "13") 0 72000 21(ExitRule "Std")) + (P 14(N "14") 0 78000 21(ExitRule "Std")) + (P 15(N "15") 0 84000 21(ExitRule "Std")) + (P 16(N "16") 0 90000 21(ExitRule "Std")) + (P 17(N "17") -36000 90000 21(ExitRule "Std")) + (P 18(N "18") -36000 84000 21(ExitRule "Std")) + (P 19(N "19") -36000 78000 21(ExitRule "Std")) + (P 20(N "20") -36000 72000 21(ExitRule "Std")) + (P 21(N "21") -36000 66000 21(ExitRule "Std")) + (P 22(N "22") -36000 60000 21(ExitRule "Std")) + (P 23(N "23") -36000 54000 21(ExitRule "Std")) + (P 24(N "24") -36000 48000 21(ExitRule "Std")) + (P 25(N "25") -36000 42000 21(ExitRule "Std")) + (P 26(N "26") -36000 36000 21(ExitRule "Std")) + (P 27(N "27") -36000 30000 21(ExitRule "Std")) + (P 28(N "28") -36000 24000 21(ExitRule "Std")) + (P 29(N "29") -36000 18000 21(ExitRule "Std")) + (P 30(N "30") -36000 12000 21(ExitRule "Std")) + (P 31(N "31") -36000 6000 21(ExitRule "Std")) + (P 32(N "32") -36000 0 21(ExitRule "Std")) + ) +(SYM 85(N "RC02_R88")(Uid 1138 3000 0 0 0)(Derived 340) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 86(N "RC02_R89")(Uid 1140 3000 0 0 0)(Derived 341) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 87(N "RC02_R90")(Uid 1142 3000 0 0 0)(Derived 342) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 88(N "RC02_R91")(Uid 1144 3000 0 0 0)(Derived 343) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 89(N "RC02_R92")(Uid 1146 3000 0 0 0)(Derived 344) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 90(N "8dip300_DD28")(Uid 1148 -9000 9000 0 0)(Derived 345) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") -18000 18000 19(ExitRule "Std")) + (P 6(N "6") -18000 12000 19(ExitRule "Std")) + (P 7(N "7") -18000 6000 19(ExitRule "Std")) + (P 8(N "8") -18000 0 19(ExitRule "Std")) + ) +(SYM 91(N "8dip300_DD29")(Uid 1155 -9000 9000 0 0)(Derived 346) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") -18000 18000 19(ExitRule "Std")) + (P 6(N "6") -18000 12000 19(ExitRule "Std")) + (P 7(N "7") -18000 6000 19(ExitRule "Std")) + (P 8(N "8") -18000 0 19(ExitRule "Std")) + ) +(SYM 92(N "RC02_R93")(Uid 1160 3000 0 0 0)(Derived 347) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 93(N "RC02_R94")(Uid 1163 3000 0 0 0)(Derived 348) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 94(N "16DIP300_DD30")(Uid 1165 21000 9000 0 0)(Derived 349) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 18000 -42000 17(ExitRule "Std")) + (P 10(N "10") 18000 -36000 17(ExitRule "Std")) + (P 11(N "11") 18000 -30000 17(ExitRule "Std")) + (P 12(N "12") 18000 -24000 17(ExitRule "Std")) + (P 13(N "13") 18000 -18000 17(ExitRule "Std")) + (P 14(N "14") 18000 -12000 17(ExitRule "Std")) + (P 15(N "15") 18000 -6000 17(ExitRule "Std")) + (P 16(N "16") 18000 0 17(ExitRule "Std")) + ) +(SYM 95(N "RC02_R95")(Uid 1173 3000 0 0 0)(Derived 350) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 96(N "RC02_R96")(Uid 1175 3000 0 0 0)(Derived 351) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 97(N "RC02_R97")(Uid 1177 3000 0 0 0)(Derived 352) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 98(N "EL05_ZQ1")(Uid 1179 -6000 0 0 0)(Derived 353) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -12000 28(ExitRule "Std")) + ) +(SYM 99(N "RC05_R98")(Uid 1183 12000 0 0 0)(Derived 354) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -24000 17(ExitRule "Std")) + ) +(SYM 100(N "RC02_C10")(Uid 1185 -3000 0 0 0)(Derived 355) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 101(N "RC02_C11")(Uid 1188 3000 0 0 0)(Derived 356) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 102(N "RC02_R99")(Uid 1190 0 3000 0 0)(Derived 357) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 103(N "RC02_R100")(Uid 1192 3000 0 0 0)(Derived 358) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 104(N "CAP1_C12")(Uid 1195 -12000 0 0 0)(Derived 359) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -24000 28(ExitRule "Std")) + ) +(SYM 105(N "20DIP300_DD32")(Uid 1197 -27000 -9000 0 0) + (Derived 360) + (P 1(N "1") 0 0 27(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + (P 3(N "3") 0 -12000 28(ExitRule "Std")) + (P 4(N "4") 0 -18000 28(ExitRule "Std")) + (P 5(N "5") 0 -24000 28(ExitRule "Std")) + (P 6(N "6") 0 -30000 28(ExitRule "Std")) + (P 7(N "7") 0 -36000 28(ExitRule "Std")) + (P 8(N "8") 0 -42000 28(ExitRule "Std")) + (P 9(N "9") 0 -48000 28(ExitRule "Std")) + (P 10(N "10") 0 -54000 28(ExitRule "Std")) + (P 11(N "11") 18000 -54000 28(ExitRule "Std")) + (P 12(N "12") 18000 -48000 28(ExitRule "Std")) + (P 13(N "13") 18000 -42000 28(ExitRule "Std")) + (P 14(N "14") 18000 -36000 28(ExitRule "Std")) + (P 15(N "15") 18000 -30000 28(ExitRule "Std")) + (P 16(N "16") 18000 -24000 28(ExitRule "Std")) + (P 17(N "17") 18000 -18000 28(ExitRule "Std")) + (P 18(N "18") 18000 -12000 28(ExitRule "Std")) + (P 19(N "19") 18000 -6000 28(ExitRule "Std")) + (P 20(N "20") 18000 0 28(ExitRule "Std")) + ) +(SYM 106(N "20DIP300_DD33")(Uid 1200 -9000 27000 0 0) + (Derived 361) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") 0 24000 19(ExitRule "Std")) + (P 6(N "6") 0 30000 19(ExitRule "Std")) + (P 7(N "7") 0 36000 19(ExitRule "Std")) + (P 8(N "8") 0 42000 19(ExitRule "Std")) + (P 9(N "9") 0 48000 19(ExitRule "Std")) + (P 10(N "10") 0 54000 19(ExitRule "Std")) + (P 11(N "11") -18000 54000 19(ExitRule "Std")) + (P 12(N "12") -18000 48000 19(ExitRule "Std")) + (P 13(N "13") -18000 42000 19(ExitRule "Std")) + (P 14(N "14") -18000 36000 19(ExitRule "Std")) + (P 15(N "15") -18000 30000 19(ExitRule "Std")) + (P 16(N "16") -18000 24000 19(ExitRule "Std")) + (P 17(N "17") -18000 18000 19(ExitRule "Std")) + (P 18(N "18") -18000 12000 19(ExitRule "Std")) + (P 19(N "19") -18000 6000 19(ExitRule "Std")) + (P 20(N "20") -18000 0 19(ExitRule "Std")) + ) +(SYM 107(N "HD10_?")(Uid 1207 21000 0 0 0)(Derived 362) + (P 1(N "2") 0 0 19(ExitRule "Std")) + (P 2(N "3") 6000 0 19(ExitRule "Std")) + (P 3(N "4") 12000 0 19(ExitRule "Std")) + (P 4(N "5") 18000 0 19(ExitRule "Std")) + (P 5(N "6") 24000 0 19(ExitRule "Std")) + (P 6(N "7") 30000 0 19(ExitRule "Std")) + (P 7(N "8") 36000 0 19(ExitRule "Std")) + (P 8(N "9") 42000 0 19(ExitRule "Std")) + (P 9(N "10") 48000 0 19(ExitRule "Std")) + (P 10(N "1") -6000 0 19(ExitRule "Std")) + ) +(SYM 108(N "10DIP100_R102-106")(Uid 1209 3000 -12000 0 0) + (Derived 363) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") -6000 0 21(ExitRule "Std")) + (P 3(N "3") 0 6000 21(ExitRule "Std")) + (P 4(N "4") -6000 6000 21(ExitRule "Std")) + (P 5(N "5") 0 12000 21(ExitRule "Std")) + (P 6(N "6") -6000 12000 21(ExitRule "Std")) + (P 7(N "7") 0 18000 21(ExitRule "Std")) + (P 8(N "8") -6000 18000 21(ExitRule "Std")) + (P 9(N "9") 0 24000 21(ExitRule "Std")) + (P 10(N "10") -6000 24000 21(ExitRule "Std")) + ) +(SYM 109(N "RC02_R107")(Uid 1212 3000 0 0 0)(Derived 364) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 110(N "24DIP600_DD34-2")(Uid 1215 18000 -33000 0 0) + (Derived 365) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") 0 42000 21(ExitRule "Std")) + (P 9(N "9") 0 48000 21(ExitRule "Std")) + (P 10(N "10") 0 54000 21(ExitRule "Std")) + (P 11(N "11") 0 60000 21(ExitRule "Std")) + (P 12(N "12") 0 66000 21(ExitRule "Std")) + (P 13(N "13") -36000 66000 21(ExitRule "Std")) + (P 14(N "14") -36000 60000 21(ExitRule "Std")) + (P 15(N "15") -36000 54000 21(ExitRule "Std")) + (P 16(N "16") -36000 48000 21(ExitRule "Std")) + (P 17(N "17") -36000 42000 21(ExitRule "Std")) + (P 18(N "18") -36000 36000 21(ExitRule "Std")) + (P 19(N "19") -36000 30000 21(ExitRule "Std")) + (P 20(N "20") -36000 24000 21(ExitRule "Std")) + (P 21(N "21") -36000 18000 21(ExitRule "Std")) + (P 22(N "22") -36000 12000 21(ExitRule "Std")) + (P 23(N "23") -36000 6000 21(ExitRule "Std")) + (P 24(N "24") -36000 0 21(ExitRule "Std")) + ) +(SYM 111(N "208qfp10_DD35")(Uid 1226 -30000 -35400 0 0) + (Derived 366) + (P 1(N "1") 0 0 37(ExitRule "Std")) + (P 2(N "3") 2400 0 37(ExitRule "Std")) + (P 3(N "4") 3600 0 37(ExitRule "Std")) + (P 4(N "5") 4800 0 37(ExitRule "Std")) + (P 5(N "6") 6000 0 37(ExitRule "Std")) + (P 6(N "7") 7200 0 37(ExitRule "Std")) + (P 7(N "8") 8400 0 37(ExitRule "Std")) + (P 8(N "9") 9600 0 37(ExitRule "Std")) + (P 9(N "10") 10800 0 37(ExitRule "Std")) + (P 10(N "11") 12000 0 37(ExitRule "Std")) + (P 11(N "12") 13200 0 37(ExitRule "Std")) + (P 12(N "13") 14400 0 37(ExitRule "Std")) + (P 13(N "14") 15600 0 37(ExitRule "Std")) + (P 14(N "15") 16800 0 37(ExitRule "Std")) + (P 15(N "16") 18000 0 37(ExitRule "Std")) + (P 16(N "17") 19200 0 37(ExitRule "Std")) + (P 17(N "18") 20400 0 37(ExitRule "Std")) + (P 18(N "19") 21600 0 37(ExitRule "Std")) + (P 19(N "20") 22800 0 37(ExitRule "Std")) + (P 20(N "21") 24000 0 37(ExitRule "Std")) + (P 21(N "22") 25200 0 37(ExitRule "Std")) + (P 22(N "23") 26400 0 37(ExitRule "Std")) + (P 23(N "24") 27600 0 37(ExitRule "Std")) + (P 24(N "25") 28800 0 37(ExitRule "Std")) + (P 25(N "26") 30000 0 37(ExitRule "Std")) + (P 26(N "27") 31200 0 37(ExitRule "Std")) + (P 27(N "28") 32400 0 37(ExitRule "Std")) + (P 28(N "29") 33600 0 37(ExitRule "Std")) + (P 29(N "30") 34800 0 37(ExitRule "Std")) + (P 30(N "31") 36000 0 37(ExitRule "Std")) + (P 31(N "32") 37200 0 37(ExitRule "Std")) + (P 32(N "33") 38400 0 37(ExitRule "Std")) + (P 33(N "34") 39600 0 37(ExitRule "Std")) + (P 34(N "35") 40800 0 37(ExitRule "Std")) + (P 35(N "36") 42000 0 37(ExitRule "Std")) + (P 36(N "37") 43200 0 37(ExitRule "Std")) + (P 37(N "38") 44400 0 37(ExitRule "Std")) + (P 38(N "39") 45600 0 37(ExitRule "Std")) + (P 39(N "40") 46800 0 37(ExitRule "Std")) + (P 40(N "41") 48000 0 37(ExitRule "Std")) + (P 41(N "42") 49200 0 37(ExitRule "Std")) + (P 42(N "43") 50400 0 37(ExitRule "Std")) + (P 43(N "44") 51600 0 37(ExitRule "Std")) + (P 44(N "45") 52800 0 37(ExitRule "Std")) + (P 45(N "46") 54000 0 37(ExitRule "Std")) + (P 46(N "47") 55200 0 37(ExitRule "Std")) + (P 47(N "48") 56400 0 37(ExitRule "Std")) + (P 48(N "49") 57600 0 37(ExitRule "Std")) + (P 49(N "50") 58800 0 37(ExitRule "Std")) + (P 50(N "51") 60000 0 37(ExitRule "Std")) + (P 51(N "52") 61200 0 37(ExitRule "Std")) + (P 52(N "2") 1200 0 37(ExitRule "Std")) + (P 53(N "53") 66600 5400 38(ExitRule "Std")) + (P 54(N "54") 66600 6600 38(ExitRule "Std")) + (P 55(N "55") 66600 7800 38(ExitRule "Std")) + (P 56(N "56") 66600 9000 38(ExitRule "Std")) + (P 57(N "57") 66600 10200 38(ExitRule "Std")) + (P 58(N "58") 66600 11400 38(ExitRule "Std")) + (P 59(N "59") 66600 12600 38(ExitRule "Std")) + (P 60(N "60") 66600 13800 38(ExitRule "Std")) + (P 61(N "61") 66600 15000 38(ExitRule "Std")) + (P 62(N "62") 66600 16200 38(ExitRule "Std")) + (P 63(N "63") 66600 17400 38(ExitRule "Std")) + (P 64(N "64") 66600 18600 38(ExitRule "Std")) + (P 65(N "65") 66600 19800 38(ExitRule "Std")) + (P 66(N "66") 66600 21000 38(ExitRule "Std")) + (P 67(N "67") 66600 22200 38(ExitRule "Std")) + (P 68(N "68") 66600 23400 38(ExitRule "Std")) + (P 69(N "69") 66600 24600 38(ExitRule "Std")) + (P 70(N "70") 66600 25800 38(ExitRule "Std")) + (P 71(N "71") 66600 27000 38(ExitRule "Std")) + (P 72(N "72") 66600 28200 38(ExitRule "Std")) + (P 73(N "73") 66600 29400 38(ExitRule "Std")) + (P 74(N "74") 66600 30600 38(ExitRule "Std")) + (P 75(N "75") 66600 31800 38(ExitRule "Std")) + (P 76(N "76") 66600 33000 38(ExitRule "Std")) + (P 77(N "77") 66600 34200 38(ExitRule "Std")) + (P 78(N "78") 66600 35400 38(ExitRule "Std")) + (P 79(N "79") 66600 36600 38(ExitRule "Std")) + (P 80(N "80") 66600 37800 38(ExitRule "Std")) + (P 81(N "81") 66600 39000 38(ExitRule "Std")) + (P 82(N "82") 66600 40200 38(ExitRule "Std")) + (P 83(N "83") 66600 41400 38(ExitRule "Std")) + (P 84(N "84") 66600 42600 38(ExitRule "Std")) + (P 85(N "85") 66600 43800 38(ExitRule "Std")) + (P 86(N "86") 66600 45000 38(ExitRule "Std")) + (P 87(N "87") 66600 46200 38(ExitRule "Std")) + (P 88(N "88") 66600 47400 38(ExitRule "Std")) + (P 89(N "89") 66600 48600 38(ExitRule "Std")) + (P 90(N "90") 66600 49800 38(ExitRule "Std")) + (P 91(N "91") 66600 51000 38(ExitRule "Std")) + (P 92(N "92") 66600 52200 38(ExitRule "Std")) + (P 93(N "93") 66600 53400 38(ExitRule "Std")) + (P 94(N "94") 66600 54600 38(ExitRule "Std")) + (P 95(N "95") 66600 55800 38(ExitRule "Std")) + (P 96(N "96") 66600 57000 38(ExitRule "Std")) + (P 97(N "97") 66600 58200 38(ExitRule "Std")) + (P 98(N "98") 66600 59400 38(ExitRule "Std")) + (P 99(N "99") 66600 60600 38(ExitRule "Std")) + (P 100(N "100") 66600 61800 38(ExitRule "Std")) + (P 101(N "101") 66600 63000 38(ExitRule "Std")) + (P 102(N "102") 66600 64200 38(ExitRule "Std")) + (P 103(N "103") 66600 65400 38(ExitRule "Std")) + (P 104(N "104") 66600 66600 38(ExitRule "Std")) + (P 105(N "105") 61200 72000 37(ExitRule "Std")) + (P 106(N "106") 60000 72000 37(ExitRule "Std")) + (P 107(N "107") 58800 72000 37(ExitRule "Std")) + (P 108(N "108") 57600 72000 37(ExitRule "Std")) + (P 109(N "109") 56400 72000 37(ExitRule "Std")) + (P 110(N "110") 55200 72000 37(ExitRule "Std")) + (P 111(N "111") 54000 72000 37(ExitRule "Std")) + (P 112(N "112") 52800 72000 37(ExitRule "Std")) + (P 113(N "113") 51600 72000 37(ExitRule "Std")) + (P 114(N "114") 50400 72000 37(ExitRule "Std")) + (P 115(N "115") 49200 72000 37(ExitRule "Std")) + (P 116(N "116") 48000 72000 37(ExitRule "Std")) + (P 117(N "117") 46800 72000 37(ExitRule "Std")) + (P 118(N "118") 45600 72000 37(ExitRule "Std")) + (P 119(N "119") 44400 72000 37(ExitRule "Std")) + (P 120(N "120") 43200 72000 37(ExitRule "Std")) + (P 121(N "121") 42000 72000 37(ExitRule "Std")) + (P 122(N "122") 40800 72000 37(ExitRule "Std")) + (P 123(N "123") 39600 72000 37(ExitRule "Std")) + (P 124(N "124") 38400 72000 37(ExitRule "Std")) + (P 125(N "125") 37200 72000 37(ExitRule "Std")) + (P 126(N "126") 36000 72000 37(ExitRule "Std")) + (P 127(N "127") 34800 72000 37(ExitRule "Std")) + (P 128(N "128") 33600 72000 37(ExitRule "Std")) + (P 129(N "129") 32400 72000 37(ExitRule "Std")) + (P 130(N "130") 31200 72000 37(ExitRule "Std")) + (P 131(N "131") 30000 72000 37(ExitRule "Std")) + (P 132(N "132") 28800 72000 37(ExitRule "Std")) + (P 133(N "133") 27600 72000 37(ExitRule "Std")) + (P 134(N "134") 26400 72000 37(ExitRule "Std")) + (P 135(N "135") 25200 72000 37(ExitRule "Std")) + (P 136(N "136") 24000 72000 37(ExitRule "Std")) + (P 137(N "137") 22800 72000 37(ExitRule "Std")) + (P 138(N "138") 21600 72000 37(ExitRule "Std")) + (P 139(N "139") 20400 72000 37(ExitRule "Std")) + (P 140(N "140") 19200 72000 37(ExitRule "Std")) + (P 141(N "141") 18000 72000 37(ExitRule "Std")) + (P 142(N "142") 16800 72000 37(ExitRule "Std")) + (P 143(N "143") 15600 72000 37(ExitRule "Std")) + (P 144(N "144") 14400 72000 37(ExitRule "Std")) + (P 145(N "145") 13200 72000 37(ExitRule "Std")) + (P 146(N "146") 12000 72000 37(ExitRule "Std")) + (P 147(N "147") 10800 72000 37(ExitRule "Std")) + (P 148(N "148") 9600 72000 37(ExitRule "Std")) + (P 149(N "149") 8400 72000 37(ExitRule "Std")) + (P 150(N "150") 7200 72000 37(ExitRule "Std")) + (P 151(N "151") 6000 72000 37(ExitRule "Std")) + (P 152(N "152") 4800 72000 37(ExitRule "Std")) + (P 153(N "153") 3600 72000 37(ExitRule "Std")) + (P 154(N "154") 2400 72000 37(ExitRule "Std")) + (P 155(N "155") 1200 72000 37(ExitRule "Std")) + (P 156(N "156") 0 72000 37(ExitRule "Std")) + (P 157(N "157") -5400 66600 38(ExitRule "Std")) + (P 158(N "158") -5400 65400 38(ExitRule "Std")) + (P 159(N "159") -5400 64200 38(ExitRule "Std")) + (P 160(N "160") -5400 63000 38(ExitRule "Std")) + (P 161(N "161") -5400 61800 38(ExitRule "Std")) + (P 162(N "162") -5400 60600 38(ExitRule "Std")) + (P 163(N "163") -5400 59400 38(ExitRule "Std")) + (P 164(N "164") -5400 58200 38(ExitRule "Std")) + (P 165(N "165") -5400 57000 38(ExitRule "Std")) + (P 166(N "166") -5400 55800 38(ExitRule "Std")) + (P 167(N "167") -5400 54600 38(ExitRule "Std")) + (P 168(N "168") -5400 53400 38(ExitRule "Std")) + (P 169(N "169") -5400 52200 38(ExitRule "Std")) + (P 170(N "170") -5400 51000 38(ExitRule "Std")) + (P 171(N "171") -5400 49800 38(ExitRule "Std")) + (P 172(N "172") -5400 48600 38(ExitRule "Std")) + (P 173(N "173") -5400 47400 38(ExitRule "Std")) + (P 174(N "174") -5400 46200 38(ExitRule "Std")) + (P 175(N "175") -5400 45000 38(ExitRule "Std")) + (P 176(N "176") -5400 43800 38(ExitRule "Std")) + (P 177(N "177") -5400 42600 38(ExitRule "Std")) + (P 178(N "178") -5400 41400 38(ExitRule "Std")) + (P 179(N "179") -5400 40200 38(ExitRule "Std")) + (P 180(N "180") -5400 39000 38(ExitRule "Std")) + (P 181(N "181") -5400 37800 38(ExitRule "Std")) + (P 182(N "182") -5400 36600 38(ExitRule "Std")) + (P 183(N "183") -5400 35400 38(ExitRule "Std")) + (P 184(N "184") -5400 34200 38(ExitRule "Std")) + (P 185(N "185") -5400 33000 38(ExitRule "Std")) + (P 186(N "186") -5400 31800 38(ExitRule "Std")) + (P 187(N "187") -5400 30600 38(ExitRule "Std")) + (P 188(N "188") -5400 29400 38(ExitRule "Std")) + (P 189(N "189") -5400 28200 38(ExitRule "Std")) + (P 190(N "190") -5400 27000 38(ExitRule "Std")) + (P 191(N "191") -5400 25800 38(ExitRule "Std")) + (P 192(N "192") -5400 24600 38(ExitRule "Std")) + (P 193(N "193") -5400 23400 38(ExitRule "Std")) + (P 194(N "194") -5400 22200 38(ExitRule "Std")) + (P 195(N "195") -5400 21000 38(ExitRule "Std")) + (P 196(N "196") -5400 19800 38(ExitRule "Std")) + (P 197(N "197") -5400 18600 38(ExitRule "Std")) + (P 198(N "198") -5400 17400 38(ExitRule "Std")) + (P 199(N "199") -5400 16200 38(ExitRule "Std")) + (P 200(N "200") -5400 15000 38(ExitRule "Std")) + (P 201(N "201") -5400 13800 38(ExitRule "Std")) + (P 202(N "202") -5400 12600 38(ExitRule "Std")) + (P 203(N "203") -5400 11400 38(ExitRule "Std")) + (P 204(N "204") -5400 10200 38(ExitRule "Std")) + (P 205(N "205") -5400 9000 38(ExitRule "Std")) + (P 206(N "206") -5400 7800 38(ExitRule "Std")) + (P 207(N "207") -5400 6600 38(ExitRule "Std")) + (P 208(N "208") -5400 5400 38(ExitRule "Std")) + ) +(SYM 112(N "20dip300_DD36")(Uid 1366 9000 -27000 0 0) + (Derived 367) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") 0 42000 21(ExitRule "Std")) + (P 9(N "9") 0 48000 21(ExitRule "Std")) + (P 10(N "10") 0 54000 21(ExitRule "Std")) + (P 11(N "11") -18000 54000 21(ExitRule "Std")) + (P 12(N "12") -18000 48000 21(ExitRule "Std")) + (P 13(N "13") -18000 42000 21(ExitRule "Std")) + (P 14(N "14") -18000 36000 21(ExitRule "Std")) + (P 15(N "15") -18000 30000 21(ExitRule "Std")) + (P 16(N "16") -18000 24000 21(ExitRule "Std")) + (P 17(N "17") -18000 18000 21(ExitRule "Std")) + (P 18(N "18") -18000 12000 21(ExitRule "Std")) + (P 19(N "19") -18000 6000 21(ExitRule "Std")) + (P 20(N "20") -18000 0 21(ExitRule "Std")) + ) +(SYM 113(N "20DIP300_DD37")(Uid 1376 -9000 27000 0 0) + (Derived 368) + (P 1(N "1") 0 0 24(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + (P 3(N "3") 0 12000 19(ExitRule "Std")) + (P 4(N "4") 0 18000 19(ExitRule "Std")) + (P 5(N "5") 0 24000 19(ExitRule "Std")) + (P 6(N "6") 0 30000 19(ExitRule "Std")) + (P 7(N "7") 0 36000 19(ExitRule "Std")) + (P 8(N "8") 0 42000 19(ExitRule "Std")) + (P 9(N "9") 0 48000 19(ExitRule "Std")) + (P 10(N "10") 0 54000 19(ExitRule "Std")) + (P 11(N "11") -18000 54000 19(ExitRule "Std")) + (P 12(N "12") -18000 48000 19(ExitRule "Std")) + (P 13(N "13") -18000 42000 19(ExitRule "Std")) + (P 14(N "14") -18000 36000 19(ExitRule "Std")) + (P 15(N "15") -18000 30000 19(ExitRule "Std")) + (P 16(N "16") -18000 24000 19(ExitRule "Std")) + (P 17(N "17") -18000 18000 19(ExitRule "Std")) + (P 18(N "18") -18000 12000 19(ExitRule "Std")) + (P 19(N "19") -18000 6000 19(ExitRule "Std")) + (P 20(N "20") -18000 0 19(ExitRule "Std")) + ) +(SYM 114(N "RC02_R108")(Uid 1385 0 -3000 0 0)(Derived 369) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 115(N "RC02_R109")(Uid 1387 0 3000 0 0)(Derived 370) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 116(N "RC02_R110")(Uid 1389 0 3000 0 0)(Derived 371) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 117(N "RC02_R111")(Uid 1391 0 -3000 0 0)(Derived 372) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 118(N "RC02_C13")(Uid 1394 0 -3000 0 0)(Derived 373) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 119(N "RC02_R112")(Uid 1397 3000 0 0 0)(Derived 374) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 120(N "14dip300_DD38")(Uid 1399 -18000 -9000 0 0) + (Derived 375) + (P 1(N "1") 0 0 27(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + (P 3(N "3") 0 -12000 28(ExitRule "Std")) + (P 4(N "4") 0 -18000 28(ExitRule "Std")) + (P 5(N "5") 0 -24000 28(ExitRule "Std")) + (P 6(N "6") 0 -30000 28(ExitRule "Std")) + (P 7(N "7") 0 -36000 28(ExitRule "Std")) + (P 8(N "8") 18000 -36000 28(ExitRule "Std")) + (P 9(N "9") 18000 -30000 28(ExitRule "Std")) + (P 10(N "10") 18000 -24000 28(ExitRule "Std")) + (P 11(N "11") 18000 -18000 28(ExitRule "Std")) + (P 12(N "12") 18000 -12000 28(ExitRule "Std")) + (P 13(N "13") 18000 -6000 28(ExitRule "Std")) + (P 14(N "14") 18000 0 28(ExitRule "Std")) + ) +(SYM 121(N "RC02_R113")(Uid 1410 -3000 0 0 0)(Derived 376) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 122(N "RC02_R114")(Uid 1414 -3000 0 0 0)(Derived 377) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 123(N "RC02_R115")(Uid 1417 3000 0 0 0)(Derived 378) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 124(N "RC02_R116")(Uid 1420 3000 0 0 0)(Derived 379) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 125(N "RC02_R117")(Uid 1422 -3000 0 0 0)(Derived 380) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 126(N "RC02_R118")(Uid 1424 -3000 0 0 0)(Derived 381) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 127(N "RC02_R119")(Uid 1426 -3000 0 0 0)(Derived 382) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 128(N "RC02_R120")(Uid 1428 0 3000 0 0)(Derived 383) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 129(N "RC02_R121")(Uid 1430 0 3000 0 0)(Derived 384) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 130(N "RC02_R122")(Uid 1432 0 3000 0 0)(Derived 385) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 131(N "RC02_R123")(Uid 1434 0 3000 0 0)(Derived 386) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 132(N "RC02_R124")(Uid 1436 0 -3000 0 0)(Derived 387) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 133(N "RC02_R123-2")(Uid 1438 0 3000 0 0)(Derived 388) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 134(N "RC02_R124-2")(Uid 1441 0 3000 0 0)(Derived 389) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 135(N "RC02_R125")(Uid 1443 0 3000 0 0)(Derived 390) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 136(N "RC02_R126")(Uid 1445 0 3000 0 0)(Derived 391) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 137(N "RC02_R127")(Uid 1447 3000 0 0 0)(Derived 392) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 138(N "RC02_R128")(Uid 1449 3000 0 0 0)(Derived 393) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 139(N "RC02_R129")(Uid 1451 0 3000 0 0)(Derived 394) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 140(N "14DIP300_DD39")(Uid 1453 9000 -18000 0 0) + (Derived 395) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") -18000 36000 21(ExitRule "Std")) + (P 9(N "9") -18000 30000 21(ExitRule "Std")) + (P 10(N "10") -18000 24000 21(ExitRule "Std")) + (P 11(N "11") -18000 18000 21(ExitRule "Std")) + (P 12(N "12") -18000 12000 21(ExitRule "Std")) + (P 13(N "13") -18000 6000 21(ExitRule "Std")) + (P 14(N "14") -18000 0 21(ExitRule "Std")) + ) +(SYM 141(N "14DIP300_DD40")(Uid 1458 9000 -18000 0 0) + (Derived 396) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") -18000 36000 21(ExitRule "Std")) + (P 9(N "9") -18000 30000 21(ExitRule "Std")) + (P 10(N "10") -18000 24000 21(ExitRule "Std")) + (P 11(N "11") -18000 18000 21(ExitRule "Std")) + (P 12(N "12") -18000 12000 21(ExitRule "Std")) + (P 13(N "13") -18000 6000 21(ExitRule "Std")) + (P 14(N "14") -18000 0 21(ExitRule "Std")) + ) +(SYM 142(N "RC02_R130")(Uid 1461 3000 0 0 0)(Derived 397) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 143(N "VT1_VT7")(Uid 1464 0 -6000 0 0)(Derived 398) + (P 1(N "1") 0 0 32(ExitRule "Std")) + (P 2(N "2") 0 6000 32(ExitRule "Std")) + (P 3(N "3") 0 12000 32(ExitRule "Std")) + ) +(SYM 144(N "RC02_R131")(Uid 1468 0 -3000 0 0)(Derived 399) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 145(N "RC02_R132")(Uid 1471 0 3000 0 0)(Derived 400) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 146(N "RC02_R133")(Uid 1473 0 -3000 0 0)(Derived 401) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 147(N "CAP2_C14")(Uid 1475 -6000 0 0 0)(Derived 402) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -12000 28(ExitRule "Std")) + ) +(SYM 148(N "CAP2_C15")(Uid 1478 -6000 0 0 0)(Derived 403) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -12000 28(ExitRule "Std")) + ) +(SYM 149(N "CAP3_C16")(Uid 1480 0 -3000 0 0)(Derived 404) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 150(N "RC02_R134")(Uid 1483 0 -3000 0 0)(Derived 405) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 151(N "RC02_R135")(Uid 1485 0 3000 0 0)(Derived 406) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 152(N "RC02_R136")(Uid 1487 0 -3000 0 0)(Derived 407) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 153(N "RC02_R137")(Uid 1489 0 -3000 0 0)(Derived 408) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 154(N "RC02_R138")(Uid 1491 0 3000 0 0)(Derived 409) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 155(N "RC02_R139")(Uid 1493 0 3000 0 0)(Derived 410) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 156(N "RC02_R140")(Uid 1495 0 3000 0 0)(Derived 411) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 157(N "RC02_R141")(Uid 1497 0 3000 0 0)(Derived 412) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 158(N "VD2_VD3")(Uid 1499 -6000 0 0 0)(Derived 413) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 12000 17(ExitRule "Std")) + ) +(SYM 159(N "VD2_VD4")(Uid 1502 0 -6000 0 0)(Derived 414) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 -12000 19(ExitRule "Std")) + ) +(SYM 160(N "VD2_VD5")(Uid 1504 6000 0 0 0)(Derived 415) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 12000 28(ExitRule "Std")) + ) +(SYM 161(N "VD2_VD6")(Uid 1506 -6000 0 0 0)(Derived 416) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 12000 17(ExitRule "Std")) + ) +(SYM 162(N "RC02_R142")(Uid 1509 3000 0 0 0)(Derived 417) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 163(N "RC02_XR16")(Uid 1512 3000 0 0 0)(Derived 418) + (P 1(N "1") 0 0 39(ExitRule "Std")) + (P 2(N "2") 0 -6000 39(ExitRule "Std")) + ) +(SYM 164(N "RC02_R143")(Uid 1515 0 -3000 0 0)(Derived 419) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 165(N "RC02_XR17")(Uid 1518 3000 0 0 0)(Derived 420) + (P 1(N "1") 0 0 39(ExitRule "Std")) + (P 2(N "2") 0 -6000 39(ExitRule "Std")) + ) +(SYM 166(N "HD2_XR18")(Uid 1521 3000 0 0 0)(Derived 421) + (P 1(N "1") 0 0 40(ExitRule "Std")) + (P 2(N "2") 6000 0 41(ExitRule "Std")) + ) +(SYM 167(N "HD2_XR18-2")(Uid 1526 -3000 0 0 0)(Derived 422) + (P 1(N "1") 0 0 42(ExitRule "Std")) + (P 2(N "2") 6000 0 43(ExitRule "Std")) + ) +(SYM 168(N "VT1_VT8")(Uid 1529 6000 0 0 0)(Derived 423) + (P 1(N "1") 0 0 34(ExitRule "Std")) + (P 2(N "2") 0 -6000 34(ExitRule "Std")) + (P 3(N "3") 0 -12000 34(ExitRule "Std")) + ) +(SYM 169(N "VT1_VT9")(Uid 1532 6000 0 0 0)(Derived 424) + (P 1(N "1") 0 0 34(ExitRule "Std")) + (P 2(N "2") 0 -6000 34(ExitRule "Std")) + (P 3(N "3") 0 -12000 34(ExitRule "Std")) + ) +(SYM 170(N "CAP3_C19")(Uid 1534 0 3000 0 0)(Derived 425) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 171(N "CAP3_C20")(Uid 1536 0 -3000 0 0)(Derived 426) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 172(N "CAP3_C21")(Uid 1538 3000 0 0 0)(Derived 427) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 173(N "CAP3_C22")(Uid 1540 3000 0 0 0)(Derived 428) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 174(N "CAP3_C23")(Uid 1542 3000 0 0 0)(Derived 429) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 175(N "CAP3_C24")(Uid 1544 0 -3000 0 0)(Derived 430) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 176(N "CAP3_C25")(Uid 1546 3000 0 0 0)(Derived 431) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 177(N "CAP3_C26")(Uid 1548 -3000 0 0 0)(Derived 432) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 178(N "CAP3_C27")(Uid 1550 3000 0 0 0)(Derived 433) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 179(N "CAP3_C28")(Uid 1552 0 3000 0 0)(Derived 434) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 180(N "CAP3_C29")(Uid 1554 3000 0 0 0)(Derived 435) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 181(N "CAP3_C30")(Uid 1556 -3000 0 0 0)(Derived 436) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 182(N "CAP2_C31")(Uid 1558 -6000 0 0 0)(Derived 437) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -12000 28(ExitRule "Std")) + ) +(SYM 183(N "CAP2_C32")(Uid 1560 -6000 0 0 0)(Derived 438) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -12000 28(ExitRule "Std")) + ) +(SYM 184(N "CAP2_C33")(Uid 1562 -6000 0 0 0)(Derived 439) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -12000 28(ExitRule "Std")) + ) +(SYM 185(N "CAP2_C34")(Uid 1564 -6000 0 0 0)(Derived 440) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -12000 28(ExitRule "Std")) + ) +(SYM 186(N "CAP3_C35")(Uid 1566 3000 0 0 0)(Derived 441) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 187(N "CAP3_C36")(Uid 1569 -3000 0 0 0)(Derived 442) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 188(N "IND_L1")(Uid 1572 12000 0 0 0)(Derived 443) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -24000 17(ExitRule "Std")) + ) +(SYM 189(N "RC02_R144")(Uid 1575 3000 0 0 0)(Derived 444) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 190(N "34DIP100_XR6")(Uid 1577 3000 -48000 0 0)(Derived 445) + (P 1(N "1") 0 0 42(ExitRule "Std")) + (P 2(N "2") -6000 0 43(ExitRule "Std")) + (P 3(N "3") 0 6000 43(ExitRule "Std")) + (P 4(N "4") -6000 6000 43(ExitRule "Std")) + (P 5(N "5") 0 12000 43(ExitRule "Std")) + (P 6(N "6") -6000 12000 43(ExitRule "Std")) + (P 7(N "7") 0 18000 43(ExitRule "Std")) + (P 8(N "8") -6000 18000 43(ExitRule "Std")) + (P 9(N "9") 0 24000 43(ExitRule "Std")) + (P 10(N "10") -6000 24000 43(ExitRule "Std")) + (P 11(N "11") 0 30000 43(ExitRule "Std")) + (P 12(N "12") -6000 30000 43(ExitRule "Std")) + (P 13(N "13") 0 36000 43(ExitRule "Std")) + (P 14(N "14") -6000 36000 43(ExitRule "Std")) + (P 15(N "15") 0 42000 43(ExitRule "Std")) + (P 16(N "16") -6000 42000 43(ExitRule "Std")) + (P 17(N "17") 0 48000 43(ExitRule "Std")) + (P 18(N "18") -6000 48000 43(ExitRule "Std")) + (P 19(N "19") 0 54000 43(ExitRule "Std")) + (P 20(N "20") -6000 54000 43(ExitRule "Std")) + (P 21(N "21") 0 60000 43(ExitRule "Std")) + (P 22(N "22") -6000 60000 43(ExitRule "Std")) + (P 23(N "23") 0 66000 43(ExitRule "Std")) + (P 24(N "24") -6000 66000 43(ExitRule "Std")) + (P 25(N "25") 0 72000 43(ExitRule "Std")) + (P 26(N "26") -6000 72000 43(ExitRule "Std")) + (P 27(N "27") 0 78000 43(ExitRule "Std")) + (P 28(N "28") -6000 78000 43(ExitRule "Std")) + (P 29(N "29") 0 84000 43(ExitRule "Std")) + (P 30(N "30") -6000 84000 43(ExitRule "Std")) + (P 31(N "31") 0 90000 43(ExitRule "Std")) + (P 32(N "32") -6000 90000 43(ExitRule "Std")) + (P 33(N "33") 0 96000 43(ExitRule "Std")) + (P 34(N "34") -6000 96000 43(ExitRule "Std")) + ) +(SYM 191(N "10DIP100_XR7")(Uid 1585 -3000 12000 0 0)(Derived 446) + (P 1(N "1") 0 0 41(ExitRule "Std")) + (P 2(N "2") -6000 0 41(ExitRule "Std")) + (P 3(N "3") 0 6000 41(ExitRule "Std")) + (P 4(N "4") -6000 6000 41(ExitRule "Std")) + (P 5(N "5") 0 12000 41(ExitRule "Std")) + (P 6(N "6") -6000 12000 41(ExitRule "Std")) + (P 7(N "7") 0 18000 41(ExitRule "Std")) + (P 8(N "8") -6000 18000 41(ExitRule "Std")) + (P 9(N "9") 0 24000 41(ExitRule "Std")) + (P 10(N "10") -6000 24000 41(ExitRule "Std")) + ) +(SYM 192(N "16dip100_XR8")(Uid 1588 3000 -21000 0 0)(Derived 447) + (P 1(N "1") 0 0 43(ExitRule "Std")) + (P 2(N "2") -6000 0 43(ExitRule "Std")) + (P 3(N "3") 0 6000 43(ExitRule "Std")) + (P 4(N "4") -6000 6000 43(ExitRule "Std")) + (P 5(N "5") 0 12000 43(ExitRule "Std")) + (P 6(N "6") -6000 12000 43(ExitRule "Std")) + (P 7(N "7") 0 18000 43(ExitRule "Std")) + (P 8(N "8") -6000 18000 43(ExitRule "Std")) + (P 9(N "9") 0 24000 43(ExitRule "Std")) + (P 10(N "10") -6000 24000 43(ExitRule "Std")) + (P 11(N "11") 0 30000 43(ExitRule "Std")) + (P 12(N "12") -6000 30000 43(ExitRule "Std")) + (P 13(N "13") 0 36000 43(ExitRule "Std")) + (P 14(N "14") -6000 36000 43(ExitRule "Std")) + (P 15(N "15") 0 42000 43(ExitRule "Std")) + (P 16(N "16") -6000 42000 43(ExitRule "Std")) + ) +(SYM 193(N "10DIP100_XR9")(Uid 1596 -3000 12000 0 0)(Derived 448) + (P 1(N "1") 0 0 41(ExitRule "Std")) + (P 2(N "2") -6000 0 41(ExitRule "Std")) + (P 3(N "3") 0 6000 41(ExitRule "Std")) + (P 4(N "4") -6000 6000 41(ExitRule "Std")) + (P 5(N "5") 0 12000 41(ExitRule "Std")) + (P 6(N "6") -6000 12000 41(ExitRule "Std")) + (P 7(N "7") 0 18000 41(ExitRule "Std")) + (P 8(N "8") -6000 18000 41(ExitRule "Std")) + (P 9(N "9") 0 24000 41(ExitRule "Std")) + (P 10(N "10") -6000 24000 41(ExitRule "Std")) + ) +(SYM 194(N "26DIP100_XR10")(Uid 1599 3000 -36000 0 0) + (Derived 449) + (P 1(N "1") 0 0 43(ExitRule "Std")) + (P 2(N "2") -6000 0 43(ExitRule "Std")) + (P 3(N "3") 0 6000 43(ExitRule "Std")) + (P 4(N "4") -6000 6000 43(ExitRule "Std")) + (P 5(N "5") 0 12000 43(ExitRule "Std")) + (P 6(N "6") -6000 12000 43(ExitRule "Std")) + (P 7(N "7") 0 18000 43(ExitRule "Std")) + (P 8(N "8") -6000 18000 43(ExitRule "Std")) + (P 9(N "9") 0 24000 43(ExitRule "Std")) + (P 10(N "10") -6000 24000 43(ExitRule "Std")) + (P 11(N "11") 0 30000 43(ExitRule "Std")) + (P 12(N "12") -6000 30000 43(ExitRule "Std")) + (P 13(N "13") 0 36000 43(ExitRule "Std")) + (P 14(N "14") -6000 36000 43(ExitRule "Std")) + (P 15(N "15") 0 42000 43(ExitRule "Std")) + (P 16(N "16") -6000 42000 43(ExitRule "Std")) + (P 17(N "17") 0 48000 43(ExitRule "Std")) + (P 18(N "18") -6000 48000 43(ExitRule "Std")) + (P 19(N "19") 0 54000 43(ExitRule "Std")) + (P 20(N "20") -6000 54000 43(ExitRule "Std")) + (P 21(N "21") 0 60000 43(ExitRule "Std")) + (P 22(N "22") -6000 60000 43(ExitRule "Std")) + (P 23(N "23") 0 66000 43(ExitRule "Std")) + (P 24(N "24") -6000 66000 43(ExitRule "Std")) + (P 25(N "25") 0 72000 43(ExitRule "Std")) + (P 26(N "26") -6000 72000 43(ExitRule "Std")) + ) +(SYM 195(N "34DIP100_XR11")(Uid 1611 3000 -48000 0 0) + (Derived 450) + (P 1(N "1") 0 0 43(ExitRule "Std")) + (P 2(N "2") -6000 0 43(ExitRule "Std")) + (P 3(N "3") 0 6000 43(ExitRule "Std")) + (P 4(N "4") -6000 6000 43(ExitRule "Std")) + (P 5(N "5") 0 12000 43(ExitRule "Std")) + (P 6(N "6") -6000 12000 43(ExitRule "Std")) + (P 7(N "7") 0 18000 43(ExitRule "Std")) + (P 8(N "8") -6000 18000 43(ExitRule "Std")) + (P 9(N "9") 0 24000 43(ExitRule "Std")) + (P 10(N "10") -6000 24000 43(ExitRule "Std")) + (P 11(N "11") 0 30000 43(ExitRule "Std")) + (P 12(N "12") -6000 30000 43(ExitRule "Std")) + (P 13(N "13") 0 36000 43(ExitRule "Std")) + (P 14(N "14") -6000 36000 43(ExitRule "Std")) + (P 15(N "15") 0 42000 43(ExitRule "Std")) + (P 16(N "16") -6000 42000 43(ExitRule "Std")) + (P 17(N "17") 0 48000 43(ExitRule "Std")) + (P 18(N "18") -6000 48000 43(ExitRule "Std")) + (P 19(N "19") 0 54000 43(ExitRule "Std")) + (P 20(N "20") -6000 54000 43(ExitRule "Std")) + (P 21(N "21") 0 60000 43(ExitRule "Std")) + (P 22(N "22") -6000 60000 43(ExitRule "Std")) + (P 23(N "23") 0 66000 43(ExitRule "Std")) + (P 24(N "24") -6000 66000 43(ExitRule "Std")) + (P 25(N "25") 0 72000 43(ExitRule "Std")) + (P 26(N "26") -6000 72000 43(ExitRule "Std")) + (P 27(N "27") 0 78000 43(ExitRule "Std")) + (P 28(N "28") -6000 78000 43(ExitRule "Std")) + (P 29(N "29") 0 84000 43(ExitRule "Std")) + (P 30(N "30") -6000 84000 43(ExitRule "Std")) + (P 31(N "31") 0 90000 43(ExitRule "Std")) + (P 32(N "32") -6000 90000 43(ExitRule "Std")) + (P 33(N "33") 0 96000 43(ExitRule "Std")) + (P 34(N "34") -6000 96000 43(ExitRule "Std")) + ) +(SYM 196(N "40DIP100_XR12")(Uid 1617 57000 3000 0 0)(Derived 451) + (P 1(N "1") 0 0 39(ExitRule "Std")) + (P 2(N "2") 6000 0 39(ExitRule "Std")) + (P 3(N "3") 0 -6000 39(ExitRule "Std")) + (P 4(N "4") 6000 -6000 39(ExitRule "Std")) + (P 5(N "5") 0 -12000 39(ExitRule "Std")) + (P 6(N "6") 6000 -12000 39(ExitRule "Std")) + (P 7(N "7") 0 -18000 39(ExitRule "Std")) + (P 8(N "8") 6000 -18000 39(ExitRule "Std")) + (P 9(N "9") 0 -24000 39(ExitRule "Std")) + (P 10(N "10") 6000 -24000 39(ExitRule "Std")) + (P 11(N "11") 0 -30000 39(ExitRule "Std")) + (P 12(N "12") 6000 -30000 39(ExitRule "Std")) + (P 13(N "13") 0 -36000 39(ExitRule "Std")) + (P 14(N "14") 6000 -36000 39(ExitRule "Std")) + (P 15(N "15") 0 -42000 39(ExitRule "Std")) + (P 16(N "16") 6000 -42000 39(ExitRule "Std")) + (P 17(N "17") 0 -48000 39(ExitRule "Std")) + (P 18(N "18") 6000 -48000 39(ExitRule "Std")) + (P 19(N "19") 0 -54000 39(ExitRule "Std")) + (P 20(N "20") 6000 -54000 39(ExitRule "Std")) + (P 21(N "21") 0 -60000 39(ExitRule "Std")) + (P 22(N "22") 6000 -60000 39(ExitRule "Std")) + (P 23(N "23") 0 -66000 39(ExitRule "Std")) + (P 24(N "24") 6000 -66000 39(ExitRule "Std")) + (P 25(N "25") 0 -72000 39(ExitRule "Std")) + (P 26(N "26") 6000 -72000 39(ExitRule "Std")) + (P 27(N "27") 0 -78000 39(ExitRule "Std")) + (P 28(N "28") 6000 -78000 39(ExitRule "Std")) + (P 29(N "29") 0 -84000 39(ExitRule "Std")) + (P 30(N "30") 6000 -84000 39(ExitRule "Std")) + (P 31(N "31") 0 -90000 39(ExitRule "Std")) + (P 32(N "32") 6000 -90000 39(ExitRule "Std")) + (P 33(N "33") 0 -96000 39(ExitRule "Std")) + (P 34(N "34") 6000 -96000 39(ExitRule "Std")) + (P 35(N "35") 0 -102000 39(ExitRule "Std")) + (P 36(N "36") 6000 -102000 39(ExitRule "Std")) + (P 37(N "37") 0 -108000 39(ExitRule "Std")) + (P 38(N "38") 6000 -108000 39(ExitRule "Std")) + (P 39(N "39") 0 -114000 39(ExitRule "Std")) + (P 40(N "40") 6000 -114000 39(ExitRule "Std")) + ) +(SYM 197(N "CON31X2_XR13")(Uid 1630 -6000 -90000 0 0) + (Derived 452) + (P 1(N "A1") 0 0 43(ExitRule "Std")) + (P 2(N "A2") 0 6000 43(ExitRule "Std")) + (P 3(N "A3") 0 12000 43(ExitRule "Std")) + (P 4(N "A4") 0 18000 43(ExitRule "Std")) + (P 5(N "A5") 0 24000 43(ExitRule "Std")) + (P 6(N "A6") 0 30000 43(ExitRule "Std")) + (P 7(N "A7") 0 36000 43(ExitRule "Std")) + (P 8(N "A8") 0 42000 43(ExitRule "Std")) + (P 9(N "A9") 0 48000 43(ExitRule "Std")) + (P 10(N "A10") 0 54000 43(ExitRule "Std")) + (P 11(N "A11") 0 60000 43(ExitRule "Std")) + (P 12(N "A12") 0 66000 43(ExitRule "Std")) + (P 13(N "A13") 0 72000 43(ExitRule "Std")) + (P 14(N "A14") 0 78000 43(ExitRule "Std")) + (P 15(N "A15") 0 84000 43(ExitRule "Std")) + (P 16(N "A16") 0 90000 43(ExitRule "Std")) + (P 17(N "A17") 0 96000 43(ExitRule "Std")) + (P 18(N "A18") 0 102000 43(ExitRule "Std")) + (P 19(N "A19") 0 108000 43(ExitRule "Std")) + (P 20(N "A20") 0 114000 43(ExitRule "Std")) + (P 21(N "A21") 0 120000 43(ExitRule "Std")) + (P 22(N "A22") 0 126000 43(ExitRule "Std")) + (P 23(N "A23") 0 132000 43(ExitRule "Std")) + (P 24(N "A24") 0 138000 43(ExitRule "Std")) + (P 25(N "A25") 0 144000 43(ExitRule "Std")) + (P 26(N "A26") 0 150000 43(ExitRule "Std")) + (P 27(N "A27") 0 156000 43(ExitRule "Std")) + (P 28(N "A28") 0 162000 43(ExitRule "Std")) + (P 29(N "A29") 0 168000 43(ExitRule "Std")) + (P 30(N "A30") 0 174000 43(ExitRule "Std")) + (P 31(N "A31") 0 180000 43(ExitRule "Std")) + (P 32(N "B1") 12000 0 43(ExitRule "Std")) + (P 33(N "B2") 12000 6000 43(ExitRule "Std")) + (P 34(N "B3") 12000 12000 43(ExitRule "Std")) + (P 35(N "B4") 12000 18000 43(ExitRule "Std")) + (P 36(N "B5") 12000 24000 43(ExitRule "Std")) + (P 37(N "B6") 12000 30000 43(ExitRule "Std")) + (P 38(N "B7") 12000 36000 43(ExitRule "Std")) + (P 39(N "B8") 12000 42000 43(ExitRule "Std")) + (P 40(N "B9") 12000 48000 43(ExitRule "Std")) + (P 41(N "B10") 12000 54000 43(ExitRule "Std")) + (P 42(N "B11") 12000 60000 43(ExitRule "Std")) + (P 43(N "B12") 12000 66000 43(ExitRule "Std")) + (P 44(N "B13") 12000 72000 43(ExitRule "Std")) + (P 45(N "B14") 12000 78000 43(ExitRule "Std")) + (P 46(N "B15") 12000 84000 43(ExitRule "Std")) + (P 47(N "B16") 12000 90000 43(ExitRule "Std")) + (P 48(N "B17") 12000 96000 43(ExitRule "Std")) + (P 49(N "B18") 12000 102000 43(ExitRule "Std")) + (P 50(N "B19") 12000 108000 43(ExitRule "Std")) + (P 51(N "B20") 12000 114000 43(ExitRule "Std")) + (P 52(N "B21") 12000 120000 43(ExitRule "Std")) + (P 53(N "B22") 12000 126000 43(ExitRule "Std")) + (P 54(N "B23") 12000 132000 43(ExitRule "Std")) + (P 55(N "B24") 12000 138000 43(ExitRule "Std")) + (P 56(N "B25") 12000 144000 43(ExitRule "Std")) + (P 57(N "B26") 12000 150000 43(ExitRule "Std")) + (P 58(N "B27") 12000 156000 43(ExitRule "Std")) + (P 59(N "B28") 12000 162000 43(ExitRule "Std")) + (P 60(N "B29") 12000 168000 43(ExitRule "Std")) + (P 61(N "B30") 12000 174000 43(ExitRule "Std")) + (P 62(N "B31") 12000 180000 43(ExitRule "Std")) + ) +(SYM 198(N "CON31X2_XR14")(Uid 1700 -6000 -90000 0 0) + (Derived 453) + (P 1(N "A1") 0 0 43(ExitRule "Std")) + (P 2(N "A2") 0 6000 43(ExitRule "Std")) + (P 3(N "A3") 0 12000 43(ExitRule "Std")) + (P 4(N "A4") 0 18000 43(ExitRule "Std")) + (P 5(N "A5") 0 24000 43(ExitRule "Std")) + (P 6(N "A6") 0 30000 43(ExitRule "Std")) + (P 7(N "A7") 0 36000 43(ExitRule "Std")) + (P 8(N "A8") 0 42000 43(ExitRule "Std")) + (P 9(N "A9") 0 48000 43(ExitRule "Std")) + (P 10(N "A10") 0 54000 43(ExitRule "Std")) + (P 11(N "A11") 0 60000 43(ExitRule "Std")) + (P 12(N "A12") 0 66000 43(ExitRule "Std")) + (P 13(N "A13") 0 72000 43(ExitRule "Std")) + (P 14(N "A14") 0 78000 43(ExitRule "Std")) + (P 15(N "A15") 0 84000 43(ExitRule "Std")) + (P 16(N "A16") 0 90000 43(ExitRule "Std")) + (P 17(N "A17") 0 96000 43(ExitRule "Std")) + (P 18(N "A18") 0 102000 43(ExitRule "Std")) + (P 19(N "A19") 0 108000 43(ExitRule "Std")) + (P 20(N "A20") 0 114000 43(ExitRule "Std")) + (P 21(N "A21") 0 120000 43(ExitRule "Std")) + (P 22(N "A22") 0 126000 43(ExitRule "Std")) + (P 23(N "A23") 0 132000 43(ExitRule "Std")) + (P 24(N "A24") 0 138000 43(ExitRule "Std")) + (P 25(N "A25") 0 144000 43(ExitRule "Std")) + (P 26(N "A26") 0 150000 43(ExitRule "Std")) + (P 27(N "A27") 0 156000 43(ExitRule "Std")) + (P 28(N "A28") 0 162000 43(ExitRule "Std")) + (P 29(N "A29") 0 168000 43(ExitRule "Std")) + (P 30(N "A30") 0 174000 43(ExitRule "Std")) + (P 31(N "A31") 0 180000 43(ExitRule "Std")) + (P 32(N "B1") 12000 0 43(ExitRule "Std")) + (P 33(N "B2") 12000 6000 43(ExitRule "Std")) + (P 34(N "B3") 12000 12000 43(ExitRule "Std")) + (P 35(N "B4") 12000 18000 43(ExitRule "Std")) + (P 36(N "B5") 12000 24000 43(ExitRule "Std")) + (P 37(N "B6") 12000 30000 43(ExitRule "Std")) + (P 38(N "B7") 12000 36000 43(ExitRule "Std")) + (P 39(N "B8") 12000 42000 43(ExitRule "Std")) + (P 40(N "B9") 12000 48000 43(ExitRule "Std")) + (P 41(N "B10") 12000 54000 43(ExitRule "Std")) + (P 42(N "B11") 12000 60000 43(ExitRule "Std")) + (P 43(N "B12") 12000 66000 43(ExitRule "Std")) + (P 44(N "B13") 12000 72000 43(ExitRule "Std")) + (P 45(N "B14") 12000 78000 43(ExitRule "Std")) + (P 46(N "B15") 12000 84000 43(ExitRule "Std")) + (P 47(N "B16") 12000 90000 43(ExitRule "Std")) + (P 48(N "B17") 12000 96000 43(ExitRule "Std")) + (P 49(N "B18") 12000 102000 43(ExitRule "Std")) + (P 50(N "B19") 12000 108000 43(ExitRule "Std")) + (P 51(N "B20") 12000 114000 43(ExitRule "Std")) + (P 52(N "B21") 12000 120000 43(ExitRule "Std")) + (P 53(N "B22") 12000 126000 43(ExitRule "Std")) + (P 54(N "B23") 12000 132000 43(ExitRule "Std")) + (P 55(N "B24") 12000 138000 43(ExitRule "Std")) + (P 56(N "B25") 12000 144000 43(ExitRule "Std")) + (P 57(N "B26") 12000 150000 43(ExitRule "Std")) + (P 58(N "B27") 12000 156000 43(ExitRule "Std")) + (P 59(N "B28") 12000 162000 43(ExitRule "Std")) + (P 60(N "B29") 12000 168000 43(ExitRule "Std")) + (P 61(N "B30") 12000 174000 43(ExitRule "Std")) + (P 62(N "B31") 12000 180000 43(ExitRule "Std")) + ) +(SYM 199(N "14DIP300_DD41")(Uid 1703 18000 9000 0 0)(Derived 454) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 18000 -36000 17(ExitRule "Std")) + (P 9(N "9") 18000 -30000 17(ExitRule "Std")) + (P 10(N "10") 18000 -24000 17(ExitRule "Std")) + (P 11(N "11") 18000 -18000 17(ExitRule "Std")) + (P 12(N "12") 18000 -12000 17(ExitRule "Std")) + (P 13(N "13") 18000 -6000 17(ExitRule "Std")) + (P 14(N "14") 18000 0 17(ExitRule "Std")) + ) +(SYM 200(N "RC02_R145")(Uid 1705 3000 0 0 0)(Derived 455) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 201(N "CAP2_C37")(Uid 1707 0 -6000 0 0)(Derived 456) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 12000 21(ExitRule "Std")) + ) +(SYM 202(N "RC02_R146")(Uid 1709 3000 0 0 0)(Derived 457) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 203(N "16DIP300_DD42")(Uid 1711 9000 -21000 0 0) + (Derived 458) + (P 1(N "1") 0 0 20(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + (P 3(N "3") 0 12000 21(ExitRule "Std")) + (P 4(N "4") 0 18000 21(ExitRule "Std")) + (P 5(N "5") 0 24000 21(ExitRule "Std")) + (P 6(N "6") 0 30000 21(ExitRule "Std")) + (P 7(N "7") 0 36000 21(ExitRule "Std")) + (P 8(N "8") 0 42000 21(ExitRule "Std")) + (P 9(N "9") -18000 42000 21(ExitRule "Std")) + (P 10(N "10") -18000 36000 21(ExitRule "Std")) + (P 11(N "11") -18000 30000 21(ExitRule "Std")) + (P 12(N "12") -18000 24000 21(ExitRule "Std")) + (P 13(N "13") -18000 18000 21(ExitRule "Std")) + (P 14(N "14") -18000 12000 21(ExitRule "Std")) + (P 15(N "15") -18000 6000 21(ExitRule "Std")) + (P 16(N "16") -18000 0 21(ExitRule "Std")) + ) +(SYM 204(N "RC02_R153")(Uid 1713 0 -3000 0 0)(Derived 459) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 205(N "RC02_R154")(Uid 1715 0 -3000 0 0)(Derived 460) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 206(N "RC02_R155")(Uid 1717 0 -3000 0 0)(Derived 461) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 207(N "RC02_R156")(Uid 1719 0 -3000 0 0)(Derived 462) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 208(N "RC02_R157")(Uid 1721 0 -3000 0 0)(Derived 463) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 209(N "RC02_R158")(Uid 1723 0 -3000 0 0)(Derived 464) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 210(N "RC02_R159")(Uid 1725 3000 0 0 0)(Derived 465) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 211(N "RC02_R160")(Uid 1727 3000 0 0 0)(Derived 466) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 212(N "RC02_R161")(Uid 1729 0 -3000 0 0)(Derived 467) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 213(N "10DIP100_XR15")(Uid 1731 -3000 12000 0 0) + (Derived 468) + (P 1(N "1") 0 0 41(ExitRule "Std")) + (P 2(N "2") -6000 0 41(ExitRule "Std")) + (P 3(N "3") 0 6000 41(ExitRule "Std")) + (P 4(N "4") -6000 6000 41(ExitRule "Std")) + (P 5(N "5") 0 12000 41(ExitRule "Std")) + (P 6(N "6") -6000 12000 41(ExitRule "Std")) + (P 7(N "7") 0 18000 41(ExitRule "Std")) + (P 8(N "8") -6000 18000 41(ExitRule "Std")) + (P 9(N "9") 0 24000 41(ExitRule "Std")) + (P 10(N "10") -6000 24000 41(ExitRule "Std")) + ) +(SYM 214(N "VD2_VD8")(Uid 1734 0 -6000 0 0)(Derived 469) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 -12000 19(ExitRule "Std")) + ) +(SYM 215(N "CAP2_C40")(Uid 1736 0 6000 0 0)(Derived 470) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 12000 19(ExitRule "Std")) + ) +(SYM 216(N "RC02_R162")(Uid 1738 3000 0 0 0)(Derived 471) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 217(N "PIN_PIN-6")(Uid 1741 0 0 0 0)(Derived 472) + (P 1(N "1") 0 0 17(ExitRule "Std")) + ) +(SYM 218(N "PIN_PIN-7")(Uid 1743 0 0 0 0)(Derived 473) + (P 1(N "1") 0 0 17(ExitRule "Std")) + ) +(SYM 219(N "CAP3_C42")(Uid 1745 0 -3000 0 0)(Derived 474) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 220(N "CAP3_C43")(Uid 1747 0 3000 0 0)(Derived 475) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 221(N "RC02_R165")(Uid 1749 3000 0 0 0)(Derived 476) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 222(N "VD3_VD11")(Uid 1751 0 -3000 0 0)(Derived 477) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 6000 0 28(ExitRule "Std")) + ) +(SYM 223(N "VD3_VD1")(Uid 1754 0 -3000 0 0)(Derived 478) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 6000 0 28(ExitRule "Std")) + ) +(SYM 224(N "VD3_VD13")(Uid 1757 0 3000 0 0)(Derived 479) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 6000 0 17(ExitRule "Std")) + ) +(SYM 225(N "VD3_VD14")(Uid 1760 0 3000 0 0)(Derived 480) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 6000 0 17(ExitRule "Std")) + ) +(SYM 226(N "VD3_VD12")(Uid 1762 3000 0 0 0)(Derived 481) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") -6000 0 21(ExitRule "Std")) + ) +(SYM 227(N "VD3_VD15")(Uid 1764 0 -3000 0 0)(Derived 482) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 6000 0 28(ExitRule "Std")) + ) +(SYM 228(N "VD3_VD2-2")(Uid 1767 0 3000 0 0)(Derived 483) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 6000 0 17(ExitRule "Std")) + ) +(SYM 229(N "VD3_VD17")(Uid 1769 -3000 0 0 0)(Derived 484) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") -6000 0 19(ExitRule "Std")) + ) +(SYM 230(N "VD2_VD***")(Uid 1772 -6000 0 0 0)(Derived 485) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") -12000 0 19(ExitRule "Std")) + ) +(SYM 231(N "RC02_R**")(Uid 1775 0 -3000 0 0)(Derived 486) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 232(N "RC02_R**-2")(Uid 1777 0 -3000 0 0)(Derived 487) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 233(N "RC02_R**-3")(Uid 1779 3000 0 0 0)(Derived 488) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 234(N "RC02_R**-4")(Uid 1781 0 -3000 0 0)(Derived 489) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 235(N "RC02_R**-5")(Uid 1783 3000 0 0 0)(Derived 490) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 236(N "RC02_R**-6")(Uid 1785 3000 0 0 0)(Derived 491) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 237(N "RC02_R**-7")(Uid 1787 3000 0 0 0)(Derived 492) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 238(N "RC02_R**-8")(Uid 1789 3000 0 0 0)(Derived 493) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 239(N "CAP2_C***")(Uid 1791 -6000 0 0 0)(Derived 494) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 12000 0 21(ExitRule "Std")) + ) +(SYM 240(N "CAP2_C***-2")(Uid 1793 -6000 0 0 0)(Derived 495) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 12000 0 21(ExitRule "Std")) + ) +(SYM 241(N "RC02_R**-9")(Uid 1795 0 -3000 0 0)(Derived 496) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 242(N "RC02_R**-10")(Uid 1797 0 -3000 0 0)(Derived 497) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 243(N "PIN_PIN-8")(Uid 1799 0 0 0 0)(Derived 498) + (P 1(N "1") 0 0 19(ExitRule "Std")) + ) +(SYM 244(N "RC02_R**-11")(Uid 1801 3000 0 0 0)(Derived 499) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 245(N "RC02_R**-12")(Uid 1803 3000 0 0 0)(Derived 500) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 246(N "CAP2_C***-3")(Uid 1805 0 -6000 0 0)(Derived 501) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -12000 0 17(ExitRule "Std")) + ) +(SYM 247(N "CAP2_C***-4")(Uid 1807 0 6000 0 0)(Derived 502) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") -12000 0 28(ExitRule "Std")) + ) +(SYM 248(N "PIN_PIN-9")(Uid 1809 0 0 0 0)(Derived 503) + (P 1(N "1") 0 0 41(ExitRule "Std")) + ) +(SYM 249(N "RC02_R**-13")(Uid 1811 3000 0 0 0)(Derived 504) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 250(N "RC02_R**-14")(Uid 1813 3000 0 0 0)(Derived 505) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 251(N "RC02_R**-15")(Uid 1815 3000 0 0 0)(Derived 506) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 252(N "RC02_R**-16")(Uid 1817 3000 0 0 0)(Derived 507) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 253(N "XPOWER_X**")(Uid 1819 18000 0 0 0)(Derived 508) + (P 1(N "1") 0 0 44(ExitRule "Std")) + (P 2(N "2") 9000 0 44(ExitRule "Std")) + (P 3(N "3") 18000 0 44(ExitRule "Std")) + (P 4(N "4") 27000 0 44(ExitRule "Std")) + (P 5(N "5") 36000 0 44(ExitRule "Std")) + (P 6(N "6") 45000 0 44(ExitRule "Std")) + ) +(SYM 254(N "rc05_R***")(Uid 1822 12000 0 0 0)(Derived 509) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 24000 0 19(ExitRule "Std")) + ) +(SYM 255(N "rc05_R***-2")(Uid 1825 0 12000 0 0)(Derived 510) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") -24000 0 28(ExitRule "Std")) + ) +(SYM 256(N "PLCC44")(Uid 427 3000 15000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -6000 17(ExitRule "Std")) + (P 4(N "4") -6000 -12000 17(ExitRule "Std")) + (P 5(N "5") 0 -12000 17(ExitRule "Std")) + (P 6(N "6") -6000 -18000 17(ExitRule "Std")) + (P 7(N "7") 0 -24000 17(ExitRule "Std")) + (P 8(N "8") 0 -18000 17(ExitRule "Std")) + (P 9(N "9") 6000 -24000 17(ExitRule "Std")) + (P 10(N "10") 6000 -18000 17(ExitRule "Std")) + (P 11(N "11") 12000 -24000 17(ExitRule "Std")) + (P 12(N "12") 12000 -18000 17(ExitRule "Std")) + (P 13(N "13") 18000 -24000 17(ExitRule "Std")) + (P 14(N "14") 18000 -18000 17(ExitRule "Std")) + (P 15(N "15") 24000 -24000 17(ExitRule "Std")) + (P 16(N "16") 24000 -18000 17(ExitRule "Std")) + (P 17(N "17") 30000 -24000 17(ExitRule "Std")) + (P 18(N "18") 36000 -18000 17(ExitRule "Std")) + (P 19(N "19") 30000 -18000 17(ExitRule "Std")) + (P 20(N "20") 36000 -12000 17(ExitRule "Std")) + (P 21(N "21") 30000 -12000 17(ExitRule "Std")) + (P 22(N "22") 36000 -6000 17(ExitRule "Std")) + (P 23(N "23") 30000 -6000 17(ExitRule "Std")) + (P 24(N "24") 36000 0 17(ExitRule "Std")) + (P 25(N "25") 30000 0 17(ExitRule "Std")) + (P 26(N "26") 36000 6000 17(ExitRule "Std")) + (P 27(N "27") 30000 6000 17(ExitRule "Std")) + (P 28(N "28") 36000 12000 17(ExitRule "Std")) + (P 29(N "29") 30000 18000 17(ExitRule "Std")) + (P 30(N "30") 30000 12000 17(ExitRule "Std")) + (P 31(N "31") 24000 18000 17(ExitRule "Std")) + (P 32(N "32") 24000 12000 17(ExitRule "Std")) + (P 33(N "33") 18000 18000 17(ExitRule "Std")) + (P 34(N "34") 18000 12000 17(ExitRule "Std")) + (P 35(N "35") 12000 18000 17(ExitRule "Std")) + (P 36(N "36") 12000 12000 17(ExitRule "Std")) + (P 37(N "37") 6000 18000 17(ExitRule "Std")) + (P 38(N "38") 6000 12000 17(ExitRule "Std")) + (P 39(N "39") 0 18000 17(ExitRule "Std")) + (P 40(N "40") -6000 12000 17(ExitRule "Std")) + (P 41(N "41") 0 12000 17(ExitRule "Std")) + (P 42(N "42") -6000 6000 17(ExitRule "Std")) + (P 43(N "43") 0 6000 17(ExitRule "Std")) + (P 44(N "44") -6000 0 17(ExitRule "Std")) + ) +(SYM 257(N "32dip300")(Uid 513 45000 9000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) 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30(N "30") 18000 -12000 17(ExitRule "Std")) + (P 31(N "31") 18000 -6000 17(ExitRule "Std")) + (P 32(N "32") 18000 0 17(ExitRule "Std")) + ) +(SYM 258(N "32dip300")(Uid 544 45000 9000 0 0)(Derived 0) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 0 -42000 17(ExitRule "Std")) + (P 9(N "9") 0 -48000 17(ExitRule "Std")) + (P 10(N "10") 0 -54000 17(ExitRule "Std")) + (P 11(N "11") 0 -60000 17(ExitRule "Std")) + (P 12(N "12") 0 -66000 17(ExitRule "Std")) + (P 13(N "13") 0 -72000 17(ExitRule "Std")) + (P 14(N "14") 0 -78000 17(ExitRule "Std")) + (P 15(N "15") 0 -84000 17(ExitRule "Std")) + (P 16(N "16") 0 -90000 17(ExitRule "Std")) + (P 17(N "17") 18000 -90000 17(ExitRule "Std")) + (P 18(N "18") 18000 -84000 17(ExitRule "Std")) + (P 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"CAP3")(Uid 1569 -3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 0 -6000 28(ExitRule "Std")) + ) +(SYM 443(N "IND")(Uid 1572 12000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -24000 17(ExitRule "Std")) + ) +(SYM 444(N "RC02")(Uid 1575 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 445(N "34DIP100")(Uid 1577 3000 -48000 0 0)(Derived 0) + (P 1(N "1") 0 0 42(ExitRule "Std")) + (P 2(N "2") -6000 0 43(ExitRule "Std")) + (P 3(N "3") 0 6000 43(ExitRule "Std")) + (P 4(N "4") -6000 6000 43(ExitRule "Std")) + (P 5(N "5") 0 12000 43(ExitRule "Std")) + (P 6(N "6") -6000 12000 43(ExitRule "Std")) + (P 7(N "7") 0 18000 43(ExitRule "Std")) + (P 8(N "8") -6000 18000 43(ExitRule "Std")) + (P 9(N "9") 0 24000 43(ExitRule "Std")) + (P 10(N "10") -6000 24000 43(ExitRule "Std")) + (P 11(N "11") 0 30000 43(ExitRule "Std")) + (P 12(N "12") -6000 30000 43(ExitRule "Std")) + (P 13(N "13") 0 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(P 33(N "B2") 12000 6000 43(ExitRule "Std")) + (P 34(N "B3") 12000 12000 43(ExitRule "Std")) + (P 35(N "B4") 12000 18000 43(ExitRule "Std")) + (P 36(N "B5") 12000 24000 43(ExitRule "Std")) + (P 37(N "B6") 12000 30000 43(ExitRule "Std")) + (P 38(N "B7") 12000 36000 43(ExitRule "Std")) + (P 39(N "B8") 12000 42000 43(ExitRule "Std")) + (P 40(N "B9") 12000 48000 43(ExitRule "Std")) + (P 41(N "B10") 12000 54000 43(ExitRule "Std")) + (P 42(N "B11") 12000 60000 43(ExitRule "Std")) + (P 43(N "B12") 12000 66000 43(ExitRule "Std")) + (P 44(N "B13") 12000 72000 43(ExitRule "Std")) + (P 45(N "B14") 12000 78000 43(ExitRule "Std")) + (P 46(N "B15") 12000 84000 43(ExitRule "Std")) + (P 47(N "B16") 12000 90000 43(ExitRule "Std")) + (P 48(N "B17") 12000 96000 43(ExitRule "Std")) + (P 49(N "B18") 12000 102000 43(ExitRule "Std")) + (P 50(N "B19") 12000 108000 43(ExitRule "Std")) + (P 51(N "B20") 12000 114000 43(ExitRule "Std")) + (P 52(N "B21") 12000 120000 43(ExitRule "Std")) + (P 53(N "B22") 12000 126000 43(ExitRule "Std")) + (P 54(N "B23") 12000 132000 43(ExitRule "Std")) + (P 55(N "B24") 12000 138000 43(ExitRule "Std")) + (P 56(N "B25") 12000 144000 43(ExitRule "Std")) + (P 57(N "B26") 12000 150000 43(ExitRule "Std")) + (P 58(N "B27") 12000 156000 43(ExitRule "Std")) + (P 59(N "B28") 12000 162000 43(ExitRule "Std")) + (P 60(N "B29") 12000 168000 43(ExitRule "Std")) + (P 61(N "B30") 12000 174000 43(ExitRule "Std")) + (P 62(N "B31") 12000 180000 43(ExitRule "Std")) + ) +(SYM 453(N "CON31X2")(Uid 1700 -6000 -90000 0 0)(Derived 0) + (P 1(N "A1") 0 0 43(ExitRule "Std")) + (P 2(N "A2") 0 6000 43(ExitRule "Std")) + (P 3(N "A3") 0 12000 43(ExitRule "Std")) + (P 4(N "A4") 0 18000 43(ExitRule "Std")) + (P 5(N "A5") 0 24000 43(ExitRule "Std")) + (P 6(N "A6") 0 30000 43(ExitRule "Std")) + (P 7(N "A7") 0 36000 43(ExitRule "Std")) + (P 8(N "A8") 0 42000 43(ExitRule "Std")) + (P 9(N "A9") 0 48000 43(ExitRule "Std")) + (P 10(N "A10") 0 54000 43(ExitRule "Std")) + (P 11(N "A11") 0 60000 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6000 43(ExitRule "Std")) + (P 34(N "B3") 12000 12000 43(ExitRule "Std")) + (P 35(N "B4") 12000 18000 43(ExitRule "Std")) + (P 36(N "B5") 12000 24000 43(ExitRule "Std")) + (P 37(N "B6") 12000 30000 43(ExitRule "Std")) + (P 38(N "B7") 12000 36000 43(ExitRule "Std")) + (P 39(N "B8") 12000 42000 43(ExitRule "Std")) + (P 40(N "B9") 12000 48000 43(ExitRule "Std")) + (P 41(N "B10") 12000 54000 43(ExitRule "Std")) + (P 42(N "B11") 12000 60000 43(ExitRule "Std")) + (P 43(N "B12") 12000 66000 43(ExitRule "Std")) + (P 44(N "B13") 12000 72000 43(ExitRule "Std")) + (P 45(N "B14") 12000 78000 43(ExitRule "Std")) + (P 46(N "B15") 12000 84000 43(ExitRule "Std")) + (P 47(N "B16") 12000 90000 43(ExitRule "Std")) + (P 48(N "B17") 12000 96000 43(ExitRule "Std")) + (P 49(N "B18") 12000 102000 43(ExitRule "Std")) + (P 50(N "B19") 12000 108000 43(ExitRule "Std")) + (P 51(N "B20") 12000 114000 43(ExitRule "Std")) + (P 52(N "B21") 12000 120000 43(ExitRule "Std")) + (P 53(N "B22") 12000 126000 43(ExitRule "Std")) + (P 54(N "B23") 12000 132000 43(ExitRule "Std")) + (P 55(N "B24") 12000 138000 43(ExitRule "Std")) + (P 56(N "B25") 12000 144000 43(ExitRule "Std")) + (P 57(N "B26") 12000 150000 43(ExitRule "Std")) + (P 58(N "B27") 12000 156000 43(ExitRule "Std")) + (P 59(N "B28") 12000 162000 43(ExitRule "Std")) + (P 60(N "B29") 12000 168000 43(ExitRule "Std")) + (P 61(N "B30") 12000 174000 43(ExitRule "Std")) + (P 62(N "B31") 12000 180000 43(ExitRule "Std")) + ) +(SYM 454(N "14DIP300")(Uid 1703 18000 9000 0 0)(Derived 0) + (P 1(N "1") 0 0 18(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + (P 3(N "3") 0 -12000 17(ExitRule "Std")) + (P 4(N "4") 0 -18000 17(ExitRule "Std")) + (P 5(N "5") 0 -24000 17(ExitRule "Std")) + (P 6(N "6") 0 -30000 17(ExitRule "Std")) + (P 7(N "7") 0 -36000 17(ExitRule "Std")) + (P 8(N "8") 18000 -36000 17(ExitRule "Std")) + (P 9(N "9") 18000 -30000 17(ExitRule "Std")) + (P 10(N "10") 18000 -24000 17(ExitRule "Std")) + (P 11(N "11") 18000 -18000 17(ExitRule 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21(ExitRule "Std")) + ) +(SYM 464(N "RC02")(Uid 1723 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 465(N "RC02")(Uid 1725 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 466(N "RC02")(Uid 1727 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 467(N "RC02")(Uid 1729 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 468(N "10DIP100")(Uid 1731 -3000 12000 0 0)(Derived 0) + (P 1(N "1") 0 0 41(ExitRule "Std")) + (P 2(N "2") -6000 0 41(ExitRule "Std")) + (P 3(N "3") 0 6000 41(ExitRule "Std")) + (P 4(N "4") -6000 6000 41(ExitRule "Std")) + (P 5(N "5") 0 12000 41(ExitRule "Std")) + (P 6(N "6") -6000 12000 41(ExitRule "Std")) + (P 7(N "7") 0 18000 41(ExitRule "Std")) + (P 8(N "8") -6000 18000 41(ExitRule "Std")) + (P 9(N "9") 0 24000 41(ExitRule "Std")) + (P 10(N "10") -6000 24000 41(ExitRule "Std")) + ) +(SYM 469(N "VD2")(Uid 1734 0 -6000 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 -12000 19(ExitRule "Std")) + ) +(SYM 470(N "CAP2")(Uid 1736 0 6000 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 12000 19(ExitRule "Std")) + ) +(SYM 471(N "RC02")(Uid 1738 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 472(N "PIN")(Uid 1741 0 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + ) +(SYM 473(N "PIN")(Uid 1743 0 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + ) +(SYM 474(N "CAP3")(Uid 1745 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 0 6000 21(ExitRule "Std")) + ) +(SYM 475(N "CAP3")(Uid 1747 0 3000 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 0 6000 19(ExitRule "Std")) + ) +(SYM 476(N "RC02")(Uid 1749 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 0 -6000 17(ExitRule "Std")) + ) +(SYM 477(N "VD3")(Uid 1751 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 6000 0 28(ExitRule "Std")) + ) +(SYM 478(N "VD3")(Uid 1754 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 6000 0 28(ExitRule "Std")) + ) +(SYM 479(N "VD3")(Uid 1757 0 3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 6000 0 17(ExitRule "Std")) + ) +(SYM 480(N "VD3")(Uid 1760 0 3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 6000 0 17(ExitRule "Std")) + ) +(SYM 481(N "VD3")(Uid 1762 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") -6000 0 21(ExitRule "Std")) + ) +(SYM 482(N "VD3")(Uid 1764 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 28(ExitRule "Std")) + (P 2(N "2") 6000 0 28(ExitRule "Std")) + ) +(SYM 483(N "VD3")(Uid 1767 0 3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") 6000 0 17(ExitRule "Std")) + ) +(SYM 484(N "VD3")(Uid 1769 -3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") -6000 0 19(ExitRule "Std")) + ) +(SYM 485(N "VD2")(Uid 1772 -6000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") -12000 0 19(ExitRule "Std")) + ) +(SYM 486(N "RC02")(Uid 1775 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 487(N "RC02")(Uid 1777 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 488(N "RC02")(Uid 1779 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 489(N "RC02")(Uid 1781 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 490(N "RC02")(Uid 1783 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 491(N "RC02")(Uid 1785 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 492(N "RC02")(Uid 1787 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 493(N "RC02")(Uid 1789 3000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule "Std")) + (P 2(N "2") 6000 0 19(ExitRule "Std")) + ) +(SYM 494(N "CAP2")(Uid 1791 -6000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 12000 0 21(ExitRule "Std")) + ) +(SYM 495(N "CAP2")(Uid 1793 -6000 0 0 0)(Derived 0) + (P 1(N "1") 0 0 21(ExitRule "Std")) + (P 2(N "2") 12000 0 21(ExitRule "Std")) + ) +(SYM 496(N "RC02")(Uid 1795 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 497(N "RC02")(Uid 1797 0 -3000 0 0)(Derived 0) + (P 1(N "1") 0 0 17(ExitRule "Std")) + (P 2(N "2") -6000 0 17(ExitRule "Std")) + ) +(SYM 498(N "PIN")(Uid 1799 0 0 0 0)(Derived 0) + (P 1(N "1") 0 0 19(ExitRule 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+ ) +(SYM 513(N "VIA3")(Uid -2160 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 3(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 514(N "VIA4")(Uid -2161 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 4(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 515(N "VIA5")(Uid -2162 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 5(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 516(N "VIA6")(Uid -2163 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 6(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 517(N "VIA7")(Uid -2164 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 7(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 518(N "VIA8")(Uid -2165 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 8(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 519(N "VIA9")(Uid -2166 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 9(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 520(N "VIA10")(Uid -2167 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 10(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 521(N "VIA11")(Uid -2168 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 11(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 522(N "VIA12")(Uid -2169 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 12(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 523(N "VIA13")(Uid -2170 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 13(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 524(N "VIA14")(Uid -2171 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 14(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 525(N "VIA15")(Uid -2172 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 15(ExitRule "Std")(ForcedThermalRelief)) + ) +(SYM 526(N "VIA16")(Uid -2173 0 0 0 0)(Via)(Derived 0) + (P 1(N "FV") 0 0 16(ExitRule "Std")(ForcedThermalRelief)) + ) +(COMP 1(N "DD1")(N "EPM7032")(Uid 427) (334500 -199500)(R 5400) + (Value "EPM7032")(Sym 1)) +(COMP 2(N "DD2")(N "62C512")(Uid 513) (135000 -360000)(R 5400) + (Value "62C512")(Sym 2)) +(COMP 3(N "DD3")(N "62C512")(Uid 544) (135000 -387000)(R 5400) + (Value "62C512")(Sym 3)) +(COMP 4(N "DD4")(N "62C512")(Uid 556) (33000 -306000)(R 5400) + (Value "62C512")(Sym 4)) +(COMP 5(N "DD5")(N "1533IR23")(Uid 568) (237000 -387000)(R 5400) + (Value "1533IR23")(Sym 5)) +(COMP 6(N "DD6")(N "1533IR23")(Uid 582) (237000 -360000)(R 5400) + (Value "1533IR23")(Sym 6)) +(COMP 7(N "DD7")(N "1533IR23")(Uid 592) (237000 -333000)(R 5400) + (Value "1533IR23")(Sym 7)) +(COMP 8(N "R1-R16")(N "R2Rmatrx")(Uid 610) (300000 -387000) + (Value "R2Rmatrx")(Sym 8)) +(COMP 9(N "R17-R32")(N "R2Rmatrx")(Uid 622) (300000 -360000) + (Value "R2Rmatrx")(Sym 9)) +(COMP 10(N "R33-R48")(N "R2Rmatrx")(Uid 632) (300000 -333000) + (Value "R2Rmatrx")(Sym 10)) +(COMP 11(N "DD8")(N "1533TM9")(Uid 642) (390000 -105000)(R 10800) + (Value "1533TM9")(Sym 11)) +(COMP 12(N "DD9")(N "K555AP3")(Uid 658) (441000 -159000)(R 10800) + (Value "K555AP3")(Sym 12)) +(COMP 13(N "DD10")(N "Z84C15")(Uid 672) (195000 -178500) + (Value "Z84C15")(Sym 13)) +(COMP 14(N "DD12")(N "1533AP6")(Uid 806) (66000 -261000) + (Value "1533AP6")(Sym 14)) +(COMP 15(N "DD13")(N "1533AP6")(Uid 817) (66000 -195000) + (Value "1533AP6")(Sym 15)) +(COMP 16(N "XR1")(N "KBD_XR")(Uid 827) (399000 -51000)(R 5400) + (Value "KBD_XR")(Sym 16)) +(COMP 17(N "XR2")(N "POWER_XR")(Uid 840) (432000 -78000)(R 5400) + (Value "POWER_XR")(Sym 17)) +(COMP 18(N "DD14")(N "1533AP6")(Uid 847) (477000 -249000)(R 16200) + (Value "1533AP6")(Sym 18)) +(COMP 19(N "DD15")(N "1533AP6")(Uid 857) (477000 -225000)(R 16200) + (Value "1533AP6")(Sym 19)) +(COMP 20(N "SIMM")(N "SIMM_4Mb")(Uid 867) (261000 -271500)(R 10800) + (Value "SIMM_4Mb")(Sym 20)) +(COMP 21(N "PIN")(N "PIN")(Uid 904) (471000 -367500)(R 5400) + (Value "PIN")(Sym 21)) +(COMP 22(N "DD16")(N "62C512")(Uid 907) (33000 -333000)(R 5400) + (Value "62C512")(Sym 22)) +(COMP 23(N "DD17")(N "62C512")(Uid 910) (33000 -387000)(R 5400) + (Value "62C512")(Sym 23)) +(COMP 24(N "DD18")(N "62C512")(Uid 912) (33000 -360000)(R 5400) + (Value "62C512")(Sym 24)) +(COMP 25(N "VT1-2")(N "temp0")(Uid 914) (351000 -375000)(R 10800) + (Value "attr25")(Sym 25)) +(COMP 26(N "VT2")(N "temp1")(Uid 919) (351000 -348000)(R 10800) + (Value "attr26")(Sym 26)) +(COMP 27(N "VT3")(N "temp2")(Uid 922) (351000 -321000)(R 10800) + (Value "attr27")(Sym 27)) +(COMP 28(N "VT4")(N "temp3")(Uid 925) (369000 -375000)(R 10800) + (Value "attr28")(Sym 28)) +(COMP 29(N "PIN-2")(N "PIN")(Uid 929) (30000 -33000)(R 5400) + (Value "PIN")(Sym 29)) +(COMP 30(N "PIN-3")(N "PIN")(Uid 931) (471000 -33000)(R 5400) + (Value "PIN")(Sym 30)) +(COMP 31(N "PIN-4")(N "PIN")(Uid 933) (57000 -276000)(R 5400) + (Value "PIN")(Sym 31)) +(COMP 32(N "R49")(N "1k")(Uid 935) (351000 -369000)(R 5400) + (Value "1k")(Sym 32)) +(COMP 33(N "R50")(N "51")(Uid 940) (357000 -387000)(R 5400) + (Value "51")(Sym 33)) +(COMP 34(N "R51")(N "150")(Uid 943) (363000 -381000)(R 16200) + (Value "150")(Sym 34)) +(COMP 35(N "R52")(N "1k")(Uid 946) (351000 -342000)(R 5400) + (Value "1k")(Sym 35)) +(COMP 36(N "R53")(N "51")(Uid 948) (357000 -360000)(R 5400) + (Value "51")(Sym 36)) +(COMP 37(N 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Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "41" (pinName "41") (partNum 1) (symPinNum 41) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "42" (pinName "42") (partNum 1) (symPinNum 42) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "43" (pinName "43") (partNum 1) (symPinNum 43) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "44" (pinName "44") (partNum 1) (symPinNum 44) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PLCC44_DD1") + (numPads 44) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + (padNum 41) (compPinRef "41") + (padNum 42) (compPinRef "42") + (padNum 43) (compPinRef "43") + (padNum 44) (compPinRef "44") + ) + ) + ) + (compDef "32dip300_DD2_1" + (originalName "32dip300_DD2") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD2") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "32dip300_DD3_2" + (originalName "32dip300_DD3") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD3") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "32dip300_DD4_3" + (originalName "32dip300_DD4") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD4") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "20DIP300_DD5_4" + (originalName "20DIP300_DD5") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD5") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "20DIP300_DD6_5" + (originalName "20DIP300_DD6") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD6") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "20DIP300_DD7_6" + (originalName "20DIP300_DD7") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD7") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "PLATA_R1-R16_7" + (originalName "PLATA_R1-R16") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PLATA_R1-R16") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "PLATA_R17-R32_8" + (originalName "PLATA_R17-R32") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PLATA_R17-R32") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "PLATA_R33-R48_9" + (originalName "PLATA_R33-R48") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PLATA_R33-R48") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "16DIP300_DD8_10" + (originalName "16DIP300_DD8") + (compHeader + (sourceLibrary "") + (numPins 16) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "16DIP300_DD8") + (numPads 16) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + ) + ) + ) + (compDef "20DIP300_DD9_11" + (originalName "20DIP300_DD9") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD9") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "QFP100_DD10_12" + (originalName "QFP100_DD10") + (compHeader + (sourceLibrary "") + (numPins 100) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "41" (pinName "41") (partNum 1) (symPinNum 41) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "42" (pinName "42") (partNum 1) (symPinNum 42) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "43" (pinName "43") (partNum 1) (symPinNum 43) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "44" (pinName "44") (partNum 1) (symPinNum 44) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "45" (pinName "45") (partNum 1) (symPinNum 45) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "46" (pinName "46") (partNum 1) (symPinNum 46) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "47" (pinName "47") (partNum 1) (symPinNum 47) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "48" (pinName "48") (partNum 1) (symPinNum 48) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "49" (pinName "49") (partNum 1) (symPinNum 49) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "50" (pinName "50") (partNum 1) (symPinNum 50) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "51" (pinName "51") (partNum 1) (symPinNum 51) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "52" (pinName "52") (partNum 1) (symPinNum 52) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "53" (pinName "53") (partNum 1) (symPinNum 53) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "54" (pinName "54") (partNum 1) (symPinNum 54) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "55" (pinName "55") (partNum 1) (symPinNum 55) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "56" (pinName "56") (partNum 1) (symPinNum 56) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "57" (pinName "57") (partNum 1) (symPinNum 57) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "58" (pinName "58") (partNum 1) (symPinNum 58) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "59" (pinName "59") (partNum 1) (symPinNum 59) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "60" (pinName "60") (partNum 1) (symPinNum 60) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "61" (pinName "61") (partNum 1) (symPinNum 61) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "62" (pinName "62") (partNum 1) (symPinNum 62) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "63" (pinName "63") (partNum 1) (symPinNum 63) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "64" (pinName "64") (partNum 1) (symPinNum 64) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "65" (pinName "65") (partNum 1) (symPinNum 65) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "66" (pinName "66") (partNum 1) (symPinNum 66) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "67" (pinName "67") (partNum 1) (symPinNum 67) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "68" (pinName "68") (partNum 1) (symPinNum 68) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "69" (pinName "69") (partNum 1) (symPinNum 69) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "70" (pinName "70") (partNum 1) (symPinNum 70) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "71" (pinName "71") (partNum 1) (symPinNum 71) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "72" (pinName "72") (partNum 1) (symPinNum 72) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "73" (pinName "73") (partNum 1) (symPinNum 73) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "74" (pinName "74") (partNum 1) (symPinNum 74) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "75" (pinName "75") (partNum 1) (symPinNum 75) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "76" (pinName "76") (partNum 1) (symPinNum 76) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "77" (pinName "77") (partNum 1) (symPinNum 77) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "78" (pinName "78") (partNum 1) (symPinNum 78) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "79" (pinName "79") (partNum 1) (symPinNum 79) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "80" (pinName "80") (partNum 1) (symPinNum 80) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "81" (pinName "81") (partNum 1) (symPinNum 81) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "82" (pinName "82") (partNum 1) (symPinNum 82) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "83" (pinName "83") (partNum 1) (symPinNum 83) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "84" (pinName "84") (partNum 1) (symPinNum 84) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "85" (pinName "85") (partNum 1) (symPinNum 85) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "86" (pinName "86") (partNum 1) (symPinNum 86) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "87" (pinName "87") (partNum 1) (symPinNum 87) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "88" (pinName "88") (partNum 1) (symPinNum 88) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "89" (pinName "89") (partNum 1) (symPinNum 89) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "90" (pinName "90") (partNum 1) (symPinNum 90) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "91" (pinName "91") (partNum 1) (symPinNum 91) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "92" (pinName "92") (partNum 1) (symPinNum 92) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "93" (pinName "93") (partNum 1) (symPinNum 93) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "94" (pinName "94") (partNum 1) (symPinNum 94) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "95" (pinName "95") (partNum 1) (symPinNum 95) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "96" (pinName "96") (partNum 1) (symPinNum 96) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "97" (pinName "97") (partNum 1) (symPinNum 97) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "98" (pinName "98") (partNum 1) (symPinNum 98) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "99" (pinName "99") (partNum 1) (symPinNum 99) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "100" (pinName "100") (partNum 1) (symPinNum 100) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "QFP100_DD10") + (numPads 100) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + (padNum 41) (compPinRef "41") + (padNum 42) (compPinRef "42") + (padNum 43) (compPinRef "43") + (padNum 44) (compPinRef "44") + (padNum 45) (compPinRef "45") + (padNum 46) (compPinRef "46") + (padNum 47) (compPinRef "47") + (padNum 48) (compPinRef "48") + (padNum 49) (compPinRef "49") + (padNum 50) (compPinRef "50") + (padNum 51) (compPinRef "51") + (padNum 52) (compPinRef "52") + (padNum 53) (compPinRef "53") + (padNum 54) (compPinRef "54") + (padNum 55) (compPinRef "55") + (padNum 56) (compPinRef "56") + (padNum 57) (compPinRef "57") + (padNum 58) (compPinRef "58") + (padNum 59) (compPinRef "59") + (padNum 60) (compPinRef "60") + (padNum 61) (compPinRef "61") + (padNum 62) (compPinRef "62") + (padNum 63) (compPinRef "63") + (padNum 64) (compPinRef "64") + (padNum 65) (compPinRef "65") + (padNum 66) (compPinRef "66") + (padNum 67) (compPinRef "67") + (padNum 68) (compPinRef "68") + (padNum 69) (compPinRef "69") + (padNum 70) (compPinRef "70") + (padNum 71) (compPinRef "71") + (padNum 72) (compPinRef "72") + (padNum 73) (compPinRef "73") + (padNum 74) (compPinRef "74") + (padNum 75) (compPinRef "75") + (padNum 76) (compPinRef "76") + (padNum 77) (compPinRef "77") + (padNum 78) (compPinRef "78") + (padNum 79) (compPinRef "79") + (padNum 80) (compPinRef "80") + (padNum 81) (compPinRef "81") + (padNum 82) (compPinRef "82") + (padNum 83) (compPinRef "83") + (padNum 84) (compPinRef "84") + (padNum 85) (compPinRef "85") + (padNum 86) (compPinRef "86") + (padNum 87) (compPinRef "87") + (padNum 88) (compPinRef "88") + (padNum 89) (compPinRef "89") + (padNum 90) (compPinRef "90") + (padNum 91) (compPinRef "91") + (padNum 92) (compPinRef "92") + (padNum 93) (compPinRef "93") + (padNum 94) (compPinRef "94") + (padNum 95) (compPinRef "95") + (padNum 96) (compPinRef "96") + (padNum 97) (compPinRef "97") + (padNum 98) (compPinRef "98") + (padNum 99) (compPinRef "99") + (padNum 100) (compPinRef "100") + ) + ) + ) + (compDef "20DIP300_DD12_13" + (originalName "20DIP300_DD12") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD12") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "20DIP300_DD13_14" + (originalName "20DIP300_DD13") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD13") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "ONC5_XR1_15" + (originalName "ONC5_XR1") + (compHeader + (sourceLibrary "") + (numPins 9) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X1" (pinName "X1") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X2" (pinName "X2") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X3" (pinName "X3") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X4" (pinName "X4") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "ONC5_XR1") + (numPads 9) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "X1") + (padNum 7) (compPinRef "X2") + (padNum 8) (compPinRef "X3") + (padNum 9) (compPinRef "X4") + ) + ) + ) + (compDef "XPOWER_XR2_16" + (originalName "XPOWER_XR2") + (compHeader + (sourceLibrary "") + (numPins 6) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "XPOWER_XR2") + (numPads 6) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + ) + ) + ) + (compDef "20DIP300_DD14_17" + (originalName "20DIP300_DD14") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD14") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "20DIP300_DD15_18" + (originalName "20DIP300_DD15") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD15") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "SIMM72_SIMM_19" + (originalName "SIMM72_SIMM") + (compHeader + (sourceLibrary "") + (numPins 75) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "41" (pinName "41") (partNum 1) (symPinNum 41) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "42" (pinName "42") (partNum 1) (symPinNum 42) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "43" (pinName "43") (partNum 1) (symPinNum 43) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "44" (pinName "44") (partNum 1) (symPinNum 44) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "45" (pinName "45") (partNum 1) (symPinNum 45) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "46" (pinName "46") (partNum 1) (symPinNum 46) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "47" (pinName "47") (partNum 1) (symPinNum 47) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "48" (pinName "48") (partNum 1) (symPinNum 48) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "49" (pinName "49") (partNum 1) (symPinNum 49) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "50" (pinName "50") (partNum 1) (symPinNum 50) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "51" (pinName "51") (partNum 1) (symPinNum 51) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "52" (pinName "52") (partNum 1) (symPinNum 52) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "53" (pinName "53") (partNum 1) (symPinNum 53) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "54" (pinName "54") (partNum 1) (symPinNum 54) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "55" (pinName "55") (partNum 1) (symPinNum 55) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "56" (pinName "56") (partNum 1) (symPinNum 56) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "57" (pinName "57") (partNum 1) (symPinNum 57) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "58" (pinName "58") (partNum 1) (symPinNum 58) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "59" (pinName "59") (partNum 1) (symPinNum 59) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "60" (pinName "60") (partNum 1) (symPinNum 60) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "61" (pinName "61") (partNum 1) (symPinNum 61) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "62" (pinName "62") (partNum 1) (symPinNum 62) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "63" (pinName "63") (partNum 1) (symPinNum 63) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "64" (pinName "64") (partNum 1) (symPinNum 64) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "65" (pinName "65") (partNum 1) (symPinNum 65) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "66" (pinName "66") (partNum 1) (symPinNum 66) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "67" (pinName "67") (partNum 1) (symPinNum 67) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "68" (pinName "68") (partNum 1) (symPinNum 68) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "69" (pinName "69") (partNum 1) (symPinNum 69) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "70" (pinName "70") (partNum 1) (symPinNum 70) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "71" (pinName "71") (partNum 1) (symPinNum 71) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "72" (pinName "72") (partNum 1) (symPinNum 72) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "Hole1" (pinName "Hole1") (partNum 1) (symPinNum 73) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X3" (pinName "X3") (partNum 1) (symPinNum 74) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "Hole2" (pinName "Hole2") (partNum 1) (symPinNum 75) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "SIMM72_SIMM") + (numPads 75) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + (padNum 41) (compPinRef "41") + (padNum 42) (compPinRef "42") + (padNum 43) (compPinRef "43") + (padNum 44) (compPinRef "44") + (padNum 45) (compPinRef "45") + (padNum 46) (compPinRef "46") + (padNum 47) (compPinRef "47") + (padNum 48) (compPinRef "48") + (padNum 49) (compPinRef "49") + (padNum 50) (compPinRef "50") + (padNum 51) (compPinRef "51") + (padNum 52) (compPinRef "52") + (padNum 53) (compPinRef "53") + (padNum 54) (compPinRef "54") + (padNum 55) (compPinRef "55") + (padNum 56) (compPinRef "56") + (padNum 57) (compPinRef "57") + (padNum 58) (compPinRef "58") + (padNum 59) (compPinRef "59") + (padNum 60) (compPinRef "60") + (padNum 61) (compPinRef "61") + (padNum 62) (compPinRef "62") + (padNum 63) (compPinRef "63") + (padNum 64) (compPinRef "64") + (padNum 65) (compPinRef "65") + (padNum 66) (compPinRef "66") + (padNum 67) (compPinRef "67") + (padNum 68) (compPinRef "68") + (padNum 69) (compPinRef "69") + (padNum 70) (compPinRef "70") + (padNum 71) (compPinRef "71") + (padNum 72) (compPinRef "72") + (padNum 73) (compPinRef "Hole1") + (padNum 74) (compPinRef "X3") + (padNum 75) (compPinRef "Hole2") + ) + ) + ) + (compDef "pin_PIN_20" + (originalName "pin_PIN") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "Hole3" (pinName "Hole3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "pin_PIN") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "Hole3") + ) + ) + ) + (compDef "32dip300_DD16_21" + (originalName "32dip300_DD16") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD16") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "32dip300_DD17_22" + (originalName "32dip300_DD17") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD17") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "32dip300_DD18_23" + (originalName "32dip300_DD18") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD18") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "VT1_VT1-2_24" + (originalName "VT1_VT1-2") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT1-2") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "VT1_VT2_25" + (originalName "VT1_VT2") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT2") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "VT1_VT3_26" + (originalName "VT1_VT3") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT3") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "VT1_VT4_27" + (originalName "VT1_VT4") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT4") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "pin_PIN-2_28" + (originalName "pin_PIN-2") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "Hole4" (pinName "Hole4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "pin_PIN-2") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "Hole4") + ) + ) + ) + (compDef "pin_PIN-3_29" + (originalName "pin_PIN-3") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "Hole5" (pinName "Hole5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "pin_PIN-3") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "Hole5") + ) + ) + ) + (compDef "pin_PIN-4_30" + (originalName "pin_PIN-4") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "Hole6" (pinName "Hole6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "pin_PIN-4") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "Hole6") + ) + ) + ) + (compDef "RC02_R49_31" + (originalName "RC02_R49") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R49") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R50_32" + (originalName "RC02_R50") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R50") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R51_33" + (originalName "RC02_R51") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R51") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R52_34" + (originalName "RC02_R52") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R52") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R53_35" + (originalName "RC02_R53") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R53") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R54_36" + (originalName "RC02_R54") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R54") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R55_37" + (originalName "RC02_R55") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R55") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R56_38" + (originalName "RC02_R56") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R56") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R57_39" + (originalName "RC02_R57") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R57") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R58_40" + (originalName "RC02_R58") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R58") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R59_41" + (originalName "RC02_R59") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R59") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R60_42" + (originalName "RC02_R60") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R60") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "40DIP600_DD19_43" + (originalName "40DIP600_DD19") + (compHeader + (sourceLibrary "") + (numPins 40) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "40DIP600_DD19") + (numPads 40) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + ) + ) + ) + (compDef "HD10_R61-R70_44" + (originalName "HD10_R61-R70") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "HD10_R61-R70") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "2") + (padNum 2) (compPinRef "3") + (padNum 3) (compPinRef "4") + (padNum 4) (compPinRef "5") + (padNum 5) (compPinRef "6") + (padNum 6) (compPinRef "7") + (padNum 7) (compPinRef "8") + (padNum 8) (compPinRef "9") + (padNum 9) (compPinRef "10") + (padNum 10) (compPinRef "1") + ) + ) + ) + (compDef "VT1_VT5_45" + (originalName "VT1_VT5") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT5") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "VT1_VT6_46" + (originalName "VT1_VT6") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT6") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "RC02_R71_47" + (originalName "RC02_R71") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R71") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC05_R72_48" + (originalName "RC05_R72") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC05_R72") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC05_R73_49" + (originalName "RC05_R73") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC05_R73") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R74_50" + (originalName "RC02_R74") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R74") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "14DIP300_DD20_51" + (originalName "14DIP300_DD20") + (compHeader + (sourceLibrary "") + (numPins 14) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "14DIP300_DD20") + (numPads 14) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + ) + ) + ) + (compDef "RC02_R75_52" + (originalName "RC02_R75") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R75") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R76_53" + (originalName "RC02_R76") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R76") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C1_54" + (originalName "CAP1_C1") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C1") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "pin_PIN-5_55" + (originalName "pin_PIN-5") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "Hole7" (pinName "Hole7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "pin_PIN-5") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "Hole7") + ) + ) + ) + (compDef "2200mkf_C2_56" + (originalName "2200mkf_C2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "2200mkf_C2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "20dip300_DD21_57" + (originalName "20dip300_DD21") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20dip300_DD21") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "32dip300_DD22_58" + (originalName "32dip300_DD22") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD22") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "16DIP300_DD23_59" + (originalName "16DIP300_DD23") + (compHeader + (sourceLibrary "") + (numPins 16) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "16DIP300_DD23") + (numPads 16) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + ) + ) + ) + (compDef "RC02_XR3_60" + (originalName "RC02_XR3") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_XR3") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R77_61" + (originalName "RC02_R77") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R77") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R78_62" + (originalName "RC02_R78") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R78") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R79_63" + (originalName "RC02_R79") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R79") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R80_64" + (originalName "RC02_R80") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R80") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_XR5_65" + (originalName "RC02_XR5") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_XR5") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "2200MKF_C3_66" + (originalName "2200MKF_C3") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "2200MKF_C3") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C4_67" + (originalName "CAP1_C4") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C4") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C5_68" + (originalName "CAP1_C5") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C5") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C6_69" + (originalName "CAP1_C6") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C6") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C7_70" + (originalName "CAP1_C7") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C7") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C8_71" + (originalName "CAP1_C8") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C8") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C9_72" + (originalName "CAP1_C9") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C9") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R81_73" + (originalName "RC02_R81") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R81") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R82_74" + (originalName "RC02_R82") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R82") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R83_75" + (originalName "RC02_R83") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R83") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R84_76" + (originalName "RC02_R84") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R84") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R85_77" + (originalName "RC02_R85") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R85") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "20DIP300_DD34_78" + (originalName "20DIP300_DD34") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD34") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "RC02_R86_79" + (originalName "RC02_R86") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R86") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R87_80" + (originalName "RC02_R87") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R87") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "32dip300_DD25_81" + (originalName "32dip300_DD25") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD25") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "32dip300_DD26_82" + (originalName "32dip300_DD26") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip300_DD26") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "32dip600_DD27_83" + (originalName "32dip600_DD27") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32dip600_DD27") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "RC02_R88_84" + (originalName "RC02_R88") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R88") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R89_85" + (originalName "RC02_R89") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R89") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R90_86" + (originalName "RC02_R90") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R90") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R91_87" + (originalName "RC02_R91") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R91") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R92_88" + (originalName "RC02_R92") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R92") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "8dip300_DD28_89" + (originalName "8dip300_DD28") + (compHeader + (sourceLibrary "") + (numPins 8) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "8dip300_DD28") + (numPads 8) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + ) + ) + ) + (compDef "8dip300_DD29_90" + (originalName "8dip300_DD29") + (compHeader + (sourceLibrary "") + (numPins 8) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "8dip300_DD29") + (numPads 8) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + ) + ) + ) + (compDef "RC02_R93_91" + (originalName "RC02_R93") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R93") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R94_92" + (originalName "RC02_R94") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R94") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "16DIP300_DD30_93" + (originalName "16DIP300_DD30") + (compHeader + (sourceLibrary "") + (numPins 16) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "16DIP300_DD30") + (numPads 16) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + ) + ) + ) + (compDef "RC02_R95_94" + (originalName "RC02_R95") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R95") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R96_95" + (originalName "RC02_R96") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R96") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R97_96" + (originalName "RC02_R97") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R97") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "EL05_ZQ1_97" + (originalName "EL05_ZQ1") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "EL05_ZQ1") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC05_R98_98" + (originalName "RC05_R98") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC05_R98") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_C10_99" + (originalName "RC02_C10") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_C10") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_C11_100" + (originalName "RC02_C11") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_C11") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R99_101" + (originalName "RC02_R99") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R99") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R100_102" + (originalName "RC02_R100") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R100") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP1_C12_103" + (originalName "CAP1_C12") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1_C12") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "20DIP300_DD32_104" + (originalName "20DIP300_DD32") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD32") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "20DIP300_DD33_105" + (originalName "20DIP300_DD33") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300_DD33") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "HD10_?_106" + (originalName "HD10_?") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "HD10_?") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "2") + (padNum 2) (compPinRef "3") + (padNum 3) (compPinRef "4") + (padNum 4) (compPinRef "5") + (padNum 5) (compPinRef "6") + (padNum 6) (compPinRef "7") + (padNum 7) (compPinRef "8") + (padNum 8) (compPinRef "9") + (padNum 9) (compPinRef "10") + (padNum 10) (compPinRef "1") + ) + ) + ) + (compDef "10DIP100_R102-106_107" + (originalName "10DIP100_R102-106") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "10DIP100_R102-106") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + ) + ) + ) + (compDef "RC02_R107_108" + (originalName "RC02_R107") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R107") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "24DIP600_DD34-2_109" + (originalName "24DIP600_DD34-2") + (compHeader + (sourceLibrary "") + (numPins 24) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "24DIP600_DD34-2") + (numPads 24) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + ) + ) + ) + (compDef "208qfp10_DD35_110" + (originalName "208qfp10_DD35") + (compHeader + (sourceLibrary "") + (numPins 208) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "41" (pinName "41") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "42" (pinName "42") (partNum 1) (symPinNum 41) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "43" (pinName "43") (partNum 1) (symPinNum 42) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "44" (pinName "44") (partNum 1) (symPinNum 43) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "45" (pinName "45") (partNum 1) (symPinNum 44) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "46" (pinName "46") (partNum 1) (symPinNum 45) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "47" (pinName "47") (partNum 1) (symPinNum 46) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "48" (pinName "48") (partNum 1) (symPinNum 47) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "49" (pinName "49") (partNum 1) (symPinNum 48) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "50" (pinName "50") (partNum 1) (symPinNum 49) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "51" (pinName "51") (partNum 1) (symPinNum 50) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "52" (pinName "52") (partNum 1) (symPinNum 51) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 52) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "53" (pinName "53") (partNum 1) (symPinNum 53) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "54" (pinName "54") (partNum 1) (symPinNum 54) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "55" (pinName "55") (partNum 1) (symPinNum 55) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "56" (pinName "56") (partNum 1) (symPinNum 56) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "57" (pinName "57") (partNum 1) (symPinNum 57) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "58" (pinName "58") (partNum 1) (symPinNum 58) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "59" (pinName "59") (partNum 1) (symPinNum 59) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "60" (pinName "60") (partNum 1) (symPinNum 60) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "61" (pinName "61") (partNum 1) (symPinNum 61) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "62" (pinName "62") (partNum 1) (symPinNum 62) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "63" (pinName "63") (partNum 1) (symPinNum 63) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "64" (pinName "64") (partNum 1) (symPinNum 64) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "65" (pinName "65") (partNum 1) (symPinNum 65) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "66" (pinName "66") (partNum 1) (symPinNum 66) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "67" (pinName "67") (partNum 1) (symPinNum 67) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "68" (pinName "68") (partNum 1) (symPinNum 68) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "69" (pinName "69") (partNum 1) (symPinNum 69) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "70" (pinName "70") (partNum 1) (symPinNum 70) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "71" (pinName "71") (partNum 1) (symPinNum 71) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "72" (pinName "72") (partNum 1) (symPinNum 72) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "73" (pinName "73") (partNum 1) (symPinNum 73) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "74" (pinName "74") (partNum 1) (symPinNum 74) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "75" (pinName "75") (partNum 1) (symPinNum 75) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "76" (pinName "76") (partNum 1) (symPinNum 76) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "77" (pinName "77") (partNum 1) (symPinNum 77) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "78" (pinName "78") (partNum 1) (symPinNum 78) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "79" (pinName "79") (partNum 1) (symPinNum 79) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "80" (pinName "80") (partNum 1) (symPinNum 80) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "81" (pinName "81") (partNum 1) (symPinNum 81) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "82" (pinName "82") (partNum 1) (symPinNum 82) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "83" (pinName "83") (partNum 1) (symPinNum 83) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "84" (pinName "84") (partNum 1) (symPinNum 84) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "85" (pinName "85") (partNum 1) (symPinNum 85) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "86" (pinName "86") (partNum 1) (symPinNum 86) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "87" (pinName "87") (partNum 1) (symPinNum 87) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "88" (pinName "88") (partNum 1) (symPinNum 88) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "89" (pinName "89") (partNum 1) (symPinNum 89) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "90" (pinName "90") (partNum 1) (symPinNum 90) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "91" (pinName "91") (partNum 1) (symPinNum 91) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "92" (pinName "92") (partNum 1) (symPinNum 92) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "93" (pinName "93") (partNum 1) (symPinNum 93) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "94" (pinName "94") (partNum 1) (symPinNum 94) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "95" (pinName "95") (partNum 1) (symPinNum 95) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "96" (pinName "96") (partNum 1) (symPinNum 96) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "97" (pinName "97") (partNum 1) (symPinNum 97) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "98" (pinName "98") (partNum 1) (symPinNum 98) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "99" (pinName "99") (partNum 1) (symPinNum 99) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "100" (pinName "100") (partNum 1) (symPinNum 100) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "101" (pinName "101") (partNum 1) (symPinNum 101) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "102" (pinName "102") (partNum 1) (symPinNum 102) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "103" (pinName "103") (partNum 1) (symPinNum 103) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "104" (pinName "104") (partNum 1) (symPinNum 104) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "105" (pinName "105") (partNum 1) (symPinNum 105) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "106" (pinName "106") (partNum 1) (symPinNum 106) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "107" (pinName "107") (partNum 1) (symPinNum 107) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "108" (pinName "108") (partNum 1) (symPinNum 108) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "109" (pinName "109") (partNum 1) (symPinNum 109) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "110" (pinName "110") (partNum 1) (symPinNum 110) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "111" (pinName "111") (partNum 1) (symPinNum 111) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "112" (pinName "112") (partNum 1) (symPinNum 112) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "113" (pinName "113") (partNum 1) (symPinNum 113) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "114" (pinName "114") (partNum 1) (symPinNum 114) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "115" (pinName "115") (partNum 1) (symPinNum 115) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "116" (pinName "116") (partNum 1) (symPinNum 116) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "117" (pinName "117") (partNum 1) (symPinNum 117) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "118" (pinName "118") (partNum 1) (symPinNum 118) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "119" (pinName "119") (partNum 1) (symPinNum 119) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "120" (pinName "120") (partNum 1) (symPinNum 120) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "121" (pinName "121") (partNum 1) (symPinNum 121) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "122" (pinName "122") (partNum 1) (symPinNum 122) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "123" (pinName "123") (partNum 1) (symPinNum 123) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "124" (pinName "124") (partNum 1) (symPinNum 124) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "125" (pinName "125") (partNum 1) (symPinNum 125) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "126" (pinName "126") (partNum 1) (symPinNum 126) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "127" (pinName "127") (partNum 1) (symPinNum 127) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "128" (pinName "128") (partNum 1) (symPinNum 128) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "129" (pinName "129") (partNum 1) (symPinNum 129) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "130" (pinName "130") (partNum 1) (symPinNum 130) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "131" (pinName "131") (partNum 1) (symPinNum 131) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "132" (pinName "132") (partNum 1) (symPinNum 132) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "133" (pinName "133") (partNum 1) (symPinNum 133) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "134" (pinName "134") (partNum 1) (symPinNum 134) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "135" (pinName "135") (partNum 1) (symPinNum 135) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "136" (pinName "136") (partNum 1) (symPinNum 136) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "137" (pinName "137") (partNum 1) (symPinNum 137) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "138" (pinName "138") (partNum 1) (symPinNum 138) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "139" (pinName "139") (partNum 1) (symPinNum 139) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "140" (pinName "140") (partNum 1) (symPinNum 140) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "141" (pinName "141") (partNum 1) (symPinNum 141) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "142" (pinName "142") (partNum 1) (symPinNum 142) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "143" (pinName "143") (partNum 1) (symPinNum 143) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "144" (pinName "144") (partNum 1) (symPinNum 144) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "145" (pinName "145") (partNum 1) (symPinNum 145) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "146" (pinName "146") (partNum 1) (symPinNum 146) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "147" (pinName "147") (partNum 1) (symPinNum 147) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "148" (pinName "148") (partNum 1) (symPinNum 148) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "149" (pinName "149") (partNum 1) (symPinNum 149) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "150" (pinName "150") (partNum 1) (symPinNum 150) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "151" (pinName "151") (partNum 1) (symPinNum 151) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "152" (pinName "152") (partNum 1) (symPinNum 152) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "153" (pinName "153") (partNum 1) (symPinNum 153) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "154" (pinName "154") (partNum 1) (symPinNum 154) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "155" (pinName "155") (partNum 1) (symPinNum 155) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "156" (pinName "156") (partNum 1) (symPinNum 156) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "157" (pinName "157") (partNum 1) (symPinNum 157) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "158" (pinName "158") (partNum 1) (symPinNum 158) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "159" (pinName "159") (partNum 1) (symPinNum 159) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "160" (pinName "160") (partNum 1) (symPinNum 160) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "161" (pinName "161") (partNum 1) (symPinNum 161) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "162" (pinName "162") (partNum 1) (symPinNum 162) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "163" (pinName "163") (partNum 1) (symPinNum 163) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "164" (pinName "164") (partNum 1) (symPinNum 164) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "165" (pinName "165") (partNum 1) (symPinNum 165) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "166" (pinName "166") (partNum 1) (symPinNum 166) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "167" (pinName "167") (partNum 1) (symPinNum 167) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "168" (pinName "168") (partNum 1) (symPinNum 168) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "169" (pinName "169") (partNum 1) (symPinNum 169) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "170" (pinName "170") (partNum 1) (symPinNum 170) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "171" (pinName "171") (partNum 1) (symPinNum 171) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "172" (pinName "172") (partNum 1) (symPinNum 172) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "173" (pinName "173") (partNum 1) (symPinNum 173) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "174" (pinName "174") (partNum 1) (symPinNum 174) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "175" (pinName "175") (partNum 1) (symPinNum 175) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "176" (pinName "176") (partNum 1) (symPinNum 176) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "177" (pinName "177") (partNum 1) (symPinNum 177) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "178" (pinName "178") (partNum 1) (symPinNum 178) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "179" (pinName "179") (partNum 1) (symPinNum 179) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "180" (pinName "180") (partNum 1) (symPinNum 180) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "181" (pinName "181") (partNum 1) (symPinNum 181) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "182" (pinName "182") (partNum 1) (symPinNum 182) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "183" (pinName "183") (partNum 1) (symPinNum 183) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "184" (pinName "184") (partNum 1) (symPinNum 184) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "185" (pinName "185") (partNum 1) (symPinNum 185) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "186" (pinName "186") (partNum 1) (symPinNum 186) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "187" (pinName "187") (partNum 1) (symPinNum 187) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "188" (pinName "188") (partNum 1) (symPinNum 188) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "189" (pinName "189") (partNum 1) (symPinNum 189) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "190" (pinName "190") (partNum 1) (symPinNum 190) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "191" (pinName "191") (partNum 1) (symPinNum 191) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "192" (pinName "192") (partNum 1) (symPinNum 192) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "193" (pinName "193") (partNum 1) (symPinNum 193) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "194" (pinName "194") (partNum 1) (symPinNum 194) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "195" (pinName "195") (partNum 1) (symPinNum 195) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "196" (pinName "196") (partNum 1) (symPinNum 196) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "197" (pinName "197") (partNum 1) (symPinNum 197) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "198" (pinName "198") (partNum 1) (symPinNum 198) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "199" (pinName "199") (partNum 1) (symPinNum 199) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "200" (pinName "200") (partNum 1) (symPinNum 200) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "201" (pinName "201") (partNum 1) (symPinNum 201) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "202" (pinName "202") (partNum 1) (symPinNum 202) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "203" (pinName "203") (partNum 1) (symPinNum 203) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "204" (pinName "204") (partNum 1) (symPinNum 204) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "205" (pinName "205") (partNum 1) (symPinNum 205) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "206" (pinName "206") (partNum 1) (symPinNum 206) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "207" (pinName "207") (partNum 1) (symPinNum 207) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "208" (pinName "208") (partNum 1) (symPinNum 208) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "208qfp10_DD35") + (numPads 208) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "3") + (padNum 3) (compPinRef "4") + (padNum 4) (compPinRef "5") + (padNum 5) (compPinRef "6") + (padNum 6) (compPinRef "7") + (padNum 7) (compPinRef "8") + (padNum 8) (compPinRef "9") + (padNum 9) (compPinRef "10") + (padNum 10) (compPinRef "11") + (padNum 11) (compPinRef "12") + (padNum 12) (compPinRef "13") + (padNum 13) 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(alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R112") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "14dip300_DD38_119" + (originalName "14dip300_DD38") + (compHeader + (sourceLibrary "") + (numPins 14) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin 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(compPinRef "2") + ) + ) + ) + (compDef "RC02_R114_121" + (originalName "RC02_R114") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R114") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R115_122" + (originalName "RC02_R115") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R115") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R116_123" + (originalName "RC02_R116") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R116") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R117_124" + (originalName "RC02_R117") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R117") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R118_125" + (originalName "RC02_R118") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R118") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R119_126" + (originalName "RC02_R119") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R119") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R120_127" + (originalName "RC02_R120") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R120") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R121_128" + (originalName "RC02_R121") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R121") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R122_129" + (originalName "RC02_R122") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R122") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R123_130" + (originalName "RC02_R123") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R123") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R124_131" + (originalName "RC02_R124") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R124") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R123-2_132" + (originalName "RC02_R123-2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R123-2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R124-2_133" + (originalName "RC02_R124-2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R124-2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R125_134" + (originalName "RC02_R125") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R125") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R126_135" + (originalName "RC02_R126") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R126") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R127_136" + (originalName "RC02_R127") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R127") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R128_137" + (originalName "RC02_R128") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R128") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R129_138" + (originalName "RC02_R129") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R129") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "14DIP300_DD39_139" + (originalName "14DIP300_DD39") + (compHeader + (sourceLibrary "") + (numPins 14) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "14DIP300_DD39") + (numPads 14) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + ) + ) + ) + (compDef "14DIP300_DD40_140" + (originalName "14DIP300_DD40") + (compHeader + (sourceLibrary "") + (numPins 14) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "14DIP300_DD40") + (numPads 14) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + ) + ) + ) + (compDef "RC02_R130_141" + (originalName "RC02_R130") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R130") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VT1_VT7_142" + (originalName "VT1_VT7") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT7") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "RC02_R131_143" + (originalName "RC02_R131") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R131") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R132_144" + (originalName "RC02_R132") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R132") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R133_145" + (originalName "RC02_R133") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R133") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C14_146" + (originalName "CAP2_C14") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C14") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C15_147" + (originalName "CAP2_C15") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C15") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C16_148" + (originalName "CAP3_C16") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C16") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R134_149" + (originalName "RC02_R134") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R134") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R135_150" + (originalName "RC02_R135") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R135") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R136_151" + (originalName "RC02_R136") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R136") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R137_152" + (originalName "RC02_R137") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R137") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R138_153" + (originalName "RC02_R138") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R138") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R139_154" + (originalName "RC02_R139") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R139") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R140_155" + (originalName "RC02_R140") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R140") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R141_156" + (originalName "RC02_R141") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R141") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD2_VD3_157" + (originalName "VD2_VD3") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD2_VD3") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD2_VD4_158" + (originalName "VD2_VD4") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD2_VD4") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD2_VD5_159" + (originalName "VD2_VD5") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD2_VD5") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD2_VD6_160" + (originalName "VD2_VD6") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD2_VD6") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R142_161" + (originalName "RC02_R142") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R142") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_XR16_162" + (originalName "RC02_XR16") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_XR16") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R143_163" + (originalName "RC02_R143") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R143") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_XR17_164" + (originalName "RC02_XR17") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_XR17") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "HD2_XR18_165" + (originalName "HD2_XR18") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "HD2_XR18") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "HD2_XR18-2_166" + (originalName "HD2_XR18-2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "HD2_XR18-2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VT1_VT8_167" + (originalName "VT1_VT8") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT8") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "VT1_VT9_168" + (originalName "VT1_VT9") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1_VT9") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "CAP3_C19_169" + (originalName "CAP3_C19") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C19") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C20_170" + (originalName "CAP3_C20") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C20") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C21_171" + (originalName "CAP3_C21") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C21") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C22_172" + (originalName "CAP3_C22") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C22") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C23_173" + (originalName "CAP3_C23") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C23") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C24_174" + (originalName "CAP3_C24") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C24") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C25_175" + (originalName "CAP3_C25") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C25") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C26_176" + (originalName "CAP3_C26") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C26") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C27_177" + (originalName "CAP3_C27") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C27") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C28_178" + (originalName "CAP3_C28") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C28") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C29_179" + (originalName "CAP3_C29") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C29") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C30_180" + (originalName "CAP3_C30") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C30") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C31_181" + (originalName "CAP2_C31") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C31") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C32_182" + (originalName "CAP2_C32") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C32") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C33_183" + (originalName "CAP2_C33") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C33") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C34_184" + (originalName "CAP2_C34") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C34") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C35_185" + (originalName "CAP3_C35") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C35") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C36_186" + (originalName "CAP3_C36") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C36") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "IND_L1_187" + (originalName "IND_L1") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "IND_L1") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R144_188" + (originalName "RC02_R144") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R144") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "34DIP100_XR6_189" + (originalName "34DIP100_XR6") + (compHeader + (sourceLibrary "") + (numPins 34) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "34DIP100_XR6") + (numPads 34) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + ) + ) + ) + (compDef "10DIP100_XR7_190" + (originalName "10DIP100_XR7") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "10DIP100_XR7") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + ) + ) + ) + (compDef "16dip100_XR8_191" + (originalName "16dip100_XR8") + (compHeader + (sourceLibrary "") + (numPins 16) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "16dip100_XR8") + (numPads 16) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + ) + ) + ) + (compDef "10DIP100_XR9_192" + (originalName "10DIP100_XR9") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "10DIP100_XR9") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + ) + ) + ) + (compDef "26DIP100_XR10_193" + (originalName "26DIP100_XR10") + (compHeader + (sourceLibrary "") + (numPins 26) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "26DIP100_XR10") + (numPads 26) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + ) + ) + ) + (compDef "34DIP100_XR11_194" + (originalName "34DIP100_XR11") + (compHeader + (sourceLibrary "") + (numPins 34) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "34DIP100_XR11") + (numPads 34) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + ) + ) + ) + (compDef "40DIP100_XR12_195" + (originalName "40DIP100_XR12") + (compHeader + (sourceLibrary "") + (numPins 40) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "40DIP100_XR12") + (numPads 40) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + ) + ) + ) + (compDef "CON31X2_XR13_196" + (originalName "CON31X2_XR13") + (compHeader + (sourceLibrary "") + (numPins 62) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "A1" (pinName "A1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A2" (pinName "A2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A3" (pinName "A3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A4" (pinName "A4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A5" (pinName "A5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A6" (pinName "A6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A7" (pinName "A7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A8" (pinName "A8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A9" (pinName "A9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A10" (pinName "A10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A11" (pinName "A11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A12" (pinName "A12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A13" (pinName "A13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A14" (pinName "A14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A15" (pinName "A15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A16" (pinName "A16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A17" (pinName "A17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A18" (pinName "A18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A19" (pinName "A19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A20" (pinName "A20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A21" (pinName "A21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A22" (pinName "A22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A23" (pinName "A23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A24" (pinName "A24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A25" (pinName "A25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A26" (pinName "A26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A27" (pinName "A27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A28" (pinName "A28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A29" (pinName "A29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A30" (pinName "A30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A31" (pinName "A31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B1" (pinName "B1") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B2" (pinName "B2") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B3" (pinName "B3") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B4" (pinName "B4") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B5" (pinName "B5") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B6" (pinName "B6") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B7" (pinName "B7") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B8" (pinName "B8") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B9" (pinName "B9") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B10" (pinName "B10") (partNum 1) (symPinNum 41) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B11" (pinName "B11") (partNum 1) (symPinNum 42) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B12" (pinName "B12") (partNum 1) (symPinNum 43) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B13" (pinName "B13") (partNum 1) (symPinNum 44) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B14" (pinName "B14") (partNum 1) (symPinNum 45) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B15" (pinName "B15") (partNum 1) (symPinNum 46) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B16" (pinName "B16") (partNum 1) (symPinNum 47) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B17" (pinName "B17") (partNum 1) (symPinNum 48) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B18" (pinName "B18") (partNum 1) (symPinNum 49) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B19" (pinName "B19") (partNum 1) (symPinNum 50) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B20" (pinName "B20") (partNum 1) (symPinNum 51) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B21" (pinName "B21") (partNum 1) (symPinNum 52) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B22" (pinName "B22") (partNum 1) (symPinNum 53) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B23" (pinName "B23") (partNum 1) (symPinNum 54) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B24" (pinName "B24") (partNum 1) (symPinNum 55) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B25" (pinName "B25") (partNum 1) (symPinNum 56) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B26" (pinName "B26") (partNum 1) (symPinNum 57) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B27" (pinName "B27") (partNum 1) (symPinNum 58) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B28" (pinName "B28") (partNum 1) (symPinNum 59) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B29" (pinName "B29") (partNum 1) (symPinNum 60) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B30" (pinName "B30") (partNum 1) (symPinNum 61) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B31" (pinName "B31") (partNum 1) (symPinNum 62) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CON31X2_XR13") + (numPads 62) + (padPinMap + (padNum 1) (compPinRef "A1") + (padNum 2) (compPinRef "A2") + (padNum 3) (compPinRef "A3") + (padNum 4) (compPinRef "A4") + (padNum 5) (compPinRef "A5") + (padNum 6) (compPinRef "A6") + (padNum 7) (compPinRef "A7") + (padNum 8) (compPinRef "A8") + (padNum 9) (compPinRef "A9") + (padNum 10) (compPinRef "A10") + (padNum 11) (compPinRef "A11") + (padNum 12) (compPinRef "A12") + (padNum 13) (compPinRef "A13") + (padNum 14) (compPinRef "A14") + (padNum 15) (compPinRef "A15") + (padNum 16) (compPinRef "A16") + (padNum 17) (compPinRef "A17") + (padNum 18) (compPinRef "A18") + (padNum 19) (compPinRef "A19") + (padNum 20) (compPinRef "A20") + (padNum 21) (compPinRef "A21") + (padNum 22) (compPinRef "A22") + (padNum 23) (compPinRef "A23") + (padNum 24) (compPinRef "A24") + (padNum 25) (compPinRef "A25") + (padNum 26) (compPinRef "A26") + (padNum 27) (compPinRef "A27") + (padNum 28) (compPinRef "A28") + (padNum 29) (compPinRef "A29") + (padNum 30) (compPinRef "A30") + (padNum 31) (compPinRef "A31") + (padNum 32) (compPinRef "B1") + (padNum 33) (compPinRef "B2") + (padNum 34) (compPinRef "B3") + (padNum 35) (compPinRef "B4") + (padNum 36) (compPinRef "B5") + (padNum 37) (compPinRef "B6") + (padNum 38) (compPinRef "B7") + (padNum 39) (compPinRef "B8") + (padNum 40) (compPinRef "B9") + (padNum 41) (compPinRef "B10") + (padNum 42) (compPinRef "B11") + (padNum 43) (compPinRef "B12") + (padNum 44) (compPinRef "B13") + (padNum 45) (compPinRef "B14") + (padNum 46) (compPinRef "B15") + (padNum 47) (compPinRef "B16") + (padNum 48) (compPinRef "B17") + (padNum 49) (compPinRef "B18") + (padNum 50) (compPinRef "B19") + (padNum 51) (compPinRef "B20") + (padNum 52) (compPinRef "B21") + (padNum 53) (compPinRef "B22") + (padNum 54) (compPinRef "B23") + (padNum 55) (compPinRef "B24") + (padNum 56) (compPinRef "B25") + (padNum 57) (compPinRef "B26") + (padNum 58) (compPinRef "B27") + (padNum 59) (compPinRef "B28") + (padNum 60) (compPinRef "B29") + (padNum 61) (compPinRef "B30") + (padNum 62) (compPinRef "B31") + ) + ) + ) + (compDef "CON31X2_XR14_197" + (originalName "CON31X2_XR14") + (compHeader + (sourceLibrary "") + (numPins 62) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "A1" (pinName "A1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A2" (pinName "A2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A3" (pinName "A3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A4" (pinName "A4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A5" (pinName "A5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A6" (pinName "A6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A7" (pinName "A7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A8" (pinName "A8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A9" (pinName "A9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A10" (pinName "A10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A11" (pinName "A11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A12" (pinName "A12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A13" (pinName "A13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A14" (pinName "A14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A15" (pinName "A15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A16" (pinName "A16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A17" (pinName "A17") (partNum 1) (symPinNum 17) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A18" (pinName "A18") (partNum 1) (symPinNum 18) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A19" (pinName "A19") (partNum 1) (symPinNum 19) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A20" (pinName "A20") (partNum 1) (symPinNum 20) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A21" (pinName "A21") (partNum 1) (symPinNum 21) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A22" (pinName "A22") (partNum 1) (symPinNum 22) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A23" (pinName "A23") (partNum 1) (symPinNum 23) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A24" (pinName "A24") (partNum 1) (symPinNum 24) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A25" (pinName "A25") (partNum 1) (symPinNum 25) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A26" (pinName "A26") (partNum 1) (symPinNum 26) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A27" (pinName "A27") (partNum 1) (symPinNum 27) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A28" (pinName "A28") (partNum 1) (symPinNum 28) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A29" (pinName "A29") (partNum 1) (symPinNum 29) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A30" (pinName "A30") (partNum 1) (symPinNum 30) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A31" (pinName "A31") (partNum 1) (symPinNum 31) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B1" (pinName "B1") (partNum 1) (symPinNum 32) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B2" (pinName "B2") (partNum 1) (symPinNum 33) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B3" (pinName "B3") (partNum 1) (symPinNum 34) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B4" (pinName "B4") (partNum 1) (symPinNum 35) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B5" (pinName "B5") (partNum 1) (symPinNum 36) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B6" (pinName "B6") (partNum 1) (symPinNum 37) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B7" (pinName "B7") (partNum 1) (symPinNum 38) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B8" (pinName "B8") (partNum 1) (symPinNum 39) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B9" (pinName "B9") (partNum 1) (symPinNum 40) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B10" (pinName "B10") (partNum 1) (symPinNum 41) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B11" (pinName "B11") (partNum 1) (symPinNum 42) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B12" (pinName "B12") (partNum 1) (symPinNum 43) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B13" (pinName "B13") (partNum 1) (symPinNum 44) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B14" (pinName "B14") (partNum 1) (symPinNum 45) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B15" (pinName "B15") (partNum 1) (symPinNum 46) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B16" (pinName "B16") (partNum 1) (symPinNum 47) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B17" (pinName "B17") (partNum 1) (symPinNum 48) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B18" (pinName "B18") (partNum 1) (symPinNum 49) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B19" (pinName "B19") (partNum 1) (symPinNum 50) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B20" (pinName "B20") (partNum 1) (symPinNum 51) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B21" (pinName "B21") (partNum 1) (symPinNum 52) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B22" (pinName "B22") (partNum 1) (symPinNum 53) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B23" (pinName "B23") (partNum 1) (symPinNum 54) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B24" (pinName "B24") (partNum 1) (symPinNum 55) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B25" (pinName "B25") (partNum 1) (symPinNum 56) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B26" (pinName "B26") (partNum 1) (symPinNum 57) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B27" (pinName "B27") (partNum 1) (symPinNum 58) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B28" (pinName "B28") (partNum 1) (symPinNum 59) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B29" (pinName "B29") (partNum 1) (symPinNum 60) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B30" (pinName "B30") (partNum 1) (symPinNum 61) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B31" (pinName "B31") (partNum 1) (symPinNum 62) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CON31X2_XR14") + (numPads 62) + (padPinMap + (padNum 1) (compPinRef "A1") + (padNum 2) (compPinRef "A2") + (padNum 3) (compPinRef "A3") + (padNum 4) (compPinRef "A4") + (padNum 5) (compPinRef "A5") + (padNum 6) (compPinRef "A6") + (padNum 7) (compPinRef "A7") + (padNum 8) (compPinRef "A8") + (padNum 9) (compPinRef "A9") + (padNum 10) (compPinRef "A10") + (padNum 11) (compPinRef "A11") + (padNum 12) (compPinRef "A12") + (padNum 13) (compPinRef "A13") + (padNum 14) (compPinRef "A14") + (padNum 15) (compPinRef "A15") + (padNum 16) (compPinRef "A16") + (padNum 17) (compPinRef "A17") + (padNum 18) (compPinRef "A18") + (padNum 19) (compPinRef "A19") + (padNum 20) (compPinRef "A20") + (padNum 21) (compPinRef "A21") + (padNum 22) (compPinRef "A22") + (padNum 23) (compPinRef "A23") + (padNum 24) (compPinRef "A24") + (padNum 25) (compPinRef "A25") + (padNum 26) (compPinRef "A26") + (padNum 27) (compPinRef "A27") + (padNum 28) (compPinRef "A28") + (padNum 29) (compPinRef "A29") + (padNum 30) (compPinRef "A30") + (padNum 31) (compPinRef "A31") + (padNum 32) (compPinRef "B1") + (padNum 33) (compPinRef "B2") + (padNum 34) (compPinRef "B3") + (padNum 35) (compPinRef "B4") + (padNum 36) (compPinRef "B5") + (padNum 37) (compPinRef "B6") + (padNum 38) (compPinRef "B7") + (padNum 39) (compPinRef "B8") + (padNum 40) (compPinRef "B9") + (padNum 41) (compPinRef "B10") + (padNum 42) (compPinRef "B11") + (padNum 43) (compPinRef "B12") + (padNum 44) (compPinRef "B13") + (padNum 45) (compPinRef "B14") + (padNum 46) (compPinRef "B15") + (padNum 47) (compPinRef "B16") + (padNum 48) (compPinRef "B17") + (padNum 49) (compPinRef "B18") + (padNum 50) (compPinRef "B19") + (padNum 51) (compPinRef "B20") + (padNum 52) (compPinRef "B21") + (padNum 53) (compPinRef "B22") + (padNum 54) (compPinRef "B23") + (padNum 55) (compPinRef "B24") + (padNum 56) (compPinRef "B25") + (padNum 57) (compPinRef "B26") + (padNum 58) (compPinRef "B27") + (padNum 59) (compPinRef "B28") + (padNum 60) (compPinRef "B29") + (padNum 61) (compPinRef "B30") + (padNum 62) (compPinRef "B31") + ) + ) + ) + (compDef "14DIP300_DD41_198" + (originalName "14DIP300_DD41") + (compHeader + (sourceLibrary "") + (numPins 14) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "14DIP300_DD41") + (numPads 14) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + ) + ) + ) + (compDef "RC02_R145_199" + (originalName "RC02_R145") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R145") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C37_200" + (originalName "CAP2_C37") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C37") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R146_201" + (originalName "RC02_R146") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R146") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "16DIP300_DD42_202" + (originalName "16DIP300_DD42") + (compHeader + (sourceLibrary "") + (numPins 16) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 11) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 12) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 13) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 14) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 15) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 16) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "16DIP300_DD42") + (numPads 16) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + ) + ) + ) + (compDef "RC02_R153_203" + (originalName "RC02_R153") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R153") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R154_204" + (originalName "RC02_R154") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R154") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R155_205" + (originalName "RC02_R155") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R155") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R156_206" + (originalName "RC02_R156") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R156") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R157_207" + (originalName "RC02_R157") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R157") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R158_208" + (originalName "RC02_R158") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R158") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R159_209" + (originalName "RC02_R159") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R159") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R160_210" + (originalName "RC02_R160") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R160") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R161_211" + (originalName "RC02_R161") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R161") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "10DIP100_XR15_212" + (originalName "10DIP100_XR15") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 3) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 4) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 5) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 6) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 7) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 8) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 9) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 10) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "10DIP100_XR15") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + ) + ) + ) + (compDef "VD2_VD8_213" + (originalName "VD2_VD8") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD2_VD8") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP2_C40_214" + (originalName "CAP2_C40") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2_C40") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R162_215" + (originalName "RC02_R162") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R162") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "PIN_PIN-6_216" + (originalName "PIN_PIN-6") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PIN_PIN-6") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "1") + ) + ) + ) + (compDef "PIN_PIN-7_217" + (originalName "PIN_PIN-7") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PIN_PIN-7") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "1") + ) + ) + ) + (compDef "CAP3_C42_218" + (originalName "CAP3_C42") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C42") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_C43_219" + (originalName "CAP3_C43") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3_C43") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R165_220" + (originalName "RC02_R165") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R165") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD11_221" + (originalName "VD3_VD11") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD11") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD1_222" + (originalName "VD3_VD1") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD1") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD13_223" + (originalName "VD3_VD13") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD13") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD14_224" + (originalName "VD3_VD14") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD14") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD12_225" + (originalName "VD3_VD12") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD12") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD15_226" + (originalName "VD3_VD15") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD15") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD2-2_227" + (originalName "VD3_VD2-2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD2-2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD3_VD17_228" + (originalName "VD3_VD17") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD3_VD17") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD2_VD***_229" + (originalName "VD2_VD***") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD2_VD***") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R**_230" + (originalName "RC02_R**") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R**") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R**-2_231" + (originalName "RC02_R**-2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R**-2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R**-3_232" + (originalName "RC02_R**-3") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R**-3") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R**-4_233" + (originalName "RC02_R**-4") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R**-4") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R**-5_234" + (originalName "RC02_R**-5") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R**-5") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_R**-6_235" + (originalName "RC02_R**-6") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 2) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_R**-6") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + 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b/pcb/converted/readme.txt @@ -0,0 +1,38 @@ +SPRINT05.BD1 - , SPRINT05.PCB ghb OrCAD 32bit version +SPRINT05.max - SPRINT05.BD1 OrCAD 7.10 +SPRINT05.MIN - , OrCAD 7.10 DipTrace +SPRINT05_PCAD.PCB - , DipTrace + + + "" : + +1. *.brd orcad 2.xx, PCB2 ( ) + +2. 386+, 32-. 3., ( 2. ). + frompcb2.exe, 16- PCB2 32- PCB386+ + +3. 32- "" *.max ( 2003 ). + tomax.exe , . 9 . + + PCB386+ orcad layout . + +4. *.max , " sp2003 (https://reverse.sprinter.ru/orcad920)". + +, , : +orcad max -> MIN Interchange ( DipTrace) + MIN Interchange -> DipTrace + DipTrace -> pcad ascii + + + + : +1. ( ). , )) +2. . , . +3. assy . +4. . , . +5. () . , . + + + + + , RomanRom2 diff --git a/pcb/docs/PCAD_2006_ASCII.pdf b/pcb/docs/PCAD_2006_ASCII.pdf new file mode 100644 index 0000000..fc06807 Binary files /dev/null and b/pcb/docs/PCAD_2006_ASCII.pdf differ diff --git a/pcb/parsed/SPRINT05.BRD b/pcb/parsed/SPRINT05.BRD new file mode 100644 index 0000000..9e941c5 Binary files /dev/null and b/pcb/parsed/SPRINT05.BRD differ diff --git a/pcb/parsed/readme.txt b/pcb/parsed/readme.txt new file mode 100644 index 0000000..100478e --- /dev/null +++ b/pcb/parsed/readme.txt @@ -0,0 +1,14 @@ +, OrCAD 2.00 p-cad ASCII version 7.5 + +SPRINT05.BRD - OrCAD 2.00 +sprint05_pcad.pcb - +sprint05_pcad_fixed.pcb - +sprint05_pcad_fixed_bot.png +sprint05_pcad_fixed_top.png + +sprint05_pcad_fixed.pcb - , DRC. , ) + +1. via 5-10mil, DRC +2. +3. +4. , . . diff --git a/pcb/parsed/sprint05_pcad.pcb b/pcb/parsed/sprint05_pcad.pcb new file mode 100644 index 0000000..55cdb64 --- /dev/null +++ b/pcb/parsed/sprint05_pcad.pcb @@ -0,0 +1,20286 @@ +ACCEL_ASCII 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Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") 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(padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "32DIP300_1_1" + (originalName "32DIP300_1") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32DIP300_1") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "20DIP300_1" + (originalName "20DIP300") + (compHeader + (sourceLibrary "") + (numPins 20) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "20DIP300") + (numPads 20) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + ) + ) + ) + (compDef "PLATA_1" + (originalName "PLATA") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PLATA") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "16DIP300_1" + (originalName "16DIP300") + (compHeader + (sourceLibrary "") + (numPins 16) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "16DIP300") + (numPads 16) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + ) + ) + ) + (compDef "QFP100_1" + (originalName "QFP100") + (compHeader + (sourceLibrary "") + (numPins 100) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "41" (pinName "41") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "42" (pinName "42") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "43" (pinName "43") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "44" (pinName "44") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "45" (pinName "45") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "46" (pinName "46") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "47" (pinName "47") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "48" (pinName "48") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "49" (pinName "49") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "50" (pinName "50") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "51" (pinName "51") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "52" (pinName "52") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "53" (pinName "53") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "54" (pinName "54") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "55" (pinName "55") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "56" (pinName "56") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "57" (pinName "57") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "58" (pinName "58") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "59" (pinName "59") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "60" (pinName "60") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "61" (pinName "61") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "62" (pinName "62") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "63" (pinName "63") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "64" (pinName "64") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "65" (pinName "65") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "66" (pinName "66") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "67" (pinName "67") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "68" (pinName "68") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "69" (pinName "69") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "70" (pinName "70") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "71" (pinName "71") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "72" (pinName "72") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "73" (pinName "73") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "74" (pinName "74") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "75" (pinName "75") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "76" (pinName "76") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "77" (pinName "77") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "78" (pinName "78") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "79" (pinName "79") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "80" (pinName "80") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "81" (pinName "81") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "82" (pinName "82") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "83" (pinName "83") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "84" (pinName "84") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "85" (pinName "85") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "86" (pinName "86") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "87" (pinName "87") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "88" (pinName "88") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "89" (pinName "89") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "90" (pinName "90") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "91" (pinName "91") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "92" (pinName "92") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "93" (pinName "93") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "94" (pinName "94") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "95" (pinName "95") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "96" (pinName "96") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "97" (pinName "97") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "98" (pinName "98") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "99" (pinName "99") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "100" (pinName "100") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "QFP100") + (numPads 100) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + (padNum 41) (compPinRef "41") + (padNum 42) (compPinRef "42") + (padNum 43) (compPinRef "43") + (padNum 44) (compPinRef "44") + (padNum 45) (compPinRef "45") + (padNum 46) (compPinRef "46") + (padNum 47) (compPinRef "47") + (padNum 48) (compPinRef "48") + (padNum 49) (compPinRef "49") + (padNum 50) (compPinRef "50") + (padNum 51) (compPinRef "51") + (padNum 52) (compPinRef "52") + (padNum 53) (compPinRef "53") + (padNum 54) (compPinRef "54") + (padNum 55) (compPinRef "55") + (padNum 56) (compPinRef "56") + (padNum 57) (compPinRef "57") + (padNum 58) (compPinRef "58") + (padNum 59) (compPinRef "59") + (padNum 60) (compPinRef "60") + (padNum 61) (compPinRef "61") + (padNum 62) (compPinRef "62") + (padNum 63) (compPinRef "63") + (padNum 64) (compPinRef "64") + (padNum 65) (compPinRef "65") + (padNum 66) (compPinRef "66") + (padNum 67) (compPinRef "67") + (padNum 68) (compPinRef "68") + (padNum 69) (compPinRef "69") + (padNum 70) (compPinRef "70") + (padNum 71) (compPinRef "71") + (padNum 72) (compPinRef "72") + (padNum 73) (compPinRef "73") + (padNum 74) (compPinRef "74") + (padNum 75) (compPinRef "75") + (padNum 76) (compPinRef "76") + (padNum 77) (compPinRef "77") + (padNum 78) (compPinRef "78") + (padNum 79) (compPinRef "79") + (padNum 80) (compPinRef "80") + (padNum 81) (compPinRef "81") + (padNum 82) (compPinRef "82") + (padNum 83) (compPinRef "83") + (padNum 84) (compPinRef "84") + (padNum 85) (compPinRef "85") + (padNum 86) (compPinRef "86") + (padNum 87) (compPinRef "87") + (padNum 88) (compPinRef "88") + (padNum 89) (compPinRef "89") + (padNum 90) (compPinRef "90") + (padNum 91) (compPinRef "91") + (padNum 92) (compPinRef "92") + (padNum 93) (compPinRef "93") + (padNum 94) (compPinRef "94") + (padNum 95) (compPinRef "95") + (padNum 96) (compPinRef "96") + (padNum 97) (compPinRef "97") + (padNum 98) (compPinRef "98") + (padNum 99) (compPinRef "99") + (padNum 100) (compPinRef "100") + ) + ) + ) + (compDef "ONC5_1" + (originalName "ONC5") + (compHeader + (sourceLibrary "") + (numPins 9) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X1" (pinName "X1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X2" (pinName "X2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X3" (pinName "X3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X4" (pinName "X4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "ONC5") + (numPads 9) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "X1") + (padNum 7) (compPinRef "X2") + (padNum 8) (compPinRef "X3") + (padNum 9) (compPinRef "X4") + ) + ) + ) + (compDef "XPOWER_1" + (originalName "XPOWER") + (compHeader + (sourceLibrary "") + (numPins 6) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "XPOWER") + (numPads 6) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + ) + ) + ) + (compDef "SIMM72_1" + (originalName "SIMM72") + (compHeader + (sourceLibrary "") + (numPins 75) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "41" (pinName "41") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "42" (pinName "42") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "43" (pinName "43") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "44" (pinName "44") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "45" (pinName "45") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "46" (pinName "46") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "47" (pinName "47") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "48" (pinName "48") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "49" (pinName "49") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "50" (pinName "50") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "51" (pinName "51") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "52" (pinName "52") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "53" (pinName "53") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "54" (pinName "54") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "55" (pinName "55") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "56" (pinName "56") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "57" (pinName "57") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "58" (pinName "58") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "59" (pinName "59") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "60" (pinName "60") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "61" (pinName "61") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "62" (pinName "62") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "63" (pinName "63") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "64" (pinName "64") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "65" (pinName "65") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "66" (pinName "66") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "67" (pinName "67") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "68" (pinName "68") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "69" (pinName "69") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "70" (pinName "70") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "71" (pinName "71") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "72" (pinName "72") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X1" (pinName "X1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X3" (pinName "X3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "X2" (pinName "X2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "SIMM72") + (numPads 75) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + (padNum 41) (compPinRef "41") + (padNum 42) (compPinRef "42") + (padNum 43) (compPinRef "43") + (padNum 44) (compPinRef "44") + (padNum 45) (compPinRef "45") + (padNum 46) (compPinRef "46") + (padNum 47) (compPinRef "47") + (padNum 48) (compPinRef "48") + (padNum 49) (compPinRef "49") + (padNum 50) (compPinRef "50") + (padNum 51) (compPinRef "51") + (padNum 52) (compPinRef "52") + (padNum 53) (compPinRef "53") + (padNum 54) (compPinRef "54") + (padNum 55) (compPinRef "55") + (padNum 56) (compPinRef "56") + (padNum 57) (compPinRef "57") + (padNum 58) (compPinRef "58") + (padNum 59) (compPinRef "59") + (padNum 60) (compPinRef "60") + (padNum 61) (compPinRef "61") + (padNum 62) (compPinRef "62") + (padNum 63) (compPinRef "63") + (padNum 64) (compPinRef "64") + (padNum 65) (compPinRef "65") + (padNum 66) (compPinRef "66") + (padNum 67) (compPinRef "67") + (padNum 68) (compPinRef "68") + (padNum 69) (compPinRef "69") + (padNum 70) (compPinRef "70") + (padNum 71) (compPinRef "71") + (padNum 72) (compPinRef "72") + (padNum 73) (compPinRef "X1") + (padNum 74) (compPinRef "X3") + (padNum 75) (compPinRef "X2") + ) + ) + ) + (compDef "PIN_1" + (originalName "PIN") + (compHeader + (sourceLibrary "") + (numPins 1) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "PIN") + (numPads 1) + (padPinMap + (padNum 1) (compPinRef "1") + ) + ) + ) + (compDef "VT1_1" + (originalName "VT1") + (compHeader + (sourceLibrary "") + (numPins 3) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VT1") + (numPads 3) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + ) + ) + ) + (compDef "RC02_1" + (originalName "RC02") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "40DIP600_1" + (originalName "40DIP600") + (compHeader + (sourceLibrary "") + (numPins 40) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "40DIP600") + (numPads 40) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + ) + ) + ) + (compDef "HD10_1" + (originalName "HD10") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "HD10") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "2") + (padNum 2) (compPinRef "3") + (padNum 3) (compPinRef "4") + (padNum 4) (compPinRef "5") + (padNum 5) (compPinRef "6") + (padNum 6) (compPinRef "7") + (padNum 7) (compPinRef "8") + (padNum 8) (compPinRef "9") + (padNum 9) (compPinRef "10") + (padNum 10) (compPinRef "1") + ) + ) + ) + (compDef "RC05_1" + (originalName "RC05") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC05") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "14DIP300_1" + (originalName "14DIP300") + (compHeader + (sourceLibrary "") + (numPins 14) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "14DIP300") + (numPads 14) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + ) + ) + ) + (compDef "CAP1_1" + (originalName "CAP1") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP1") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "2200MKF_1" + (originalName "2200MKF") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "2200MKF") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "RC02_12_1" + (originalName "RC02_12") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "RC02_12") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "32DIP600_1" + (originalName "32DIP600") + (compHeader + (sourceLibrary "") + (numPins 32) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "32DIP600") + (numPads 32) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + ) + ) + ) + (compDef "8DIP300_1" + (originalName "8DIP300") + (compHeader + (sourceLibrary "") + (numPins 8) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "8DIP300") + (numPads 8) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + ) + ) + ) + (compDef "EL05_1" + (originalName "EL05") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "EL05") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "10DIP100_1" + (originalName "10DIP100") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "10DIP100") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + ) + ) + ) + (compDef "24DIP600_1" + (originalName "24DIP600") + (compHeader + (sourceLibrary "") + (numPins 24) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "24DIP600") + (numPads 24) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + ) + ) + ) + (compDef "208QFP10_1" + (originalName "208QFP10") + (compHeader + (sourceLibrary "") + (numPins 208) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "41" (pinName "41") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "42" (pinName "42") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "43" (pinName "43") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "44" (pinName "44") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "45" (pinName "45") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "46" (pinName "46") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "47" (pinName "47") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "48" (pinName "48") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "49" (pinName "49") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "50" (pinName "50") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "51" (pinName "51") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "52" (pinName "52") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "53" (pinName "53") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "54" (pinName "54") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "55" (pinName "55") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "56" (pinName "56") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "57" (pinName "57") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "58" (pinName "58") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "59" (pinName "59") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "60" (pinName "60") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "61" (pinName "61") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "62" (pinName "62") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "63" (pinName "63") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "64" (pinName "64") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "65" (pinName "65") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "66" (pinName "66") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "67" (pinName "67") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "68" (pinName "68") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "69" (pinName "69") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "70" (pinName "70") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "71" (pinName "71") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "72" (pinName "72") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "73" (pinName "73") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "74" (pinName "74") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "75" (pinName "75") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "76" (pinName "76") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "77" (pinName "77") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "78" (pinName "78") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "79" (pinName "79") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "80" (pinName "80") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "81" (pinName "81") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "82" (pinName "82") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "83" (pinName "83") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "84" (pinName "84") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "85" (pinName "85") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "86" (pinName "86") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "87" (pinName "87") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "88" (pinName "88") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "89" (pinName "89") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "90" (pinName "90") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "91" (pinName "91") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "92" (pinName "92") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "93" (pinName "93") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "94" (pinName "94") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "95" (pinName "95") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "96" (pinName "96") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "97" (pinName "97") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "98" (pinName "98") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "99" (pinName "99") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "100" (pinName "100") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "101" (pinName "101") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "102" (pinName "102") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "103" (pinName "103") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "104" (pinName "104") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "105" (pinName "105") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "106" (pinName "106") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "107" (pinName "107") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "108" (pinName "108") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "109" (pinName "109") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "110" (pinName "110") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "111" (pinName "111") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "112" (pinName "112") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "113" (pinName "113") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "114" (pinName "114") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "115" (pinName "115") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "116" (pinName "116") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "117" (pinName "117") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "118" (pinName "118") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "119" (pinName "119") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "120" (pinName "120") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "121" (pinName "121") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "122" (pinName "122") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "123" (pinName "123") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "124" (pinName "124") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "125" (pinName "125") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "126" (pinName "126") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "127" (pinName "127") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "128" (pinName "128") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "129" (pinName "129") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "130" (pinName "130") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "131" (pinName "131") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "132" (pinName "132") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "133" (pinName "133") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "134" (pinName "134") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "135" (pinName "135") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "136" (pinName "136") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "137" (pinName "137") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "138" (pinName "138") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "139" (pinName "139") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "140" (pinName "140") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "141" (pinName "141") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "142" (pinName "142") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "143" (pinName "143") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "144" (pinName "144") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "145" (pinName "145") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "146" (pinName "146") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "147" (pinName "147") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "148" (pinName "148") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "149" (pinName "149") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "150" (pinName "150") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "151" (pinName "151") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "152" (pinName "152") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "153" (pinName "153") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "154" (pinName "154") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "155" (pinName "155") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "156" (pinName "156") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "157" (pinName "157") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "158" (pinName "158") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "159" (pinName "159") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "160" (pinName "160") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "161" (pinName "161") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "162" (pinName "162") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "163" (pinName "163") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "164" (pinName "164") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "165" (pinName "165") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "166" (pinName "166") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "167" (pinName "167") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "168" (pinName "168") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "169" (pinName "169") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "170" (pinName "170") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "171" (pinName "171") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "172" (pinName "172") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "173" (pinName "173") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "174" (pinName "174") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "175" (pinName "175") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "176" (pinName "176") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "177" (pinName "177") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "178" (pinName "178") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "179" (pinName "179") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "180" (pinName "180") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "181" (pinName "181") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "182" (pinName "182") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "183" (pinName "183") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "184" (pinName "184") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "185" (pinName "185") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "186" (pinName "186") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "187" (pinName "187") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "188" (pinName "188") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "189" (pinName "189") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "190" (pinName "190") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "191" (pinName "191") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "192" (pinName "192") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "193" (pinName "193") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "194" (pinName "194") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "195" (pinName "195") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "196" (pinName "196") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "197" (pinName "197") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "198" (pinName "198") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "199" (pinName "199") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "200" (pinName "200") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "201" (pinName "201") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "202" (pinName "202") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "203" (pinName "203") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "204" (pinName "204") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "205" (pinName "205") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "206" (pinName "206") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "207" (pinName "207") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "208" (pinName "208") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "208QFP10") + (numPads 208) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "3") + (padNum 3) (compPinRef "4") + (padNum 4) (compPinRef "5") + (padNum 5) (compPinRef "6") + (padNum 6) (compPinRef "7") + (padNum 7) (compPinRef "8") + (padNum 8) (compPinRef "9") + (padNum 9) (compPinRef "10") + (padNum 10) (compPinRef "11") + (padNum 11) (compPinRef "12") + (padNum 12) (compPinRef "13") + (padNum 13) (compPinRef "14") + (padNum 14) (compPinRef "15") + (padNum 15) (compPinRef "16") + (padNum 16) (compPinRef "17") + (padNum 17) (compPinRef "18") + (padNum 18) (compPinRef "19") + (padNum 19) (compPinRef "20") + (padNum 20) (compPinRef "21") + (padNum 21) (compPinRef "22") + (padNum 22) (compPinRef "23") + (padNum 23) (compPinRef "24") + (padNum 24) (compPinRef "25") + (padNum 25) (compPinRef "26") + (padNum 26) (compPinRef "27") + (padNum 27) (compPinRef "28") + (padNum 28) (compPinRef "29") + (padNum 29) (compPinRef "30") + (padNum 30) (compPinRef "31") + (padNum 31) (compPinRef "32") + (padNum 32) (compPinRef "33") + (padNum 33) (compPinRef "34") + (padNum 34) (compPinRef "35") + (padNum 35) (compPinRef "36") + (padNum 36) (compPinRef "37") + (padNum 37) (compPinRef "38") + (padNum 38) (compPinRef "39") + (padNum 39) (compPinRef "40") + (padNum 40) (compPinRef "41") + (padNum 41) (compPinRef "42") + (padNum 42) (compPinRef "43") + (padNum 43) (compPinRef "44") + (padNum 44) (compPinRef "45") + (padNum 45) (compPinRef "46") + (padNum 46) (compPinRef "47") + (padNum 47) (compPinRef "48") + (padNum 48) (compPinRef "49") + (padNum 49) (compPinRef "50") + (padNum 50) (compPinRef "51") + (padNum 51) (compPinRef "52") + (padNum 52) (compPinRef "2") + (padNum 53) (compPinRef "53") + (padNum 54) (compPinRef "54") + (padNum 55) (compPinRef "55") + (padNum 56) (compPinRef "56") + (padNum 57) (compPinRef "57") + (padNum 58) (compPinRef "58") + (padNum 59) (compPinRef "59") + (padNum 60) (compPinRef "60") + (padNum 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(originalName "CAP2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "CAP3_1" + (originalName "CAP3") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "CAP3") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "VD2_1" + (originalName "VD2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "VD2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "HD2_1" + (originalName "HD2") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "HD2") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "IND_1" + (originalName "IND") + (compHeader + (sourceLibrary "") + (numPins 2) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "IND") + (numPads 2) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + ) + ) + ) + (compDef "34DIP100_1" + (originalName "34DIP100") + (compHeader + (sourceLibrary "") + (numPins 34) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "34DIP100") + (numPads 34) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + ) + ) + ) + (compDef "10DIP100_23_1" + (originalName "10DIP100_23") + (compHeader + (sourceLibrary "") + (numPins 10) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "10DIP100_23") + (numPads 10) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + ) + ) + ) + (compDef "16DIP100_1" + (originalName "16DIP100") + (compHeader + (sourceLibrary "") + (numPins 16) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "16DIP100") + (numPads 16) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + ) + ) + ) + (compDef "26DIP100_1" + (originalName "26DIP100") + (compHeader + (sourceLibrary "") + (numPins 26) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "26DIP100") + (numPads 26) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + ) + ) + ) + (compDef "34DIP100_31_1" + (originalName "34DIP100_31") + (compHeader + (sourceLibrary "") + (numPins 34) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "34DIP100_31") + (numPads 34) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + ) + ) + ) + (compDef "40DIP100_1" + (originalName "40DIP100") + (compHeader + (sourceLibrary "") + (numPins 40) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "1" (pinName "1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "2" (pinName "2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "3" (pinName "3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "4" (pinName "4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "5" (pinName "5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "6" (pinName "6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "7" (pinName "7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "8" (pinName "8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "9" (pinName "9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "10" (pinName "10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "11" (pinName "11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "12" (pinName "12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "13" (pinName "13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "14" (pinName "14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "15" (pinName "15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "16" (pinName "16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "17" (pinName "17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "18" (pinName "18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "19" (pinName "19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "20" (pinName "20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "21" (pinName "21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "22" (pinName "22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "23" (pinName "23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "24" (pinName "24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "25" (pinName "25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "26" (pinName "26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "27" (pinName "27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "28" (pinName "28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "29" (pinName "29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "30" (pinName "30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "31" (pinName "31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "32" (pinName "32") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "33" (pinName "33") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "34" (pinName "34") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "35" (pinName "35") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "36" (pinName "36") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "37" (pinName "37") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "38" (pinName "38") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "39" (pinName "39") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "40" (pinName "40") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (attachedPattern (patternNum 1) (patternName "40DIP100") + (numPads 40) + (padPinMap + (padNum 1) (compPinRef "1") + (padNum 2) (compPinRef "2") + (padNum 3) (compPinRef "3") + (padNum 4) (compPinRef "4") + (padNum 5) (compPinRef "5") + (padNum 6) (compPinRef "6") + (padNum 7) (compPinRef "7") + (padNum 8) (compPinRef "8") + (padNum 9) (compPinRef "9") + (padNum 10) (compPinRef "10") + (padNum 11) (compPinRef "11") + (padNum 12) (compPinRef "12") + (padNum 13) (compPinRef "13") + (padNum 14) (compPinRef "14") + (padNum 15) (compPinRef "15") + (padNum 16) (compPinRef "16") + (padNum 17) (compPinRef "17") + (padNum 18) (compPinRef "18") + (padNum 19) (compPinRef "19") + (padNum 20) (compPinRef "20") + (padNum 21) (compPinRef "21") + (padNum 22) (compPinRef "22") + (padNum 23) (compPinRef "23") + (padNum 24) (compPinRef "24") + (padNum 25) (compPinRef "25") + (padNum 26) (compPinRef "26") + (padNum 27) (compPinRef "27") + (padNum 28) (compPinRef "28") + (padNum 29) (compPinRef "29") + (padNum 30) (compPinRef "30") + (padNum 31) (compPinRef "31") + (padNum 32) (compPinRef "32") + (padNum 33) (compPinRef "33") + (padNum 34) (compPinRef "34") + (padNum 35) (compPinRef "35") + (padNum 36) (compPinRef "36") + (padNum 37) (compPinRef "37") + (padNum 38) (compPinRef "38") + (padNum 39) (compPinRef "39") + (padNum 40) (compPinRef "40") + ) + ) + ) + (compDef "CON31X2_1" + (originalName "CON31X2") + (compHeader + (sourceLibrary "") + (numPins 62) + (numParts 1) + (alts (ieeeAlt True) (deMorganAlt False)) + (refDesPrefix "U") + ) + (compPin "A1" (pinName "A1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A2" (pinName "A2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A3" (pinName "A3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A4" (pinName "A4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A5" (pinName "A5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A6" (pinName "A6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A7" (pinName "A7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A8" (pinName "A8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A9" (pinName "A9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A10" (pinName "A10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A11" (pinName "A11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A12" (pinName "A12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A13" (pinName "A13") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A14" (pinName "A14") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A15" (pinName "A15") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A16" (pinName "A16") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A17" (pinName "A17") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A18" (pinName "A18") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A19" (pinName "A19") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A20" (pinName "A20") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A21" (pinName "A21") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A22" (pinName "A22") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A23" (pinName "A23") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A24" (pinName "A24") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A25" (pinName "A25") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A26" (pinName "A26") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A27" (pinName "A27") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A28" (pinName "A28") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A29" (pinName "A29") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A30" (pinName "A30") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "A31" (pinName "A31") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B1" (pinName "B1") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B2" (pinName "B2") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B3" (pinName "B3") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B4" (pinName "B4") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B5" (pinName "B5") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B6" (pinName "B6") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B7" (pinName "B7") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B8" (pinName "B8") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B9" (pinName "B9") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B10" (pinName "B10") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B11" (pinName "B11") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B12" (pinName "B12") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) ) + (compPin "B13" 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(width 40) (netNameRef "VCC") ) + (line (pt 6700 5725) (pt 6575 5600) (width 40) (netNameRef "VCC") ) + (line (pt 6575 5600) (pt 6425 5600) (width 40) (netNameRef "VCC") ) + (line (pt 6425 5600) (pt 6275 5600) (width 40) (netNameRef "VCC") ) + (line (pt 6350 5925) (pt 6450 5925) (width 40) (netNameRef "VCC") ) + (line (pt 6450 6525) (pt 6450 6425) (width 20) (netNameRef "GND") ) + (line (pt 6350 6525) (pt 6350 6425) (width 20) (netNameRef "GND") ) + (line (pt 6350 6325) (pt 6350 6225) (width 20) (netNameRef "KBD_DD") ) + (line (pt 6450 6225) (pt 6450 6325) (width 20) (netNameRef "KBD_CC") ) + (line (pt 6450 6125) (pt 6450 6025) (width 20) (netNameRef "KBD_CLK") ) + (line (pt 6350 6025) (pt 6350 6125) (width 20) (netNameRef "KBD_DAT") ) + (line (pt 7800 5250) (pt 7900 5250) (width 20) (netNameRef "GND") ) + (line (pt 7900 5250) (pt 7900 5200) (width 20) (netNameRef "GND") ) + (line (pt 7150 5725) (pt 7150 5950) (width 40) (netNameRef "VCC") ) + (line (pt 7400 5250) (pt 7450 5250) (width 8) (netNameRef "WG12V") ) + (line (pt 7450 5250) (pt 7550 5350) (width 8) (netNameRef "WG12V") ) + (line (pt 7350 5350) (pt 7350 5425) (width 20) (netNameRef "VCC") ) + (line (pt 7350 5425) (pt 7425 5500) (width 20) (netNameRef "VCC") ) + (line (pt 7425 5500) (pt 7425 5725) (width 20) (netNameRef "VCC") ) + (line (pt 7425 5725) (pt 7675 5725) (width 20) (netNameRef "VCC") ) + (line (pt 7675 5725) (pt 7800 5600) (width 20) (netNameRef "VCC") ) + (line (pt 7400 5250) (pt 7355 5295) (width 8) (netNameRef "WG12V") ) + (line (pt 7355 5295) (pt 6995 5295) (width 8) (netNameRef "WG12V") ) + (line (pt 6995 5295) (pt 6950 5250) (width 8) (netNameRef "WG12V") ) + (line (pt 7300 4950) (pt 7200 4950) (width 20) (netNameRef "VCC") ) + (line (pt 7600 5150) (pt 7800 5350) (width 20) (netNameRef "VCC") ) + (line (pt 7800 5350) (pt 7800 5600) (width 20) (netNameRef "VCC") ) + (text (pt 1020 1075) "(C) PeterS" (textStyleRef "txt0") (rotation 0) (isFlipped True) (justify Center) ) + (text (pt 1000 1975) "Sprinter" (textStyleRef "txt0") (rotation 0) (isFlipped True) (justify Center) ) + (text (pt 5575 6375) "Sprinter" (textStyleRef "txt2") (rotation 0) (isFlipped True) (justify Center) ) + (text (pt 3325 2775) "99.08.18" (textStyleRef "txt1") (rotation 0) (isFlipped True) (justify Center) ) + (text (pt 3325 2900) "Sprinter" (textStyleRef "txt1") (rotation 0) (isFlipped True) (justify Center) ) + (text (pt 3275 2650) "(C)Peters+" (textStyleRef "txt1") (rotation 0) (isFlipped True) (justify Center) ) + ) + (layerContents (layerNumRef 3) + (line (pt 1100 350) (pt 8150 350) (width 8) ) + (line (pt 8150 350) (pt 8150 6550) (width 8) ) + (line (pt 8150 6550) (pt 1100 6550) (width 8) ) + (line (pt 1100 6550) (pt 300 6550) (width 8) ) + (line (pt 300 6550) (pt 300 350) (width 8) ) + (line (pt 300 350) (pt 1100 350) (width 8) ) + ) + (layerSets + (layerSet "All Layers" "1" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11") + (layerSet "Signal Layers" "1" "1" "2") + (layerSet "Plane Layers" "-1") + (layerSet "Nonsignal Layers" "6" "6" "3" "4" "5" "7" "8" "9" "10" "11") + (layerSet "TOP" "1" "1" "6" "3") + (layerSet "BOT" "2" "2" "3" "7") + ) + (layersStackup + (layerStackupData + (layerStackupName "Top") + (layerStackupMaterial "") + (layerStackupThickness "") + (layerStackupDielectricConstant "") + (layerStackupDisplay True) + ) + (layerStackupData + (layerStackupName "Bottom") + (layerStackupMaterial "") + (layerStackupThickness "") + (layerStackupDielectricConstant "") + (layerStackupDisplay True) + ) + ) +) diff --git a/pcb/parsed/sprint05_pcad_fixed.pcb b/pcb/parsed/sprint05_pcad_fixed.pcb new file mode 100644 index 0000000..f4ae744 Binary files /dev/null and b/pcb/parsed/sprint05_pcad_fixed.pcb differ diff --git a/pcb/parsed/sprint05_pcad_fixed_bot.png b/pcb/parsed/sprint05_pcad_fixed_bot.png new file mode 100644 index 0000000..344bbc5 Binary files /dev/null and b/pcb/parsed/sprint05_pcad_fixed_bot.png differ diff --git a/pcb/parsed/sprint05_pcad_fixed_top.png b/pcb/parsed/sprint05_pcad_fixed_top.png new file mode 100644 index 0000000..57aecc4 Binary files /dev/null and b/pcb/parsed/sprint05_pcad_fixed_top.png differ diff --git a/pcb/php-builder/builder.php b/pcb/php-builder/builder.php new file mode 100644 index 0000000..b23681c --- /dev/null +++ b/pcb/php-builder/builder.php @@ -0,0 +1,113 @@ +HDR['comp_count_real']['v']."
"; +$pcad_lib = ""; +for($i=0; $iPATTERN_STYLE); $i++) +{ + $PTR = $pcb->PATTERN_STYLE[$i]; + + $pcad_lib .= " (compDef \"".$PTR['name']."_1\"\r\n"; + $pcad_lib .= " (originalName \"".$PTR['name']."\")\r\n"; + $pcad_lib .= " (compHeader\r\n"; + $pcad_lib .= " (sourceLibrary \"\")\r\n"; + $pcad_lib .= " (numPins ".$PTR['pads_count'].")\r\n"; + $pcad_lib .= " (numParts 1)\r\n"; + $pcad_lib .= " (alts (ieeeAlt True) (deMorganAlt False))\r\n"; + $pcad_lib .= " (refDesPrefix \"U\")\r\n"; + $pcad_lib .= " )\r\n"; + + for ($j=1; $j<=$PTR['pads_count']; $j++) + { + $pad_des = $PTR['pad'.$j.'_des']; + $pcad_lib .= " (compPin \"$pad_des\" (pinName \"$pad_des\") (partNum 1) (symPinNum 1) (gateEq 1) (pinEq 0) (pinType Input) )\r\n"; + } + + $pcad_lib .= " (attachedPattern (patternNum 1) (patternName \"".$PTR['name']."\")\r\n"; + $pcad_lib .= " (numPads ".$PTR['pads_count'].")\r\n"; + $pcad_lib .= " (padPinMap\r\n"; + + for ($j=1; $j<=$PTR['pads_count']; $j++) + { + $pad_des = $PTR['pad'.$j.'_des']; + $pcad_lib .= " (padNum $j) (compPinRef \"$pad_des\")\r\n"; + } + + $pcad_lib .= " )\r\n"; + $pcad_lib .= " )\r\n"; + $pcad_lib .= " )\r\n"; + +} +file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX); diff --git a/pcb/php-builder/lib_pad.php b/pcb/php-builder/lib_pad.php new file mode 100644 index 0000000..43051fd --- /dev/null +++ b/pcb/php-builder/lib_pad.php @@ -0,0 +1,96 @@ +PAD_STYLE); $i++) + { + $style = $pcb->PAD_STYLE[$i]; + if ( + ($style['shape'] == $pad['shape']) + and ($style['width'] == $pad['width']) + and ($style['height'] == $pad['height']) + and ($style['hole_dia'] == $pad['hole_dia']) + and ($style['flags'] == $pad['flags']) + ) + return $style['name']; + } + + return false; +} +function padAddStyle($pcb, $pad) +{ + $st = padGetStyle($pcb, $pad); + if ($st) + return false; + + $i = sizeof($pcb->PAD_STYLE); + $pcb->PAD_STYLE[$i]['shape'] = $pad['shape']; + $pcb->PAD_STYLE[$i]['width'] = $pad['width']; + $pcb->PAD_STYLE[$i]['height'] = $pad['height']; + $pcb->PAD_STYLE[$i]['hole_dia'] = $pad['hole_dia']; + $pcb->PAD_STYLE[$i]['flags'] = $pad['flags']; + $pcb->PAD_STYLE[$i]['name'] = "pad".$i; + + return $pcb->PAD_STYLE[$i]['name']; +} + +echo"
"; +echo"generate pad styles...
"; +for($i=0; $i<=$pcb->HDR['comp_count_real']['v']; $i++) +{ + $C = $pcb->COMP[$i]; + + for ($j=1; $j<=$C['pads_count']['v']; $j++) + { + $pad['shape'] = $C['pad'.$j.'_shape']['v']; + $pad['width'] = $C['pad'.$j.'_width']['v']; + $pad['height'] = $C['pad'.$j.'_height']['v']; + $pad['hole_dia'] = $C['pad'.$j.'_hole_dia']['v']; + $pad['flags'] = $C['pad'.$j.'_flags']['v']; + + if ($pad_style = padAddStyle($pcb, $pad)) + { + echo"comp [$i], pad [$j], added new pad {"; + echo"shape=".$pad['shape'].""; + echo", hole_dia=".$pad['hole_dia'].""; + echo", size=".$pad['width']."x".$pad['height'].""; + echo", flags=".$pad['flags'].""; + echo"}, style=[$pad_style]
"; + } + + $pcb->COMP[$i]['pad'.$j.'_style']['v'] = padGetStyle($pcb, $pad); + } +} +echo"save pad styles: ".sizeof($pcb->PAD_STYLE)."
"; +$pcad_lib = ""; +for ($i=0; $iPAD_STYLE); $i++) +{ + $pcad_lib .= " (padStyleDef \"".$pcb->PAD_STYLE[$i]['name']."\"\r\n"; + $pcad_lib .= " (holeDiam ".$pcb->PAD_STYLE[$i]['hole_dia'].")\r\n"; + $pcad_lib .= " (StartRange 1)\r\n"; + $pcad_lib .= " (EndRange 2)\r\n"; + + $s1 = "Ellipse"; if ($pcb->PAD_STYLE[$i]['shape'] == 2) $s1 = "Rect"; + $w1 = $pcb->PAD_STYLE[$i]['width']; + $h1 = $pcb->PAD_STYLE[$i]['height']; + + $w2 = $w1; + $h2 = $w1; + $s2 = $s1; + if (!$pcb->PAD_STYLE[$i]['hole_dia']) + { + $w2 = "0"; + $h2 = "0"; + $s2 = "NoConnect"; + } + $pcad_lib .= " (padShape (layerNumRef 1) (padShapeType $s1) (shapeWidth $w1) (shapeHeight $h1) )\r\n"; + $pcad_lib .= " (padShape (layerNumRef 2) (padShapeType $s2) (shapeWidth $w2) (shapeHeight $h2) )\r\n"; + $pcad_lib .= " (padShape (layerType Signal) (padShapeType $s2) (shapeWidth $w2) (shapeHeight $h2) )\r\n"; + $pcad_lib .= " (padShape (layerType Plane) (padShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n"; + $pcad_lib .= " (padShape (layerType NonSignal) (padShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n"; + $pcad_lib .= " )\r\n"; + +} +file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX); diff --git a/pcb/php-builder/lib_pattern.php b/pcb/php-builder/lib_pattern.php new file mode 100644 index 0000000..05b46ae --- /dev/null +++ b/pcb/php-builder/lib_pattern.php @@ -0,0 +1,162 @@ +PATTERN_STYLE); $i++) + { + $style = $pcb->PATTERN_STYLE[$i]; + + // 1. name + $pattern_name_bool = strtoupper($style['pattern']) == strtoupper($pattern['pattern']); + + // 2. pads count + if ($pattern_name_bool) + { + $pads_count_bool = $style['pads_count'] == $pattern['pads_count']; + if (!$pads_count_bool) + return false; + + // 3. pad styles + for ($j=1; $j<=$pattern['pads_count']; $j++) + { + $pad_style_bool = $style['pad'.$j.'_style'] == $pattern['pad'.$j.'_style']; + if (!$pad_style_bool) + break; + } + + if (!$pad_style_bool) + continue; + + return $style; + } + } + + return false; +} +function patternCheckName($pcb, $name) +{ + for ($i=0; $i < sizeof($pcb->PATTERN_STYLE); $i++) + { + $style = $pcb->PATTERN_STYLE[$i]; + if ($style['name'] == $name) + return $name."_".$i; + } + return $name; +} +function patternAddStyle($pcb, $pattern, $ind) +{ + $st = patternGetStyle($pcb, $pattern, $ind); + if ($st['name']) + return false; + + $i = sizeof($pcb->PATTERN_STYLE); + $pcb->PATTERN_STYLE[$i] = $pattern; + $pcb->PATTERN_STYLE[$i]['name'] = patternCheckName($pcb, strtoupper($pattern['pattern'])); +// $pcb->PATTERN_STYLE[$i]['rotate'] = strtoupper($pattern['rotate']); + + return $pcb->PATTERN_STYLE[$i]['name']; +} + +echo"
"; +echo"generate patterns...
"; +for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++) +{ + $C = $pcb->COMP[$i]; + + $pattern = array(); + $pattern['pattern'] = $C['pattern']['v']; + $pattern['rotate'] = $C['rotate']['v']; + $pattern['pads_count'] = $C['pads_count']['v']; + + for ($j=1; $j<=$pattern['pads_count']; $j++) + { + $pattern['pad'.$j.'_num'] = $j; + $pattern['pad'.$j.'_style'] = $C['pad'.$j.'_style']['v']; + $pattern['pad'.$j.'_rotate'] = $C['pad'.$j.'_rotate']['v']; + $pattern['pad'.$j.'_pos_x'] = $C['pos_x']['v'] - $C['pad'.$j.'_pos_x']['v']; + $pattern['pad'.$j.'_pos_y'] = $C['pos_y']['v'] - $C['pad'.$j.'_pos_y']['v']; + $pattern['pad'.$j.'_des'] = $C['pad'.$j.'_des']['v']; + } + + $pattern['lines_count'] = $C['lines_count']['v']; + for ($j=1; $j<=$pattern['lines_count']; $j++) + { + $pattern['line'.$j.'_pos_x'] = $C['pos_x']['v'] - $C['line'.$j.'_pos_x']['v']; + $pattern['line'.$j.'_pos_y'] = $C['pos_y']['v'] - $C['line'.$j.'_pos_y']['v']; + $pattern['line'.$j.'_size'] = "8.0"; + $pattern['line'.$j.'_flags'] = $C['line'.$j.'_flags']['v']; + } + + if ($pattern_style = patternAddStyle($pcb, $pattern, $i)) + { + echo"comp [$i], added NEW pattern {"; + echo"name=".$pattern['pattern'].""; + echo", pads=".$pattern['pads_count'].""; + echo", lines=".$pattern['lines_count'].""; + echo", style_rotate=".$pattern['rotate'].""; + echo"}, style=[$pattern_style]
"; + } + + // save pattern style to component + $st = patternGetStyle($pcb, $pattern, $i); + $pcb->COMP[$i]['style']['v'] = $st['name']; + $pcb->COMP[$i]['style_rotate']['v'] = $st['rotate']; +} + +echo"save patterns: ".sizeof($pcb->PATTERN_STYLE)."
"; +$pcad_lib = ""; +for($i=0; $iPATTERN_STYLE); $i++) +{ + $PTR = $pcb->PATTERN_STYLE[$i]; + + // begin library pattern + $pcad_lib .= " (patternDefExtended \"".$PTR['name']."_1\"\r\n"; + $pcad_lib .= " (originalName \"".$PTR['name']."\")\r\n"; + $pcad_lib .= " (patternGraphicsNameRef \"Primary\")\r\n"; + $pcad_lib .= " (patternGraphicsDef \r\n"; + $pcad_lib .= " (patternGraphicsNameDef \"Primary\")\r\n"; + + // multilayer, pads + $pcad_lib .= " (multiLayer \r\n"; + for ($j=1; $j<=$PTR['pads_count']; $j++) + { + $rot = ($PTR['pad'.$j.'_rotate'] * 90); + $x = $PTR['pad'.$j.'_pos_x']; + $y = $PTR['pad'.$j.'_pos_y']; + + $pcad_lib .= " (pad (padNum $j) (padStyleRef \"".$PTR['pad'.$j.'_style']."\") (pt $y $x) (rotation $rot) (defaultPinDes \"".$PTR['pad'.$j.'_des']."\") )\r\n"; + } + $pcad_lib .= " )\r\n"; + + // layer 6 - top silk + $pcad_lib .= " (layerContents (layerNumRef 6)\r\n"; + for ($j=1; $j<$PTR['lines_count']; $j++) + { + $flags2 = $PTR['line'.($j+1).'_flags']; + if (!$flags2) continue; // next point flags = 0, begin other line + + $x1 = $PTR['line'.$j.'_pos_x']; + $y1 = $PTR['line'.$j.'_pos_y']; + + $x2 = $PTR['line'.($j+1).'_pos_x']; + $y2 = $PTR['line'.($j+1).'_pos_y']; + + $w = $PTR['line'.$j.'_size']; + +if ( ($x1 == $x2) and ($y1 == $y2) ) {} else // HACK !!! + $pcad_lib .= " (line (pt $y2 $x2) (pt $y1 $x1) (width $w) )\r\n"; + } +// $rot = ($PTR['pad'.$j.'_rotate'] * 90); //(rotation $rot) + $pcad_lib .= " (attr \"RefDes\" \"\" (isVisible False) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n"; + $pcad_lib .= " (attr \"Type\" \"\" (isVisible False) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n"; + $pcad_lib .= " (attr \"Value\" \"\" (isVisible False) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n"; + $pcad_lib .= " )\r\n"; + + // end + $pcad_lib .= " )\r\n"; // patternGraphicsDef + $pcad_lib .= " )\r\n"; // patternDefExtended + +} +file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX); diff --git a/pcb/php-builder/lib_text.php b/pcb/php-builder/lib_text.php new file mode 100644 index 0000000..bbf4d9b --- /dev/null +++ b/pcb/php-builder/lib_text.php @@ -0,0 +1,102 @@ +TXT_STYLE); $i++) + { + $style = $pcb->TXT_STYLE[$i]; + if ( ($style['size_v'] == $txt['size_v']) ) + return $style['name']; + } + + return false; +} +function txtAddStyle($pcb, $txt) +{ + for ($i=0; $i < sizeof($pcb->TXT_STYLE); $i++) + { + $style = $pcb->TXT_STYLE[$i]; + if ( ($style['size_v'] == $txt['size_v']) ) + return false; + } + + $pcb->TXT_STYLE[$i]['size_v'] = $txt['size_v']; + $pcb->TXT_STYLE[$i]['name'] = "txt".$i; + + return $pcb->TXT_STYLE[$i]['name']; +} + +echo"
"; +echo"generate text styles...
"; +for($i=1; $i<=$pcb->HDR['texts_count']['v']; $i++) +{ + $T = $pcb->TXT[$i]; + + $txt['size_v'] = round(1.5*$T['size_v']['v']); + + if ($txt_style = txtAddStyle($pcb, $txt)) + { + echo"text [$i], added new text {"; + echo"size_v=".$txt['size_v'].""; + echo"}, style=[$txt_style]
"; + } + + // save style to text + $pcb->TXT[$i]['style']['v'] = txtGetStyle($pcb, $txt); +} +echo"save text styles: ".sizeof($pcb->TXT_STYLE)."
"; + + $pcad_font_stroke = " (font\r\n"; + $pcad_font_stroke .= " (fontType Stroke)\r\n"; + $pcad_font_stroke .= " (fontFamily SanSerif)\r\n"; + $pcad_font_stroke .= " (fontFace \"Quality\")\r\n"; + $pcad_font_stroke .= " (fontHeight 100)\r\n"; + $pcad_font_stroke .= " (strokeWidth 8)\r\n"; + $pcad_font_stroke .= " )\r\n"; + + $pcad_font_truetype = " (font\r\n"; + $pcad_font_truetype .= " (fontType TrueType)\r\n"; + $pcad_font_truetype .= " (fontFamily Modern)\r\n"; + $pcad_font_truetype .= " (fontFace \"Arial\")\r\n"; + $pcad_font_truetype .= " (fontHeight 100)\r\n"; + $pcad_font_truetype .= " (strokeWidth 10)\r\n"; + $pcad_font_truetype .= " (fontWeight 400)\r\n"; + $pcad_font_truetype .= " (fontCharSet 0)\r\n"; + $pcad_font_truetype .= " (fontOutPrecision 7)\r\n"; + $pcad_font_truetype .= " (fontClipPrecision 32)\r\n"; + $pcad_font_truetype .= " (fontQuality 1)\r\n"; + $pcad_font_truetype .= " (fontPitchAndFamily 6)\r\n"; + $pcad_font_truetype .= " )\r\n"; + + + $pcad_lib = " (textStyleDef \"(Default)\"\r\n"; + $pcad_lib .= $pcad_font_stroke; + $pcad_lib .= " )\r\n"; + + $pcad_lib .= " (textStyleDef \"(DefaultTTF)\"\r\n"; + $pcad_lib .= $pcad_font_stroke; + $pcad_lib .= $pcad_font_truetype; + $pcad_lib .= " (textStyleAllowTType True)\r\n"; + $pcad_lib .= " (textStyleDisplayTType True)\r\n"; + $pcad_lib .= " )\r\n"; +file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX); + +$pcad_lib = ""; +for ($i=0; $iTXT_STYLE); $i++) +{ + $pcad_lib .= " (textStyleDef \"".$pcb->TXT_STYLE[$i]['name']."\"\r\n"; + $pcad_lib .= " (font\r\n"; + $pcad_lib .= " (fontType Stroke)\r\n"; + $pcad_lib .= " (fontFamily SanSerif)\r\n"; + $pcad_lib .= " (fontFace \"Quality\")\r\n"; + $pcad_lib .= " (fontHeight ".$pcb->TXT_STYLE[$i]['size_v'].")\r\n"; + $pcad_lib .= " (strokeWidth 8)\r\n"; + $pcad_lib .= " )\r\n"; + $pcad_lib .= " (textStyleAllowTType False)\r\n"; + $pcad_lib .= " (textStyleDisplayTType False)\r\n"; + $pcad_lib .= " )\r\n"; + +} +file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX); diff --git a/pcb/php-builder/lib_via.php b/pcb/php-builder/lib_via.php new file mode 100644 index 0000000..16b0e47 --- /dev/null +++ b/pcb/php-builder/lib_via.php @@ -0,0 +1,86 @@ +VIA_STYLE); $i++) + { + $style = $pcb->VIA_STYLE[$i]; + if ( ($style['shape'] == $via['shape']) and ($style['dia'] == $via['dia']) ) + return $style['name']; + } + + return false; +} +function viaAddStyle($pcb, $via) +{ + for ($i=0; $i < sizeof($pcb->VIA_STYLE); $i++) + { + $style = $pcb->VIA_STYLE[$i]; + if ( ($style['shape'] == $via['shape']) and ($style['dia'] == $via['dia']) ) + return false; + } + + $pcb->VIA_STYLE[$i]['shape'] = $via['shape']; + $pcb->VIA_STYLE[$i]['dia'] = $via['dia']; + $pcb->VIA_STYLE[$i]['name'] = "via".$i; + + return $pcb->VIA_STYLE[$i]['name']; +} + +echo"generate via styles...
"; +for($i=0; $i<=$pcb->HDR['net_points_count']['v']; $i++) +{ + $flags = hex($pcb->NETPOI[$i]['flags']['v']); + $flags_hdr = substr($flags, 1, 1); + + if ( ($flags_hdr == "6") or ($flags_hdr == "7") ) {} else continue; + + $via['shape'] = $pcb->NETPOI[$i]['size']['v']; + $via['dia'] = $via['shape'] / 2; + + if ($via_style = viaAddStyle($pcb, $via)) + { + echo"net point [$i], added new via {shape=".$via['shape'].", dia=".$via['dia']."}, style=[$via_style]
"; + } + + $pcb->NETPOI[$i]['style']['v'] = viaGetStyle($pcb, $via); +} +echo"save via styles: ".sizeof($pcb->VIA_STYLE)."
"; + $pcad_lib = " (viaStyleDef \"(Default)\"\r\n"; + $pcad_lib .= " (holeDiam 18)\r\n"; + $pcad_lib .= " (StartRange 1)\r\n"; + $pcad_lib .= " (EndRange 2)\r\n"; + $s = "Ellipse"; + $w = "40"; + $h = "40"; + $pcad_lib .= " (viaShape (layerNumRef 1) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n"; + $pcad_lib .= " (viaShape (layerNumRef 2) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n"; + $pcad_lib .= " (viaShape (layerType Signal) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n"; + $pcad_lib .= " (viaShape (layerType Plane) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n"; + $pcad_lib .= " (viaShape (layerType NonSignal) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n"; + $pcad_lib .= " )\r\n"; +file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX); + +$pcad_lib = ""; +for ($i=0; $iVIA_STYLE); $i++) +{ + $pcad_lib .= " (viaStyleDef \"".$pcb->VIA_STYLE[$i]['name']."\"\r\n"; + $pcad_lib .= " (holeDiam ".$pcb->VIA_STYLE[$i]['dia'].")\r\n"; + $pcad_lib .= " (StartRange 1)\r\n"; + $pcad_lib .= " (EndRange 2)\r\n"; + + $s = "Ellipse"; + $w = $pcb->VIA_STYLE[$i]['shape']; + $h = $pcb->VIA_STYLE[$i]['shape']; + + $pcad_lib .= " (viaShape (layerNumRef 1) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n"; + $pcad_lib .= " (viaShape (layerNumRef 2) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n"; + $pcad_lib .= " (viaShape (layerType Signal) (viaShapeType $s) (shapeWidth $w) (shapeHeight $h) )\r\n"; + $pcad_lib .= " (viaShape (layerType Plane) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n"; + $pcad_lib .= " (viaShape (layerType NonSignal) (viaShapeType NoConnect) (shapeWidth 0) (shapeHeight 0) )\r\n"; + $pcad_lib .= " )\r\n"; + +} +file_put_contents($out_file, $pcad_lib, FILE_APPEND | LOCK_EX); diff --git a/pcb/php-builder/net.php b/pcb/php-builder/net.php new file mode 100644 index 0000000..9c77d67 --- /dev/null +++ b/pcb/php-builder/net.php @@ -0,0 +1,81 @@ +HDR['comp_count_real']['v']; $i++) +{ + $C = $pcb->COMP[$i]; + + $name1 = ValidateRef($C['name1_str']['v']); + $name2 = ValidateRef($C['name2_str']['v']); + $pattern = $C['style']['v']; + $pcad_net .= " (compInst \"$name1\"\r\n"; + $pcad_net .= " (compRef \"".$pattern."_1\")\r\n"; + $pcad_net .= " (originalName \"$pattern\")\r\n"; + $pcad_net .= " (compValue \"$name2\")\r\n"; + $pcad_net .= " )\r\n"; +} +file_put_contents($out_file, $pcad_net, FILE_APPEND | LOCK_EX); + + + +echo"generate net list...
"; +$net_lists = array(); +for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++) +{ + $C = $pcb->COMP[$i]; + for ($j=1; $j<=$C['pads_count']['v']; $j++) + { + $net = $C['pad'.$j.'_net']['v']; +if (!trim($net)) continue; + + if (!in_array($net, $net_list)) + { + $net_list[] = $net; + } + } +} +echo"nets from components: ".sizeof($net_list)."
"; +//for($n=0; $n"; + +$pcad_net = ""; +for($n=0; $nHDR['comp_count_real']['v']; $i++) + { + $C = $pcb->COMP[$i]; + for ($j=1; $j<=$C['pads_count']['v']; $j++) + { + $pad_net = $C['pad'.$j.'_net']['v']; + $pad_des = $C['pad'.$j.'_des']['v']; + if ($net == $pad_net) + { + $pcad_net .= " (node \"".ValidateRef($C['name1_str']['v'])."\" \"$pad_des\")\r\n"; + } + } + } +//*/ + $pcad_net .= " )\r\n"; + +} +file_put_contents($out_file, $pcad_net, FILE_APPEND | LOCK_EX); + + +echo"generate netclass...
"; +$pcad_net = " (netClass \"DefaultNetClass\"\r\n"; +for($n=0; $nMaxPosX; // "30000"; +$work_height = 2 * $pcb->MaxPosY; // "20000"; + +$pcad_pcb = " (pcbDesignHeader \r\n"; +$pcad_pcb .= " (workspaceSize $work_width $work_height) ;; MaxX=".$pcb->MaxPosX.", MaxY=".$pcb->MaxPosY."\r\n"; +$pcad_pcb .= " (gridDfns \r\n"; +//$pcad_pcb .= " (grid \"0.05mm\")\r\n"; +//$pcad_pcb .= " (grid \"0.1mm\")\r\n"; +$pcad_pcb .= " (grid \"5.0mil\")\r\n"; +$pcad_pcb .= " (grid \"10.0mil\")\r\n"; +$pcad_pcb .= " (grid \"100.0mil\")\r\n"; +$pcad_pcb .= " )\r\n"; +$pcad_pcb .= " (designInfo \r\n"; +$pcad_pcb .= " (fieldSet \"(Default)\"\r\n"; +$pcad_pcb .= " (fieldDef \"Date\" \"$dt\")\r\n"; +$pcad_pcb .= " (fieldDef \"Time\" \"$tm\")\r\n"; +$pcad_pcb .= " (fieldDef \"Author\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Revision\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Title\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Approved By\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Checked By\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Company Name\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Drawing Number\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Drawn By\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Engineer\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Variant Name\" \"\")\r\n"; +$pcad_pcb .= " (fieldDef \"Variant Description\" \"\")\r\n"; +$pcad_pcb .= " )\r\n"; +$pcad_pcb .= " )\r\n"; +$pcad_pcb .= " (solderSwell 4.0)\r\n"; +$pcad_pcb .= " (pasteSwell 0.0)\r\n"; +$pcad_pcb .= " (planeSwell 20.0)\r\n"; +$pcad_pcb .= " (refPointSize 100.0)\r\n"; +$pcad_pcb .= " (infoPointSize 100.0)\r\n"; +$pcad_pcb .= " (gluePointSize 100.0)\r\n"; +$pcad_pcb .= " (pickPointSize 100.0)\r\n"; +$pcad_pcb .= " (testPointSize 100.0)\r\n"; +$pcad_pcb .= " (refPointSizePrint 100.0)\r\n"; +$pcad_pcb .= " (infoPointSizePrint 100.0)\r\n"; +$pcad_pcb .= " (gluePointSizePrint 100.0)\r\n"; +$pcad_pcb .= " (pickPointSizePrint 100.0)\r\n"; +$pcad_pcb .= " (testPointSizePrint 100.0)\r\n"; +$pcad_pcb .= " (solderFlowDirection solderFlowTopToBottom)\r\n"; +$pcad_pcb .= " (globalCopperPourCutoutBackoffFlag False)\r\n"; +$pcad_pcb .= " )\r\n"; + +file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX); diff --git a/pcb/php-builder/pcb_layerdef.php b/pcb/php-builder/pcb_layerdef.php new file mode 100644 index 0000000..07a3ad2 --- /dev/null +++ b/pcb/php-builder/pcb_layerdef.php @@ -0,0 +1,79 @@ +HDR['net_points_count']['v']; $i++) +{ + $flags1 = hex($pcb->NETPOI[$i]['flags']['v']); + $flags1_layer = substr($flags1, 0, 1); // 0-bot, 1-top + $flags1_head = substr($flags1, 1, 1); // 0-start line, 1-continue, 6,7 via + $net1 = $pcb->NETPOI[$i]['net_id']['v']; + $x1 = $pcb->NETPOI[$i]['pos_x']['v']; + $y1 = $pcb->NETPOI[$i]['pos_y']['v']; + $size = $pcb->NETPOI[$i]['size']['v']; + + + $flags2 = hex($pcb->NETPOI[($i+1)]['flags']['v']); + $flags2_layer = substr($flags2, 0, 1); // 0-bot, 1-top + $flags2_head = substr($flags2, 1, 1); // 0-start line, 1-continue, 6,7 via + $net2 = $pcb->NETPOI[($i+1)]['net_id']['v']; + $x2 = $pcb->NETPOI[($i+1)]['pos_x']['v']; + $y2 = $pcb->NETPOI[($i+1)]['pos_y']['v']; + + if ($net1 != $net2) continue; // next point is from other net + if ($flags2_head == 0) continue; // next point is start + if ($flags2_head == 8) continue; // next point is start + if ($flags2_layer != $flags1_layer) continue; // next point at another layer, via is here + if (($flags1_layer == $flags2_layer) and ($flags2_head == 6)) continue; + + + +//if ($net1 != 16521) continue; // ISA RES +//if ($net1 != 78) continue; // GND +//if ($net1 != 90) continue; // VCC +//if ($net1 != 66) continue; // VCC + + + + $line['id1'] = $i; + $line['x1'] = $x1; + $line['y1'] = $y1; + $line['id2'] = $i+1; + $line['x2'] = $x2; + $line['y2'] = $y2; + $line['net'] = getNetByPadOfs($pcb, $net1); + $line['size'] = $size; + + $LAYER[$flags1_layer][] = $line; +} + +for($i=1; $i<$pcb->HDR['brd_points_count']['v']; $i++) +{ + $flags1 = hex($pcb->BRDPOI[$i]['flags']['v']); + $flags1_head = substr($flags1, 1, 1); // 0-start line, 1-continue, 6,7 via + $x1 = $pcb->BRDPOI[$i]['pos_x']['v']; + $y1 = $pcb->BRDPOI[$i]['pos_y']['v']; + + $flags2 = hex($pcb->BRDPOI[($i+1)]['flags']['v']); + $flags2_head = substr($flags2, 1, 1); // 0-start line, 1-continue, 6,7 via + $x2 = $pcb->BRDPOI[($i+1)]['pos_x']['v']; + $y2 = $pcb->BRDPOI[($i+1)]['pos_y']['v']; + + if ($flags2_head == 0) continue; // next point is start + + $line['x1'] = $x1; + $line['y1'] = $y1; + $line['x2'] = $x2; + $line['y2'] = $y2; + $line['size'] = "8"; + + $LAYER[3][] = $line; +} + +function createLayerContent($pcb, $LAYER, $orcad_layer) +{ + $pcad_pcb = ""; + for($i=1; $iHDR['texts_count']['v']; $i++) + { + $T = $pcb->TXT[$i]; + if ($T['layer']['v'] != $orcad_layer) continue; // 0-bot, 1-top + + $style = "(DefaultTTF)"; + $style = $T['style']['v']; + $x = $T['pos_x']['v']; + $y = $T['pos_y']['v']; + $s = $T['str']['v']; + $r = ($T['rotate']['v']); +// $r = $r - 1; // rotate -90 + if ($r<0) $r = 4 + $r; + if ($orcad_layer == 1) // HACK FOR TOP LAYER ONLY !!! + { + if ($r==3) $r = 1; + } + $r = $r * 90; + + $flip = ""; + $flags = hex($T['flags']['v']); + $mirrored = substr($flags, 0, 1); // 1 - not mirrored, 0 - mirrored (why ???) + $visible = substr($flags, 1, 1); // 1 - visible, 0 - not visible + if ($mirrored == "0") $flip = "(isFlipped True) "; + $pcad_pcb .= " (text (pt $y $x) \"$s\" (textStyleRef \"$style\") (rotation $r) $flip(justify Center) $ext)\r\n"; + } + + return $pcad_pcb; +} + + +// layer1, pcad top +// ================================================================================================ +$pcad_pcb = " (layerContents (layerNumRef 1)\r\n"; +$pcad_pcb .= createLayerContent($pcb, $LAYER, 1); +$pcad_pcb .= " )\r\n"; +file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX); + +// layer2, pcad bottom +// ================================================================================================ +$pcad_pcb = " (layerContents (layerNumRef 2)\r\n"; +$pcad_pcb .= createLayerContent($pcb, $LAYER, 0); +$pcad_pcb .= " )\r\n"; +file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX); + +// board +// ================================================================================================ +$pcad_pcb = " (layerContents (layerNumRef 3)\r\n"; +// - lines +for($i=1; $iHDR['net_points_count']['v']; $i++) +{ + $net1 = $pcb->NETPOI[$i]['net_id']['v']; + $net = getNetByPadOfs($pcb, $net1); + $netref = ""; + if ($net) $netref = "(netNameRef \"$net\") "; + + $flags = hex($pcb->NETPOI[$i]['flags']['v']); + $flags_hdr = substr($flags, 1, 1); + + if ( ($flags_hdr == "6") or ($flags_hdr == "7") ) {} else continue; + + $st = $pcb->NETPOI[$i]['style']['v']; + $x = $pcb->NETPOI[$i]['pos_x']['v']; + $y = $pcb->NETPOI[$i]['pos_y']['v']; + + $pcad_pcb .= " (via (viaStyleRef \"$st\") (pt $y $x) $netref)\r\n"; +} +//file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX); + +// - components +for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++) +{ + $C = $pcb->COMP[$i]; + + $name1 = ValidateRef($C['name1_str']['v']); + $name2 = ValidateRef($C['name2_str']['v']); + $pattern = $C['style']['v'] . "_1"; + $x = $C['pos_x']['v']; + $y = $C['pos_y']['v']; + + $delta = $C['rotate']['v'] - $C['style_rotate']['v']; + $r = (2 - $delta); + + $comment = ""; +// $comment = ";; styleR=[".$C['style_rotate']['v']."], compR=".$C['rotate']['v'].", calcR=$r"; + + $pcad_pcb .= " (pattern (patternRef \"$pattern\") (refDesRef \"$name1\") (pt $y $x) (rotation ".($r*90).") (patternGraphicsNameRef \"Primary\")\r\n"; + $pcad_pcb .= " (patternGraphicsRef $comment\r\n"; + $pcad_pcb .= " (patternGraphicsNameRef \"Primary\")\r\n"; + + $tr = ($C['rotate']['v'] +3) %4; + if (($tr == 1) or ($tr == 3)) $tr = ($tr +2) %4; + +// can be experimenting +if ($C['pads_count']['v'] > 12) + $pcad_pcb .= " (attr \"RefDes\" \"$name1\" (rotation ".($tr*90).") (isVisible True) (justify Center) (textStyleRef \"(DefaultTTF)\") )\r\n"; + + $pcad_pcb .= " )\r\n"; + $pcad_pcb .= " )\r\n"; + +//file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX); +} + +// multilayer end. +$pcad_pcb .= " )\r\n"; +file_put_contents($out_file, $pcad_pcb, FILE_APPEND | LOCK_EX); + diff --git a/pcb/php-builder/pcb_stackup.php b/pcb/php-builder/pcb_stackup.php new file mode 100644 index 0000000..218dbd9 --- /dev/null +++ b/pcb/php-builder/pcb_stackup.php @@ -0,0 +1,35 @@ + { R_0 = 0, R_90 = 1, R_180 = 2, R_270 = 3, } TRotate; typedef enum { Bottom = 0, Top = 1, } TLayer; typedef enum { Begin = 0, Continue = 1, } TLineFlags; typedef struct THeader { char file_name[8]; short unk1; // version? always ADh short comp_count ; // real count + 1, why? short unk3; short unk4; short unk5; short unk6; short unk7; short unk8; short unk9; short unk10; short unk11; short texts_ofs ; short texts_size ; // in bytes short brd_points_count ; short net_points_count ; short unk16; short unk17; short unk18; char file_ext[4]; }; THeader hdr; // components // ================================================================================================ SetBackColor( cLtPurple ); struct TComponent { char timestamp[8]; byte unk1; // version? always AAh TRotate rotate; TLayer lines_layer; byte unk3; short pos_x_left; short pos_x_right; short pos_y_bottom; short pos_y_top; short pos_x; short pos_y; short height; short width; short lines_ofs; short names_ofs; short pads_ofs; short next_ofs1; short next_ofs2; char pattern[8] ; short next_ofs3; // lines SetBackColor( cLtYellow ); local int lines_count = (names_ofs - lines_ofs) / 6; struct Tlines { byte unk1; TLineFlags flags; short pos_x; short pos_y; } line[lines_count]; // names SetBackColor( cLtGreen ); local short names_count = (pads_ofs - names_ofs) / 24; struct TNames { short unk1; short unk2; char str[8] ; short unk4; short unk5; short unk6; short unk7; short pos_x; short pos_y; } name[names_count] ; // pads typedef enum { SMD = 1, Plated = 3, } TPadsFlags; SetBackColor( cGray ); local short pads_count = (next_ofs1 - pads_ofs) / 24; struct TPad { char des[4]; char net[8]; byte shape; short height; short width; TRotate rotate; TPadsFlags flags; byte hole_dia; short pos_x; short pos_y; local string des_net = des + net; } pad[pads_count] ; local string name_pattern = name[0].str + pattern; } comp[hdr.comp_count-1] ; // text strings // ================================================================================================ typedef enum { Flipped = 0, NotFlipped = 1, } TFlagsA; typedef enum { NotVisible = 0, Visible = 1, } TFlagsB; typedef struct { BigEndian(); byte raw ; LittleEndian(); FSkip (-1); BitfieldLeftToRight(); TFlagsA PadType: 4; TFlagsB PinType: 4; } TTextsFlags; typedef struct { char unk[12]; byte len; short size_h; short size_v; TRotate rotate; TLayer layer; TTextsFlags flags; short pos_x; short pos_y; char str[len]; } TTextString; SetBackColor( cWhite ); local int index; index = 0; do { TTextString txt ; index = index + 24 + txt.len; } while (index < hdr.texts_size); // board points // ================================================================================================ SetBackColor( cLtBlue ); typedef struct { TLineFlags flags; byte unk2; short pos_x; short pos_y; short unk5; } TBoardPoint; TBoardPoint brd[hdr.brd_points_count]; // net points // ================================================================================================ typedef enum { NetBegin = 0, NetContinue = 1, VIA_special = 6, VIA = 7, } TNetPoiFlagsB; typedef struct { BigEndian(); byte raw ; LittleEndian(); FSkip (-1); BitfieldLeftToRight(); byte layer: 4; TNetPoiFlagsB PinType: 4; } TNetPoiFlags; SetBackColor( cBlue ); typedef struct { TNetPoiFlags flags; byte size; short pos_x; short pos_y; short net_id; } TNetPoint; TNetPoint net[hdr.net_points_count] ; \ No newline at end of file diff --git a/pcb/php-parser/Class_OrCad21.php b/pcb/php-parser/Class_OrCad21.php new file mode 100644 index 0000000..65e7edb --- /dev/null +++ b/pcb/php-parser/Class_OrCad21.php @@ -0,0 +1,486 @@ +FileName = $fn; + $this->Load($this->FileName); + + $this->MinPosX = 1000000; + $this->MinPosY = 1000000; + $this->MaxPosX = 0; + $this->MaxPosY = 0; + } + + // private + private function hex($int) + { + $h = dechex($int); + if (strlen($h)%2 != 0) + { + $h = str_pad($h, strlen($h) + 1, '0', STR_PAD_LEFT); + } + return strtoupper($h)."h"; + } + + private function GetStr($strl, $descr = "") + { + $result['ofs'] = $this->ParseIndex; + for ($i=0; $i<$strl; $i++) + { + if ($i > 0) $result['buf'] .= " "; + $result['buf'] .= $this->hex(ord($this->BUF[$this->ParseIndex + $i])); + if ((ord($this->BUF[$this->ParseIndex + $i]) > 31) and (ord($this->BUF[$this->ParseIndex + $i]) < 128)) + { + $result['v'] .= $this->BUF[$this->ParseIndex + $i]; + } + } + $result['descr'] = $descr; + $this->ParseIndex += $strl; + return $result; + } + + private function GetByte($descr = "") + { + $result['ofs'] = $this->ParseIndex; + $result['buf'] = $this->hex(ord($this->BUF[$this->ParseIndex])); + $result['v'] = ord($this->BUF[$this->ParseIndex]); + $result['descr'] = $descr; + $this->ParseIndex++; + return $result; + } + + private function GetWord($descr = "") + { + $result['ofs'] = $this->ParseIndex; + $result['buf'] = $this->hex(ord($this->BUF[$this->ParseIndex])) . " " . $this->hex(ord($this->BUF[$this->ParseIndex + 1])); + $result['v'] = ord($this->BUF[$this->ParseIndex]) + 256 * ord($this->BUF[$this->ParseIndex + 1]); + $result['descr'] = $descr; + $this->ParseIndex += 2; + return $result; + } + + private function ParseHeader() + { + $this->Error = 0; + $this->LastErrorStr = ""; + + $this->ParseIndex = 0; + $this->HDR['file_name'] = $this->GetStr(8); + $this->HDR['file_name']['v'] = trim($this->HDR['file_name']['v']); + $this->HDR['unk1'] = $this->GetWord(); + $this->HDR['comp_count'] = $this->GetWord(); + $this->HDR['unk3'] = $this->GetWord(); + $this->HDR['unk4'] = $this->GetWord(); + $this->HDR['unk5'] = $this->GetWord(); + $this->HDR['unk6'] = $this->GetWord(); + $this->HDR['unk7'] = $this->GetWord(); + $this->HDR['unk8'] = $this->GetWord(); + $this->HDR['unk9'] = $this->GetWord(); + $this->HDR['unk10'] = $this->GetWord(); + $this->HDR['unk11'] = $this->GetWord(); + $this->HDR['texts_ofs'] = $this->GetWord(); + $this->HDR['texts_ofs_real']['v'] = $this->HDR['texts_ofs']['v'] * 2 + self::HDR_SIZE; + $this->HDR['texts_size'] = $this->GetWord(); + $this->HDR['brd_points_count'] = $this->GetWord(); + $this->HDR['net_points_count'] = $this->GetWord(); + $this->HDR['unk16'] = $this->GetWord(); + $this->HDR['unk17'] = $this->GetWord(); + $this->HDR['unk18'] = $this->GetWord(); + $this->HDR['file_ext'] = $this->GetStr(4); + $this->HDR['file_ext']['v'] = trim($this->HDR['file_ext']['v']); + + // check range + if ($this->ParseIndex > $this->FileSize) + { + $this->Error = 1; + $this->LastErrorStr = "ParseIndex is out of FileSize during ParseHeader()"; + return false; + } + + return true; + } + + private function ParseComponent($i) + { + $this->COMP[$i]['ofs'] = $this->ParseIndex; + + $this->COMP[$i]['timestamp'] = $this->GetStr(8); + $this->COMP[$i]['unk1'] = $this->GetByte(); + $this->COMP[$i]['rotate'] = $this->GetByte("0-0, 1-90, 2-180, 3-270"); + $this->COMP[$i]['layer'] = $this->GetByte("0-bot, 1-top"); + $this->COMP[$i]['unk3'] = $this->GetByte(); + $this->COMP[$i]['unk4'] = $this->GetWord(); + $this->COMP[$i]['unk5'] = $this->GetWord(); + $this->COMP[$i]['unk6'] = $this->GetWord(); + $this->COMP[$i]['unk7'] = $this->GetWord(); + $this->COMP[$i]['pos_y'] = $this->GetWord(); + $this->COMP[$i]['pos_x'] = $this->GetWord(); + $this->COMP[$i]['unk10'] = $this->GetWord(); + $this->COMP[$i]['unk11'] = $this->GetWord(); + $this->COMP[$i]['lines_ofs'] = $this->GetWord(); + $this->COMP[$i]['names_ofs'] = $this->GetWord(); + $this->COMP[$i]['pads_ofs'] = $this->GetWord(); + $this->COMP[$i]['next_ofs1'] = $this->GetWord(); + $this->COMP[$i]['next_ofs2'] = $this->GetWord(); + $this->COMP[$i]['pattern'] = $this->GetStr(8); + $this->COMP[$i]['pattern']['v'] = trim($this->COMP[$i]['pattern']['v']); + $this->COMP[$i]['next_ofs3'] = $this->GetWord(); + + $this->COMP[$i]['lines_count']['v'] = ($this->COMP[$i]['names_ofs']['v'] - $this->COMP[$i]['lines_ofs']['v']) / 6; + $this->COMP[$i]['names_count']['v'] = ($this->COMP[$i]['pads_ofs']['v'] - $this->COMP[$i]['names_ofs']['v']) / 24; + $this->COMP[$i]['pads_count']['v'] = ($this->COMP[$i]['next_ofs1']['v'] - $this->COMP[$i]['pads_ofs']['v']) / 24; + + // lines + for($j=1; $j<=$this->COMP[$i]['lines_count']['v']; $j++) + { + $this->COMP[$i]['line'.$j.'_flags'] = $this->GetWord(); + $this->COMP[$i]['line'.$j.'_pos_y'] = $this->GetWord(); + $this->COMP[$i]['line'.$j.'_pos_x'] = $this->GetWord(); + } + + // names + for($j=1; $j<=$this->COMP[$i]['names_count']['v']; $j++) + { + $this->COMP[$i]['name'.$j.'_unk1'] = $this->GetWord(); + $this->COMP[$i]['name'.$j.'_unk2'] = $this->GetWord(); + $this->COMP[$i]['name'.$j.'_str'] = $this->GetStr(8); + $this->COMP[$i]['name'.$j.'_str']['v'] = trim($this->COMP[$i]['name'.$j.'_str']['v']); + $this->COMP[$i]['name'.$j.'_unk4'] = $this->GetWord(); + $this->COMP[$i]['name'.$j.'_unk5'] = $this->GetWord(); + $this->COMP[$i]['name'.$j.'_unk6'] = $this->GetWord(); + $this->COMP[$i]['name'.$j.'_unk7'] = $this->GetWord(); + $this->COMP[$i]['name'.$j.'_pos_y'] = $this->GetWord(); + $this->COMP[$i]['name'.$j.'_pos_x'] = $this->GetWord(); + } + + // pads + for($j=1; $j<=$this->COMP[$i]['pads_count']['v']; $j++) + { + $this->COMP[$i]['pad'.$j.'_ofs_real']['v'] = $this->ParseIndex; + $this->COMP[$i]['pad'.$j.'_ofs']['v'] = round($this->ParseIndex / 2) - 24; + $this->COMP[$i]['pad'.$j.'_des'] = $this->GetStr(4); + $this->COMP[$i]['pad'.$j.'_des']['v'] = trim($this->COMP[$i]['pad'.$j.'_des']['v']); + $this->COMP[$i]['pad'.$j.'_net'] = $this->GetStr(8); + $this->COMP[$i]['pad'.$j.'_net']['v'] = trim($this->COMP[$i]['pad'.$j.'_net']['v']); + $this->COMP[$i]['pad'.$j.'_shape'] = $this->GetByte("1-circ, 2-rect"); + $this->COMP[$i]['pad'.$j.'_width'] = $this->GetWord(); + $this->COMP[$i]['pad'.$j.'_height'] = $this->GetWord(); + $this->COMP[$i]['pad'.$j.'_rotate'] = $this->GetByte("0-0, 1-90, 2-180, 3-270"); + $this->COMP[$i]['pad'.$j.'_flags'] = $this->GetByte("1-smd, 3-plated"); + $this->COMP[$i]['pad'.$j.'_hole_dia'] = $this->GetByte(); + $this->COMP[$i]['pad'.$j.'_pos_y'] = $this->GetWord(); + $this->COMP[$i]['pad'.$j.'_pos_x'] = $this->GetWord(); + } + } + + private function ParseComponents() + { + $this->Error = 0; + $this->LastErrorStr = ""; + + // 'comp_count' = 'comp_count_real' + 1, + // so needs check 'ParseIndex' does not over 'texts_ofs_real' + for($i=1; $i<=$this->HDR['comp_count']['v']; $i++) + { + $this->ParseComponent($i); + + // check components size + if($this->ParseIndex >= $this->HDR['texts_ofs_real']['v']) + { + $this->HDR['comp_count_real']['v'] = $i; + return true; + } + + // check range + if ($this->ParseIndex > $this->FileSize) + { + $this->Error = 1; + $this->LastErrorStr = "ParseIndex is out of FileSize during ParseComponents(), i=" . $i; + return false; + } + } + + return false; + } + + private function ParseTexts() + { + $this->Error = 0; + $this->LastErrorStr = ""; + + $i = 1; + while (1) + { + $this->TXT[$i]['ofs'] = $this->ParseIndex; + + $this->TXT[$i]['unk1'] = $this->GetWord(); + $this->TXT[$i]['unk2'] = $this->GetWord(); + $this->TXT[$i]['unk3'] = $this->GetWord(); + $this->TXT[$i]['unk4'] = $this->GetWord(); + $this->TXT[$i]['unk5'] = $this->GetWord(); + $this->TXT[$i]['unk6'] = $this->GetWord(); + $this->TXT[$i]['len'] = $this->GetByte(); + $this->TXT[$i]['size_h'] = $this->GetWord(); + $this->TXT[$i]['size_v'] = $this->GetWord(); + $this->TXT[$i]['rotate'] = $this->GetByte("0-0, 1-90, 2-180, 3-270"); + $this->TXT[$i]['layer'] = $this->GetByte("0-bot, 1-top"); + $this->TXT[$i]['flags'] = $this->GetByte("(HL), H-mirrored(0-yes)"); + $this->TXT[$i]['pos_y'] = $this->GetWord(); + $this->TXT[$i]['pos_x'] = $this->GetWord(); + $this->TXT[$i]['str'] = $this->GetStr($this->TXT[$i]['len']['v']); + + // check texts size + if ($this->ParseIndex >= ($this->HDR['texts_ofs_real']['v'] + $this->HDR['texts_size']['v'])) + break; + + // check range + if ($this->ParseIndex > $this->FileSize) + { + $this->Error = 1; + $this->LastErrorStr = "ParseIndex is out of FileSize during ParseTexts(), i=" . $i; + return false; + } + + $i++; + } + + $this->HDR['texts_count']['v'] = $i; + return true; + } + + private function ParseBoardPoints() + { + $this->Error = 0; + $this->LastErrorStr = ""; + + for($i=1; $i<=$this->HDR['brd_points_count']['v']; $i++) + { + + $this->BRDPOI[$i]['ofs'] = $this->ParseIndex; + + $this->BRDPOI[$i]['flags'] = $this->GetByte(); + $this->BRDPOI[$i]['unk2'] = $this->GetByte(); + $this->BRDPOI[$i]['pos_y'] = $this->GetWord(); + $this->BRDPOI[$i]['pos_x'] = $this->GetWord(); + $this->BRDPOI[$i]['unk5'] = $this->GetByte(); + $this->BRDPOI[$i]['unk6'] = $this->GetByte(); + + if ($this->BRDPOI[$i]['pos_x']['v'] < $this->MinPosX) $this->MinPosX = $this->BRDPOI[$i]['pos_x']['v']; + if ($this->BRDPOI[$i]['pos_y']['v'] < $this->MinPosY) $this->MinPosY = $this->BRDPOI[$i]['pos_y']['v']; + + if ($this->BRDPOI[$i]['pos_x']['v'] > $this->MaxPosX) $this->MaxPosX = $this->BRDPOI[$i]['pos_x']['v']; + if ($this->BRDPOI[$i]['pos_y']['v'] > $this->MaxPosY) $this->MaxPosY = $this->BRDPOI[$i]['pos_y']['v']; + + // check range + if ($this->ParseIndex > $this->FileSize) + { + $this->Error = 1; + $this->LastErrorStr = "ParseIndex is out of FileSize during ParseBoardPoints(), i=" . $i; + return false; + } + } + + return true; + } + + private function ParseNetPoints() + { + $this->Error = 0; + $this->LastErrorStr = ""; + + for($i=1; $i<=$this->HDR['net_points_count']['v']; $i++) + { + + $this->NETPOI[$i]['ofs'] = $this->ParseIndex; + + $this->NETPOI[$i]['flags'] = $this->GetByte("(1x)h-layer, (x1)h-head"); + $this->NETPOI[$i]['size'] = $this->GetByte(); + $this->NETPOI[$i]['pos_y'] = $this->GetWord(); + $this->NETPOI[$i]['pos_x'] = $this->GetWord(); + $this->NETPOI[$i]['net_id'] = $this->GetWord(); + + // check range + if ($this->ParseIndex > $this->FileSize) + { + $this->Error = 1; + $this->LastErrorStr = "ParseIndex is out of FileSize during ParseNetPoints(), i=" . $i; + return false; + } + } + + return true; + } + + // public + public function Load() + { + $this->ParseIndex = 0; + $this->BUF = file_get_contents($this->FileName); + $this->FileSize = filesize($this->FileName); + if (!$this->FileSize) + { + $this->FileSize = 0; + } + } + + public function Parse() + { + $this->ParseHeader(); + $this->ParseComponents(); + $this->ParseTexts(); + $this->ParseBoardPoints(); + $this->ParseNetPoints(); + + if ($this->FileSize == $this->ParseIndex) + return true; + + return false; + } + + public function ChangePos($dx, $dy, $reverse_x, $reverse_y, $swap = 0) + { + // component + for($i=1; $i<=sizeof($this->COMP); $i++) + { + if (!$this->COMP[$i]['ofs']) continue; + + $this->COMP[$i]['pos_x']['v'] += $dx; + $this->COMP[$i]['pos_y']['v'] += $dy; + if ($reverse_x) $this->COMP[$i]['pos_x']['v'] = $reverse_x - $this->COMP[$i]['pos_x']['v']; + if ($reverse_y) $this->COMP[$i]['pos_y']['v'] = $reverse_y - $this->COMP[$i]['pos_y']['v']; + if ($swap) + { + $tmp = $this->COMP[$i]['pos_x']['v']; + $this->COMP[$i]['pos_x']['v'] = $this->COMP[$i]['pos_y']['v']; + $this->COMP[$i]['pos_y']['v'] = $tmp; + } + + // lines + for($j=1; $j<=$this->COMP[$i]['lines_count']['v']; $j++) + { + $this->COMP[$i]['line'.$j.'_pos_y']['v'] += $dy; + $this->COMP[$i]['line'.$j.'_pos_x']['v'] += $dx; + if ($reverse_x) $this->COMP[$i]['line'.$j.'_pos_x']['v'] = $reverse_x - $this->COMP[$i]['line'.$j.'_pos_x']['v']; + if ($reverse_y) $this->COMP[$i]['line'.$j.'_pos_y']['v'] = $reverse_y - $this->COMP[$i]['line'.$j.'_pos_y']['v']; + if ($swap) + { + $tmp = $this->COMP[$i]['line'.$j.'_pos_x']['v']; + $this->COMP[$i]['line'.$j.'_pos_x']['v'] = $this->COMP[$i]['line'.$j.'_pos_y']['v']; + $this->COMP[$i]['line'.$j.'_pos_y']['v'] = $tmp; + } + } + + // names + for($j=1; $j<=$this->COMP[$i]['names_count']['v']; $j++) + { + $this->COMP[$i]['name'.$j.'_pos_y']['v'] += $dy; + $this->COMP[$i]['name'.$j.'_pos_x']['v'] += $dx; + if ($reverse_x) $this->COMP[$i]['name'.$j.'_pos_x']['v'] = $reverse_x - $this->COMP[$i]['name'.$j.'_pos_x']['v']; + if ($reverse_y) $this->COMP[$i]['name'.$j.'_pos_y']['v'] = $reverse_y - $this->COMP[$i]['name'.$j.'_pos_y']['v']; + if ($swap) + { + $tmp = $this->COMP[$i]['name'.$j.'_pos_x']['v']; + $this->COMP[$i]['name'.$j.'_pos_x']['v'] = $this->COMP[$i]['name'.$j.'_pos_y']['v']; + $this->COMP[$i]['name'.$j.'_pos_y']['v'] = $tmp; + } + } + + // pads + for($j=1; $j<=$this->COMP[$i]['pads_count']['v']; $j++) + { + $this->COMP[$i]['pad'.$j.'_pos_y']['v'] += $dy; + $this->COMP[$i]['pad'.$j.'_pos_x']['v'] += $dx; + if ($reverse_x) $this->COMP[$i]['pad'.$j.'_pos_x']['v'] = $reverse_x - $this->COMP[$i]['pad'.$j.'_pos_x']['v']; + if ($reverse_y) $this->COMP[$i]['pad'.$j.'_pos_y']['v'] = $reverse_y - $this->COMP[$i]['pad'.$j.'_pos_y']['v']; + if ($swap) + { + $tmp = $this->COMP[$i]['pad'.$j.'_pos_x']['v']; + $this->COMP[$i]['pad'.$j.'_pos_x']['v'] = $this->COMP[$i]['pad'.$j.'_pos_y']['v']; + $this->COMP[$i]['pad'.$j.'_pos_y']['v'] = $tmp; + + $tmp = $this->COMP[$i]['pad'.$j.'_width']['v']; + $this->COMP[$i]['pad'.$j.'_width']['v'] = $this->COMP[$i]['pad'.$j.'_height']['v']; + $this->COMP[$i]['pad'.$j.'_height']['v'] = $tmp; + } + } + } + + // text + for($i=1; $i<=sizeof($this->TXT); $i++) + { + $this->TXT[$i]['pos_y']['v'] += $dy; + $this->TXT[$i]['pos_x']['v'] += $dx; + if ($reverse_x) $this->TXT[$i]['pos_x']['v'] = $reverse_x - $this->TXT[$i]['pos_x']['v']; + if ($reverse_y) $this->TXT[$i]['pos_y']['v'] = $reverse_y - $this->TXT[$i]['pos_y']['v']; + if ($swap) + { + $tmp = $this->TXT[$i]['pos_x']['v']; + $this->TXT[$i]['pos_x']['v'] = $this->TXT[$i]['pos_y']['v']; + $this->TXT[$i]['pos_y']['v'] = $tmp; + } + } + + // board points + for($i=1; $i<=$this->HDR['brd_points_count']['v']; $i++) + { + $this->BRDPOI[$i]['pos_y']['v'] += $dy; + $this->BRDPOI[$i]['pos_x']['v'] += $dx; + if ($reverse_x) $this->BRDPOI[$i]['pos_x']['v'] = $reverse_x - $this->BRDPOI[$i]['pos_x']['v']; + if ($reverse_y) $this->BRDPOI[$i]['pos_y']['v'] = $reverse_y - $this->BRDPOI[$i]['pos_y']['v']; + if ($swap) + { + $tmp = $this->BRDPOI[$i]['pos_y']['v']; + $this->BRDPOI[$i]['pos_y']['v'] = $this->BRDPOI[$i]['pos_x']['v']; + $this->BRDPOI[$i]['pos_x']['v'] = $tmp; + } + } + + // net pointes + for($i=1; $i<=$this->HDR['net_points_count']['v']; $i++) + { + $this->NETPOI[$i]['pos_y']['v'] += $dy; + $this->NETPOI[$i]['pos_x']['v'] += $dx; + if ($reverse_x) $this->NETPOI[$i]['pos_x']['v'] = $reverse_x - $this->NETPOI[$i]['pos_x']['v']; + if ($reverse_y) $this->NETPOI[$i]['pos_y']['v'] = $reverse_y - $this->NETPOI[$i]['pos_y']['v']; + if ($swap) + { + $tmp = $this->NETPOI[$i]['pos_x']['v']; + $this->NETPOI[$i]['pos_x']['v'] = $this->NETPOI[$i]['pos_y']['v']; + $this->NETPOI[$i]['pos_y']['v'] = $tmp; + } + } + + } + + +} diff --git a/pcb/php-parser/parser.php b/pcb/php-parser/parser.php new file mode 100644 index 0000000..00f4001 --- /dev/null +++ b/pcb/php-parser/parser.php @@ -0,0 +1,123 @@ +HDR['comp_count_real']['v']; $i++) + { + for ($j=1; $j<=$pcb->COMP[$i]['pads_count']['v']; $j++) + { + $pad_ofs = $pcb->COMP[$i]['pad'.$j.'_ofs']['v']; + if ($pad_ofs == $ofs) + { + return $pcb->COMP[$i]['pad'.$j.'_net']['v']; + } + } + } +} + +// include class +include("p/" . $proj[$PROJ_ID]['dir'] . "/Class_OrCad21.php"); + +// parse +// ------------------------------------------------------------------------------------------------ +$pcb = new orcad21("p/" . $proj[$PROJ_ID]['dir'] . "/sprint05.pcb"); +echo"file size = [".$pcb->FileSize."]
"; + +if (!$pcb->Parse()) +{ + echo"parser error
"; + return; +} + +// print results +// ------------------------------------------------------------------------------------------------ +echo"min_x = ".$pcb->MinPosX.", min_y = ".$pcb->MinPosY."
"; +echo"max_x = ".$pcb->MaxPosX.", max_y = ".$pcb->MaxPosY."
"; + +// transform all coordinates from "orcad-top-left" to "pcad-bottom-left" +$pcb->ChangePos(0,0, 0,($pcb->MaxPosY + $pcb->MinPosY), 1); + +// check ref duplicated +$REF = array(); +echo"validate ref...
"; +for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++) +{ + $ref1 = $pcb->COMP[$i]['name1_str']['v']; + $ref2 = ValidateRef($pcb->COMP[$i]['name1_str']['v']); + if ($ref1 != $ref2) + { + echo"name [$ref1] change to [$ref2]
"; + $pcb->COMP[$i]['name1_str']['v'] = $ref2; + } + +} + +echo"check duplicates...
"; +$found = 0; +for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++) +{ + $ref = $pcb->COMP[$i]['name1_str']['v']; + $REF[$ref] = $REF[$ref] + 1; + if ($REF[$ref] > 1) + $found = 1; +} +if ($found) +{ + echo"duplicate found!
"; + foreach ($REF as $ref => $m) + { + if ($REF[$ref] > 1) + { + echo"[$ref] = ".$REF[$ref]."
"; + $id = 1; + for($i=0; $i<=$pcb->HDR['comp_count_real']['v']; $i++) + { + $comp_ref = $pcb->COMP[$i]['name1_str']['v']; + if ($comp_ref == $ref) + { + $pcb->COMP[$i]['name1_str']['v'] = $comp_ref . "_DUP".$id; + $id++; + } + } + } + } +} + +$REF = array(); +echo"check duplicates...
"; +$found = 0; +for($i=1; $i<=$pcb->HDR['comp_count_real']['v']; $i++) +{ + $ref = $pcb->COMP[$i]['name1_str']['v']; + $REF[$ref] = $REF[$ref] + 1; + if ($REF[$ref] > 1) + $found = 1; +} +if ($found) + echo"duplicate found!
"; +else + echo"no duplicates now
"; + +echo"
"; + +// build ... diff --git a/pcb/sp97-sch-v1-neiro_upscale_1.png b/pcb/sp97-sch-v1-neiro_upscale_1.png new file mode 100644 index 0000000..868e468 Binary files /dev/null and b/pcb/sp97-sch-v1-neiro_upscale_1.png differ diff --git a/pcb/sp97-sch-v1-neiro_upscale_2.jpg b/pcb/sp97-sch-v1-neiro_upscale_2.jpg new file mode 100644 index 0000000..546e70a Binary files /dev/null and b/pcb/sp97-sch-v1-neiro_upscale_2.jpg differ diff --git a/pcb/sp97-sch-v1.jpg b/pcb/sp97-sch-v1.jpg new file mode 100644 index 0000000..b47098e Binary files /dev/null and b/pcb/sp97-sch-v1.jpg differ diff --git a/photos/altium.jpg b/photos/altium.jpg new file mode 100644 index 0000000..a71a2bb Binary files /dev/null and b/photos/altium.jpg differ diff --git a/photos/orcad440.jpg b/photos/orcad440.jpg new file mode 100644 index 0000000..ca62768 Binary files /dev/null and b/photos/orcad440.jpg differ diff --git a/photos/orcad440of.jpg b/photos/orcad440of.jpg new file mode 100644 index 0000000..e852e9e Binary files /dev/null and b/photos/orcad440of.jpg differ diff --git a/photos/parser1.jpg b/photos/parser1.jpg new file mode 100644 index 0000000..ba9dbd0 Binary files /dev/null and b/photos/parser1.jpg differ diff --git a/photos/parser2.jpg b/photos/parser2.jpg new file mode 100644 index 0000000..19af070 Binary files /dev/null and b/photos/parser2.jpg differ diff --git a/photos/sp97_bot.jpg b/photos/sp97_bot.jpg new file mode 100644 index 0000000..f3c1e09 Binary files /dev/null and b/photos/sp97_bot.jpg differ diff --git a/photos/sp97_top.jpg b/photos/sp97_top.jpg new file mode 100644 index 0000000..4c3f664 Binary files /dev/null and b/photos/sp97_top.jpg differ diff --git a/photos/sp98_bot.jpg b/photos/sp98_bot.jpg new file mode 100644 index 0000000..692ba65 Binary files /dev/null and b/photos/sp98_bot.jpg differ diff --git a/photos/sp98_mont.jpg b/photos/sp98_mont.jpg new file mode 100644 index 0000000..b84c06f Binary files /dev/null and b/photos/sp98_mont.jpg differ diff --git a/photos/sp98_top.jpg b/photos/sp98_top.jpg new file mode 100644 index 0000000..12d7a83 Binary files /dev/null and b/photos/sp98_top.jpg differ diff --git a/photos/sp_proto.jpg b/photos/sp_proto.jpg new file mode 100644 index 0000000..8d8130a Binary files /dev/null and b/photos/sp_proto.jpg differ