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https://github.com/holub/mame
synced 2025-06-09 14:22:41 +03:00
hd647180x: Eliminate data space and instead map internal RAM into program space using memory view
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a928d3c40c
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0049b39696
@ -18,8 +18,7 @@
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TODO: the current emulation is incomplete, implementing mostly
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TODO: the current emulation is incomplete, implementing mostly
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the internal memory and parallel ports. Timer 2 (which is very
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the internal memory and parallel ports. Timer 2 (which is very
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similar to the additional timer of the HD6301) is not emulated at
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similar to the additional timer of the HD6301) is not emulated at
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all. Programs trying to execute from internal RAM will also fail,
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all.
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though this likely capability is merely theoretical so far.
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**********************************************************************/
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**********************************************************************/
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@ -33,47 +32,22 @@
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DEFINE_DEVICE_TYPE(HD647180X, hd647180x_device, "hd647180x", "Hitachi HD647180X MCU")
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DEFINE_DEVICE_TYPE(HD647180X, hd647180x_device, "hd647180x", "Hitachi HD647180X MCU")
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hd647180x_device::hd647180x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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hd647180x_device::hd647180x_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: z180_device(mconfig, HD647180X, tag, owner, clock, true, address_map_constructor(FUNC(hd647180x_device::prom_map), this))
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: z180_device(mconfig, HD647180X, tag, owner, clock, true, address_map_constructor(FUNC(hd647180x_device::internal_map), this))
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, m_port_input_cb(*this)
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, m_port_input_cb(*this)
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, m_port_output_cb(*this)
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, m_port_output_cb(*this)
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, m_data_config("data", ENDIANNESS_LITTLE, 8, 9, 0, address_map_constructor(FUNC(hd647180x_device::ram_map), this))
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, m_ram_view(*this, "ram_view")
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{
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{
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// arbitrary initial states
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// arbitrary initial states
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m_ccsr = 0;
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m_ccsr = 0;
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std::fill(std::begin(m_odr), std::end(m_odr), 0);
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std::fill(std::begin(m_odr), std::end(m_odr), 0);
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}
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}
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void hd647180x_device::prom_map(address_map &map)
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void hd647180x_device::internal_map(address_map &map)
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{
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{
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map(0x00000, 0x03fff).rom().region(DEVICE_SELF, 0); // 16 KB internal PROM (not used in mode 1)
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map(0x00000, 0x03fff).rom().region(DEVICE_SELF, 0); // 16 KB internal PROM (not used in mode 1)
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}
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map(0x00000, 0xfffff).view(m_ram_view);
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for (unsigned pos = 0; pos < 16; pos++)
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void hd647180x_device::ram_map(address_map &map)
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m_ram_view[pos](offs_t(pos) << 16 | 0xfe00, offs_t(pos) << 16 | 0xffff).ram().share("ram");
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{
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map(0x000, 0x1ff).ram(); // 512 bytes remappable internal RAM (available in all modes)
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}
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device_memory_interface::space_config_vector hd647180x_device::memory_space_config() const
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{
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auto spaces = z180_device::memory_space_config();
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spaces.emplace_back(AS_DATA, &m_data_config);
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return spaces;
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}
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uint8_t hd647180x_device::z180_read_memory(offs_t addr)
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{
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if ((addr & 0xffe00) == (offs_t(m_rmcr) << 12 | 0x0fe00))
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return m_data->read_byte(addr & 0x1ff);
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else
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return z180_device::z180_read_memory(addr);
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}
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void hd647180x_device::z180_write_memory(offs_t addr, uint8_t data)
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{
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if ((addr & 0xffe00) == (offs_t(m_rmcr) << 12 | 0x0fe00))
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m_data->write_byte(addr & 0x1ff, data);
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else
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z180_device::z180_write_memory(addr, data);
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}
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}
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uint8_t hd647180x_device::z180_internal_port_read(uint8_t port)
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uint8_t hd647180x_device::z180_internal_port_read(uint8_t port)
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@ -236,6 +210,7 @@ void hd647180x_device::z180_internal_port_write(uint8_t port, uint8_t data)
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case 0x51:
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case 0x51:
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LOG("HD647180X RMCR wr $%02x\n", data);
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LOG("HD647180X RMCR wr $%02x\n", data);
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m_rmcr = data & 0xf0;
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m_rmcr = data & 0xf0;
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m_ram_view.select(m_rmcr >> 4);
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break;
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break;
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case 0x53:
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case 0x53:
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@ -285,8 +260,6 @@ void hd647180x_device::device_start()
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{
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{
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z180_device::device_start();
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z180_device::device_start();
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m_data = &space(AS_DATA);
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state_add(HD647180X_T2FRC, "T2FRC", m_t2frc.w);
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state_add(HD647180X_T2FRC, "T2FRC", m_t2frc.w);
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state_add(HD647180X_T2OCR1, "T2OCR1", m_t2ocr[0].w);
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state_add(HD647180X_T2OCR1, "T2OCR1", m_t2ocr[0].w);
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state_add(HD647180X_T2OCR2, "T2OCR2", m_t2ocr[1].w);
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state_add(HD647180X_T2OCR2, "T2OCR2", m_t2ocr[1].w);
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@ -294,7 +267,7 @@ void hd647180x_device::device_start()
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state_add(HD647180X_T2CSR1, "T2CSR1", m_t2csr[0]);
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state_add(HD647180X_T2CSR1, "T2CSR1", m_t2csr[0]);
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state_add(HD647180X_T2CSR2, "T2CSR2", m_t2csr[1]).mask(0xef);
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state_add(HD647180X_T2CSR2, "T2CSR2", m_t2csr[1]).mask(0xef);
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state_add(HD647180X_CCSR, "CCSR", m_ccsr).mask(0xbf);
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state_add(HD647180X_CCSR, "CCSR", m_ccsr).mask(0xbf);
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state_add(HD647180X_RMCR, "RMCR", m_rmcr).mask(0xf0);
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state_add(HD647180X_RMCR, "RMCR", m_rmcr, [this](u8 data) { m_rmcr = data; m_ram_view.select(data >> 4); }).mask(0xf0);
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state_add(HD647180X_DERA, "DERA", m_dera);
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state_add(HD647180X_DERA, "DERA", m_dera);
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for (int i = 0; i < 6; i++)
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for (int i = 0; i < 6; i++)
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{
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{
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@ -325,6 +298,7 @@ void hd647180x_device::device_reset()
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m_t2csr[1] = 0x00;
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m_t2csr[1] = 0x00;
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m_ccsr = (m_ccsr & 0x80) | 0x2c;
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m_ccsr = (m_ccsr & 0x80) | 0x2c;
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m_rmcr = 0;
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m_rmcr = 0;
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m_ram_view.select(0);
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m_dera = 0;
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m_dera = 0;
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std::fill(std::begin(m_ddr), std::end(m_ddr), 0);
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std::fill(std::begin(m_ddr), std::end(m_ddr), 0);
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}
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}
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@ -47,27 +47,20 @@ protected:
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virtual void device_start() override;
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_reset() override;
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// device_memory_interface overrides
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virtual space_config_vector memory_space_config() const override;
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// z180_device overrides
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// z180_device overrides
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virtual uint8_t z180_read_memory(offs_t addr) override;
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virtual void z180_write_memory(offs_t addr, uint8_t data) override;
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virtual uint8_t z180_internal_port_read(uint8_t port) override;
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virtual uint8_t z180_internal_port_read(uint8_t port) override;
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virtual void z180_internal_port_write(uint8_t port, uint8_t data) override;
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virtual void z180_internal_port_write(uint8_t port, uint8_t data) override;
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private:
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private:
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// internal memory maps
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// internal memory map
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void prom_map(address_map &map);
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void internal_map(address_map &map);
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void ram_map(address_map &map);
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// port callbacks
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// port callbacks
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devcb_read8::array<7> m_port_input_cb;
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devcb_read8::array<7> m_port_input_cb;
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devcb_write8::array<6> m_port_output_cb;
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devcb_write8::array<6> m_port_output_cb;
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// internal RAM space
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// internal RAM space
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address_space_config m_data_config;
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memory_view m_ram_view;
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address_space *m_data;
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// internal registers
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// internal registers
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PAIR16 m_t2frc;
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PAIR16 m_t2frc;
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@ -482,16 +482,6 @@ device_memory_interface::space_config_vector z180_device::memory_space_config()
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};
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};
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}
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}
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uint8_t z180_device::z180_read_memory(offs_t addr)
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{
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return m_program.read_byte(addr);
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}
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void z180_device::z180_write_memory(offs_t addr, uint8_t data)
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{
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m_program.write_byte(addr, data);
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}
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uint8_t z180_device::z180_readcontrol(offs_t port)
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uint8_t z180_device::z180_readcontrol(offs_t port)
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{
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{
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// normal external readport (ignore the data)
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// normal external readport (ignore the data)
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@ -140,8 +140,6 @@ protected:
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// device_disasm_interface overrides
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// device_disasm_interface overrides
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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virtual uint8_t z180_read_memory(offs_t addr);
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virtual void z180_write_memory(offs_t addr, uint8_t data);
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virtual uint8_t z180_internal_port_read(uint8_t port);
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virtual uint8_t z180_internal_port_read(uint8_t port);
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virtual void z180_internal_port_write(uint8_t port, uint8_t data);
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virtual void z180_internal_port_write(uint8_t port, uint8_t data);
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@ -152,6 +150,9 @@ protected:
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void set_address_width(int bits);
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void set_address_width(int bits);
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private:
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private:
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uint8_t z180_read_memory(offs_t addr) { return m_program.read_byte(addr); }
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void z180_write_memory(offs_t addr, uint8_t data) { m_program.write_byte(addr, data); }
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int memory_wait_states() const { return (m_dcntl & 0xc0) >> 6; }
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int memory_wait_states() const { return (m_dcntl & 0xc0) >> 6; }
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int io_wait_states() const { return (m_dcntl & 0x30) == 0 ? 0 : ((m_dcntl & 0x30) >> 4) + 1; }
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int io_wait_states() const { return (m_dcntl & 0x30) == 0 ? 0 : ((m_dcntl & 0x30) >> 4) + 1; }
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bool is_internal_io_address(uint16_t port) const { return ((port ^ m_iocr) & (m_extended_io ? 0xff80 : 0xffc0)) == 0; }
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bool is_internal_io_address(uint16_t port) const { return ((port ^ m_iocr) & (m_extended_io ? 0xff80 : 0xffc0)) == 0; }
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