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https://github.com/holub/mame
synced 2025-04-24 01:11:11 +03:00
mb8421: Create 16-bit expanded variant and add it to thndzone/dassault
This commit is contained in:
AJR
parent
779fb78d09
commit
00573e7976
@ -1,13 +1,13 @@
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// license:BSD-3-Clause
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// copyright-holders:hap
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// copyright-holders:hap,AJR
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/**********************************************************************
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Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
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CMOS 16K-bit (2KB) dual-port SRAM
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MB84x2 lacks interrupt pins, it's basically as simple as AM_RAM AM_SHARE("x")
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MB843x is same as MB842x, except that it supports slave mode. It makes
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sure there are no clashes, with the _BUSY pin.
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MB843x is same as MB842x, except that it supports slave mode for 16-bit or
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32-bit expansion. It makes sure there are no clashes with the _BUSY pin.
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**********************************************************************/
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@ -15,16 +15,35 @@
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#include "machine/mb8421.h"
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DEFINE_DEVICE_TYPE(MB8421, mb8421_device, "mb8421", "MB8421 DPSRAM")
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DEFINE_DEVICE_TYPE(MB8421, mb8421_device, "mb8421", "MB8421 8-bit Dual-Port SRAM")
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DEFINE_DEVICE_TYPE(MB8421_MB8431_16BIT, mb8421_mb8431_16_device, "mb8421_mb8431_16", "MB8421/MB8431 16-bit Dual-Port SRAM")
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//-------------------------------------------------
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// mb8421_master_device - constructor
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//-------------------------------------------------
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mb8421_master_device::mb8421_master_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
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: device_t(mconfig, type, tag, owner, clock),
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m_intl_handler(*this),
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m_intr_handler(*this)
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{
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}
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//-------------------------------------------------
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// mb8421_device - constructor
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//-------------------------------------------------
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mb8421_device::mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, MB8421, tag, owner, clock),
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m_intl_handler(*this),
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m_intr_handler(*this)
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mb8421_device::mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: mb8421_master_device(mconfig, MB8421, tag, owner, clock)
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{
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}
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//-------------------------------------------------
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// mb8421_mb8431_16_device - constructor
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//-------------------------------------------------
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mb8421_mb8431_16_device::mb8421_mb8431_16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: mb8421_master_device(mconfig, MB8421_MB8431_16BIT, tag, owner, clock)
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{
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}
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@ -32,64 +51,132 @@ mb8421_device::mb8421_device(const machine_config &mconfig, const char *tag, dev
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// device_start - device-specific startup
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//-------------------------------------------------
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void mb8421_device::device_start()
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void mb8421_master_device::device_start()
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{
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memset(m_ram, 0, 0x800);
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// resolve callbacks
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m_intl_handler.resolve_safe();
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m_intr_handler.resolve_safe();
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}
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void mb8421_device::device_start()
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{
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mb8421_master_device::device_start();
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m_ram = make_unique_clear<u8[]>(0x800);
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// state save
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save_item(NAME(m_ram));
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save_pointer(NAME(m_ram.get()), 0x800);
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}
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void mb8421_mb8431_16_device::device_start()
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{
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mb8421_master_device::device_start();
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m_ram = make_unique_clear<u16[]>(0x800);
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// state save
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save_pointer(NAME(m_ram.get()), 0x800);
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void mb8421_device::device_reset()
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void mb8421_master_device::device_reset()
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{
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m_intl_handler(0);
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m_intr_handler(0);
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}
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//-------------------------------------------------
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// update_intr - update interrupt lines upon
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// read or write accesses to special locations
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//-------------------------------------------------
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template<read_or_write row, bool is_right>
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void mb8421_master_device::update_intr(offs_t offset)
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{
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if (machine().side_effect_disabled())
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return;
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if (row == read_or_write::WRITE && offset == (is_right ? 0x7fe : 0x7ff))
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(is_right ? m_intl_handler : m_intr_handler)(1);
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else if (row == read_or_write::READ && offset == (is_right ? 0x7ff : 0x7fe))
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(is_right ? m_intr_handler : m_intl_handler)(0);
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}
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//-------------------------------------------------
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// left_w - write access for left-side bus
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// (write to 7FF asserts INTR)
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//-------------------------------------------------
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WRITE8_MEMBER(mb8421_device::left_w)
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{
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offset &= 0x7ff;
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m_ram[offset] = data;
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if (offset == 0x7ff)
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m_intr_handler(1);
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update_intr<read_or_write::WRITE, false>(offset);
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}
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WRITE16_MEMBER(mb8421_mb8431_16_device::left_w)
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{
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offset &= 0x7ff;
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m_ram[offset] = data;
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update_intr<read_or_write::WRITE, false>(offset);
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}
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//-------------------------------------------------
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// left_r - read access for left-side bus
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// (read from 7FE acknowledges INTL)
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//-------------------------------------------------
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READ8_MEMBER(mb8421_device::left_r)
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{
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offset &= 0x7ff;
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if (offset == 0x7fe && !machine().side_effect_disabled())
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m_intl_handler(0);
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update_intr<read_or_write::READ, false>(offset);
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return m_ram[offset];
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}
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READ16_MEMBER(mb8421_mb8431_16_device::left_r)
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{
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offset &= 0x7ff;
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update_intr<read_or_write::READ, false>(offset);
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return m_ram[offset];
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}
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//-------------------------------------------------
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// right_w - write access for right-side bus
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// (write to 7FE asserts INTL)
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//-------------------------------------------------
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WRITE8_MEMBER(mb8421_device::right_w)
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{
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offset &= 0x7ff;
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m_ram[offset] = data;
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if (offset == 0x7fe)
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m_intl_handler(1);
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update_intr<read_or_write::WRITE, true>(offset);
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}
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WRITE16_MEMBER(mb8421_mb8431_16_device::right_w)
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{
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offset &= 0x7ff;
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m_ram[offset] = data;
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update_intr<read_or_write::WRITE, true>(offset);
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}
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//-------------------------------------------------
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// right_r - read access for right-side bus
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// (read from 7FF acknowledges INTR)
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//-------------------------------------------------
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READ8_MEMBER(mb8421_device::right_r)
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{
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offset &= 0x7ff;
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if (offset == 0x7ff && !machine().side_effect_disabled())
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m_intr_handler(0);
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update_intr<read_or_write::READ, true>(offset);
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return m_ram[offset];
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}
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READ16_MEMBER(mb8421_mb8431_16_device::right_r)
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{
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offset &= 0x7ff;
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update_intr<read_or_write::READ, true>(offset);
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return m_ram[offset];
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}
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@ -1,5 +1,5 @@
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// license:BSD-3-Clause
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// copyright-holders:hap
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// copyright-holders:hap,AJR
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/**********************************************************************
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Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
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@ -13,7 +13,6 @@
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#pragma once
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//**************************************************************************
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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@ -21,11 +20,10 @@
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// note: INT pins are only available on MB84x1
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// INTL is for the CPU on the left side, INTR for the one on the right
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#define MCFG_MB8421_INTL_HANDLER(_devcb) \
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devcb = &mb8421_device::set_intl_handler(*device, DEVCB_##_devcb);
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devcb = &mb8421_master_device::set_intl_handler(*device, DEVCB_##_devcb);
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#define MCFG_MB8421_INTR_HANDLER(_devcb) \
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devcb = &mb8421_device::set_intr_handler(*device, DEVCB_##_devcb);
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devcb = &mb8421_master_device::set_intr_handler(*device, DEVCB_##_devcb);
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//**************************************************************************
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@ -34,37 +32,76 @@
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// ======================> mb8421_device
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class mb8421_device : public device_t
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class mb8421_master_device : public device_t
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{
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public:
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mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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// static configuration helpers
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template <class Object> static devcb_base &set_intl_handler(device_t &device, Object &&cb) { return downcast<mb8421_device &>(device).m_intl_handler.set_callback(std::forward<Object>(cb)); }
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template <class Object> static devcb_base &set_intr_handler(device_t &device, Object &&cb) { return downcast<mb8421_device &>(device).m_intr_handler.set_callback(std::forward<Object>(cb)); }
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template <class Object> static devcb_base &set_intl_handler(device_t &device, Object &&cb) { return downcast<mb8421_master_device &>(device).m_intl_handler.set_callback(std::forward<Object>(cb)); }
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template <class Object> static devcb_base &set_intr_handler(device_t &device, Object &&cb) { return downcast<mb8421_master_device &>(device).m_intr_handler.set_callback(std::forward<Object>(cb)); }
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DECLARE_READ_LINE_MEMBER( busy_r ) { return 0; } // _BUSY pin - not emulated
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uint8_t peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
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DECLARE_WRITE8_MEMBER( left_w );
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DECLARE_READ8_MEMBER( left_r );
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DECLARE_WRITE8_MEMBER( right_w );
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DECLARE_READ8_MEMBER( right_r );
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DECLARE_READ_LINE_MEMBER(busy_r) { return 0; } // _BUSY pin - not emulated
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protected:
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mb8421_master_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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private:
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uint8_t m_ram[0x800];
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// internal helpers
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template<read_or_write row, bool is_right> void update_intr(offs_t offset);
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private:
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devcb_write_line m_intl_handler;
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devcb_write_line m_intr_handler;
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};
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// ======================> mb8421_device
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class mb8421_device : public mb8421_master_device
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{
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public:
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mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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u8 peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
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DECLARE_WRITE8_MEMBER(left_w);
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DECLARE_READ8_MEMBER(left_r);
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DECLARE_WRITE8_MEMBER(right_w);
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DECLARE_READ8_MEMBER(right_r);
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protected:
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// device-level overrides
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virtual void device_start() override;
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private:
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std::unique_ptr<u8[]> m_ram;
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};
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// ======================> mb8421_mb8431_16_device
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class mb8421_mb8431_16_device : public mb8421_master_device
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{
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public:
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mb8421_mb8431_16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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u16 peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
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DECLARE_WRITE16_MEMBER(left_w);
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DECLARE_READ16_MEMBER(left_r);
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DECLARE_WRITE16_MEMBER(right_w);
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DECLARE_READ16_MEMBER(right_r);
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protected:
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// device-level overrides
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virtual void device_start() override;
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private:
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std::unique_ptr<u16[]> m_ram;
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};
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// device type definition
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extern const device_type MB8421;
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DECLARE_DEVICE_TYPE(MB8421, mb8421_device)
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DECLARE_DEVICE_TYPE(MB8421_MB8431_16BIT, mb8421_mb8431_16_device)
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#endif // MAME_MACHINE_MB8421_H
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@ -211,6 +211,7 @@ Dip locations verified with US conversion kit manual.
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#include "cpu/m68000/m68000.h"
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#include "cpu/h6280/h6280.h"
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#include "machine/mb8421.h"
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#include "sound/2203intf.h"
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#include "sound/ym2151.h"
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#include "screen.h"
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@ -254,38 +255,6 @@ READ16_MEMBER(dassault_state::dassault_sub_control_r)
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return ioport("VBLANK1")->read();
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}
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/* The CPU-CPU irq controller is overlaid onto the end of the shared memory */
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READ16_MEMBER(dassault_state::dassault_irq_r)
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{
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switch (offset)
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{
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case 0: m_maincpu->set_input_line(5, CLEAR_LINE); break;
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case 1: m_subcpu->set_input_line(6, CLEAR_LINE); break;
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}
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return m_shared_ram[(0xffc / 2) + offset]; /* The values probably don't matter */
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}
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WRITE16_MEMBER(dassault_state::dassault_irq_w)
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{
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switch (offset)
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{
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case 0: m_maincpu->set_input_line(5, ASSERT_LINE); break;
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case 1: m_subcpu->set_input_line(6, ASSERT_LINE); break;
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}
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COMBINE_DATA(&m_shared_ram[(0xffc / 2) + offset]); /* The values probably don't matter */
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}
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WRITE16_MEMBER(dassault_state::shared_ram_w)
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{
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COMBINE_DATA(&m_shared_ram[offset]);
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}
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READ16_MEMBER(dassault_state::shared_ram_r)
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{
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return m_shared_ram[offset];
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}
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/**********************************************************************************/
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static ADDRESS_MAP_START( dassault_map, AS_PROGRAM, 16, dassault_state )
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@ -313,8 +282,7 @@ static ADDRESS_MAP_START( dassault_map, AS_PROGRAM, 16, dassault_state )
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AM_RANGE(0x3f8000, 0x3fbfff) AM_RAM AM_SHARE("ram") /* Main ram */
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AM_RANGE(0x3fc000, 0x3fcfff) AM_RAM AM_SHARE("spriteram2") /* Spriteram (2nd) */
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AM_RANGE(0x3feffc, 0x3fefff) AM_READWRITE(dassault_irq_r, dassault_irq_w)
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AM_RANGE(0x3fe000, 0x3fefff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_SHARE("shared_ram") /* Shared ram */
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AM_RANGE(0x3fe000, 0x3fefff) AM_DEVREADWRITE("sharedram", mb8421_mb8431_16_device, left_r, left_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( dassault_sub_map, AS_PROGRAM, 16, dassault_state )
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@ -326,8 +294,7 @@ static ADDRESS_MAP_START( dassault_sub_map, AS_PROGRAM, 16, dassault_state )
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AM_RANGE(0x3f8000, 0x3fbfff) AM_RAM AM_SHARE("ram2") /* Sub cpu ram */
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AM_RANGE(0x3fc000, 0x3fcfff) AM_RAM AM_SHARE("spriteram") /* Sprite ram */
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AM_RANGE(0x3feffc, 0x3fefff) AM_READWRITE(dassault_irq_r, dassault_irq_w)
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AM_RANGE(0x3fe000, 0x3fefff) AM_READWRITE(shared_ram_r, shared_ram_w)
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AM_RANGE(0x3fe000, 0x3fefff) AM_DEVREADWRITE("sharedram", mb8421_mb8431_16_device, right_r, right_w)
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ADDRESS_MAP_END
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/******************************************************************************/
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@ -548,6 +515,10 @@ static MACHINE_CONFIG_START( dassault )
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// MCFG_QUANTUM_TIME(attotime::from_hz(8400)) /* 140 CPU slices per frame */
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MCFG_QUANTUM_PERFECT_CPU("maincpu") // I was seeing random lockups.. let's see if this helps
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MCFG_DEVICE_ADD("sharedram", MB8421_MB8431_16BIT, 0)
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MCFG_MB8421_INTL_HANDLER(INPUTLINE("maincpu", M68K_IRQ_5))
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MCFG_MB8421_INTR_HANDLER(INPUTLINE("sub", M68K_IRQ_6))
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/* video hardware */
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MCFG_SCREEN_ADD("screen", RASTER)
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MCFG_SCREEN_REFRESH_RATE(60)
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@ -34,7 +34,6 @@ public:
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m_pf2_rowscroll(*this, "pf2_rowscroll"),
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m_pf4_rowscroll(*this, "pf4_rowscroll"),
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m_ram(*this, "ram"),
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m_shared_ram(*this, "shared_ram"),
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m_ram2(*this, "ram2")
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{ }
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@ -58,16 +57,11 @@ public:
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required_shared_ptr<uint16_t> m_pf2_rowscroll;
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required_shared_ptr<uint16_t> m_pf4_rowscroll;
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required_shared_ptr<uint16_t> m_ram;
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required_shared_ptr<uint16_t> m_shared_ram;
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required_shared_ptr<uint16_t> m_ram2;
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DECLARE_READ16_MEMBER(dassault_control_r);
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DECLARE_WRITE16_MEMBER(dassault_control_w);
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DECLARE_READ16_MEMBER(dassault_sub_control_r);
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DECLARE_READ16_MEMBER(dassault_irq_r);
|
||||
DECLARE_WRITE16_MEMBER(dassault_irq_w);
|
||||
DECLARE_WRITE16_MEMBER(shared_ram_w);
|
||||
DECLARE_READ16_MEMBER(shared_ram_r);
|
||||
DECLARE_WRITE8_MEMBER(sound_bankswitch_w);
|
||||
DECLARE_DRIVER_INIT(thndzone);
|
||||
DECLARE_DRIVER_INIT(dassault);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user