mb8421: Create 16-bit expanded variant and add it to thndzone/dassault

src/devices/machine/mb8421.cpp

@@ -1,13 +1,13 @@
 // license:BSD-3-Clause
-// copyright-holders:hap
+// copyright-holders:hap,AJR
 /**********************************************************************
 
     Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
     CMOS 16K-bit (2KB) dual-port SRAM
 
     MB84x2 lacks interrupt pins, it's basically as simple as AM_RAM AM_SHARE("x")
-    MB843x is same as MB842x, except that it supports slave mode. It makes
+    MB843x is same as MB842x, except that it supports slave mode for 16-bit or
-    sure there are no clashes, with the _BUSY pin.
+    32-bit expansion. It makes sure there are no clashes with the _BUSY pin.
 
 **********************************************************************/
 
@@ -15,16 +15,35 @@
 #include "machine/mb8421.h"
 
 
-DEFINE_DEVICE_TYPE(MB8421, mb8421_device, "mb8421", "MB8421 DPSRAM")
+DEFINE_DEVICE_TYPE(MB8421, mb8421_device, "mb8421", "MB8421 8-bit Dual-Port SRAM")
+DEFINE_DEVICE_TYPE(MB8421_MB8431_16BIT, mb8421_mb8431_16_device, "mb8421_mb8431_16", "MB8421/MB8431 16-bit Dual-Port SRAM")
+
+//-------------------------------------------------
+//  mb8421_master_device - constructor
+//-------------------------------------------------
+
+mb8421_master_device::mb8421_master_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
+	: device_t(mconfig, type, tag, owner, clock),
+		m_intl_handler(*this),
+		m_intr_handler(*this)
+{
+}
 
 //-------------------------------------------------
 //  mb8421_device - constructor
 //-------------------------------------------------
 
-mb8421_device::mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+mb8421_device::mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
-	: device_t(mconfig, MB8421, tag, owner, clock),
+	: mb8421_master_device(mconfig, MB8421, tag, owner, clock)
-		m_intl_handler(*this),
+{
-		m_intr_handler(*this)
+}
+
+//-------------------------------------------------
+//  mb8421_mb8431_16_device - constructor
+//-------------------------------------------------
+
+mb8421_mb8431_16_device::mb8421_mb8431_16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+	: mb8421_master_device(mconfig, MB8421_MB8431_16BIT, tag, owner, clock)
 {
 }
 
@@ -32,64 +51,132 @@ mb8421_device::mb8421_device(const machine_config &mconfig, const char *tag, dev
 //  device_start - device-specific startup
 //-------------------------------------------------
 
-void mb8421_device::device_start()
+void mb8421_master_device::device_start()
 {
-	memset(m_ram, 0, 0x800);
-
 	// resolve callbacks
 	m_intl_handler.resolve_safe();
 	m_intr_handler.resolve_safe();
+}
+
+void mb8421_device::device_start()
+{
+	mb8421_master_device::device_start();
+
+	m_ram = make_unique_clear<u8[]>(0x800);
 
 	// state save
-	save_item(NAME(m_ram));
+	save_pointer(NAME(m_ram.get()), 0x800);
+}
+
+void mb8421_mb8431_16_device::device_start()
+{
+	mb8421_master_device::device_start();
+
+	m_ram = make_unique_clear<u16[]>(0x800);
+
+	// state save
+	save_pointer(NAME(m_ram.get()), 0x800);
 }
 
 //-------------------------------------------------
 //  device_reset - device-specific reset
 //-------------------------------------------------
 
-void mb8421_device::device_reset()
+void mb8421_master_device::device_reset()
 {
 	m_intl_handler(0);
 	m_intr_handler(0);
 }
 
+//-------------------------------------------------
+//  update_intr - update interrupt lines upon
+//  read or write accesses to special locations
+//-------------------------------------------------
 
+template<read_or_write row, bool is_right>
+void mb8421_master_device::update_intr(offs_t offset)
+{
+	if (machine().side_effect_disabled())
+		return;
+
+	if (row == read_or_write::WRITE && offset == (is_right ? 0x7fe : 0x7ff))
+		(is_right ? m_intl_handler : m_intr_handler)(1);
+	else if (row == read_or_write::READ && offset == (is_right ? 0x7ff : 0x7fe))
+		(is_right ? m_intr_handler : m_intl_handler)(0);
+}
+
+//-------------------------------------------------
+//  left_w - write access for left-side bus
+//  (write to 7FF asserts INTR)
+//-------------------------------------------------
 
 WRITE8_MEMBER(mb8421_device::left_w)
 {
 	offset &= 0x7ff;
 	m_ram[offset] = data;
-
+	update_intr<read_or_write::WRITE, false>(offset);
-	if (offset == 0x7ff)
-		m_intr_handler(1);
 }
 
+WRITE16_MEMBER(mb8421_mb8431_16_device::left_w)
+{
+	offset &= 0x7ff;
+	m_ram[offset] = data;
+	update_intr<read_or_write::WRITE, false>(offset);
+}
+
+//-------------------------------------------------
+//  left_r - read access for left-side bus
+//  (read from 7FE acknowledges INTL)
+//-------------------------------------------------
+
 READ8_MEMBER(mb8421_device::left_r)
 {
 	offset &= 0x7ff;
-
+	update_intr<read_or_write::READ, false>(offset);
-	if (offset == 0x7fe && !machine().side_effect_disabled())
-		m_intl_handler(0);
-
 	return m_ram[offset];
 }
 
+READ16_MEMBER(mb8421_mb8431_16_device::left_r)
+{
+	offset &= 0x7ff;
+	update_intr<read_or_write::READ, false>(offset);
+	return m_ram[offset];
+}
+
+//-------------------------------------------------
+//  right_w - write access for right-side bus
+//  (write to 7FE asserts INTL)
+//-------------------------------------------------
+
 WRITE8_MEMBER(mb8421_device::right_w)
 {
 	offset &= 0x7ff;
 	m_ram[offset] = data;
-
+	update_intr<read_or_write::WRITE, true>(offset);
-	if (offset == 0x7fe)
-		m_intl_handler(1);
 }
 
+WRITE16_MEMBER(mb8421_mb8431_16_device::right_w)
+{
+	offset &= 0x7ff;
+	m_ram[offset] = data;
+	update_intr<read_or_write::WRITE, true>(offset);
+}
+
+//-------------------------------------------------
+//  right_r - read access for right-side bus
+//  (read from 7FF acknowledges INTR)
+//-------------------------------------------------
+
 READ8_MEMBER(mb8421_device::right_r)
 {
 	offset &= 0x7ff;
-
+	update_intr<read_or_write::READ, true>(offset);
-	if (offset == 0x7ff && !machine().side_effect_disabled())
+	return m_ram[offset];
-		m_intr_handler(0);
+}
-
+
+READ16_MEMBER(mb8421_mb8431_16_device::right_r)
+{
+	offset &= 0x7ff;
+	update_intr<read_or_write::READ, true>(offset);
 	return m_ram[offset];
 }

src/devices/machine/mb8421.h

@@ -1,5 +1,5 @@
 // license:BSD-3-Clause
-// copyright-holders:hap
+// copyright-holders:hap,AJR
 /**********************************************************************
 
     Fujitsu MB8421/22/31/32-90/-90L/-90LL/-12/-12L/-12LL
@@ -13,7 +13,6 @@
 #pragma once
 
 
-
 //**************************************************************************
 //  INTERFACE CONFIGURATION MACROS
 //**************************************************************************
@@ -21,11 +20,10 @@
 // note: INT pins are only available on MB84x1
 // INTL is for the CPU on the left side, INTR for the one on the right
 #define MCFG_MB8421_INTL_HANDLER(_devcb) \
-	devcb = &mb8421_device::set_intl_handler(*device, DEVCB_##_devcb);
+	devcb = &mb8421_master_device::set_intl_handler(*device, DEVCB_##_devcb);
 
 #define MCFG_MB8421_INTR_HANDLER(_devcb) \
-	devcb = &mb8421_device::set_intr_handler(*device, DEVCB_##_devcb);
+	devcb = &mb8421_master_device::set_intr_handler(*device, DEVCB_##_devcb);
-
 
 
 //**************************************************************************
@@ -34,17 +32,38 @@
 
 // ======================> mb8421_device
 
-class mb8421_device : public device_t
+class mb8421_master_device : public device_t
 {
 public:
-	mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
 	// static configuration helpers
-	template <class Object> static devcb_base &set_intl_handler(device_t &device, Object &&cb) { return downcast<mb8421_device &>(device).m_intl_handler.set_callback(std::forward<Object>(cb)); }
+	template <class Object> static devcb_base &set_intl_handler(device_t &device, Object &&cb) { return downcast<mb8421_master_device &>(device).m_intl_handler.set_callback(std::forward<Object>(cb)); }
-	template <class Object> static devcb_base &set_intr_handler(device_t &device, Object &&cb) { return downcast<mb8421_device &>(device).m_intr_handler.set_callback(std::forward<Object>(cb)); }
+	template <class Object> static devcb_base &set_intr_handler(device_t &device, Object &&cb) { return downcast<mb8421_master_device &>(device).m_intr_handler.set_callback(std::forward<Object>(cb)); }
 
 	DECLARE_READ_LINE_MEMBER(busy_r) { return 0; } // _BUSY pin - not emulated
-	uint8_t peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
+
+protected:
+	mb8421_master_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
+
+	// device-level overrides
+	virtual void device_start() override;
+	virtual void device_reset() override;
+
+	// internal helpers
+	template<read_or_write row, bool is_right> void update_intr(offs_t offset);
+
+private:
+	devcb_write_line m_intl_handler;
+	devcb_write_line m_intr_handler;
+};
+
+// ======================> mb8421_device
+
+class mb8421_device : public mb8421_master_device
+{
+public:
+	mb8421_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+	u8 peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
 
 	DECLARE_WRITE8_MEMBER(left_w);
 	DECLARE_READ8_MEMBER(left_r);
@@ -54,17 +73,35 @@ public:
 protected:
 	// device-level overrides
 	virtual void device_start() override;
-	virtual void device_reset() override;
 
 private:
-	uint8_t m_ram[0x800];
+	std::unique_ptr<u8[]> m_ram;
+};
 
-	devcb_write_line m_intl_handler;
+// ======================> mb8421_mb8431_16_device
-	devcb_write_line m_intr_handler;
+
+class mb8421_mb8431_16_device : public mb8421_master_device
+{
+public:
+	mb8421_mb8431_16_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+	u16 peek(offs_t offset) { return m_ram[offset & 0x7ff]; }
+
+	DECLARE_WRITE16_MEMBER(left_w);
+	DECLARE_READ16_MEMBER(left_r);
+	DECLARE_WRITE16_MEMBER(right_w);
+	DECLARE_READ16_MEMBER(right_r);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override;
+
+private:
+	std::unique_ptr<u16[]> m_ram;
 };
 
 // device type definition
-extern const device_type MB8421;
 DECLARE_DEVICE_TYPE(MB8421, mb8421_device)
+DECLARE_DEVICE_TYPE(MB8421_MB8431_16BIT, mb8421_mb8431_16_device)
 
 #endif // MAME_MACHINE_MB8421_H

src/mame/drivers/dassault.cpp

@@ -211,6 +211,7 @@ Dip locations verified with US conversion kit manual.
 
 #include "cpu/m68000/m68000.h"
 #include "cpu/h6280/h6280.h"
+#include "machine/mb8421.h"
 #include "sound/2203intf.h"
 #include "sound/ym2151.h"
 #include "screen.h"
@@ -254,38 +255,6 @@ READ16_MEMBER(dassault_state::dassault_sub_control_r)
 	return ioport("VBLANK1")->read();
 }
 
-/* The CPU-CPU irq controller is overlaid onto the end of the shared memory */
-READ16_MEMBER(dassault_state::dassault_irq_r)
-{
-	switch (offset)
-	{
-	case 0: m_maincpu->set_input_line(5, CLEAR_LINE); break;
-	case 1: m_subcpu->set_input_line(6, CLEAR_LINE); break;
-	}
-	return m_shared_ram[(0xffc / 2) + offset]; /* The values probably don't matter */
-}
-
-WRITE16_MEMBER(dassault_state::dassault_irq_w)
-{
-	switch (offset)
-	{
-	case 0: m_maincpu->set_input_line(5, ASSERT_LINE); break;
-	case 1: m_subcpu->set_input_line(6, ASSERT_LINE); break;
-	}
-
-	COMBINE_DATA(&m_shared_ram[(0xffc / 2) + offset]); /* The values probably don't matter */
-}
-
-WRITE16_MEMBER(dassault_state::shared_ram_w)
-{
-	COMBINE_DATA(&m_shared_ram[offset]);
-}
-
-READ16_MEMBER(dassault_state::shared_ram_r)
-{
-	return m_shared_ram[offset];
-}
-
 /**********************************************************************************/
 
 static ADDRESS_MAP_START( dassault_map, AS_PROGRAM, 16, dassault_state )
@@ -313,8 +282,7 @@ static ADDRESS_MAP_START( dassault_map, AS_PROGRAM, 16, dassault_state )
 
 	AM_RANGE(0x3f8000, 0x3fbfff) AM_RAM AM_SHARE("ram") /* Main ram */
 	AM_RANGE(0x3fc000, 0x3fcfff) AM_RAM AM_SHARE("spriteram2") /* Spriteram (2nd) */
-	AM_RANGE(0x3feffc, 0x3fefff) AM_READWRITE(dassault_irq_r, dassault_irq_w)
+	AM_RANGE(0x3fe000, 0x3fefff) AM_DEVREADWRITE("sharedram", mb8421_mb8431_16_device, left_r, left_w)
-	AM_RANGE(0x3fe000, 0x3fefff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_SHARE("shared_ram") /* Shared ram */
 ADDRESS_MAP_END
 
 static ADDRESS_MAP_START( dassault_sub_map, AS_PROGRAM, 16, dassault_state )
@@ -326,8 +294,7 @@ static ADDRESS_MAP_START( dassault_sub_map, AS_PROGRAM, 16, dassault_state )
 
 	AM_RANGE(0x3f8000, 0x3fbfff) AM_RAM AM_SHARE("ram2") /* Sub cpu ram */
 	AM_RANGE(0x3fc000, 0x3fcfff) AM_RAM AM_SHARE("spriteram") /* Sprite ram */
-	AM_RANGE(0x3feffc, 0x3fefff) AM_READWRITE(dassault_irq_r, dassault_irq_w)
+	AM_RANGE(0x3fe000, 0x3fefff) AM_DEVREADWRITE("sharedram", mb8421_mb8431_16_device, right_r, right_w)
-	AM_RANGE(0x3fe000, 0x3fefff) AM_READWRITE(shared_ram_r, shared_ram_w)
 ADDRESS_MAP_END
 
 /******************************************************************************/
@@ -548,6 +515,10 @@ static MACHINE_CONFIG_START( dassault )
 //  MCFG_QUANTUM_TIME(attotime::from_hz(8400)) /* 140 CPU slices per frame */
 	MCFG_QUANTUM_PERFECT_CPU("maincpu") // I was seeing random lockups.. let's see if this helps
 
+	MCFG_DEVICE_ADD("sharedram", MB8421_MB8431_16BIT, 0)
+	MCFG_MB8421_INTL_HANDLER(INPUTLINE("maincpu", M68K_IRQ_5))
+	MCFG_MB8421_INTR_HANDLER(INPUTLINE("sub", M68K_IRQ_6))
+
 	/* video hardware */
 	MCFG_SCREEN_ADD("screen", RASTER)
 	MCFG_SCREEN_REFRESH_RATE(60)

src/mame/includes/dassault.h

@@ -34,7 +34,6 @@ public:
 		m_pf2_rowscroll(*this, "pf2_rowscroll"),
 		m_pf4_rowscroll(*this, "pf4_rowscroll"),
 		m_ram(*this, "ram"),
-		m_shared_ram(*this, "shared_ram"),
 		m_ram2(*this, "ram2")
 
 	{ }
@@ -58,16 +57,11 @@ public:
 	required_shared_ptr<uint16_t> m_pf2_rowscroll;
 	required_shared_ptr<uint16_t> m_pf4_rowscroll;
 	required_shared_ptr<uint16_t> m_ram;
-	required_shared_ptr<uint16_t> m_shared_ram;
 	required_shared_ptr<uint16_t> m_ram2;
 
 	DECLARE_READ16_MEMBER(dassault_control_r);
 	DECLARE_WRITE16_MEMBER(dassault_control_w);
 	DECLARE_READ16_MEMBER(dassault_sub_control_r);
-	DECLARE_READ16_MEMBER(dassault_irq_r);
-	DECLARE_WRITE16_MEMBER(dassault_irq_w);
-	DECLARE_WRITE16_MEMBER(shared_ram_w);
-	DECLARE_READ16_MEMBER(shared_ram_r);
 	DECLARE_WRITE8_MEMBER(sound_bankswitch_w);
 	DECLARE_DRIVER_INIT(thndzone);
 	DECLARE_DRIVER_INIT(dassault);