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https://github.com/holub/mame
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fs3216: A very preliminary MMU (nw)
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6aa1dbe27d
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@ -13,6 +13,7 @@
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#include "cpu/m68000/m68000.h"
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#include "cpu/8x300/8x300.h"
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//#include "imagedev/floppy.h"
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#include "machine/bankdev.h"
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//#include "machine/com8116.h"
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#include "machine/upd765.h"
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#include "machine/x2212.h"
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@ -28,6 +29,7 @@ public:
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fs3216_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_clb(*this, "clb")
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, m_ctc(*this, "ctc")
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, m_fdc(*this, "fdc")
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, m_earom(*this, "earom")
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@ -38,10 +40,16 @@ public:
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protected:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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private:
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MC6845_UPDATE_ROW(update_row);
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DECLARE_READ16_MEMBER(mmu_read);
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DECLARE_WRITE16_MEMBER(mmu_write);
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DECLARE_WRITE_LINE_MEMBER(mmu_reset_w);
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void mmu_init_w(u16 data);
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DECLARE_READ8_MEMBER(ctc_r);
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DECLARE_WRITE8_MEMBER(ctc_w);
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void floppy_select_w(u8 data);
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@ -53,15 +61,20 @@ private:
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u16 earom_store_r();
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void main_map(address_map &map);
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void clb_map(address_map &map);
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void wdcpu_prog_map(address_map &map);
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void wdcpu_bank_map(address_map &map);
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required_device<cpu_device> m_maincpu;
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required_device<m68000_device> m_maincpu;
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required_device<address_map_bank_device> m_clb;
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required_device<z80ctc_device> m_ctc;
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required_device<upd765a_device> m_fdc;
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required_device<x2212_device> m_earom;
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std::unique_ptr<u8[]> m_fdc_ram;
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bool m_in_reset;
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bool m_mmu_init;
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};
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@ -69,6 +82,18 @@ void fs3216_state::machine_start()
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{
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m_fdc_ram = make_unique_clear<u8[]>(0x400);
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save_pointer(NAME(m_fdc_ram), 0x400);
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save_item(NAME(m_in_reset));
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save_item(NAME(m_mmu_init));
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}
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void fs3216_state::machine_reset()
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{
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m_in_reset = true;
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m_mmu_init = false;
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// FIXME: fix the 68000 so that it doesn't read vectors during device_reset
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m_maincpu->reset();
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}
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@ -77,6 +102,48 @@ MC6845_UPDATE_ROW(fs3216_state::update_row)
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}
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READ16_MEMBER(fs3216_state::mmu_read)
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{
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if (m_in_reset)
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{
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if (m_mmu_init && !BIT(offset, 22) && !machine().side_effects_disabled())
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m_in_reset = false;
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else
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offset = (offset & 0x03ffff) | 0x1c0000;
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}
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// TODO: MMU segments
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return m_clb->read16(space, offset & 0x1fffff, mem_mask);
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}
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WRITE16_MEMBER(fs3216_state::mmu_write)
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{
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if (m_in_reset)
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{
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if (m_mmu_init && !BIT(offset, 22) && !machine().side_effects_disabled())
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m_in_reset = false;
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else
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offset = (offset & 0x03ffff) | 0x1c0000;
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}
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// TODO: MMU segments
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m_clb->write16(space, offset & 0x1fffff, data, mem_mask);
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}
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WRITE_LINE_MEMBER(fs3216_state::mmu_reset_w)
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{
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if (state)
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{
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m_in_reset = true;
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m_mmu_init = false;
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}
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}
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void fs3216_state::mmu_init_w(u16 data)
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{
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m_mmu_init = true;
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}
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READ8_MEMBER(fs3216_state::ctc_r)
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{
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return m_ctc->read(space, offset >> 1);
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@ -134,23 +201,27 @@ void fs3216_state::fdc_ram_w(offs_t offset, u8 data)
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void fs3216_state::main_map(address_map &map)
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{
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map(0x000000, 0x003fff).rom().region("bios", 0);
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map(0x015000, 0x017fff).ram();
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map(0x000000, 0xffffff).rw(FUNC(fs3216_state::mmu_read), FUNC(fs3216_state::mmu_write));
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}
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void fs3216_state::clb_map(address_map &map)
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{
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map(0x000000, 0x017fff).ram();
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map(0x380000, 0x383fff).rom().region("momrom", 0);
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map(0x392000, 0x392003).m(m_fdc, FUNC(upd765a_device::map)).umask16(0x00ff);
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map(0x392041, 0x392041).w(FUNC(fs3216_state::floppy_select_w));
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map(0x392051, 0x392051).r(FUNC(fs3216_state::floppy_status_r));
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map(0x394680, 0x39468f).rw(FUNC(fs3216_state::ctc_r), FUNC(fs3216_state::ctc_w)).umask16(0x00ff);
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map(0x394701, 0x394701).rw("dart", FUNC(z80dart_device::da_r), FUNC(z80dart_device::da_w));
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map(0x394709, 0x394709).rw("dart", FUNC(z80dart_device::ca_r), FUNC(z80dart_device::ca_w));
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map(0x394711, 0x394711).rw("dart", FUNC(z80dart_device::db_r), FUNC(z80dart_device::db_w));
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map(0x394719, 0x394719).rw("dart", FUNC(z80dart_device::cb_r), FUNC(z80dart_device::cb_w));
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map(0x780000, 0x783fff).rom().region("bios", 0);
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map(0x792000, 0x792003).m(m_fdc, FUNC(upd765a_device::map)).umask16(0x00ff);
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map(0x792041, 0x792041).w(FUNC(fs3216_state::floppy_select_w));
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map(0x792051, 0x792051).r(FUNC(fs3216_state::floppy_status_r));
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map(0x7f6000, 0x7f6001).w(FUNC(fs3216_state::fdc_reset_w));
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map(0x7f6800, 0x7f6fff).rw(FUNC(fs3216_state::fdc_ram_r), FUNC(fs3216_state::fdc_ram_w)).umask16(0x00ff);
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map(0x7f7000, 0x7f7001).r(FUNC(fs3216_state::earom_recall_r));
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map(0x7f7200, 0x7f7201).r(FUNC(fs3216_state::earom_store_r));
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map(0x7f7400, 0x7f75ff).rw(m_earom, FUNC(x2212_device::read), FUNC(x2212_device::write)).umask16(0x00ff);
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map(0x800000, 0x803fff).rom().region("bios", 0);
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map(0x3f5000, 0x3f5001).w(FUNC(fs3216_state::mmu_init_w));
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map(0x3f6000, 0x3f6001).w(FUNC(fs3216_state::fdc_reset_w));
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map(0x3f6800, 0x3f6fff).rw(FUNC(fs3216_state::fdc_ram_r), FUNC(fs3216_state::fdc_ram_w)).umask16(0x00ff);
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map(0x3f7000, 0x3f7001).r(FUNC(fs3216_state::earom_recall_r));
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map(0x3f7200, 0x3f7201).r(FUNC(fs3216_state::earom_store_r));
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map(0x3f7400, 0x3f75ff).rw(m_earom, FUNC(x2212_device::read), FUNC(x2212_device::write)).umask16(0x00ff);
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}
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void fs3216_state::wdcpu_prog_map(address_map &map)
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@ -168,6 +239,13 @@ void fs3216_state::fs3216(machine_config &config)
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{
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M68000(config, m_maincpu, 44.2368_MHz_XTAL / 8); // 5.5 MHz
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m_maincpu->set_addrmap(AS_PROGRAM, &fs3216_state::main_map);
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m_maincpu->set_reset_callback(write_line_delegate(FUNC(fs3216_state::mmu_reset_w), this));
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ADDRESS_MAP_BANK(config, m_clb);
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m_clb->set_addrmap(0, &fs3216_state::clb_map);
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m_clb->set_data_width(16);
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m_clb->set_addr_width(24);
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m_clb->set_endianness(ENDIANNESS_BIG);
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Z80CTC(config, m_ctc, 44.2368_MHz_XTAL / 8); // Z8430BPS
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m_ctc->set_clk<0>(44.2368_MHz_XTAL / 16); // CLK0 rate guessed
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@ -207,7 +285,7 @@ INPUT_PORTS_END
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// XTALs on Video Controller board (1000443-1 Rev. I): 14.580 MHz (1H)
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// XTALs on WD-1001 CLB Disk Controller board (1473-008): 20.000 (Y1), 8.00? [somewhat defaced] (Y2)
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ROM_START(fs3216)
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ROM_REGION16_BE(0x4000, "bios", 0)
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ROM_REGION16_BE(0x4000, "momrom", 0)
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ROM_LOAD16_BYTE("17k_1260-02_h.bin", 0x0000, 0x2000, CRC(75ed6de8) SHA1(0360548493b778995ae436da475b6356945e1872))
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ROM_LOAD16_BYTE("15k_1260-01_l.bin", 0x0001, 0x2000, CRC(82695233) SHA1(0d69309f41306298bf6a4ba6928c53f908bb3f2c))
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