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https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
saitek_osa/odyssey2 slot devices: add anonymous namespace
This commit is contained in:
hap
parent
17869b56a3
commit
0076419cb4
@ -15,13 +15,34 @@ Used in:
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#include "emu.h"
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#include "4in1.h"
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DEFINE_DEVICE_TYPE(O2_ROM_4IN1, o2_4in1_device, "o2_4in1", "Videopac 40 Cartridge")
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namespace {
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//-------------------------------------------------
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// o2_4in1_device - constructor
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// initialization
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//-------------------------------------------------
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class o2_4in1_device : public device_t, public device_o2_cart_interface
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{
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public:
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o2_4in1_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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protected:
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virtual void device_start() override;
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virtual void cart_init() override;
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virtual u8 read_rom04(offs_t offset) override { return m_rom[offset + 0x400]; }
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virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0xc00]; }
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virtual void write_p1(u8 data) override { m_control = data; }
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virtual void write_p2(u8 data) override { m_bank = data; }
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virtual u8 io_read(offs_t offset) override;
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private:
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u8 m_control = 0;
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u8 m_bank = 0;
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};
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o2_4in1_device::o2_4in1_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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device_t(mconfig, O2_ROM_4IN1, tag, owner, clock),
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device_o2_cart_interface(mconfig, *this)
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@ -51,3 +72,8 @@ u8 o2_4in1_device::io_read(offs_t offset)
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else
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return 0xff;
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}
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} // anonymous namespace
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DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_4IN1, device_o2_cart_interface, o2_4in1_device, "o2_4in1", "Videopac 40 Cartridge")
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@ -13,35 +13,6 @@
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#include "slot.h"
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// ======================> o2_4in1_device
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class o2_4in1_device : public device_t,
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public device_o2_cart_interface
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{
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public:
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// construction/destruction
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o2_4in1_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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protected:
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// device-level overrides
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virtual void device_start() override;
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virtual void cart_init() override;
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virtual u8 read_rom04(offs_t offset) override { return m_rom[offset + 0x400]; }
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virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0xc00]; }
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virtual void write_p1(u8 data) override { m_control = data; }
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virtual void write_p2(u8 data) override { m_bank = data; }
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virtual u8 io_read(offs_t offset) override;
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private:
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u8 m_control = 0;
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u8 m_bank = 0;
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};
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// device type definition
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DECLARE_DEVICE_TYPE(O2_ROM_4IN1, o2_4in1_device)
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DECLARE_DEVICE_TYPE(O2_ROM_4IN1, device_o2_cart_interface)
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#endif // MAME_BUS_ODYSSEY2_4IN1_H
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@ -14,13 +14,45 @@ Hardware notes:
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#include "emu.h"
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#include "chess.h"
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DEFINE_DEVICE_TYPE(O2_ROM_CHESS, o2_chess_device, "o2_chess", "Videopac C7010 Cartridge")
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#include "cpu/z80/z80.h"
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#include "machine/gen_latch.h"
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namespace {
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//-------------------------------------------------
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// o2_chess_device - constructor
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// initialization
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//-------------------------------------------------
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class o2_chess_device : public device_t, public device_o2_cart_interface
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{
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public:
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o2_chess_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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protected:
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virtual void device_start() override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual void cart_init() override;
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virtual u8 read_rom04(offs_t offset) override { return m_rom[offset]; }
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virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0x400]; }
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virtual void write_p1(u8 data) override;
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virtual void io_write(offs_t offset, u8 data) override;
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virtual u8 io_read(offs_t offset) override;
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private:
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required_device<cpu_device> m_maincpu;
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required_device_array<generic_latch_8_device, 2> m_latch;
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u8 m_control = 0;
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u8 internal_rom_r(offs_t offset) { return m_exrom[offset]; }
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void chess_io(address_map &map);
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void chess_mem(address_map &map);
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};
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o2_chess_device::o2_chess_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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device_t(mconfig, O2_ROM_CHESS, tag, owner, clock),
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device_o2_cart_interface(mconfig, *this),
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@ -40,6 +72,34 @@ void o2_chess_device::cart_init()
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}
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//-------------------------------------------------
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// mapper specific handlers
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//-------------------------------------------------
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void o2_chess_device::write_p1(u8 data)
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{
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// P11: reset
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m_maincpu->set_input_line(INPUT_LINE_RESET, (data & 2) ? CLEAR_LINE : ASSERT_LINE);
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// P10,P14: must be low to access latches
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m_control = data;
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}
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u8 o2_chess_device::io_read(offs_t offset)
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{
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if ((offset & 0xa0) == 0xa0 && (m_control & 0x11) == 0)
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return m_latch[0]->read();
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else
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return 0xff;
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}
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void o2_chess_device::io_write(offs_t offset, u8 data)
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{
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if (offset & 0x80 && (m_control & 0x11) == 0)
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m_latch[1]->write(data);
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}
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//-------------------------------------------------
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// address maps
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//-------------------------------------------------
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@ -72,30 +132,7 @@ void o2_chess_device::device_add_mconfig(machine_config &config)
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GENERIC_LATCH_8(config, m_latch[1]);
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}
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} // anonymous namespace
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//-------------------------------------------------
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// mapper specific handlers
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//-------------------------------------------------
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void o2_chess_device::write_p1(u8 data)
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{
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// P11: reset
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m_maincpu->set_input_line(INPUT_LINE_RESET, (data & 2) ? CLEAR_LINE : ASSERT_LINE);
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// P10,P14: must be low to access latches
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m_control = data;
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}
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u8 o2_chess_device::io_read(offs_t offset)
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{
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if ((offset & 0xa0) == 0xa0 && (m_control & 0x11) == 0)
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return m_latch[0]->read();
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else
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return 0xff;
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}
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void o2_chess_device::io_write(offs_t offset, u8 data)
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{
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if (offset & 0x80 && (m_control & 0x11) == 0)
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m_latch[1]->write(data);
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}
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DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_CHESS, device_o2_cart_interface, o2_chess_device, "o2_chess", "Videopac C7010 Cartridge")
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@ -13,46 +13,6 @@
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#include "slot.h"
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#include "cpu/z80/z80.h"
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#include "machine/gen_latch.h"
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// ======================> o2_chess_device
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class o2_chess_device : public device_t,
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public device_o2_cart_interface
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{
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public:
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// construction/destruction
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o2_chess_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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protected:
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// device-level overrides
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virtual void device_start() override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual void cart_init() override;
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virtual u8 read_rom04(offs_t offset) override { return m_rom[offset]; }
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virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0x400]; }
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virtual void write_p1(u8 data) override;
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virtual void io_write(offs_t offset, u8 data) override;
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virtual u8 io_read(offs_t offset) override;
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private:
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required_device<cpu_device> m_maincpu;
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required_device_array<generic_latch_8_device, 2> m_latch;
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u8 m_control = 0;
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u8 internal_rom_r(offs_t offset) { return m_exrom[offset]; }
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void chess_io(address_map &map);
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void chess_mem(address_map &map);
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};
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// device type definition
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DECLARE_DEVICE_TYPE(O2_ROM_CHESS, o2_chess_device)
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DECLARE_DEVICE_TYPE(O2_ROM_CHESS, device_o2_cart_interface)
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#endif // MAME_BUS_ODYSSEY2_CHESS_H
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@ -24,15 +24,57 @@ TODO:
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#include "emu.h"
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#include "homecomp.h"
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#include "cpu/z80/z80.h"
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#include "imagedev/cassette.h"
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#include "machine/gen_latch.h"
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#include "speaker.h"
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DEFINE_DEVICE_TYPE(O2_ROM_HOMECOMP, o2_homecomp_device, "o2_homecomp", "Videopac+ C7420 Cartridge")
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namespace {
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//-------------------------------------------------
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// o2_homecomp_device - constructor
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// initialization
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//-------------------------------------------------
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class o2_homecomp_device : public device_t, public device_o2_cart_interface
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{
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public:
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o2_homecomp_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual ioport_constructor device_input_ports() const override;
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virtual void cart_init() override;
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virtual u8 read_rom04(offs_t offset) override { return m_rom[offset]; }
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virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0x400]; }
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virtual void write_p1(u8 data) override;
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virtual void io_write(offs_t offset, u8 data) override;
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virtual u8 io_read(offs_t offset) override;
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virtual int t0_read() override { return m_latch[0]->pending_r(); }
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private:
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required_device<cpu_device> m_maincpu;
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required_device_array<generic_latch_8_device, 2> m_latch;
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required_device<cassette_image_device> m_cass;
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std::unique_ptr<u8[]> m_ram;
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u8 m_control = 0;
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bool m_installed = false;
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void internal_io_w(offs_t offset, u8 data);
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u8 internal_io_r(offs_t offset);
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u8 internal_rom_r(offs_t offset) { return m_exrom[offset]; }
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void homecomp_io(address_map &map);
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void homecomp_mem(address_map &map);
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};
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o2_homecomp_device::o2_homecomp_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
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device_t(mconfig, O2_ROM_HOMECOMP, tag, owner, clock),
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device_o2_cart_interface(mconfig, *this),
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@ -71,19 +113,33 @@ void o2_homecomp_device::cart_init()
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//-------------------------------------------------
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// input_ports - device-specific input ports
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// mapper specific handlers
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//-------------------------------------------------
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static INPUT_PORTS_START( homecomp )
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PORT_START("RAM")
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PORT_CONFNAME( 0x01, 0x00, "RAM Size" )
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PORT_CONFSETTING( 0x00, "16KB" )
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PORT_CONFSETTING( 0x01, "32KB" ) // unofficial
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INPUT_PORTS_END
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ioport_constructor o2_homecomp_device::device_input_ports() const
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void o2_homecomp_device::write_p1(u8 data)
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{
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return INPUT_PORTS_NAME(homecomp);
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// P10: Z80 INT pin
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// P10+P11: Z80 RESET pin
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, (data & 1) ? CLEAR_LINE : ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_RESET, (data & 3) ? CLEAR_LINE : ASSERT_LINE);
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// P11: must be low to access latch 0
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// P14: must be low to access latch 1
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m_control = data;
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}
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u8 o2_homecomp_device::io_read(offs_t offset)
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{
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if ((offset & 0xa0) == 0xa0 && ~m_control & 2)
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return m_latch[0]->read();
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else
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return 0xff;
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}
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void o2_homecomp_device::io_write(offs_t offset, u8 data)
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{
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if (offset & 0x80 && ~m_control & 0x10)
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m_latch[1]->write(data);
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}
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@ -153,6 +209,23 @@ void o2_homecomp_device::homecomp_io(address_map &map)
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}
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//-------------------------------------------------
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// input_ports - device-specific input ports
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//-------------------------------------------------
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static INPUT_PORTS_START( homecomp )
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PORT_START("RAM")
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PORT_CONFNAME( 0x01, 0x00, "RAM Size" )
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PORT_CONFSETTING( 0x00, "16KB" )
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PORT_CONFSETTING( 0x01, "32KB" ) // unofficial
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INPUT_PORTS_END
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ioport_constructor o2_homecomp_device::device_input_ports() const
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{
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return INPUT_PORTS_NAME(homecomp);
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}
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//-------------------------------------------------
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// device_add_mconfig - add device configuration
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//-------------------------------------------------
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@ -174,33 +247,7 @@ void o2_homecomp_device::device_add_mconfig(machine_config &config)
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m_cass->add_route(ALL_OUTPUTS, "cass_output", 0.05);
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}
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} // anonymous namespace
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//-------------------------------------------------
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// mapper specific handlers
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//-------------------------------------------------
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void o2_homecomp_device::write_p1(u8 data)
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{
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// P10: Z80 INT pin
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// P10+P11: Z80 RESET pin
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m_maincpu->set_input_line(INPUT_LINE_IRQ0, (data & 1) ? CLEAR_LINE : ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_RESET, (data & 3) ? CLEAR_LINE : ASSERT_LINE);
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// P11: must be low to access latch 0
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// P14: must be low to access latch 1
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m_control = data;
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}
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u8 o2_homecomp_device::io_read(offs_t offset)
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{
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if ((offset & 0xa0) == 0xa0 && ~m_control & 2)
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return m_latch[0]->read();
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else
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return 0xff;
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}
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void o2_homecomp_device::io_write(offs_t offset, u8 data)
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{
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if (offset & 0x80 && ~m_control & 0x10)
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m_latch[1]->write(data);
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}
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DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_HOMECOMP, device_o2_cart_interface, o2_homecomp_device, "o2_homecomp", "Videopac+ C7420 Cartridge")
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@ -13,55 +13,6 @@
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#include "slot.h"
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#include "cpu/z80/z80.h"
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#include "imagedev/cassette.h"
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#include "machine/gen_latch.h"
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// ======================> o2_homecomp_device
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class o2_homecomp_device : public device_t,
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public device_o2_cart_interface
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{
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public:
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// construction/destruction
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o2_homecomp_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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protected:
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_add_mconfig(machine_config &config) override;
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virtual ioport_constructor device_input_ports() const override;
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virtual void cart_init() override;
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virtual u8 read_rom04(offs_t offset) override { return m_rom[offset]; }
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virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0x400]; }
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virtual void write_p1(u8 data) override;
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virtual void io_write(offs_t offset, u8 data) override;
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virtual u8 io_read(offs_t offset) override;
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virtual int t0_read() override { return m_latch[0]->pending_r(); }
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private:
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required_device<cpu_device> m_maincpu;
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required_device_array<generic_latch_8_device, 2> m_latch;
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required_device<cassette_image_device> m_cass;
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std::unique_ptr<u8[]> m_ram;
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u8 m_control = 0;
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bool m_installed = false;
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void internal_io_w(offs_t offset, u8 data);
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u8 internal_io_r(offs_t offset);
|
||||
u8 internal_rom_r(offs_t offset) { return m_exrom[offset]; }
|
||||
|
||||
void homecomp_io(address_map &map);
|
||||
void homecomp_mem(address_map &map);
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_HOMECOMP, o2_homecomp_device)
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_HOMECOMP, device_o2_cart_interface)
|
||||
|
||||
#endif // MAME_BUS_ODYSSEY2_HOMECOMP_H
|
||||
|
||||
@ -11,13 +11,33 @@ Bankswitched ROM with page size of 3KB.
|
||||
#include "emu.h"
|
||||
#include "ktaa.h"
|
||||
|
||||
DEFINE_DEVICE_TYPE(O2_ROM_KTAA, o2_ktaa_device, "o2_ktaa", "Videopac+ KTAA Cartridge")
|
||||
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// o2_ktaa_device - constructor
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
class o2_ktaa_device : public device_t, public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
o2_ktaa_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override;
|
||||
virtual u8 read_rom0c(offs_t offset) override { return read_rom04(offset + 0x800); }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_bank = data & m_bank_mask; }
|
||||
|
||||
private:
|
||||
u32 m_page_size = 0;
|
||||
u8 m_bank_mask = 0;
|
||||
u8 m_bank = 0;
|
||||
};
|
||||
|
||||
o2_ktaa_device::o2_ktaa_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, O2_ROM_KTAA, tag, owner, clock),
|
||||
device_o2_cart_interface(mconfig, *this)
|
||||
@ -61,3 +81,8 @@ u8 o2_ktaa_device::read_rom04(offs_t offset)
|
||||
offset += m_page_size - 0xc00;
|
||||
return m_rom[offset + m_bank * m_page_size];
|
||||
}
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_KTAA, device_o2_cart_interface, o2_ktaa_device, "o2_ktaa", "Videopac+ KTAA Cartridge")
|
||||
|
||||
@ -13,34 +13,6 @@
|
||||
|
||||
#include "slot.h"
|
||||
|
||||
|
||||
// ======================> o2_ktaa_device
|
||||
|
||||
class o2_ktaa_device : public device_t,
|
||||
public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
o2_ktaa_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override;
|
||||
virtual u8 read_rom0c(offs_t offset) override { return read_rom04(offset + 0x800); }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_bank = data & m_bank_mask; }
|
||||
|
||||
private:
|
||||
u32 m_page_size = 0;
|
||||
u8 m_bank_mask = 0;
|
||||
u8 m_bank = 0;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_KTAA, o2_ktaa_device)
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_KTAA, device_o2_cart_interface)
|
||||
|
||||
#endif // MAME_BUS_ODYSSEY2_KTAA_H
|
||||
|
||||
@ -19,13 +19,33 @@ Used in:
|
||||
#include "emu.h"
|
||||
#include "rally.h"
|
||||
|
||||
DEFINE_DEVICE_TYPE(O2_ROM_RALLY, o2_rally_device, "o2_rally", "Videopac+ 60 Cartridge")
|
||||
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// o2_rally_device - constructor
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
class o2_rally_device : public device_t, public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
o2_rally_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override;
|
||||
virtual u8 read_rom0c(offs_t offset) override { return read_rom04(offset + 0x400); }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_control = data; }
|
||||
virtual void io_write(offs_t offset, u8 data) override;
|
||||
|
||||
private:
|
||||
u8 m_control = 0;
|
||||
u8 m_bank = 0;
|
||||
};
|
||||
|
||||
o2_rally_device::o2_rally_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, O2_ROM_RALLY, tag, owner, clock),
|
||||
device_o2_cart_interface(mconfig, *this)
|
||||
@ -60,3 +80,8 @@ void o2_rally_device::io_write(offs_t offset, u8 data)
|
||||
if (offset & 0x80 && ~m_control & 0x10)
|
||||
m_bank = data;
|
||||
}
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_RALLY, device_o2_cart_interface, o2_rally_device, "o2_rally", "Videopac+ 60 Cartridge")
|
||||
|
||||
@ -13,34 +13,6 @@
|
||||
|
||||
#include "slot.h"
|
||||
|
||||
|
||||
// ======================> o2_rally_device
|
||||
|
||||
class o2_rally_device : public device_t,
|
||||
public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
o2_rally_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override;
|
||||
virtual u8 read_rom0c(offs_t offset) override { return read_rom04(offset + 0x400); }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_control = data; }
|
||||
virtual void io_write(offs_t offset, u8 data) override;
|
||||
|
||||
private:
|
||||
u8 m_control = 0;
|
||||
u8 m_bank = 0;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_RALLY, o2_rally_device)
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_RALLY, device_o2_cart_interface)
|
||||
|
||||
#endif // MAME_BUS_ODYSSEY2_RALLY_H
|
||||
|
||||
@ -9,13 +9,32 @@ Standard cartridges emulation, optionally bankswitched up to 8KB.
|
||||
#include "emu.h"
|
||||
#include "rom.h"
|
||||
|
||||
DEFINE_DEVICE_TYPE(O2_ROM_STD, o2_rom_device, "o2_rom", "Odyssey 2 Standard Cartridge")
|
||||
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// o2_rom_device - constructor
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
class o2_rom_device : public device_t, public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
o2_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override;
|
||||
virtual u8 read_rom0c(offs_t offset) override { return read_rom04(offset + 0x400); }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_bank = data & 3; }
|
||||
|
||||
private:
|
||||
u32 m_cart_mask = 0;
|
||||
u8 m_bank = 0;
|
||||
};
|
||||
|
||||
o2_rom_device::o2_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, O2_ROM_STD, tag, owner, clock),
|
||||
device_o2_cart_interface(mconfig, *this)
|
||||
@ -41,3 +60,8 @@ u8 o2_rom_device::read_rom04(offs_t offset)
|
||||
offset = (offset + m_bank * 0x800) & m_cart_mask;
|
||||
return (offset < m_rom_size) ? m_rom[offset] : 0xff;
|
||||
}
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_STD, device_o2_cart_interface, o2_rom_device, "o2_rom", "Odyssey 2 Standard Cartridge")
|
||||
|
||||
@ -13,33 +13,6 @@
|
||||
|
||||
#include "slot.h"
|
||||
|
||||
|
||||
// ======================> o2_rom_device
|
||||
|
||||
class o2_rom_device : public device_t,
|
||||
public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
o2_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override;
|
||||
virtual u8 read_rom0c(offs_t offset) override { return read_rom04(offset + 0x400); }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_bank = data & 3; }
|
||||
|
||||
private:
|
||||
u32 m_cart_mask = 0;
|
||||
u8 m_bank = 0;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_STD, o2_rom_device)
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_STD, device_o2_cart_interface)
|
||||
|
||||
#endif // MAME_BUS_ODYSSEY2_ROM_H
|
||||
|
||||
@ -18,13 +18,35 @@ Hold UP to advance to next test.
|
||||
#include "emu.h"
|
||||
#include "test.h"
|
||||
|
||||
DEFINE_DEVICE_TYPE(O2_ROM_TEST, o2_test_device, "o2_test", "Videopac Service Test Cartridge")
|
||||
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// o2_test_device - constructor
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
class o2_test_device : public device_t, public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
o2_test_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override { return m_rom[offset]; }
|
||||
virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0x400]; }
|
||||
virtual void bus_write(u8 data) override { m_bus_data = data; }
|
||||
|
||||
virtual void write_p1(u8 data) override;
|
||||
|
||||
private:
|
||||
output_finder<> m_digit_out;
|
||||
|
||||
u8 m_control = 0;
|
||||
u8 m_bus_data = 0;
|
||||
};
|
||||
|
||||
o2_test_device::o2_test_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, O2_ROM_TEST, tag, owner, clock),
|
||||
device_o2_cart_interface(mconfig, *this),
|
||||
@ -63,3 +85,8 @@ void o2_test_device::write_p1(u8 data)
|
||||
|
||||
m_control = data;
|
||||
}
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_TEST, device_o2_cart_interface, o2_test_device, "o2_test", "Videopac Service Test Cartridge")
|
||||
|
||||
@ -13,36 +13,6 @@
|
||||
|
||||
#include "slot.h"
|
||||
|
||||
|
||||
// ======================> o2_test_device
|
||||
|
||||
class o2_test_device : public device_t,
|
||||
public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
o2_test_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override { return m_rom[offset]; }
|
||||
virtual u8 read_rom0c(offs_t offset) override { return m_rom[offset + 0x400]; }
|
||||
virtual void bus_write(u8 data) override { m_bus_data = data; }
|
||||
|
||||
virtual void write_p1(u8 data) override;
|
||||
|
||||
private:
|
||||
output_finder<> m_digit_out;
|
||||
|
||||
u8 m_control = 0;
|
||||
u8 m_bus_data = 0;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_TEST, o2_test_device)
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_TEST, device_o2_cart_interface)
|
||||
|
||||
#endif // MAME_BUS_ODYSSEY2_TEST_H
|
||||
|
||||
@ -20,14 +20,50 @@ TODO:
|
||||
|
||||
#include "emu.h"
|
||||
#include "voice.h"
|
||||
|
||||
#include "sound/sp0256.h"
|
||||
|
||||
#include "speaker.h"
|
||||
|
||||
DEFINE_DEVICE_TYPE(O2_ROM_VOICE, o2_voice_device, "o2_voice", "Odyssey 2 The Voice Cartridge")
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// o2_voice_device - constructor
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
class o2_voice_device : public device_t, public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
o2_voice_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
virtual u8 read_rom04(offs_t offset) override { return (m_subslot->exists()) ? m_subslot->read_rom04(offset) : 0xff; }
|
||||
virtual u8 read_rom0c(offs_t offset) override { return (m_subslot->exists()) ? m_subslot->read_rom0c(offset) : 0xff; }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_control = data; if (m_subslot->exists()) m_subslot->write_p1(data & 3); }
|
||||
virtual void write_p2(u8 data) override { if (m_subslot->exists()) m_subslot->write_p2(data & ~4); }
|
||||
virtual void bus_write(u8 data) override { if (m_subslot->exists()) m_subslot->bus_write(data); }
|
||||
virtual u8 bus_read() override { return (m_subslot->exists()) ? m_subslot->bus_read() : 0xff; }
|
||||
|
||||
virtual void io_write(offs_t offset, u8 data) override;
|
||||
virtual int t0_read() override;
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
|
||||
private:
|
||||
required_device<sp0256_device> m_speech;
|
||||
required_device<o2_cart_slot_device> m_subslot;
|
||||
|
||||
u8 m_control = 0;
|
||||
bool m_reset = false;
|
||||
};
|
||||
|
||||
o2_voice_device::o2_voice_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, O2_ROM_VOICE, tag, owner, clock),
|
||||
device_o2_cart_interface(mconfig, *this),
|
||||
@ -63,31 +99,6 @@ void o2_voice_device::device_reset()
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_add_mconfig - add device configuration
|
||||
//-------------------------------------------------
|
||||
|
||||
void o2_voice_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
SPEAKER(config, "mono").front_center();
|
||||
|
||||
SP0256(config, m_speech, 3.12_MHz_XTAL);
|
||||
// The Voice uses a speaker with its own volume control so the relative volumes to use are subjective, these sound good
|
||||
m_speech->add_route(ALL_OUTPUTS, "mono", 1.00);
|
||||
|
||||
O2_CART_SLOT(config, m_subslot, o2_cart, nullptr);
|
||||
}
|
||||
|
||||
ROM_START( o2voice )
|
||||
ROM_REGION( 0x10000, "speech", ROMREGION_ERASE00 )
|
||||
ROM_END
|
||||
|
||||
const tiny_rom_entry *o2_voice_device::device_rom_region() const
|
||||
{
|
||||
return ROM_NAME( o2voice );
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// mapper specific handlers
|
||||
//-------------------------------------------------
|
||||
@ -114,3 +125,33 @@ void o2_voice_device::io_write(offs_t offset, u8 data)
|
||||
m_reset = reset;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_add_mconfig - add device configuration
|
||||
//-------------------------------------------------
|
||||
|
||||
void o2_voice_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
SPEAKER(config, "mono").front_center();
|
||||
|
||||
SP0256(config, m_speech, 3.12_MHz_XTAL);
|
||||
// The Voice uses a speaker with its own volume control so the relative volumes to use are subjective, these sound good
|
||||
m_speech->add_route(ALL_OUTPUTS, "mono", 1.00);
|
||||
|
||||
O2_CART_SLOT(config, m_subslot, o2_cart, nullptr);
|
||||
}
|
||||
|
||||
ROM_START( o2voice )
|
||||
ROM_REGION( 0x10000, "speech", ROMREGION_ERASE00 )
|
||||
ROM_END
|
||||
|
||||
const tiny_rom_entry *o2_voice_device::device_rom_region() const
|
||||
{
|
||||
return ROM_NAME( o2voice );
|
||||
}
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(O2_ROM_VOICE, device_o2_cart_interface, o2_voice_device, "o2_voice", "Odyssey 2 The Voice Cartridge")
|
||||
|
||||
@ -12,50 +12,7 @@
|
||||
#pragma once
|
||||
|
||||
#include "slot.h"
|
||||
#include "sound/sp0256.h"
|
||||
|
||||
|
||||
// ======================> o2_voice_device
|
||||
|
||||
class o2_voice_device : public device_t,
|
||||
public device_o2_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
o2_voice_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
virtual void cart_init() override;
|
||||
|
||||
// reading and writing
|
||||
virtual u8 read_rom04(offs_t offset) override { return (m_subslot->exists()) ? m_subslot->read_rom04(offset) : 0xff; }
|
||||
virtual u8 read_rom0c(offs_t offset) override { return (m_subslot->exists()) ? m_subslot->read_rom0c(offset) : 0xff; }
|
||||
|
||||
virtual void write_p1(u8 data) override { m_control = data; if (m_subslot->exists()) m_subslot->write_p1(data & 3); }
|
||||
virtual void write_p2(u8 data) override { if (m_subslot->exists()) m_subslot->write_p2(data & ~4); }
|
||||
virtual void bus_write(u8 data) override { if (m_subslot->exists()) m_subslot->bus_write(data); }
|
||||
virtual u8 bus_read() override { return (m_subslot->exists()) ? m_subslot->bus_read() : 0xff; }
|
||||
|
||||
virtual void io_write(offs_t offset, u8 data) override;
|
||||
virtual int t0_read() override;
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
|
||||
private:
|
||||
required_device<sp0256_device> m_speech;
|
||||
required_device<o2_cart_slot_device> m_subslot;
|
||||
|
||||
u8 m_control = 0;
|
||||
bool m_reset = false;
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_VOICE, o2_voice_device)
|
||||
DECLARE_DEVICE_TYPE(O2_ROM_VOICE, device_o2_cart_interface)
|
||||
|
||||
#endif // MAME_BUS_ODYSSEY2_VOICE_H
|
||||
|
||||
@ -34,19 +34,63 @@ TODO:
|
||||
#include "maestro.h"
|
||||
|
||||
#include "bus/generic/carts.h"
|
||||
#include "bus/generic/slot.h"
|
||||
#include "cpu/m6502/r65c02.h"
|
||||
#include "video/hd44780.h"
|
||||
|
||||
#include "softlist_dev.h"
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE(OSA_MAESTRO, saitekosa_maestro_device, "osa_maestro", "Saitek OSA Maestro B-D")
|
||||
DEFINE_DEVICE_TYPE(OSA_ANALYST, saitekosa_analyst_device, "osa_analyst", "Saitek OSA Analyst")
|
||||
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
// Maestro / shared
|
||||
|
||||
class saitekosa_maestro_device : public device_t, public device_saitekosa_expansion_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
saitekosa_maestro_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
DECLARE_INPUT_CHANGED_MEMBER(change_cpu_freq);
|
||||
|
||||
// from host
|
||||
virtual u8 data_r() override;
|
||||
virtual void nmi_w(int state) override;
|
||||
virtual void ack_w(int state) override;
|
||||
|
||||
protected:
|
||||
saitekosa_maestro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
memory_share_creator<u8> m_banked_ram;
|
||||
required_memory_bank m_rambank;
|
||||
required_memory_bank m_rombank;
|
||||
required_device<generic_slot_device> m_extrom;
|
||||
|
||||
u8 m_latch = 0xff;
|
||||
bool m_latch_enable = false;
|
||||
u8 m_extrom_bank = 0;
|
||||
|
||||
virtual void main_map(address_map &map);
|
||||
|
||||
u8 extrom_r(offs_t offset);
|
||||
template <int N> void stall_w(u8 data = 0);
|
||||
u8 rts_r();
|
||||
u8 xdata_r();
|
||||
void xdata_w(u8 data);
|
||||
u8 ack_r();
|
||||
void control_w(u8 data);
|
||||
};
|
||||
|
||||
saitekosa_maestro_device::saitekosa_maestro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, type, tag, owner, clock),
|
||||
device_saitekosa_expansion_interface(mconfig, *this),
|
||||
@ -61,11 +105,34 @@ saitekosa_maestro_device::saitekosa_maestro_device(const machine_config &mconfig
|
||||
saitekosa_maestro_device(mconfig, OSA_MAESTRO, tag, owner, clock)
|
||||
{ }
|
||||
|
||||
|
||||
// Analyst
|
||||
|
||||
class saitekosa_analyst_device : public saitekosa_maestro_device
|
||||
{
|
||||
public:
|
||||
saitekosa_analyst_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
virtual u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) override;
|
||||
|
||||
static auto parent_rom_device_type() { return &OSA_MAESTRO; }
|
||||
|
||||
protected:
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
|
||||
private:
|
||||
required_device<hd44780_device> m_lcd;
|
||||
|
||||
virtual void main_map(address_map &map) override;
|
||||
};
|
||||
|
||||
saitekosa_analyst_device::saitekosa_analyst_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
saitekosa_maestro_device(mconfig, OSA_ANALYST, tag, owner, clock),
|
||||
m_lcd(*this, "lcd")
|
||||
{ }
|
||||
|
||||
|
||||
void saitekosa_maestro_device::device_start()
|
||||
{
|
||||
// init banks
|
||||
@ -90,6 +157,170 @@ INPUT_CHANGED_MEMBER(saitekosa_maestro_device::change_cpu_freq)
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// host i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
u8 saitekosa_maestro_device::data_r()
|
||||
{
|
||||
return m_latch_enable ? m_latch : 0xff;
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::nmi_w(int state)
|
||||
{
|
||||
m_maincpu->set_input_line(0, !state ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::ack_w(int state)
|
||||
{
|
||||
if (state != m_expansion->ack_state())
|
||||
machine().scheduler().perfect_quantum(attotime::from_usec(100));
|
||||
}
|
||||
|
||||
u32 saitekosa_analyst_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
bitmap.fill(0xffffff, cliprect);
|
||||
const u8 *render = m_lcd->render();
|
||||
|
||||
// draw lcd characters
|
||||
for (int i = 0; i < 16; i++)
|
||||
{
|
||||
const u8 *src = render + 16 * ((i & 7) + BIT(i, 3) * 40);
|
||||
for (int y = 0; y < 8; y++)
|
||||
for (int x = 0; x < 5; x++)
|
||||
bitmap.pix(y + 4, i * 6 + x + 2) = (BIT(src[y], 4 - x) && m_expansion->pw_state()) ? 0x282828 : 0xe8e8e8;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// internal i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
u8 saitekosa_maestro_device::extrom_r(offs_t offset)
|
||||
{
|
||||
u16 bank = m_extrom_bank * 0x4000;
|
||||
return (m_extrom->exists()) ? m_extrom->read_rom(offset | bank) : 0xff;
|
||||
}
|
||||
|
||||
template <int N> void saitekosa_maestro_device::stall_w(u8 data)
|
||||
{
|
||||
// cpu clock divider
|
||||
}
|
||||
|
||||
u8 saitekosa_maestro_device::rts_r()
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
// strobe RTS-P
|
||||
m_expansion->rts_w(1);
|
||||
m_expansion->rts_w(0);
|
||||
}
|
||||
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::xdata_w(u8 data)
|
||||
{
|
||||
// clock latch
|
||||
m_latch = data;
|
||||
}
|
||||
|
||||
u8 saitekosa_maestro_device::xdata_r()
|
||||
{
|
||||
return m_expansion->data_state();
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::control_w(u8 data)
|
||||
{
|
||||
// d0: main rom bank
|
||||
m_rombank->set_entry(data & 1);
|
||||
|
||||
// d1: ext rom bank
|
||||
// d1: ram bank
|
||||
m_extrom_bank = BIT(data, 1);
|
||||
m_rambank->set_entry(m_extrom_bank);
|
||||
|
||||
// d3: enable latch output
|
||||
m_latch_enable = bool(data & 8);
|
||||
|
||||
// d2: STB-P
|
||||
m_expansion->stb_w(BIT(data, 2));
|
||||
}
|
||||
|
||||
u8 saitekosa_maestro_device::ack_r()
|
||||
{
|
||||
// d6: _Vcc
|
||||
// d7: ACK-P
|
||||
return m_expansion->ack_state() ? 0x80 : 0x00;
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::main_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x1fff).ram();
|
||||
map(0x2000, 0x2000).mirror(0x01ff).w(FUNC(saitekosa_maestro_device::stall_w<0>));
|
||||
map(0x2200, 0x2200).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::rts_r), FUNC(saitekosa_maestro_device::stall_w<1>));
|
||||
map(0x2400, 0x2400).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::xdata_r), FUNC(saitekosa_maestro_device::xdata_w));
|
||||
map(0x2600, 0x2600).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::ack_r), FUNC(saitekosa_maestro_device::control_w));
|
||||
map(0x2800, 0x37ff).bankrw("rambank");
|
||||
map(0x4000, 0x7fff).r(FUNC(saitekosa_maestro_device::extrom_r));
|
||||
map(0x8000, 0xffff).bankr("rombank");
|
||||
}
|
||||
|
||||
void saitekosa_analyst_device::main_map(address_map &map)
|
||||
{
|
||||
saitekosa_maestro_device::main_map(map);
|
||||
map(0x3800, 0x3801).mirror(0x07fe).rw(m_lcd, FUNC(hd44780_device::read), FUNC(hd44780_device::write));
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// input_ports - device-specific input ports
|
||||
//-------------------------------------------------
|
||||
|
||||
static INPUT_PORTS_START( maestro )
|
||||
PORT_START("CPU")
|
||||
PORT_CONFNAME( 0x07, 0x04, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, saitekosa_maestro_device, change_cpu_freq, 0) // factory set
|
||||
PORT_CONFSETTING( 0x00, "4MHz" )
|
||||
PORT_CONFSETTING( 0x01, "5.67MHz" )
|
||||
PORT_CONFSETTING( 0x02, "6MHz" )
|
||||
PORT_CONFSETTING( 0x03, "7.2MHz" )
|
||||
PORT_CONFSETTING( 0x04, "8MHz" )
|
||||
PORT_CONFSETTING( 0x05, "10MHz" )
|
||||
INPUT_PORTS_END
|
||||
|
||||
ioport_constructor saitekosa_maestro_device::device_input_ports() const
|
||||
{
|
||||
return INPUT_PORTS_NAME(maestro);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_add_mconfig - add device configuration
|
||||
//-------------------------------------------------
|
||||
|
||||
void saitekosa_maestro_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
// basic machine hardware
|
||||
R65C02(config, m_maincpu, 8_MHz_XTAL);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &saitekosa_maestro_device::main_map);
|
||||
|
||||
// extension rom
|
||||
GENERIC_SOCKET(config, "extrom", generic_plain_slot, "saitek_egr");
|
||||
SOFTWARE_LIST(config, "cart_list").set_original("saitek_egr");
|
||||
}
|
||||
|
||||
void saitekosa_analyst_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
saitekosa_maestro_device::device_add_mconfig(config);
|
||||
|
||||
// video hardware
|
||||
HD44780(config, m_lcd, 270'000); // OSC = 91K resistor
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// rom_region - device-specific ROM region
|
||||
//-------------------------------------------------
|
||||
@ -194,166 +425,8 @@ const tiny_rom_entry *saitekosa_analyst_device::device_rom_region() const
|
||||
return ROM_NAME(analyst);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// input_ports - device-specific input ports
|
||||
//-------------------------------------------------
|
||||
|
||||
static INPUT_PORTS_START( maestro )
|
||||
PORT_START("CPU")
|
||||
PORT_CONFNAME( 0x07, 0x04, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, saitekosa_maestro_device, change_cpu_freq, 0) // factory set
|
||||
PORT_CONFSETTING( 0x00, "4MHz" )
|
||||
PORT_CONFSETTING( 0x01, "5.67MHz" )
|
||||
PORT_CONFSETTING( 0x02, "6MHz" )
|
||||
PORT_CONFSETTING( 0x03, "7.2MHz" )
|
||||
PORT_CONFSETTING( 0x04, "8MHz" )
|
||||
PORT_CONFSETTING( 0x05, "10MHz" )
|
||||
INPUT_PORTS_END
|
||||
|
||||
ioport_constructor saitekosa_maestro_device::device_input_ports() const
|
||||
{
|
||||
return INPUT_PORTS_NAME(maestro);
|
||||
}
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_add_mconfig - add device configuration
|
||||
//-------------------------------------------------
|
||||
|
||||
void saitekosa_maestro_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
// basic machine hardware
|
||||
R65C02(config, m_maincpu, 8_MHz_XTAL);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &saitekosa_maestro_device::main_map);
|
||||
|
||||
// extension rom
|
||||
GENERIC_SOCKET(config, "extrom", generic_plain_slot, "saitek_egr");
|
||||
SOFTWARE_LIST(config, "cart_list").set_original("saitek_egr");
|
||||
}
|
||||
|
||||
void saitekosa_analyst_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
saitekosa_maestro_device::device_add_mconfig(config);
|
||||
|
||||
// video hardware
|
||||
HD44780(config, m_lcd, 270'000); // OSC = 91K resistor
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// internal i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
u8 saitekosa_maestro_device::extrom_r(offs_t offset)
|
||||
{
|
||||
u16 bank = m_extrom_bank * 0x4000;
|
||||
return (m_extrom->exists()) ? m_extrom->read_rom(offset | bank) : 0xff;
|
||||
}
|
||||
|
||||
template <int N> void saitekosa_maestro_device::stall_w(u8 data)
|
||||
{
|
||||
// cpu clock divider
|
||||
}
|
||||
|
||||
u8 saitekosa_maestro_device::rts_r()
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
// strobe RTS-P
|
||||
m_expansion->rts_w(1);
|
||||
m_expansion->rts_w(0);
|
||||
}
|
||||
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::xdata_w(u8 data)
|
||||
{
|
||||
// clock latch
|
||||
m_latch = data;
|
||||
}
|
||||
|
||||
u8 saitekosa_maestro_device::xdata_r()
|
||||
{
|
||||
return m_expansion->data_state();
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::control_w(u8 data)
|
||||
{
|
||||
// d0: main rom bank
|
||||
m_rombank->set_entry(data & 1);
|
||||
|
||||
// d1: ext rom bank
|
||||
// d1: ram bank
|
||||
m_extrom_bank = BIT(data, 1);
|
||||
m_rambank->set_entry(m_extrom_bank);
|
||||
|
||||
// d3: enable latch output
|
||||
m_latch_enable = bool(data & 8);
|
||||
|
||||
// d2: STB-P
|
||||
m_expansion->stb_w(BIT(data, 2));
|
||||
}
|
||||
|
||||
u8 saitekosa_maestro_device::ack_r()
|
||||
{
|
||||
// d6: _Vcc
|
||||
// d7: ACK-P
|
||||
return m_expansion->ack_state() ? 0x80 : 0x00;
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::main_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x1fff).ram();
|
||||
map(0x2000, 0x2000).mirror(0x01ff).w(FUNC(saitekosa_maestro_device::stall_w<0>));
|
||||
map(0x2200, 0x2200).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::rts_r), FUNC(saitekosa_maestro_device::stall_w<1>));
|
||||
map(0x2400, 0x2400).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::xdata_r), FUNC(saitekosa_maestro_device::xdata_w));
|
||||
map(0x2600, 0x2600).mirror(0x01ff).rw(FUNC(saitekosa_maestro_device::ack_r), FUNC(saitekosa_maestro_device::control_w));
|
||||
map(0x2800, 0x37ff).bankrw("rambank");
|
||||
map(0x4000, 0x7fff).r(FUNC(saitekosa_maestro_device::extrom_r));
|
||||
map(0x8000, 0xffff).bankr("rombank");
|
||||
}
|
||||
|
||||
void saitekosa_analyst_device::main_map(address_map &map)
|
||||
{
|
||||
saitekosa_maestro_device::main_map(map);
|
||||
map(0x3800, 0x3801).mirror(0x07fe).rw(m_lcd, FUNC(hd44780_device::read), FUNC(hd44780_device::write));
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// host i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
u8 saitekosa_maestro_device::data_r()
|
||||
{
|
||||
return m_latch_enable ? m_latch : 0xff;
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::nmi_w(int state)
|
||||
{
|
||||
m_maincpu->set_input_line(0, !state ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void saitekosa_maestro_device::ack_w(int state)
|
||||
{
|
||||
if (state != m_expansion->ack_state())
|
||||
machine().scheduler().perfect_quantum(attotime::from_usec(100));
|
||||
}
|
||||
|
||||
u32 saitekosa_analyst_device::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
bitmap.fill(0xffffff, cliprect);
|
||||
const u8 *render = m_lcd->render();
|
||||
|
||||
// draw lcd characters
|
||||
for (int i = 0; i < 16; i++)
|
||||
{
|
||||
const u8 *src = render + 16 * ((i & 7) + BIT(i, 3) * 40);
|
||||
for (int y = 0; y < 8; y++)
|
||||
for (int x = 0; x < 5; x++)
|
||||
bitmap.pix(y + 4, i * 6 + x + 2) = (BIT(src[y], 4 - x) && m_expansion->pw_state()) ? 0x282828 : 0xe8e8e8;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(OSA_MAESTRO, device_saitekosa_expansion_interface, saitekosa_maestro_device, "osa_maestro", "Saitek OSA Maestro B-D")
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(OSA_ANALYST, device_saitekosa_expansion_interface, saitekosa_analyst_device, "osa_analyst", "Saitek OSA Analyst")
|
||||
|
||||
@ -13,73 +13,7 @@
|
||||
|
||||
#include "expansion.h"
|
||||
|
||||
#include "bus/generic/slot.h"
|
||||
#include "video/hd44780.h"
|
||||
|
||||
DECLARE_DEVICE_TYPE(OSA_MAESTRO, saitekosa_maestro_device)
|
||||
DECLARE_DEVICE_TYPE(OSA_ANALYST, saitekosa_analyst_device)
|
||||
|
||||
|
||||
class saitekosa_maestro_device : public device_t, public device_saitekosa_expansion_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
saitekosa_maestro_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
DECLARE_INPUT_CHANGED_MEMBER(change_cpu_freq);
|
||||
|
||||
// from host
|
||||
virtual u8 data_r() override;
|
||||
virtual void nmi_w(int state) override;
|
||||
virtual void ack_w(int state) override;
|
||||
|
||||
protected:
|
||||
saitekosa_maestro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
memory_share_creator<u8> m_banked_ram;
|
||||
required_memory_bank m_rambank;
|
||||
required_memory_bank m_rombank;
|
||||
required_device<generic_slot_device> m_extrom;
|
||||
|
||||
u8 m_latch = 0xff;
|
||||
bool m_latch_enable = false;
|
||||
u8 m_extrom_bank = 0;
|
||||
|
||||
virtual void main_map(address_map &map);
|
||||
|
||||
u8 extrom_r(offs_t offset);
|
||||
template <int N> void stall_w(u8 data = 0);
|
||||
u8 rts_r();
|
||||
u8 xdata_r();
|
||||
void xdata_w(u8 data);
|
||||
u8 ack_r();
|
||||
void control_w(u8 data);
|
||||
};
|
||||
|
||||
class saitekosa_analyst_device : public saitekosa_maestro_device
|
||||
{
|
||||
public:
|
||||
saitekosa_analyst_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
virtual u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect) override;
|
||||
|
||||
static auto parent_rom_device_type() { return &OSA_MAESTRO; }
|
||||
|
||||
protected:
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
|
||||
private:
|
||||
required_device<hd44780_device> m_lcd;
|
||||
|
||||
virtual void main_map(address_map &map) override;
|
||||
};
|
||||
DECLARE_DEVICE_TYPE(OSA_MAESTRO, device_saitekosa_expansion_interface)
|
||||
DECLARE_DEVICE_TYPE(OSA_ANALYST, device_saitekosa_expansion_interface)
|
||||
|
||||
#endif // MAME_BUS_SAITEKOSA_MAESTRO_H
|
||||
|
||||
@ -28,14 +28,47 @@ compatible for upgrading to newer Maestro versions.
|
||||
|
||||
#include "softlist_dev.h"
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE(OSA_MAESTROA, saitekosa_maestroa_device, "osa_maestroa", "Saitek OSA Maestro A")
|
||||
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
class saitekosa_maestroa_device : public device_t, public device_saitekosa_expansion_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
saitekosa_maestroa_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
DECLARE_INPUT_CHANGED_MEMBER(change_cpu_freq);
|
||||
|
||||
// from host
|
||||
virtual u8 data_r() override;
|
||||
virtual void nmi_w(int state) override;
|
||||
virtual void ack_w(int state) override;
|
||||
|
||||
protected:
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
|
||||
u8 m_latch = 0xff;
|
||||
bool m_latch_enable = false;
|
||||
|
||||
void main_map(address_map &map);
|
||||
|
||||
u8 rts_r();
|
||||
u8 xdata_r();
|
||||
void xdata_w(u8 data);
|
||||
u8 ack_r();
|
||||
void control_w(u8 data);
|
||||
};
|
||||
|
||||
saitekosa_maestroa_device::saitekosa_maestroa_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, OSA_MAESTROA, tag, owner, clock),
|
||||
device_saitekosa_expansion_interface(mconfig, *this),
|
||||
@ -61,59 +94,23 @@ INPUT_CHANGED_MEMBER(saitekosa_maestroa_device::change_cpu_freq)
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// rom_region - device-specific ROM region
|
||||
// host i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
ROM_START( maestroa )
|
||||
ROM_REGION(0x10000, "maincpu", 0)
|
||||
|
||||
ROM_DEFAULT_BIOS("a1")
|
||||
|
||||
// A
|
||||
ROM_SYSTEM_BIOS(0, "a1", "Maestro A (set 1)")
|
||||
ROMX_LOAD("m6a_a29b.u6", 0x8000, 0x8000, CRC(6ee0197a) SHA1(61f201ca64576aca582bc9f2a427638bd79e1fee), ROM_BIOS(0))
|
||||
|
||||
ROM_SYSTEM_BIOS(1, "a2", "Maestro A (set 2)")
|
||||
ROMX_LOAD("m6a_v14b.u6", 0x8000, 0x8000, CRC(d566a476) SHA1(ef81b9a0dcfbd8427025cfe9bf738d42a7a1139a), ROM_BIOS(1))
|
||||
ROM_END
|
||||
|
||||
const tiny_rom_entry *saitekosa_maestroa_device::device_rom_region() const
|
||||
u8 saitekosa_maestroa_device::data_r()
|
||||
{
|
||||
return ROM_NAME(maestroa);
|
||||
return m_latch_enable ? m_latch : 0xff;
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// input_ports - device-specific input ports
|
||||
//-------------------------------------------------
|
||||
|
||||
static INPUT_PORTS_START( maestroa )
|
||||
PORT_START("CPU")
|
||||
PORT_CONFNAME( 0x03, 0x02, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, saitekosa_maestroa_device, change_cpu_freq, 0) // factory set
|
||||
PORT_CONFSETTING( 0x00, "4MHz" )
|
||||
PORT_CONFSETTING( 0x01, "5.67MHz" )
|
||||
PORT_CONFSETTING( 0x02, "6MHz" )
|
||||
INPUT_PORTS_END
|
||||
|
||||
ioport_constructor saitekosa_maestroa_device::device_input_ports() const
|
||||
void saitekosa_maestroa_device::nmi_w(int state)
|
||||
{
|
||||
return INPUT_PORTS_NAME(maestroa);
|
||||
m_maincpu->set_input_line(INPUT_LINE_NMI, !state ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_add_mconfig - add device configuration
|
||||
//-------------------------------------------------
|
||||
|
||||
void saitekosa_maestroa_device::device_add_mconfig(machine_config &config)
|
||||
void saitekosa_maestroa_device::ack_w(int state)
|
||||
{
|
||||
// basic machine hardware
|
||||
R65C02(config, m_maincpu, 6_MHz_XTAL);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &saitekosa_maestroa_device::main_map);
|
||||
|
||||
// extension rom
|
||||
GENERIC_SOCKET(config, "extrom", generic_plain_slot, "saitek_kso");
|
||||
SOFTWARE_LIST(config, "cart_list").set_original("saitek_kso");
|
||||
if (state != m_expansion->ack_state())
|
||||
machine().scheduler().perfect_quantum(attotime::from_usec(100));
|
||||
}
|
||||
|
||||
|
||||
@ -172,21 +169,62 @@ void saitekosa_maestroa_device::main_map(address_map &map)
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// host i/o
|
||||
// input_ports - device-specific input ports
|
||||
//-------------------------------------------------
|
||||
|
||||
u8 saitekosa_maestroa_device::data_r()
|
||||
static INPUT_PORTS_START( maestroa )
|
||||
PORT_START("CPU")
|
||||
PORT_CONFNAME( 0x03, 0x02, "CPU Frequency" ) PORT_CHANGED_MEMBER(DEVICE_SELF, saitekosa_maestroa_device, change_cpu_freq, 0) // factory set
|
||||
PORT_CONFSETTING( 0x00, "4MHz" )
|
||||
PORT_CONFSETTING( 0x01, "5.67MHz" )
|
||||
PORT_CONFSETTING( 0x02, "6MHz" )
|
||||
INPUT_PORTS_END
|
||||
|
||||
ioport_constructor saitekosa_maestroa_device::device_input_ports() const
|
||||
{
|
||||
return m_latch_enable ? m_latch : 0xff;
|
||||
return INPUT_PORTS_NAME(maestroa);
|
||||
}
|
||||
|
||||
void saitekosa_maestroa_device::nmi_w(int state)
|
||||
|
||||
//-------------------------------------------------
|
||||
// device_add_mconfig - add device configuration
|
||||
//-------------------------------------------------
|
||||
|
||||
void saitekosa_maestroa_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
m_maincpu->set_input_line(INPUT_LINE_NMI, !state ? ASSERT_LINE : CLEAR_LINE);
|
||||
// basic machine hardware
|
||||
R65C02(config, m_maincpu, 6_MHz_XTAL);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &saitekosa_maestroa_device::main_map);
|
||||
|
||||
// extension rom
|
||||
GENERIC_SOCKET(config, "extrom", generic_plain_slot, "saitek_kso");
|
||||
SOFTWARE_LIST(config, "cart_list").set_original("saitek_kso");
|
||||
}
|
||||
|
||||
void saitekosa_maestroa_device::ack_w(int state)
|
||||
|
||||
//-------------------------------------------------
|
||||
// rom_region - device-specific ROM region
|
||||
//-------------------------------------------------
|
||||
|
||||
ROM_START( maestroa )
|
||||
ROM_REGION(0x10000, "maincpu", 0)
|
||||
|
||||
ROM_DEFAULT_BIOS("a1")
|
||||
|
||||
// A
|
||||
ROM_SYSTEM_BIOS(0, "a1", "Maestro A (set 1)")
|
||||
ROMX_LOAD("m6a_a29b.u6", 0x8000, 0x8000, CRC(6ee0197a) SHA1(61f201ca64576aca582bc9f2a427638bd79e1fee), ROM_BIOS(0))
|
||||
|
||||
ROM_SYSTEM_BIOS(1, "a2", "Maestro A (set 2)")
|
||||
ROMX_LOAD("m6a_v14b.u6", 0x8000, 0x8000, CRC(d566a476) SHA1(ef81b9a0dcfbd8427025cfe9bf738d42a7a1139a), ROM_BIOS(1))
|
||||
ROM_END
|
||||
|
||||
const tiny_rom_entry *saitekosa_maestroa_device::device_rom_region() const
|
||||
{
|
||||
if (state != m_expansion->ack_state())
|
||||
machine().scheduler().perfect_quantum(attotime::from_usec(100));
|
||||
return ROM_NAME(maestroa);
|
||||
}
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(OSA_MAESTROA, device_saitekosa_expansion_interface, saitekosa_maestroa_device, "osa_maestroa", "Saitek OSA Maestro A")
|
||||
|
||||
@ -13,43 +13,6 @@
|
||||
|
||||
#include "expansion.h"
|
||||
|
||||
DECLARE_DEVICE_TYPE(OSA_MAESTROA, saitekosa_maestroa_device)
|
||||
|
||||
|
||||
class saitekosa_maestroa_device : public device_t, public device_saitekosa_expansion_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
saitekosa_maestroa_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
DECLARE_INPUT_CHANGED_MEMBER(change_cpu_freq);
|
||||
|
||||
// from host
|
||||
virtual u8 data_r() override;
|
||||
virtual void nmi_w(int state) override;
|
||||
virtual void ack_w(int state) override;
|
||||
|
||||
protected:
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
|
||||
u8 m_latch = 0xff;
|
||||
bool m_latch_enable = false;
|
||||
|
||||
void main_map(address_map &map);
|
||||
|
||||
u8 rts_r();
|
||||
u8 xdata_r();
|
||||
void xdata_w(u8 data);
|
||||
u8 ack_r();
|
||||
void control_w(u8 data);
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(OSA_MAESTROA, device_saitekosa_expansion_interface)
|
||||
|
||||
#endif // MAME_BUS_SAITEKOSA_MAESTROA_H
|
||||
|
||||
@ -35,14 +35,53 @@ TODO:
|
||||
#include "emu.h"
|
||||
#include "sparc.h"
|
||||
|
||||
#include "cpu/sparc/sparc.h"
|
||||
|
||||
DEFINE_DEVICE_TYPE(OSA_SPARC, saitekosa_sparc_device, "osa_sparc", "Saitek OSA Sparc")
|
||||
|
||||
namespace {
|
||||
|
||||
//-------------------------------------------------
|
||||
// initialization
|
||||
//-------------------------------------------------
|
||||
|
||||
class saitekosa_sparc_device : public device_t, public device_saitekosa_expansion_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
saitekosa_sparc_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
// from host
|
||||
virtual u8 data_r() override;
|
||||
virtual void nmi_w(int state) override;
|
||||
virtual void ack_w(int state) override;
|
||||
|
||||
protected:
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
required_device<mb86930_device> m_maincpu;
|
||||
required_region_ptr<u32> m_rom;
|
||||
required_shared_ptr<u32> m_ram;
|
||||
|
||||
u32 m_data_out = 0;
|
||||
u32 m_rom_mask = 0;
|
||||
u32 m_ram_mask = 0;
|
||||
bool m_installed = false;
|
||||
|
||||
void debugger_map(address_map &map);
|
||||
|
||||
u32 rom_r(offs_t offset, u32 mem_mask) { return m_rom[offset & m_rom_mask]; }
|
||||
u32 ram_r(offs_t offset, u32 mem_mask) { return m_ram[offset & m_ram_mask]; }
|
||||
void ram_w(offs_t offset, u32 data, u32 mem_mask) { COMBINE_DATA(&m_ram[offset & m_ram_mask]); }
|
||||
u32 host_io_r(offs_t offset, u32 mem_mask = ~0U);
|
||||
void host_io_w(offs_t offset, u32 data, u32 mem_mask = ~0U);
|
||||
|
||||
void set_ram_mask(u8 n) { m_ram_mask = ((1 << n) / 4) - 1; }
|
||||
};
|
||||
|
||||
saitekosa_sparc_device::saitekosa_sparc_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) :
|
||||
device_t(mconfig, OSA_SPARC, tag, owner, clock),
|
||||
device_saitekosa_expansion_interface(mconfig, *this),
|
||||
@ -77,37 +116,50 @@ void saitekosa_sparc_device::device_reset()
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// rom_region - device-specific ROM region
|
||||
// host i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
#define ROM_LOAD32_BYTE_BIOS(bios, name, offset, length, hash) \
|
||||
ROMX_LOAD(name, offset, length, hash, ROM_SKIP(3) | ROM_BIOS(bios))
|
||||
|
||||
ROM_START( sparc )
|
||||
ROM_REGION32_BE(0x40000, "maincpu", 0)
|
||||
|
||||
ROM_DEFAULT_BIOS("v518")
|
||||
|
||||
ROM_SYSTEM_BIOS(0, "v512a", "Sparc (rev. 512A)")
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512.u5", 0x000000, 0x10000, CRC(96bca59d) SHA1(2c7e693d0cdf69b6e566c6dd03bd24d39e32aa82) )
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512.u4", 0x000001, 0x10000, CRC(15dd621d) SHA1(e8f7404e84fe027b086fcb918fbcaf2ce4203567) )
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512.u3", 0x000002, 0x10000, CRC(3201c6e4) SHA1(9a209219a0ab4b4f874381a16773bf33f8f7ba25) )
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512a.u2", 0x000003, 0x10000, CRC(56dedec7) SHA1(4f9d37e0ca639f892a574aa10a3fb42bba9b82c6) )
|
||||
|
||||
ROM_SYSTEM_BIOS(1, "v518", "Sparc (rev. 518)")
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u5", 0x000000, 0x10000, CRC(cee97a8f) SHA1(541d9d3ee469bacb5a4c537f443836a684e5d168) )
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u4", 0x000001, 0x10000, CRC(7ac37299) SHA1(36f95520fbc9dfed2078d848bf6c3cc7c5823895) )
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u3", 0x000002, 0x10000, CRC(29426d9e) SHA1(ad14f6f2f3e6460d834382faeab78dca9ceb2a63) )
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u2", 0x000003, 0x10000, CRC(b2274cf5) SHA1(d04f41fa1f61439a4655003398f3ae27c2d06f82) )
|
||||
|
||||
ROM_REGION(0x1000, "pals", 0)
|
||||
ROM_LOAD("palce16v8h.u23.jed", 0x0000, 0x0c25, CRC(de79fabc) SHA1(27e01ec405e261109dbe10c254b7127eda0f1886) )
|
||||
ROM_LOAD("palce16v8h.u32.jed", 0x0000, 0x0c25, CRC(422b66c8) SHA1(44b3394e0586c126ee95129c65e6692ffc01fa8e) )
|
||||
ROM_END
|
||||
|
||||
const tiny_rom_entry *saitekosa_sparc_device::device_rom_region() const
|
||||
u8 saitekosa_sparc_device::data_r()
|
||||
{
|
||||
return ROM_NAME(sparc);
|
||||
return (m_data_out & 0x400) ? 0xff : (u8)m_data_out;
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::nmi_w(int state)
|
||||
{
|
||||
m_maincpu->set_input_line(SPARC_IRQ1, !state ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::ack_w(int state)
|
||||
{
|
||||
if (state != m_expansion->ack_state())
|
||||
machine().scheduler().perfect_quantum(attotime::from_usec(100));
|
||||
}
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// internal i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
u32 saitekosa_sparc_device::host_io_r(offs_t offset, u32 mem_mask)
|
||||
{
|
||||
// d0-d7: data input latch, d8: ACK-P
|
||||
return m_expansion->data_state() | (m_expansion->ack_state() ? 0 : 0x100);
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::host_io_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
// d0-d7: data output latch, d10: output latch enable
|
||||
COMBINE_DATA(&m_data_out);
|
||||
|
||||
// d8: STB-P, d9: RTS-P
|
||||
m_expansion->stb_w(BIT(m_data_out, 8));
|
||||
m_expansion->rts_w(BIT(~m_data_out, 9));
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::debugger_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x0003ffff).rom().region("maincpu", 0);
|
||||
map(0x01000000, 0x013fffff).ram().share("ram"); // 4MB
|
||||
}
|
||||
|
||||
|
||||
@ -146,48 +198,40 @@ void saitekosa_sparc_device::device_add_mconfig(machine_config &config)
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// internal i/o
|
||||
// rom_region - device-specific ROM region
|
||||
//-------------------------------------------------
|
||||
|
||||
u32 saitekosa_sparc_device::host_io_r(offs_t offset, u32 mem_mask)
|
||||
#define ROM_LOAD32_BYTE_BIOS(bios, name, offset, length, hash) \
|
||||
ROMX_LOAD(name, offset, length, hash, ROM_SKIP(3) | ROM_BIOS(bios))
|
||||
|
||||
ROM_START( sparc )
|
||||
ROM_REGION32_BE(0x40000, "maincpu", 0)
|
||||
|
||||
ROM_DEFAULT_BIOS("v518")
|
||||
|
||||
ROM_SYSTEM_BIOS(0, "v512a", "Sparc (rev. 512A)")
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512.u5", 0x000000, 0x10000, CRC(96bca59d) SHA1(2c7e693d0cdf69b6e566c6dd03bd24d39e32aa82) )
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512.u4", 0x000001, 0x10000, CRC(15dd621d) SHA1(e8f7404e84fe027b086fcb918fbcaf2ce4203567) )
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512.u3", 0x000002, 0x10000, CRC(3201c6e4) SHA1(9a209219a0ab4b4f874381a16773bf33f8f7ba25) )
|
||||
ROM_LOAD32_BYTE_BIOS(0, "sm16b_512a.u2", 0x000003, 0x10000, CRC(56dedec7) SHA1(4f9d37e0ca639f892a574aa10a3fb42bba9b82c6) )
|
||||
|
||||
ROM_SYSTEM_BIOS(1, "v518", "Sparc (rev. 518)")
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u5", 0x000000, 0x10000, CRC(cee97a8f) SHA1(541d9d3ee469bacb5a4c537f443836a684e5d168) )
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u4", 0x000001, 0x10000, CRC(7ac37299) SHA1(36f95520fbc9dfed2078d848bf6c3cc7c5823895) )
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u3", 0x000002, 0x10000, CRC(29426d9e) SHA1(ad14f6f2f3e6460d834382faeab78dca9ceb2a63) )
|
||||
ROM_LOAD32_BYTE_BIOS(1, "sm16b_518.u2", 0x000003, 0x10000, CRC(b2274cf5) SHA1(d04f41fa1f61439a4655003398f3ae27c2d06f82) )
|
||||
|
||||
ROM_REGION(0x1000, "pals", 0)
|
||||
ROM_LOAD("palce16v8h.u23.jed", 0x0000, 0x0c25, CRC(de79fabc) SHA1(27e01ec405e261109dbe10c254b7127eda0f1886) )
|
||||
ROM_LOAD("palce16v8h.u32.jed", 0x0000, 0x0c25, CRC(422b66c8) SHA1(44b3394e0586c126ee95129c65e6692ffc01fa8e) )
|
||||
ROM_END
|
||||
|
||||
const tiny_rom_entry *saitekosa_sparc_device::device_rom_region() const
|
||||
{
|
||||
// d0-d7: data input latch, d8: ACK-P
|
||||
return m_expansion->data_state() | (m_expansion->ack_state() ? 0 : 0x100);
|
||||
return ROM_NAME(sparc);
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::host_io_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
// d0-d7: data output latch, d10: output latch enable
|
||||
COMBINE_DATA(&m_data_out);
|
||||
|
||||
// d8: STB-P, d9: RTS-P
|
||||
m_expansion->stb_w(BIT(m_data_out, 8));
|
||||
m_expansion->rts_w(BIT(~m_data_out, 9));
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::debugger_map(address_map &map)
|
||||
{
|
||||
map(0x00000000, 0x0003ffff).rom().region("maincpu", 0);
|
||||
map(0x01000000, 0x013fffff).ram().share("ram"); // 4MB
|
||||
}
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// host i/o
|
||||
//-------------------------------------------------
|
||||
|
||||
u8 saitekosa_sparc_device::data_r()
|
||||
{
|
||||
return (m_data_out & 0x400) ? 0xff : (u8)m_data_out;
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::nmi_w(int state)
|
||||
{
|
||||
m_maincpu->set_input_line(SPARC_IRQ1, !state ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void saitekosa_sparc_device::ack_w(int state)
|
||||
{
|
||||
if (state != m_expansion->ack_state())
|
||||
machine().scheduler().perfect_quantum(attotime::from_usec(100));
|
||||
}
|
||||
DEFINE_DEVICE_TYPE_PRIVATE(OSA_SPARC, device_saitekosa_expansion_interface, saitekosa_sparc_device, "osa_sparc", "Saitek OSA Sparc")
|
||||
|
||||
@ -13,48 +13,6 @@
|
||||
|
||||
#include "expansion.h"
|
||||
|
||||
#include "cpu/sparc/sparc.h"
|
||||
|
||||
DECLARE_DEVICE_TYPE(OSA_SPARC, saitekosa_sparc_device)
|
||||
|
||||
|
||||
class saitekosa_sparc_device : public device_t, public device_saitekosa_expansion_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
saitekosa_sparc_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
|
||||
// from host
|
||||
virtual u8 data_r() override;
|
||||
virtual void nmi_w(int state) override;
|
||||
virtual void ack_w(int state) override;
|
||||
|
||||
protected:
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
private:
|
||||
required_device<mb86930_device> m_maincpu;
|
||||
required_region_ptr<u32> m_rom;
|
||||
required_shared_ptr<u32> m_ram;
|
||||
|
||||
u32 m_data_out = 0;
|
||||
u32 m_rom_mask = 0;
|
||||
u32 m_ram_mask = 0;
|
||||
bool m_installed = false;
|
||||
|
||||
void debugger_map(address_map &map);
|
||||
|
||||
u32 rom_r(offs_t offset, u32 mem_mask) { return m_rom[offset & m_rom_mask]; }
|
||||
u32 ram_r(offs_t offset, u32 mem_mask) { return m_ram[offset & m_ram_mask]; }
|
||||
void ram_w(offs_t offset, u32 data, u32 mem_mask) { COMBINE_DATA(&m_ram[offset & m_ram_mask]); }
|
||||
u32 host_io_r(offs_t offset, u32 mem_mask = ~0U);
|
||||
void host_io_w(offs_t offset, u32 data, u32 mem_mask = ~0U);
|
||||
|
||||
void set_ram_mask(u8 n) { m_ram_mask = ((1 << n) / 4) - 1; }
|
||||
};
|
||||
DECLARE_DEVICE_TYPE(OSA_SPARC, device_saitekosa_expansion_interface)
|
||||
|
||||
#endif // MAME_BUS_SAITEKOSA_SPARC_H
|
||||
|
||||
Loading…
Reference in New Issue
Block a user