mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
From: Wilbert Pol [mailto:wilbert@jdg.info]
Subject: uPD7801, uPD78C05, and uPD78C06 cpu cores added to the uPD7810 cpu core This patch adds basic support for the NEC uPD7801, uPD78C05, and uPD78C06 cpus to the uPD7810 cpu core.
This commit is contained in:
Aaron Giles
parent
34781e5f4c
commit
0104d6ff63
@ -1225,8 +1225,9 @@ $(CPUOBJ)/v810/v810.o: $(CPUSRC)/v810/v810.c \
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CPUDEFS += -DHAS_UPD7810=$(if $(filter UPD7810,$(CPUS)),1,0)
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CPUDEFS += -DHAS_UPD7807=$(if $(filter UPD7807,$(CPUS)),1,0)
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CPUDEFS += -DHAS_UPD7801=$(if $(filter UPD7801,$(CPUS)),1,0)
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ifneq ($(filter UPD7810 UPD7807,$(CPUS)),)
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ifneq ($(filter UPD7810 UPD7807 UPD7801,$(CPUS)),)
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OBJDIRS += $(CPUOBJ)/upd7810
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CPUOBJS += $(CPUOBJ)/upd7810/upd7810.o
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DBGOBJS += $(CPUOBJ)/upd7810/7810dasm.o
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File diff suppressed because it is too large
Load Diff
@ -291,7 +291,7 @@ static void HALT(void)
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{
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int cycles = (upd7810_icount / 4) * 4;
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upd7810_icount -= cycles;
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upd7810_timers(cycles);
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upd7810.handle_timers(cycles);
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PC -= 1; /* continue executing HALT */
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}
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@ -816,7 +816,7 @@ static void STOP(void)
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{
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int cycles = (upd7810_icount / 4) * 4;
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upd7810_icount -= cycles;
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upd7810_timers(cycles);
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upd7810.handle_timers(cycles);
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PC -= 1;
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}
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@ -8397,9 +8397,9 @@ static void ONIW_wa_xx(void)
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static void PRE_48(void)
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{
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RDOP(OP2);
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upd7810_icount -= op48[OP2].cycles;
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upd7810_timers(op48[OP2].cycles);
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(*op48[OP2].opfunc)();
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upd7810_icount -= upd7810.op48[OP2].cycles;
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upd7810.handle_timers(upd7810.op48[OP2].cycles);
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(*upd7810.op48[OP2].opfunc)();
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}
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/* 49: 0100 1001 xxxx xxxx */
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@ -8430,18 +8430,18 @@ static void MVIX_HL_xx(void)
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static void PRE_4C(void)
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{
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RDOP(OP2);
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upd7810_icount -= op4C[OP2].cycles;
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upd7810_timers(op4C[OP2].cycles);
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(*op4C[OP2].opfunc)();
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upd7810_icount -= upd7810.op4C[OP2].cycles;
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upd7810.handle_timers(upd7810.op4C[OP2].cycles);
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(*upd7810.op4C[OP2].opfunc)();
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}
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/* 4d: prefix */
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static void PRE_4D(void)
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{
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RDOP(OP2);
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upd7810_icount -= op4D[OP2].cycles;
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upd7810_timers(op4D[OP2].cycles);
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(*op4D[OP2].opfunc)();
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upd7810_icount -= upd7810.op4D[OP2].cycles;
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upd7810.handle_timers(upd7810.op4D[OP2].cycles);
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(*upd7810.op4D[OP2].opfunc)();
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}
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/* 4e: 0100 111d dddd dddd */
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@ -8820,9 +8820,9 @@ static void SK_bit(void)
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static void PRE_60(void)
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{
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RDOP(OP2);
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upd7810_icount -= op60[OP2].cycles;
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upd7810_timers(op60[OP2].cycles);
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(*op60[OP2].opfunc)();
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upd7810_icount -= upd7810.op60[OP2].cycles;
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upd7810.handle_timers(upd7810.op60[OP2].cycles);
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(*upd7810.op60[OP2].opfunc)();
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}
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/* 61: 0110 0001 */
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@ -8883,9 +8883,9 @@ static void STAW_wa(void)
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static void PRE_64(void)
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{
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RDOP(OP2);
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upd7810_icount -= op64[OP2].cycles;
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upd7810_timers(op64[OP2].cycles);
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(*op64[OP2].opfunc)();
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upd7810_icount -= upd7810.op64[OP2].cycles;
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upd7810.handle_timers(upd7810.op64[OP2].cycles);
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(*upd7810.op64[OP2].opfunc)();
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}
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/* 65: 0110 0101 oooo oooo xxxx xxxx */
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@ -8970,9 +8970,9 @@ static void MVI_L_xx(void)
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static void PRE_70(void)
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{
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RDOP(OP2);
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upd7810_icount -= op70[OP2].cycles;
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upd7810_timers(op70[OP2].cycles);
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(*op70[OP2].opfunc)();
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upd7810_icount -= upd7810.op70[OP2].cycles;
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upd7810.handle_timers(upd7810.op70[OP2].cycles);
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(*upd7810.op70[OP2].opfunc)();
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}
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/* 71: 0111 0001 oooo oooo xxxx xxxx */
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@ -9005,9 +9005,9 @@ static void SOFTI(void)
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static void PRE_74(void)
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{
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RDOP(OP2);
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upd7810_icount -= op74[OP2].cycles;
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upd7810_timers(op74[OP2].cycles);
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(*op74[OP2].opfunc)();
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upd7810_icount -= upd7810.op74[OP2].cycles;
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upd7810.handle_timers(upd7810.op74[OP2].cycles);
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(*upd7810.op74[OP2].opfunc)();
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}
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/* 75: 0111 0101 oooo oooo xxxx xxxx */
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@ -9072,7 +9072,6 @@ static void CALT(void)
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PCH=RM(w.w.l+1);
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change_pc( PCD );
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logerror ("!!!!!!!%.4x calt %.2x %.4x; game master table position not known\n",PPC, OP, PCD);
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}
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}
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@ -9339,3 +9338,138 @@ static void JR(void)
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change_pc(PCD);
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}
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/*********************/
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/* */
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/* 7801 instructions */
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/* */
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/*********************/
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static void CALT_7801(void)
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{
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PAIR w;
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w.d = 0;
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w.w.l = 0x80 + 2 * (OP & 0x3f);
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SP--;
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WM( SPD, PCH );
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SP--;
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WM( SPD, PCL );
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PCL=RM(w.w.l);
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PCH=RM(w.w.l+1);
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change_pc( PCD );
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}
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/* DCR(W) and INR(W) instructions do not modify the CY register on at least 78c05 and 78c06 */
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static void DCR_A_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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DCR_A();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void DCR_B_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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DCR_B();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void DCR_C_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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DCR_C();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void DCRW_wa_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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DCRW_wa();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void INR_A_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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INR_A();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void INR_B_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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INR_B();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void INR_C_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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INR_C();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void INRW_wa_7801(void)
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{
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UINT32 old_CY = PSW & CY;
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INRW_wa();
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PSW = ( PSW & ~CY ) | old_CY;
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}
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static void IN(void)
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{
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logerror("unimplemented instruction: IN\n");
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}
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static void OUT(void)
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{
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logerror("unimplemented instruction: OUT\n");
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}
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static void MOV_A_S(void)
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{
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logerror("unimplemented instruction: MOV_A_S\n");
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}
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static void MOV_S_A(void)
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{
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logerror("unimplemented instruction: MOV_A_S\n");
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}
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static void PEN(void)
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{
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logerror("unimplemented instruction: PEN\n");
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}
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static void PER(void)
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{
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logerror("unimplemented instruction: PER\n");
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}
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static void PEX(void)
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{
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logerror("unimplemented instruction: PEX\n");
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}
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static void SIO(void)
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{
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logerror("unimplemented instruction: SIO\n");
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}
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static void SKIT_F0(void)
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{
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logerror("unimplemented instruction: SKIT_F0\n");
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}
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static void SKNIT_F0(void)
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{
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logerror("unimplemented instruction: SKNIT_F0\n");
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}
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static void STM(void)
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{
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upd7810.ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0;
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}
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File diff suppressed because it is too large
Load Diff
@ -59,6 +59,16 @@
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* 5B xx (CLR)
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* 5D xx (SK bit)
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*
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* 2008-02-24 (Wilbert Pol):
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* - Added preliminary support for uPD7801
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* For the uPD7801 only the basic instruction set was added. The current timer
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* and serial i/o implementations are most likely incorrect.
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* - Added basic support for uPD78C05 and uPD78C06
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* Documentation of the actual instruction set layout is missing, so we took
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* the uPD7801 instruction set and only kept the instructions mentioned in
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* the little documentation available on the uPD78c05A/06A. The serial i/o
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* implementation has not been tested and is probably incorrect.
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*
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*****************************************************************************/
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/* Hau around 23 May 2004
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gta, gti, dgt fixed
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@ -1496,6 +1506,30 @@ static void upd7810_timers(int cycles)
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}
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}
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//static void upd7801_timers(int cycles)
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//{
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//}
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static void upd78c05_timers(int cycles)
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{
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if ( upd7810.ovc0 ) {
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upd7810.ovc0 -= cycles;
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if ( upd7810.ovc0 <= 0 ) {
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IRR |= INTFT0;
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if (0x00 == (TMM & 0x03)) {
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TO ^= 1;
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if (upd7810.config.io_callback)
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(*upd7810.config.io_callback)(UPD7810_TO,TO);
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}
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while ( upd7810.ovc0 <= 0 ) {
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upd7810.ovc0 += ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0;
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}
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}
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}
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}
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static void upd7810_init(int index, int clock, const void *config, int (*irqcallback)(int))
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{
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upd7810.config = *(const UPD7810_CONFIG*) config;
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@ -1580,6 +1614,13 @@ static void upd7810_reset (void)
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upd7810.irq_callback = save_irqcallback;
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upd7810.opXX = opXX_7810;
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upd7810.op48 = op48;
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upd7810.op4C = op4C;
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upd7810.op4D = op4D;
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upd7810.op60 = op60;
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upd7810.op64 = op64;
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upd7810.op70 = op70;
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upd7810.op74 = op74;
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ETMM = 0xff;
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TMM = 0xff;
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MA = 0xff;
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@ -1599,6 +1640,7 @@ static void upd7810_reset (void)
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// gamemaster falling block "and"s to enable interrupts
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MKL = 0xff;
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MKH = 0xff; //?
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upd7810.handle_timers = upd7810_timers;
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}
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static void upd7807_reset (void)
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@ -1607,14 +1649,54 @@ static void upd7807_reset (void)
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upd7810.opXX = opXX_7807;
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}
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static void upd7801_reset( void ) {
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upd7810_reset();
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upd7810.op48 = op48_7801;
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upd7810.op4C = op4C_7801;
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upd7810.op4D = op4D_7801;
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upd7810.op60 = op60_7801;
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upd7810.op64 = op64_7801;
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upd7810.op70 = op70_7801;
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upd7810.op74 = op74_7801;
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upd7810.opXX = opXX_7801;
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}
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static void upd78c05_reset( void ) {
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upd7810_reset();
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upd7810.op48 = op48_78c05;
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upd7810.op4C = op4C_78c05;
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upd7810.op4D = op4D_78c05;
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upd7810.op60 = op60_78c05;
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upd7810.op64 = op64_78c05;
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upd7810.op70 = op70_78c05;
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upd7810.op74 = op74_78c05;
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upd7810.opXX = opXX_78c05;
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MA = 0; /* All outputs */
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MC = 0xFF; /* All inputs */
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V = 0xFF; /* The vector register is always pointing to FF00 */
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upd7810.handle_timers = upd78c05_timers;
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TM0 = 0xFF; /* Timer seems to be running from boot */
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upd7810.ovc0 = ( ( TMM & 0x04 ) ? 16 * 8 : 8 ) * TM0;
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}
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static void upd78c06_reset( void ) {
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upd78c05_reset();
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upd7810.op48 = op48_78c06;
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upd7810.op4C = op4C_78c06;
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upd7810.op4D = op4D_78c06;
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upd7810.op60 = op60_78c06;
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upd7810.op64 = op64_78c06;
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upd7810.op70 = op70_78c06;
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upd7810.op74 = op74_78c06;
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upd7810.opXX = opXX_78c06;
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}
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static void upd7810_exit (void)
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{
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}
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static int upd7810_execute (int cycles)
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{
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const struct opcode_s *opXX = upd7810.opXX;
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upd7810_icount = cycles;
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do
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@ -1631,15 +1713,15 @@ static int upd7810_execute (int cycles)
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* L0 for "MVI L,xx" or "LXI H,xxxx"
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* L1 for "MVI A,xx"
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*/
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PSW &= ~opXX[OP].mask_l0_l1;
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PSW &= ~upd7810.opXX[OP].mask_l0_l1;
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/* skip flag set and not SOFTI opcode? */
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if ((PSW & SK) && (OP != 0x72))
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{
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if (opXX[OP].cycles)
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if (upd7810.opXX[OP].cycles)
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{
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cc = opXX[OP].cycles_skip;
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PC += opXX[OP].oplen - 1;
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cc = upd7810.opXX[OP].cycles_skip;
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PC += upd7810.opXX[OP].oplen - 1;
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}
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else
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{
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@ -1647,46 +1729,46 @@ static int upd7810_execute (int cycles)
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switch (OP)
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{
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case 0x48:
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cc = op48[OP2].cycles_skip;
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PC += op48[OP2].oplen - 2;
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cc = upd7810.op48[OP2].cycles_skip;
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PC += upd7810.op48[OP2].oplen - 2;
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break;
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case 0x4c:
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cc = op4C[OP2].cycles_skip;
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PC += op4C[OP2].oplen - 2;
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cc = upd7810.op4C[OP2].cycles_skip;
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PC += upd7810.op4C[OP2].oplen - 2;
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break;
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case 0x4d:
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cc = op4D[OP2].cycles_skip;
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PC += op4D[OP2].oplen - 2;
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cc = upd7810.op4D[OP2].cycles_skip;
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PC += upd7810.op4D[OP2].oplen - 2;
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break;
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case 0x60:
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cc = op60[OP2].cycles_skip;
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PC += op60[OP2].oplen - 2;
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cc = upd7810.op60[OP2].cycles_skip;
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PC += upd7810.op60[OP2].oplen - 2;
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break;
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case 0x64:
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cc = op64[OP2].cycles_skip;
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PC += op64[OP2].oplen - 2;
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cc = upd7810.op64[OP2].cycles_skip;
|
||||
PC += upd7810.op64[OP2].oplen - 2;
|
||||
break;
|
||||
case 0x70:
|
||||
cc = op70[OP2].cycles_skip;
|
||||
PC += op70[OP2].oplen - 2;
|
||||
cc = upd7810.op70[OP2].cycles_skip;
|
||||
PC += upd7810.op70[OP2].oplen - 2;
|
||||
break;
|
||||
case 0x74:
|
||||
cc = op74[OP2].cycles_skip;
|
||||
PC += op74[OP2].oplen - 2;
|
||||
cc = upd7810.op74[OP2].cycles_skip;
|
||||
PC += upd7810.op74[OP2].oplen - 2;
|
||||
break;
|
||||
default:
|
||||
fatalerror("uPD7810 internal error: check cycle counts for main");
|
||||
}
|
||||
}
|
||||
PSW &= ~SK;
|
||||
upd7810_timers( cc );
|
||||
upd7810.handle_timers( cc );
|
||||
change_pc( PCD );
|
||||
}
|
||||
else
|
||||
{
|
||||
cc = opXX[OP].cycles;
|
||||
upd7810_timers( cc );
|
||||
(*opXX[OP].opfunc)();
|
||||
cc = upd7810.opXX[OP].cycles;
|
||||
upd7810.handle_timers( cc );
|
||||
(*upd7810.opXX[OP].opfunc)();
|
||||
}
|
||||
upd7810_icount -= cc;
|
||||
upd7810_take_irq();
|
||||
@ -2017,3 +2099,75 @@ void upd7807_get_info(UINT32 state, cpuinfo *info)
|
||||
default: upd7810_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
void upd7801_get_info(UINT32 state, cpuinfo *info) {
|
||||
switch( state ) {
|
||||
case CPUINFO_PTR_RESET: info->reset = upd7801_reset; break;
|
||||
#ifdef ENABLE_DEBUGGER
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = upd7801_dasm; break;
|
||||
#endif /* ENABLE_DEBUGGER */
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "uPD7801"); break;
|
||||
|
||||
default: upd7810_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
void upd78c05_get_info(UINT32 state, cpuinfo *info ) {
|
||||
switch ( state ) {
|
||||
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 4; break;
|
||||
|
||||
case CPUINFO_PTR_RESET: info->reset = upd78c05_reset; break;
|
||||
#ifdef ENABLE_DEBUGGER
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = upd78c05_dasm; break;
|
||||
#endif /* ENABLE_DEBUGGER */
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C05"); break;
|
||||
|
||||
/* These registers are not present in the uPD78C05 cpu */
|
||||
case CPUINFO_STR_REGISTER + UPD7810_A2:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_V2:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_EA2:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_BC2:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_DE2:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_HL2:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_MA:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_MCC:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_MC:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_MM:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_MF:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_ETMM:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_EOM:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_SML:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_SMH:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_ANM:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_MKH:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_ZCM:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_CR0:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_CR1:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_CR2:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_CR3:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_RXB:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_TXB:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_TXD:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_RXD:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_SCK:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_TI:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_TO:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_CI:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_CO0:
|
||||
case CPUINFO_STR_REGISTER + UPD7810_CO1: break;
|
||||
|
||||
default: upd7801_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
void upd78c06_get_info(UINT32 state, cpuinfo *info ) {
|
||||
switch ( state ) {
|
||||
case CPUINFO_PTR_RESET: info->reset = upd78c06_reset; break;
|
||||
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "uPD78C06"); break;
|
||||
|
||||
default: upd78c05_get_info(state, info); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -11,6 +11,9 @@
|
||||
|
||||
// unfortunatly memory configuration differs with internal rom size
|
||||
typedef enum {
|
||||
TYPE_7801,
|
||||
TYPE_78C05,
|
||||
TYPE_78C06,
|
||||
TYPE_7810,
|
||||
TYPE_7810_GAMEMASTER, // a few modifications until internal rom dumped
|
||||
TYPE_7807
|
||||
@ -62,8 +65,11 @@ enum {
|
||||
#define UPD7810_INTF2 1
|
||||
#define UPD7810_INTFE1 4
|
||||
|
||||
extern void upd7810_get_info(UINT32 state, cpuinfo *info);
|
||||
extern void upd7807_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd7810_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd7807_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd7801_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd78c05_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd78c06_get_info(UINT32 state, cpuinfo *info);
|
||||
|
||||
typedef struct {
|
||||
PAIR ppc; /* previous program counter */
|
||||
@ -144,6 +150,12 @@ typedef struct {
|
||||
const struct opcode_s *opXX; /* opcode table */
|
||||
const struct opcode_s *op48;
|
||||
const struct opcode_s *op4C;
|
||||
const struct opcode_s *op4D;
|
||||
const struct opcode_s *op60;
|
||||
const struct opcode_s *op64;
|
||||
const struct opcode_s *op70;
|
||||
const struct opcode_s *op74;
|
||||
void (*handle_timers)(int cycles);
|
||||
UPD7810_CONFIG config;
|
||||
int (*irq_callback)(int irqline);
|
||||
} UPD7810;
|
||||
@ -151,6 +163,8 @@ typedef struct {
|
||||
#ifdef ENABLE_DEBUGGER
|
||||
offs_t upd7810_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t upd7807_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t upd7801_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
offs_t upd78c05_dasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@ -141,6 +141,9 @@ enum _cpu_type
|
||||
CPU_ASAP,
|
||||
CPU_UPD7810,
|
||||
CPU_UPD7807,
|
||||
CPU_UPD7801,
|
||||
CPU_UPD78C05,
|
||||
CPU_UPD78C06,
|
||||
CPU_JAGUARGPU,
|
||||
CPU_JAGUARDSP,
|
||||
CPU_R3000BE,
|
||||
|
||||
@ -113,6 +113,9 @@ void psxcpu_get_info(UINT32 state, cpuinfo *info);
|
||||
void asap_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd7810_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd7807_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd7801_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd78c05_get_info(UINT32 state, cpuinfo *info);
|
||||
void upd78c06_get_info(UINT32 state, cpuinfo *info);
|
||||
void jaguargpu_get_info(UINT32 state, cpuinfo *info);
|
||||
void jaguardsp_get_info(UINT32 state, cpuinfo *info);
|
||||
void r3000be_get_info(UINT32 state, cpuinfo *info);
|
||||
@ -553,6 +556,11 @@ static const struct
|
||||
#if (HAS_UPD7807)
|
||||
{ CPU_UPD7807, upd7807_get_info },
|
||||
#endif
|
||||
#if (HAS_UPD7801)
|
||||
{ CPU_UPD7801, upd7801_get_info },
|
||||
{ CPU_UPD78C05, upd78c05_get_info },
|
||||
{ CPU_UPD78C06, upd78c06_get_info },
|
||||
#endif
|
||||
#if (HAS_JAGUAR)
|
||||
{ CPU_JAGUARGPU, jaguargpu_get_info },
|
||||
{ CPU_JAGUARDSP, jaguardsp_get_info },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user