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Cleanups and version bump

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This commit is contained in:
Miodrag Milanovic 2015-03-25 08:16:51 +01:00
parent fda60d87eb
commit 0147bb4cc8
206 changed files with 1714 additions and 1733 deletions
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4
hash/nes.xml
View File

@ -57391,7 +57391,7 @@ preliminary proto for the PAL version, still running on NTSC systems) or the gfx
<publisher>Union Bond</publisher>
<info name="serial" value="G-0005"/>
<part name="cart" interface="nes_cart">
<feature name="slot" value="nanjing" /> <!-- header actually says 164... -->
<feature name="slot" value="nanjing" /> <!-- header actually says 164... -->
<feature name="pcb" value="UNL-NANJING" />
<dataarea name="prg" size="524288">
<rom name="ying tao xiao wan zi (g-005) (ch).prg" size="524288" crc="8209ba79" sha1="fa56608d8dcf5a144dd1fc81282cd86fd51060fe" offset="00000" status="baddump" />
@ -75420,7 +75420,7 @@ be better to redump them properly. -->
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="cart" interface="nes_cart">
<feature name="slot" value="fk23ca" /> <!-- UNIF header pointed to FK23C, but the menu does not appear with that mapper... investigate! -->
<feature name="slot" value="fk23ca" /> <!-- UNIF header pointed to FK23C, but the menu does not appear with that mapper... investigate! -->
<feature name="pcb" value="BMC-FK23C" />
<dataarea name="prg" size="8388608">
<rom name="120-in-1 (unl)[u].prg" size="8388608" crc="678de5aa" sha1="01da22ddf1897b47d6b03ecb4ff0c093f9b39dfc" offset="00000" status="baddump" />

2
hash/pasogo.xml
View File

@ -9,7 +9,7 @@
歴代棋聖戦名曲集 (Rekidai Kisei Sen Meikyokushuu)
棋界覇王伝・古典編 (Kikai Haoh Den - Koten-hen)
棋界覇王伝・現代編 (Kikai Haoh Den - Gendai-hen)
The undumped cart numbers are KS-1005, KS-1006, KS-1007 and KS-1008
For the remaining undumped games, the game to cart number match is unknown.
-->

5
src/emu/bus/a2bus/ezcgi.c
View File

@ -43,7 +43,7 @@ MACHINE_CONFIG_END
#define MSX2_VISIBLE_YBORDER_PIXELS 14 * 2
MACHINE_CONFIG_FRAGMENT( ezcgi9938 )
MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9938_device, tms_irq_w))
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
@ -57,7 +57,7 @@ MACHINE_CONFIG_FRAGMENT( ezcgi9938 )
MACHINE_CONFIG_END
MACHINE_CONFIG_FRAGMENT( ezcgi9958 )
MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9958_device, tms_irq_w))
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
@ -311,4 +311,3 @@ WRITE_LINE_MEMBER( a2bus_ezcgi_9958_device::tms_irq_w )
lower_slot_irq();
}
}

4
src/emu/bus/scsi/omti5100.c
View File

@ -20,8 +20,8 @@ const rom_entry *omti5100_device::device_rom_region() const
omti5100_device::omti5100_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: scsihd_device(mconfig, OMTI5100, "OMTI 5100", tag, owner, clock, "omti5100", __FILE__),
m_image0(*this, "image0"),
m_image1(*this, "image1")
m_image0(*this, "image0"),
m_image1(*this, "image1")
{
}

72
src/emu/cpu/hmcs40/hmcs40.c
View File

@ -187,7 +187,7 @@ void hmcs40_cpu_device::device_start()
m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(hmcs40_cpu_device::simple_timer_cb), this));
reset_prescaler();
m_read_r0.resolve_safe(0);
m_read_r1.resolve_safe(0);
m_read_r2.resolve_safe(0);
@ -196,7 +196,7 @@ void hmcs40_cpu_device::device_start()
m_read_r5.resolve_safe(0);
m_read_r6.resolve_safe(0);
m_read_r7.resolve_safe(0);
m_write_r0.resolve_safe();
m_write_r1.resolve_safe();
m_write_r2.resolve_safe();
@ -290,15 +290,15 @@ void hmcs40_cpu_device::device_reset()
{
m_pc = m_pcmask;
m_prev_op = m_op = 0;
// clear i/o
m_d = m_polarity;
for (int i = 0; i < 16; i++)
hmcs40_cpu_device::write_d(i, 0);
for (int i = 0; i < 8; i++)
hmcs40_cpu_device::write_r(i, 0);
// clear interrupts
m_cf = 0;
m_ie = 0;
@ -316,7 +316,7 @@ UINT8 hmcs40_cpu_device::read_r(int index)
{
index &= 7;
UINT8 inp = 0;
switch (index)
{
case 0: inp = m_read_r0(index, 0xff); break;
@ -328,7 +328,7 @@ UINT8 hmcs40_cpu_device::read_r(int index)
case 6: inp = m_read_r6(index, 0xff); break;
case 7: inp = m_read_r7(index, 0xff); break;
}
return ((inp ^ m_polarity) | m_r[index]) & 0xf;
}
@ -337,7 +337,7 @@ void hmcs40_cpu_device::write_r(int index, UINT8 data)
index &= 7;
data = (data ^ m_polarity) & 0xf;
m_r[index] = data;
switch (index)
{
case 0: m_write_r0(index, data, 0xff); break;
@ -354,7 +354,7 @@ void hmcs40_cpu_device::write_r(int index, UINT8 data)
int hmcs40_cpu_device::read_d(int index)
{
index &= 15;
return ((m_read_d(index, 0xffff) ^ m_polarity) | m_d) >> index & 1;
}
@ -362,7 +362,7 @@ void hmcs40_cpu_device::write_d(int index, int state)
{
index &= 15;
state = (((state) ? 1 : 0) ^ m_polarity) & 1;
m_d = (m_d & ~(1 << index)) | state << index;
m_write_d(index, m_d, 0xffff);
}
@ -374,7 +374,7 @@ void hmcs40_cpu_device::write_d(int index, int state)
UINT8 hmcs43_cpu_device::read_r(int index)
{
index &= 7;
if (index >= 2)
logerror("%s read from %s port R%d at $%04X\n", tag(), (index >= 4) ? "unknown" : "output", index, m_prev_pc);
@ -394,7 +394,7 @@ void hmcs43_cpu_device::write_r(int index, UINT8 data)
int hmcs43_cpu_device::read_d(int index)
{
index &= 15;
if (index >= 4)
logerror("%s read from output pin D%d at $%04X\n", tag(), index, m_prev_pc);
@ -408,10 +408,10 @@ int hmcs43_cpu_device::read_d(int index)
UINT8 hmcs44_cpu_device::read_r(int index)
{
index &= 7;
if (index >= 6)
logerror("%s read from unknown port R%d at $%04X\n", tag(), index, m_prev_pc);
return hmcs40_cpu_device::read_r(index);
}
@ -432,10 +432,10 @@ void hmcs44_cpu_device::write_r(int index, UINT8 data)
UINT8 hmcs45_cpu_device::read_r(int index)
{
index &= 7;
if (index >= 6)
logerror("%s read from %s port R%d at $%04X\n", tag(), (index == 7) ? "unknown" : "output", index, m_prev_pc);
return hmcs40_cpu_device::read_r(index);
}
@ -460,10 +460,10 @@ void hmcs40_cpu_device::do_interrupt()
m_icount--;
push_stack();
m_ie = 0;
// line 0/1 for external interrupt, let's use 2 for t/c interrupt
int line = (m_iri) ? m_eint_line : 2;
// vector $3f, on page 0(timer/counter), or page 1(external)
// external interrupt has priority over t/c interrupt
m_pc = 0x3f | (m_iri ? 0x40 : 0);
@ -480,7 +480,7 @@ void hmcs40_cpu_device::execute_set_input(int line, int state)
if (line != 0 && line != 1)
return;
state = (state) ? 1 : 0;
// external interrupt request on rising edge
if (state && !m_int[line])
{
@ -490,12 +490,12 @@ void hmcs40_cpu_device::execute_set_input(int line, int state)
m_iri = 1;
m_if[line] = 1;
}
// clock tc if it is in counter mode
if (m_cf && line == 1)
increment_tc();
}
m_int[line] = state;
}
@ -511,7 +511,7 @@ TIMER_CALLBACK_MEMBER( hmcs40_cpu_device::simple_timer_cb )
// timer prescaler overflow
if (!m_cf)
increment_tc();
reset_prescaler();
}
@ -519,7 +519,7 @@ void hmcs40_cpu_device::increment_tc()
{
// increment timer/counter
m_tc = (m_tc + 1) & 0xf;
// timer interrupt request on overflow
if (m_tc == 0 && !m_tf)
{
@ -554,7 +554,7 @@ void hmcs40_cpu_device::execute_run()
while (m_icount > 0)
{
m_icount--;
// LPU is handled 1 cycle later
if ((m_prev_op & 0x3e0) == 0x340)
{
@ -571,7 +571,7 @@ void hmcs40_cpu_device::execute_run()
// remember previous state
m_prev_op = m_op;
m_prev_pc = m_pc;
// fetch next opcode
debugger_instruction_hook(this, m_pc);
m_op = m_program->read_word(m_pc << 1) & 0x3ff;
@ -582,7 +582,7 @@ void hmcs40_cpu_device::execute_run()
switch (m_op)
{
/* 0x000 */
case 0x000: case 0x001: case 0x002: case 0x003:
op_xsp(); break;
case 0x004: case 0x005: case 0x006: case 0x007:
@ -602,7 +602,7 @@ void hmcs40_cpu_device::execute_run()
op_am(); break;
case 0x03c:
op_lta(); break;
case 0x040:
op_lxa(); break;
case 0x045:
@ -626,7 +626,7 @@ void hmcs40_cpu_device::execute_run()
case 0x070: case 0x071: case 0x072: case 0x073: case 0x074: case 0x075: case 0x076: case 0x077:
case 0x078: case 0x079: case 0x07a: case 0x07b: case 0x07c: case 0x07d: case 0x07e: case 0x07f:
op_lai(); break;
case 0x080: case 0x081: case 0x082: case 0x083: case 0x084: case 0x085: case 0x086: case 0x087:
case 0x088: case 0x089: case 0x08a: case 0x08b: case 0x08c: case 0x08d: case 0x08e: case 0x08f:
op_ai(); break;
@ -655,10 +655,10 @@ void hmcs40_cpu_device::execute_run()
case 0x0f0: case 0x0f1: case 0x0f2: case 0x0f3: case 0x0f4: case 0x0f5: case 0x0f6: case 0x0f7:
case 0x0f8: case 0x0f9: case 0x0fa: case 0x0fb: case 0x0fc: case 0x0fd: case 0x0fe: case 0x0ff:
op_xamr(); break;
/* 0x100 */
case 0x110: case 0x111:
op_lmaiy(); break;
case 0x114: case 0x115:
@ -682,7 +682,7 @@ void hmcs40_cpu_device::execute_run()
case 0x170: case 0x171: case 0x172: case 0x173: case 0x174: case 0x175: case 0x176: case 0x177:
case 0x178: case 0x179: case 0x17a: case 0x17b: case 0x17c: case 0x17d: case 0x17e: case 0x17f:
op_lti(); break;
case 0x1a0:
op_tif1(); break;
case 0x1a1:
@ -706,7 +706,7 @@ void hmcs40_cpu_device::execute_run()
/* 0x200 */
case 0x200: case 0x201: case 0x202: case 0x203:
op_tm(); break;
case 0x204: case 0x205: case 0x206: case 0x207:
@ -728,7 +728,7 @@ void hmcs40_cpu_device::execute_run()
op_alem(); break;
case 0x23c:
op_lat(); break;
case 0x240:
op_laspx(); break;
case 0x244:
@ -804,8 +804,8 @@ void hmcs40_cpu_device::execute_run()
case 0x3f0: case 0x3f1: case 0x3f2: case 0x3f3: case 0x3f4: case 0x3f5: case 0x3f6: case 0x3f7:
case 0x3f8: case 0x3f9: case 0x3fa: case 0x3fb: case 0x3fc: case 0x3fd: case 0x3fe: case 0x3ff:
op_cal(); break;
default:
op_illegal(); break;
} /* big switch */

4
src/emu/cpu/hmcs40/hmcs40.h
View File

@ -182,7 +182,7 @@ protected:
int m_eint_line; // which input_line caused an interrupt
emu_timer *m_timer;
int m_icount;
UINT16 m_pc; // Program Counter
UINT16 m_prev_pc;
UINT8 m_page; // LPU prepared page
@ -213,7 +213,7 @@ protected:
// misc internal helpers
void increment_pc();
UINT8 ram_r();
void ram_w(UINT8 data);
void pop_stack();

90
src/emu/cpu/hmcs40/hmcs40d.c
View File

@ -3,7 +3,7 @@
/*
Hitachi HMCS40 MCU family disassembler
NOTE: start offset(basepc) is $3F, not 0
*/
@ -92,42 +92,42 @@ static const UINT8 hmcs40_mnemonic[0x400] =
{
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
/* 0x000 */
mNOP, mXSP, mXSP, mXSP, mSEM, mSEM, mSEM, mSEM, mLAM, mLAM, mLAM, mLAM, m, m, m, m,
mNOP, mXSP, mXSP, mXSP, mSEM, mSEM, mSEM, mSEM, mLAM, mLAM, mLAM, mLAM, m, m, m, m,
mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,mLMIIY,
mLBM, mLBM, mLBM, mLBM, mBLEM, m, m, m, m, m, m, m, m, m, m, m,
mAMC, m, m, m, mAM, m, m, m, m, m, m, m, mLTA, m, m, m,
mLBM, mLBM, mLBM, mLBM, mBLEM, m, m, m, m, m, m, m, m, m, m, m,
mAMC, m, m, m, mAM, m, m, m, m, m, m, m, mLTA, m, m, m,
/* 0x040 */
mLXA, m, m, m, m, mDAS, mDAA, m, m, m, m, m, mREC, m, m, mSEC,
mLYA, m, m, m, mIY, m, m, m, mAYY, m, m, m, m, m, m, m,
mLBA, m, m, m, mIB, m, m, m, m, m, m, m, m, m, m, m,
mLYA, m, m, m, mIY, m, m, m, mAYY, m, m, m, m, m, m, m,
mLBA, m, m, m, mIB, m, m, m, m, m, m, m, m, m, m, m,
mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI, mLAI,
/* 0x080 */
mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI, mAI,
mSED, m, m, m, mTD, m, m, m, m, m, m, m, m, m, m, m,
mSEIF1,mSECF, mSEIF0,m, mSEIE, mSETF, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mSED, m, m, m, mTD, m, m, m, m, m, m, m, m, m, m, m,
mSEIF1,mSECF, mSEIF0,m, mSEIE, mSETF, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0x0c0 */
mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, m, m, m, m, m, m, m, m,
mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, mLAR, m, m, m, m, m, m, m, m,
mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD, mSEDD,
mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, m, m, m, m, m, m, m, m,
mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, mLBR, m, m, m, m, m, m, m, m,
mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR, mXAMR,
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
/* 0x100 */
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mLMAIY,mLMAIY,m, m, mLMADY,mLMADY,m, m, mLAY, m, m, m, m, m, m, m,
mOR, m, m, m, mANEM, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mLMAIY,mLMAIY,m, m, mLMADY,mLMADY,m, m, mLAY, m, m, m, m, m, m, m,
mOR, m, m, m, mANEM, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0x140 */
mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI, mLXI,
mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI, mLYI,
mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI, mLBI,
mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI, mLTI,
/* 0x180 */
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mTIF1, mTI1, mTIF0, mTI0, m, mTTF, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mTIF1, mTI1, mTIF0, mTI0, m, mTTF, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0x1c0 */
mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR,
mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR, mBR,
@ -136,42 +136,42 @@ static const UINT8 hmcs40_mnemonic[0x400] =
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
/* 0x200 */
mTM, mTM, mTM, mTM, mREM, mREM, mREM, mREM, mXMA, mXMA, mXMA, mXMA, m, m, m, m,
mTM, mTM, mTM, mTM, mREM, mREM, mREM, mREM, mXMA, mXMA, mXMA, mXMA, m, m, m, m,
mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI, mMNEI,
mXMB, mXMB, mXMB, mXMB, mROTR, mROTL, m, m, m, m, m, m, m, m, m, m,
mSMC, m, m, m, mALEM, m, m, m, m, m, m, m, mLAT, m, m, m,
mXMB, mXMB, mXMB, mXMB, mROTR, mROTL, m, m, m, m, m, m, m, m, m, m,
mSMC, m, m, m, mALEM, m, m, m, m, m, m, m, mLAT, m, m, m,
/* 0x240 */
mLASPX,m, m, m, mNEGA, m, m, m, m, m, m, m, m, m, m, mTC,
mLASPY,m, m, m, mDY, m, m, m, mSYY, m, m, m, m, m, m, m,
mLAB, m, m, m, m, m, m, mDB, m, m, m, m, m, m, m, m,
mLASPY,m, m, m, mDY, m, m, m, mSYY, m, m, m, m, m, m, m,
mLAB, m, m, m, m, m, m, mDB, m, m, m, m, m, m, m, m,
mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI, mALEI,
/* 0x280 */
mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI, mYNEI,
mRED, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mREIF1,mRECF, mREIF0,m, mREIE, mRETF, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mRED, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mREIF1,mRECF, mREIF0,m, mREIE, mRETF, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0x2c0 */
mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, m, m, m, m, m, m, m, m,
mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, mLRA, m, m, m, m, m, m, m, m,
mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD, mREDD,
mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, mLRB, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
/* 0x300 */
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mCOMB, m, m, m, mBNEM, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
mCOMB, m, m, m, mBNEM, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0x340 */
mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU,
mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU, mLPU,
mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mTBR, mP, mP, mP, mP, mP, mP, mP, mP,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0x380 */
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, mRTNI, m, m, mRTN, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
m, m, m, m, mRTNI, m, m, mRTN, m, m, m, m, m, m, m, m,
m, m, m, m, m, m, m, m, m, m, m, m, m, m, m, m,
/* 0x3c0 */
mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL,
mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL, mCAL,
@ -188,7 +188,7 @@ CPU_DISASSEMBLE(hmcs40)
char *dst = buffer;
UINT8 instr = hmcs40_mnemonic[op];
INT8 bits = s_bits[instr];
// special case for (XY) opcode
if (bits == 99)
{
@ -202,12 +202,12 @@ CPU_DISASSEMBLE(hmcs40)
else
{
dst += sprintf(dst, "%-6s ", s_mnemonics[instr]);
// opcode parameter
if (bits != 0)
{
UINT8 param = op;
// reverse bits
if (bits < 0)
{
@ -215,16 +215,16 @@ CPU_DISASSEMBLE(hmcs40)
param >>= (8 + bits);
bits = -bits;
}
param &= ((1 << bits) - 1);
if (bits > 5)
dst += sprintf(dst, "$%02X", param);
else
dst += sprintf(dst, "%d", param);
}
}
int pos = s_next_pc[pc & 0x3f] & DASMFLAG_LENGTHMASK;
return pos | s_flags[instr] | DASMFLAG_SUPPORTED;
}

10
src/emu/cpu/hmcs40/hmcs40op.inc
View File

@ -73,19 +73,19 @@ void hmcs40_cpu_device::op_laspy()
void hmcs40_cpu_device::op_xamr()
{
// XAMR m: Exchange A and MR(m)
// determine MR(Memory Register) location
UINT8 address = m_op & 0xf;
// HMCS42: MR0 on file 0, MR4-MR15 on file 4 (there is no file 1-3)
// HMCS43: MR0-MR3 on file 0-3, MR4-MR15 on file 4
if (m_family == FAMILY_HMCS42 || m_family == FAMILY_HMCS43)
address |= (address < 4) ? (address << 4) : 0x40;
// HMCS44/45/46/47: all on last file
else
address |= 0xf0;
address &= m_datamask;
UINT8 old_a = m_a;
m_a = m_data->read_byte(address) & 0xf;
@ -657,7 +657,7 @@ void hmcs40_cpu_device::op_p()
m_icount--;
UINT16 address = m_a | m_b << 4 | m_c << 8 | (m_op & 7) << 9 | (m_pc & ~0x3f);
UINT16 o = m_program->read_word((address & m_prgmask) << 1);
// destination is determined by the 2 highest bits
if (o & 0x100)
{

2
src/emu/cpu/i386/i386ops.h
View File

@ -333,7 +333,7 @@ const i386_device::X86_OPCODE i386_device::s_x86_opcode_table[] =
{ 0x3B, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
{ 0x3C, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
{ 0x3D, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
{ 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false},
{ 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false},
{ 0x41, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovno_r16_rm16, &i386_device::pentium_cmovno_r32_rm32, false},
{ 0x42, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovb_r16_rm16, &i386_device::pentium_cmovb_r32_rm32, false},
{ 0x43, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovae_r16_rm16, &i386_device::pentium_cmovae_r32_rm32, false},

8
src/emu/cpu/i386/pentops.inc
View File

@ -1065,10 +1065,10 @@ void i386_device::pentium_movnti_m32_r32() // Opcode 0f c3
void i386_device::i386_cyrix_special() // Opcode 0x0f 3a-3d
{
/*
0f 3a BB0_RESET (set BB0 pointer = base)
0f 3b BB1_RESET (set BB1 pointer = base)
0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax)
0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx])
0f 3a BB0_RESET (set BB0 pointer = base)
0f 3b BB1_RESET (set BB1 pointer = base)
0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax)
0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx])
*/
CYCLES(1);

49
src/emu/cpu/nec/v53.c
View File

@ -237,9 +237,8 @@ void v53_base_device::install_peripheral_io()
if (m_SCTL & 0x02) // uPD71037 mode
{
if (IOAG) // 8-bit
if (IOAG) // 8-bit
{
}
else
{
@ -256,9 +255,8 @@ void v53_base_device::install_peripheral_io()
UINT16 base = (m_OPHA << 8) | m_IULA;
base &= 0xfffe;
if (IOAG) // 8-bit
if (IOAG) // 8-bit
{
}
else
{
@ -272,9 +270,8 @@ void v53_base_device::install_peripheral_io()
//printf("installing TCU to %04x\n", base);
base &= 0xfffe;
if (IOAG) // 8-bit
if (IOAG) // 8-bit
{
}
else
{
@ -290,9 +287,8 @@ void v53_base_device::install_peripheral_io()
UINT16 base = (m_OPHA << 8) | m_SULA;
base &= 0xfffe;
if (IOAG) // 8-bit
if (IOAG) // 8-bit
{
}
else
{
@ -333,9 +329,9 @@ WRITE8_MEMBER(v53_base_device::tmu_tct2_w) { m_v53tcu->write(space, 2, data); }
WRITE8_MEMBER(v53_base_device::tmu_tmd_w) { m_v53tcu->write(space, 3, data); }
READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); }
READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); }
READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); }
READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); }
READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); }
READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); }
@ -343,7 +339,7 @@ READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); }
/*** DMA ***/
// could be wrong / nonexistent
// could be wrong / nonexistent
WRITE_LINE_MEMBER(v53_base_device::dreq0_w)
{
if (!(m_SCTL & 0x02))
@ -409,20 +405,20 @@ WRITE_LINE_MEMBER(v53_base_device::hack_w)
static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register
AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA)
// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2
// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3
// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4
// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5
// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6
// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7
// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8
// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2
// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3
// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4
// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5
// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6
// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7
// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8
AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral)
AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control
AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control
AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control
AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control
// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee
// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef
// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee
// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef
AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks
AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc.
AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control
@ -430,7 +426,7 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control
AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control
AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control
// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7
// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7
AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping
AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping
AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping
@ -438,7 +434,7 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common)
AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling
AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping)
// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff
// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff
ADDRESS_MAP_END
@ -486,7 +482,7 @@ static MACHINE_CONFIG_FRAGMENT( v53 )
MCFG_PIT8253_OUT0_HANDLER(WRITELINE( v53_base_device, tcu_out0_trampoline_cb ))
MCFG_PIT8253_OUT1_HANDLER(WRITELINE( v53_base_device, tcu_out1_trampoline_cb ))
MCFG_PIT8253_OUT2_HANDLER(WRITELINE( v53_base_device, tcu_out2_trampoline_cb ))
MCFG_DEVICE_ADD("upd71071dma", V53_DMAU, 4000000)
MCFG_AM9517A_OUT_HREQ_CB(WRITELINE(v53_base_device, hreq_trampoline_cb))
@ -506,12 +502,12 @@ static MACHINE_CONFIG_FRAGMENT( v53 )
MCFG_AM9517A_OUT_DACK_2_CB(WRITELINE(v53_base_device, dma_dack2_trampoline_w))
MCFG_AM9517A_OUT_DACK_3_CB(WRITELINE(v53_base_device, dma_dack3_trampoline_w))
MCFG_PIC8259_ADD( "upd71059pic", WRITELINE(v53_base_device, internal_irq_w), VCC, READ8(v53_base_device,get_pic_ack))
MCFG_DEVICE_ADD("v53scu", V53_SCU, 0)
MCFG_DEVICE_ADD("v53scu", V53_SCU, 0)
MCFG_I8251_TXD_HANDLER(WRITELINE(v53_base_device, scu_txd_trampoline_cb))
MCFG_I8251_DTR_HANDLER(WRITELINE(v53_base_device, scu_dtr_trampoline_cb))
MCFG_I8251_RTS_HANDLER(WRITELINE(v53_base_device, scu_rts_trampoline_cb))
@ -578,4 +574,3 @@ v53a_device::v53a_device(const machine_config &mconfig, const char *tag, device_
: v53_base_device(mconfig, V53A, "V53A", tag, owner, clock, "v53a", BYTE_XOR_LE(0), 6, 1, V33_TYPE)
{
}

32
src/emu/cpu/nec/v53.h
View File

@ -131,7 +131,7 @@ public:
UINT8 m_SCTL;
UINT8 m_OPSEL;
UINT8 m_SULA;
UINT8 m_TULA;
UINT8 m_IULA;
@ -151,10 +151,10 @@ public:
template<class _Object> static devcb_base &set_syndet_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_syndet_handler.set_callback(object); }
DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); }
// TCU
@ -165,9 +165,9 @@ public:
DECLARE_READ8_MEMBER(tmu_tst2_r);
DECLARE_WRITE8_MEMBER(tmu_tct2_w);
DECLARE_WRITE8_MEMBER(tmu_tmd_w);
// static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; }
// static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; }
// static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; }
// static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; }
// static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; }
// static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; }
template<class _Object> static devcb_base &set_out0_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out0_handler.set_callback(object); }
template<class _Object> static devcb_base &set_out1_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out1_handler.set_callback(object); }
template<class _Object> static devcb_base &set_out2_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out2_handler.set_callback(object); }
@ -195,7 +195,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(hreq_trampoline_cb) { m_out_hreq_cb(state); }
DECLARE_WRITE_LINE_MEMBER(eop_trampoline_cb) { m_out_eop_cb(state); }
DECLARE_READ8_MEMBER(dma_memr_trampoline_r) { return m_in_memr_cb(space, offset); }
DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); }
DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); }
DECLARE_READ8_MEMBER(dma_io_0_trampoline_r) { return m_in_ior_0_cb(space, offset); }
DECLARE_READ8_MEMBER(dma_io_1_trampoline_r) { return m_in_ior_1_cb(space, offset); }
DECLARE_READ8_MEMBER(dma_io_2_trampoline_r) { return m_in_ior_2_cb(space, offset); }
@ -204,10 +204,10 @@ public:
DECLARE_WRITE8_MEMBER(dma_io_1_trampoline_w) { m_out_iow_1_cb(space, offset, data); }
DECLARE_WRITE8_MEMBER(dma_io_2_trampoline_w) { m_out_iow_2_cb(space, offset, data); }
DECLARE_WRITE8_MEMBER(dma_io_3_trampoline_w) { m_out_iow_3_cb(space, offset, data); }
DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dreq0_w);
@ -221,7 +221,7 @@ public:
void install_peripheral_io();
const address_space_config m_io_space_config;
const address_space_config *memory_space_config(address_spacenum spacenum) const
{
switch (spacenum)
@ -260,9 +260,9 @@ protected:
devcb_write_line m_syndet_handler;
// TCU
// double m_clk0;
// double m_clk1;
// double m_clk2;
// double m_clk0;
// double m_clk1;
// double m_clk2;
devcb_write_line m_out0_handler;
devcb_write_line m_out1_handler;
devcb_write_line m_out2_handler;
@ -285,7 +285,7 @@ protected:
devcb_write_line m_out_dack_1_cb;
devcb_write_line m_out_dack_2_cb;
devcb_write_line m_out_dack_3_cb;
};

2
src/emu/cpu/pic16c5x/pic16c5x.c
View File

@ -799,7 +799,7 @@ void pic16c5x_device::device_start()
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
m_data = &space(AS_DATA);
m_read_a.resolve_safe(0);
m_read_b.resolve_safe(0);
m_read_c.resolve_safe(0);

4
src/emu/cpu/pic16c5x/pic16c5x.h
View File

@ -81,7 +81,7 @@ public:
* the value if known (available in HEX dumps of the ROM).
*/
void pic16c5x_set_config(UINT16 data);
// or with a macro
static void set_config_static(device_t &device, UINT16 data) { downcast<pic16c5x_device &>(device).m_temp_config = data; }
@ -155,7 +155,7 @@ private:
address_space *m_program;
direct_read_data *m_direct;
address_space *m_data;
// i/o handlers
devcb_read8 m_read_a;
devcb_read8 m_read_b;

12
src/emu/cpu/z80/kl5c80a12.c
View File

@ -1,13 +1,13 @@
/***************************************************************************
Kawasaki LSI
KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Kawasaki LSI
KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
(is this different enough to need it's own core?)
(todo: everything, some code currently lives in machine/hng64_net.c but not much)
(is this different enough to need it's own core?)
(todo: everything, some code currently lives in machine/hng64_net.c but not much)
***************************************************************************/

12
src/emu/cpu/z80/kl5c80a12.h
View File

@ -1,13 +1,13 @@
/***************************************************************************
Kawasaki LSI
KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Kawasaki LSI
KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
(is this different enough to need it's own core?)
(todo: everything, some code currently lives in machine/hng64_net.c but not much)
(is this different enough to need it's own core?)
(todo: everything, some code currently lives in machine/hng64_net.c but not much)
***************************************************************************/

40
src/emu/machine/am9517a.c
View File

@ -3,15 +3,15 @@
/***************************************************************************
AMD AM9517A
Intel 8237A
NEC uPD71037
Intel 8237A
NEC uPD71037
NEC uPD71071 (extended version of above)
NEC uPD71071 (extended version of above)
a variant is used in the V53 CPU which offers subsets of both the
uPD71071 and uPD71037 functionality depending on a mode bit.
Multimode DMA Controller emulation
a variant is used in the V53 CPU which offers subsets of both the
uPD71071 and uPD71037 functionality depending on a mode bit.
Multimode DMA Controller emulation
Copyright the MESS Team.
Visit http://mamedev.org for licensing and usage restrictions.
@ -28,17 +28,17 @@
/*
When the V53 operates in uPD71071 compatible mode there are the following
differences from a real uPD71071
When the V53 operates in uPD71071 compatible mode there are the following
differences from a real uPD71071
V53 Real uPD71071
Software Reqs No Yes
Memory-to-Memory DMA No Yes
DMARQ active level High programmable
DMAAK active level Low programmable
Bus Cycle 4 4 or 3
V53 Real uPD71071
Software Reqs No Yes
Memory-to-Memory DMA No Yes
DMARQ active level High programmable
DMAAK active level Low programmable
Bus Cycle 4 4 or 3
we don't currently handle the differences
we don't currently handle the differences
*/
@ -1158,7 +1158,7 @@ READ8_MEMBER(upd71071_v53_device::read)
ret = m_command & 0xff;
break;
case 0x09: // Device control (high) // UPD71071 only?
ret = m_command_high & 0xff;
ret = m_command_high & 0xff;
break;
case 0x0b: // Status
ret = m_status;
@ -1187,14 +1187,14 @@ READ8_MEMBER(upd71071_v53_device::read)
WRITE8_MEMBER(upd71071_v53_device::write)
{
int channel = m_selected_channel;
switch (offset)
{
case 0x00: // Initialise
// TODO: reset (bit 0)
//m_buswidth = data & 0x02;
//if (data & 0x01)
// soft_reset();
// soft_reset();
logerror("DMA: Initialise [%02x]\n", data);
break;
case 0x01: // Channel
@ -1279,4 +1279,4 @@ WRITE8_MEMBER(upd71071_v53_device::write)
}
trigger(1);
}
}

2
src/emu/machine/am9517a.h
View File

@ -172,7 +172,7 @@ protected:
virtual void device_start();
virtual void device_reset();
int m_selected_channel;
int m_selected_channel;
int m_base;
UINT8 m_command_high;

132
src/emu/machine/i8251.c
View File

@ -3,10 +3,10 @@
i8251.c
Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter code
NEC uPD71051 is a clone
NEC uPD71051 is a clone
The V53/V53A use a customized version with only the Asynchronous mode
and a split command / mode register
The V53/V53A use a customized version with only the Asynchronous mode
and a split command / mode register
@ -428,29 +428,29 @@ WRITE8_MEMBER(i8251_device::command_w)
/* bit 7:
0 = normal operation
1 = hunt mode
bit 6:
0 = normal operation
1 = internal reset
bit 5:
0 = /RTS set to 1
1 = /RTS set to 0
bit 4:
0 = normal operation
1 = reset error flag
bit 3:
0 = normal operation
1 = send break character
bit 2:
0 = receive disable
1 = receive enable
bit 1:
0 = /DTR set to 1
1 = /DTR set to 0
bit 0:
0 = transmit disable
1 = transmit enable
0 = normal operation
1 = hunt mode
bit 6:
0 = normal operation
1 = internal reset
bit 5:
0 = /RTS set to 1
1 = /RTS set to 0
bit 4:
0 = normal operation
1 = reset error flag
bit 3:
0 = normal operation
1 = send break character
bit 2:
0 = receive disable
1 = receive enable
bit 1:
0 = /DTR set to 1
1 = /DTR set to 0
bit 0:
0 = transmit disable
1 = transmit enable
*/
m_rts_handler(!BIT(data, 5));
@ -484,28 +484,28 @@ WRITE8_MEMBER(i8251_device::mode_w)
{
/* Asynchronous
bit 7,6: stop bit length
0 = inhibit
1 = 1 bit
2 = 1.5 bits
3 = 2 bits
bit 5: parity type
0 = parity odd
1 = parity even
bit 4: parity test enable
0 = disable
1 = enable
bit 3,2: character length
0 = 5 bits
1 = 6 bits
2 = 7 bits
3 = 8 bits
bit 1,0: baud rate factor
0 = defines command byte for synchronous or asynchronous
1 = x1
2 = x16
3 = x64
*/
bit 7,6: stop bit length
0 = inhibit
1 = 1 bit
2 = 1.5 bits
3 = 2 bits
bit 5: parity type
0 = parity odd
1 = parity even
bit 4: parity test enable
0 = disable
1 = enable
bit 3,2: character length
0 = 5 bits
1 = 6 bits
2 = 7 bits
3 = 8 bits
bit 1,0: baud rate factor
0 = defines command byte for synchronous or asynchronous
1 = x1
2 = x16
3 = x64
*/
LOG(("I8251: Asynchronous operation\n"));
@ -597,24 +597,24 @@ WRITE8_MEMBER(i8251_device::mode_w)
else
{
/* bit 7: Number of sync characters
0 = 1 character
1 = 2 character
bit 6: Synchronous mode
0 = Internal synchronisation
1 = External synchronisation
bit 5: parity type
0 = parity odd
1 = parity even
bit 4: parity test enable
0 = disable
1 = enable
bit 3,2: character length
0 = 5 bits
1 = 6 bits
2 = 7 bits
3 = 8 bits
bit 1,0 = 0
*/
0 = 1 character
1 = 2 character
bit 6: Synchronous mode
0 = Internal synchronisation
1 = External synchronisation
bit 5: parity type
0 = parity odd
1 = parity even
bit 4: parity test enable
0 = disable
1 = enable
bit 3,2: character length
0 = 5 bits
1 = 6 bits
2 = 7 bits
3 = 8 bits
bit 1,0 = 0
*/
LOG(("I8251: Synchronous operation\n"));
/* setup for sync byte(s) */

2
src/emu/machine/i8257.c
View File

@ -79,7 +79,7 @@ inline void i8257_device::dma_request(int channel, int state)
}
else
{
m_request &= ~(1 << channel);
m_request &= ~(1 << channel);
}
trigger(1);
}

2
src/emu/machine/mcf5206e.c
View File

@ -860,7 +860,7 @@ void mcf5206e_peripheral_device::device_start()
init_regs(true);
m_timer1 = machine().scheduler().timer_alloc( timer_expired_delegate( FUNC( mcf5206e_peripheral_device::timer1_callback ), this) );
save_item(NAME(m_ICR));
save_item(NAME(m_CSAR));
save_item(NAME(m_CSMR));

2
src/emu/machine/tmp68301.c
View File

@ -123,7 +123,7 @@ void tmp68301_device::device_start()
m_in_parallel_cb.resolve_safe(0);
m_out_parallel_cb.resolve_safe();
save_item(NAME(m_regs));
save_item(NAME(m_IE));
save_item(NAME(m_irq_vector));

10
src/emu/machine/upd71071.c
View File

@ -1,7 +1,7 @@
/*
am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it
am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it
NEC uPD71071 DMA Controller
Used on the Fujitsu FM-Towns
@ -31,8 +31,8 @@
Self-explanatory, I hope. :)
NOTE: Datasheet clearly shows this as 24-bit, with register 7 unused.
But the FM-Towns definitely uses reg 7 as bits 24-31.
The documentation on the V53A manual doesn't show these bits either, maybe it's
an external connection on the FMT? might be worth checking overflow behavior etc.
The documentation on the V53A manual doesn't show these bits either, maybe it's
an external connection on the FMT? might be worth checking overflow behavior etc.
0x08:
0x09: Device Control register (16-bit)
@ -77,8 +77,8 @@
0x0f: Mask register
bit 0-3: DMARQ mask
bits 1 and 0 only in MTM transfers
Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways
Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways

9
src/emu/machine/vrc4373.c
View File

@ -111,7 +111,7 @@ void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_
if (LOG_NILE)
logerror("%s: map_extra Master Window 2 start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci2_laddr);
}
// PCI IO Window
// PCI IO Window
if (m_cpu_regs[NREG_PCIMIOW]&0x1000) {
winStart = m_cpu_regs[NREG_PCIMIOW]&0xff000000;
winEnd = winStart | (~(0x80000000 | (((m_cpu_regs[NREG_PCIMIOW]>>13)&0x7f)<<24)));
@ -122,7 +122,7 @@ void vrc4373_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_
logerror("%s: map_extra IO Window start=%08X end=%08X size=%08X laddr=%08X\n", tag(), winStart, winEnd, winSize, m_pci_io_laddr);
}
// PCI Target Window 1
if (m_cpu_regs[NREG_PCITW1]&0x1000) {
if (m_cpu_regs[NREG_PCITW1]&0x1000) {
winStart = m_cpu_regs[NREG_PCITW1]&0xffe00000;
winEnd = winStart | (~(0xf0000000 | (((m_cpu_regs[NREG_PCITW1]>>13)&0x7f)<<21)));
winSize = winEnd - winStart + 1;
@ -242,7 +242,7 @@ WRITE32_MEMBER (vrc4373_device::target2_w)
logerror("%06X:nile target2 write to offset %02X = %08X & %08X\n", space.device().safe_pc(), offset*4, data, mem_mask);
}
// CPU I/F
// CPU I/F
READ32_MEMBER (vrc4373_device::cpu_if_r)
{
UINT32 result = m_cpu_regs[offset];
@ -290,7 +290,7 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
case NREG_PCICAR:
// Bits in reserved area are used for device selection of type 0 config transactions
// Assuming 23:11 get mapped into device number for configuration
if ((data&0x3) == 0x0) {
if ((data&0x3) == 0x0) {
// Type 0 transaction
modData = 0;
// Select the device based on one hot bit
@ -341,4 +341,3 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
}
}

16
src/emu/machine/vrc4373.h
View File

@ -10,13 +10,13 @@
downcast<vrc4373_device *>(device)->set_cpu_tag(_cpu_tag);
#define VRC4373_PAGESHIFT 12
/* NILE 3 registers 0x000-0x0ff */
#define NREG_BMCR (0x000/4)
#define NREG_SIMM1 (0x004/4)
#define NREG_SIMM2 (0x008/4)
#define NREG_SIMM3 (0x00C/4)
#define NREG_SIMM4 (0x010/4)
#define NREG_BMCR (0x000/4)
#define NREG_SIMM1 (0x004/4)
#define NREG_SIMM2 (0x008/4)
#define NREG_SIMM3 (0x00C/4)
#define NREG_SIMM4 (0x010/4)
#define NREG_PCIMW1 (0x014/4)
#define NREG_PCIMW2 (0x018/4)
#define NREG_PCITW1 (0x01C/4)
@ -57,7 +57,7 @@ public:
void set_cpu_tag(const char *tag);
virtual DECLARE_ADDRESS_MAP(config_map, 32);
DECLARE_READ32_MEMBER( pcictrl_r);
DECLARE_WRITE32_MEMBER( pcictrl_w);
//cpu bus registers
@ -76,7 +76,7 @@ public:
virtual DECLARE_ADDRESS_MAP(target1_map, 32);
DECLARE_READ32_MEMBER (target1_r);
DECLARE_WRITE32_MEMBER(target1_w);
virtual DECLARE_ADDRESS_MAP(target2_map, 32);
DECLARE_READ32_MEMBER (target2_r);
DECLARE_WRITE32_MEMBER(target2_w);

4
src/emu/mame.c
View File

@ -286,11 +286,11 @@ void CLIB_DECL popmessage(const char *format, ...)
// pop it in the UI
machine_manager::instance()->machine()->ui().popup_time(temp.len() / 40 + 2, "%s", temp.cstr());
/*
// also write to error.log
logerror("popmessage: %s\n", temp.cstr());
#ifdef MAME_DEBUG
// and to command-line in a DEBUG build
osd_printf_info("popmessage: %s\n", temp.cstr());

6
src/emu/render.c
View File

@ -2494,13 +2494,13 @@ float render_manager::ui_aspect(render_container *rc)
orient = orientation_add(m_ui_target->orientation(), m_ui_container->orientation());
// based on the orientation of the target, compute height/width or width/height
if (!(orient & ORIENTATION_SWAP_XY))
aspect = (float)m_ui_target->height() / (float)m_ui_target->width();
aspect = (float)m_ui_target->height() / (float)m_ui_target->width();
else
aspect = (float)m_ui_target->width() / (float)m_ui_target->height();
aspect = (float)m_ui_target->width() / (float)m_ui_target->height();
// if we have a valid pixel aspect, apply that and return
if (m_ui_target->pixel_aspect() != 0.0f)
return (aspect / m_ui_target->pixel_aspect());
return (aspect / m_ui_target->pixel_aspect());
} else {
// single screen container

40
src/emu/sound/es1373.h
View File

@ -9,26 +9,26 @@
MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371)
/* Ensonic ES1373 registers 0x00-0x3f */
#define ES_INT_CS_CTRL (0x00/4)
#define ES_INT_CS_STATUS (0x04/4)
#define ES_UART_DATA (0x08/4)
#define ES_UART_STATUS (0x09/4)
#define ES_UART_CTRL (0x09/4)
#define ES_UART_RSVD (0x0A/4)
#define ES_MEM_PAGE (0x0C/4)
#define ES_SRC_IF (0x10/4)
#define ES_CODEC (0x14/4)
#define ES_LEGACY (0x18/4)
#define ES_CHAN_CTRL (0x1C/4)
#define ES_SERIAL_CTRL (0x20/4)
#define ES_DAC1_CNT (0x24/4)
#define ES_DAC2_CNT (0x28/4)
#define ES_ADC_CNT (0x2C/4)
#define ES_ADC_CNT (0x2C/4)
#define ES_HOST_IF0 (0x30/4)
#define ES_HOST_IF1 (0x34/4)
#define ES_HOST_IF2 (0x38/4)
#define ES_HOST_IF3 (0x3C/4)
#define ES_INT_CS_CTRL (0x00/4)
#define ES_INT_CS_STATUS (0x04/4)
#define ES_UART_DATA (0x08/4)
#define ES_UART_STATUS (0x09/4)
#define ES_UART_CTRL (0x09/4)
#define ES_UART_RSVD (0x0A/4)
#define ES_MEM_PAGE (0x0C/4)
#define ES_SRC_IF (0x10/4)
#define ES_CODEC (0x14/4)
#define ES_LEGACY (0x18/4)
#define ES_CHAN_CTRL (0x1C/4)
#define ES_SERIAL_CTRL (0x20/4)
#define ES_DAC1_CNT (0x24/4)
#define ES_DAC2_CNT (0x28/4)
#define ES_ADC_CNT (0x2C/4)
#define ES_ADC_CNT (0x2C/4)
#define ES_HOST_IF0 (0x30/4)
#define ES_HOST_IF1 (0x34/4)
#define ES_HOST_IF2 (0x38/4)
#define ES_HOST_IF3 (0x3C/4)
struct frame_reg {
UINT32 pci_addr;

2
src/emu/sound/flt_rc.c
View File

@ -37,7 +37,7 @@ void filter_rc_device::device_start()
{
m_stream = stream_alloc(1, 1, machine().sample_rate());
recalc();
save_item(NAME(m_k));
save_item(NAME(m_memory));
save_item(NAME(m_type));

4
src/emu/sound/okim9810.c
View File

@ -115,11 +115,11 @@ void okim9810_device::device_start()
save_item(NAME(m_global_volume));
save_item(NAME(m_filter_type));
save_item(NAME(m_output_level));
for (int i = 0; i < OKIM9810_VOICES; i++)
{
okim_voice *voice = get_voice(i);
save_item(NAME(voice->m_adpcm.m_signal), i);
save_item(NAME(voice->m_adpcm.m_step), i);
save_item(NAME(voice->m_adpcm2.m_signal), i);

2
src/emu/sound/okim9810.h
View File

@ -135,7 +135,7 @@ protected:
};
okim_voice *get_voice(int which);
// internal state
const address_space_config m_space_config;

2
src/emu/video.c
View File

@ -153,7 +153,7 @@ video_manager::video_manager(running_machine &machine)
filename = machine.options().avi_write();
if (filename[0] != 0)
begin_recording(filename, MF_AVI);
#ifdef MAME_DEBUG
m_dummy_recording = machine.options().dummy_write();
#endif

4
src/emu/video.h
View File

@ -176,9 +176,9 @@ private:
attotime m_avi_frame_period; // period of a single movie frame
attotime m_avi_next_frame_time; // time of next frame
UINT32 m_avi_frame; // current movie frame number
// movie recording - dummy
bool m_dummy_recording; // indicates if snapshot should be created of every frame
bool m_dummy_recording; // indicates if snapshot should be created of every frame
static const UINT8 s_skiptable[FRAMESKIP_LEVELS][FRAMESKIP_LEVELS];

4
src/emu/video/tms34061.c
View File

@ -60,7 +60,7 @@ void tms34061_device::device_start()
/* allocate memory for VRAM */
m_vram = auto_alloc_array_clear(machine(), UINT8, m_vramsize + 256 * 2);
/* allocate memory for latch RAM */
m_latchram = auto_alloc_array_clear(machine(), UINT8, m_vramsize + 256 * 2);
@ -93,7 +93,7 @@ void tms34061_device::device_start()
/* start vertical interrupt timer */
m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(tms34061_device::interrupt), this));
save_item(NAME(m_regs));
save_item(NAME(m_xmask));
save_item(NAME(m_yshift));

2
src/emu/video/voodoo_pci.c
View File

@ -56,7 +56,7 @@ void voodoo_pci_device::map_extra(UINT64 memory_window_start, UINT64 memory_wind
return;
if(UINT32(bi.adr) == UINT32(~(bi.size - 1)))
return;
UINT64 start;
address_space *space;
if(bi.flags & M_IO) {

4
src/lib/formats/d88_dsk.c
View File

@ -27,8 +27,8 @@
*
*/
#include <assert.h>
#include <assert.h>
#include "flopimg.h"
#include "imageutl.h"

2
src/lib/formats/flex_dsk.c
View File

@ -4,7 +4,7 @@
* Created on: 24/06/2014
*/
#include "emu.h" // logerror
#include "emu.h" // logerror
#include "flex_dsk.h"
flex_format::flex_format()

4
src/lib/formats/fmtowns_dsk.c
View File

@ -6,8 +6,8 @@
* Created on: 23/03/2014
*/
#include <assert.h>
#include <assert.h>
#include "formats/fmtowns_dsk.h"
fmtowns_format::fmtowns_format() : wd177x_format(formats)

4
src/lib/formats/nfd_dsk.c
View File

@ -77,8 +77,8 @@
*********************************************************************/
#include <assert.h>
#include <assert.h>
#include "nfd_dsk.h"
nfd_format::nfd_format()

24
src/mame/audio/hng64.c
View File

@ -191,12 +191,12 @@ ADDRESS_MAP_END
WRITE16_MEMBER(hng64_state::hng64_sound_port_0008_w)
{
// logerror("hng64_sound_port_0008_w %04x %04x\n", data, mem_mask);
// logerror("hng64_sound_port_0008_w %04x %04x\n", data, mem_mask);
// seems to one or more of the DMARQ on the V53, writes here when it expects DMA channel 3 to transfer ~0x20 bytes just after startup
m_audiocpu->dreq3_w(data&1);
// m_audiocpu->hack_w(1);
// m_audiocpu->hack_w(1);
}
@ -262,23 +262,23 @@ WRITE16_MEMBER(hng64_state::hng64_sound_data_02_w)
{
m_audiodat[m_audiochannel].dat[2] = data;
// if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0002 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
// if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0002 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
}
WRITE16_MEMBER(hng64_state::hng64_sound_data_04_w)
{
m_audiodat[m_audiochannel].dat[1] = data;
// if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0004 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
// if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0004 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
}
WRITE16_MEMBER(hng64_state::hng64_sound_data_06_w)
{
m_audiodat[m_audiochannel].dat[0] = data;
// if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0006 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
// if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0006 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
}
// but why not just use the V33/V53 XA mode??
@ -414,18 +414,18 @@ WRITE_LINE_MEMBER(hng64_state::tcu_tm0_cb)
WRITE_LINE_MEMBER(hng64_state::tcu_tm1_cb)
{
// these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1
// logerror("tcu_tm1_cb %02x\n", state);
// logerror("tcu_tm1_cb %02x\n", state);
m_audiocpu->set_input_line(5, state? ASSERT_LINE:CLEAR_LINE); // not accurate, just so we have a trigger
}
WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb)
{
// these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1
// logerror("tcu_tm2_cb %02x\n", state);
// logerror("tcu_tm2_cb %02x\n", state);
// NOT ACCURATE, just so that all the interrupts get triggered for now.
static int i = 0;
m_audiocpu->set_input_line(i, state? ASSERT_LINE:CLEAR_LINE);
m_audiocpu->set_input_line(i, state? ASSERT_LINE:CLEAR_LINE);
i++;
if (i == 3) i = 0;
}
@ -445,5 +445,3 @@ MACHINE_CONFIG_FRAGMENT( hng64_audio )
MCFG_V53_TCU_OUT2_HANDLER(WRITELINE(hng64_state, tcu_tm2_cb))
MACHINE_CONFIG_END

6
src/mame/drivers/argus.c
View File

@ -548,7 +548,7 @@ static MACHINE_CONFIG_START( argus, argus_state )
MCFG_GFXDECODE_ADD("gfxdecode", "palette", argus)
MCFG_PALETTE_ADD("palette", 896)
MCFG_DEVICE_ADD("blend", JALECO_BLEND, 0)
MCFG_VIDEO_START_OVERRIDE(argus_state,argus)
@ -594,7 +594,7 @@ static MACHINE_CONFIG_START( valtric, argus_state )
MCFG_GFXDECODE_ADD("gfxdecode", "palette", valtric)
MCFG_PALETTE_ADD("palette", 768)
MCFG_DEVICE_ADD("blend", JALECO_BLEND, 0)
MCFG_VIDEO_START_OVERRIDE(argus_state,valtric)
@ -640,7 +640,7 @@ static MACHINE_CONFIG_START( butasan, argus_state )
MCFG_GFXDECODE_ADD("gfxdecode", "palette", butasan)
MCFG_PALETTE_ADD("palette", 768)
MCFG_DEVICE_ADD("blend", JALECO_BLEND, 0)
MCFG_VIDEO_START_OVERRIDE(argus_state,butasan)

156
src/mame/drivers/astrcorp.c
View File

@ -1159,130 +1159,130 @@ DRIVER_INIT_MEMBER(astrocorp_state,astoneag)
for (i = 0x25100/2; i < 0x25200/2; i++)
{
x = 0x0000;
if ( (i & 0x0001) ) x |= 0x0200;
if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0080;
if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0020) || (i & 0x0001) ) x |= 0x0010;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0004;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0001;
if ( (i & 0x0001) ) x |= 0x0200;
if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0080;
if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0020) || (i & 0x0001) ) x |= 0x0010;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0004;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0001;
rom[i] ^= x;
}
/*
for (i = 0x25300/2; i < 0x25400/2; i++)
{
x = 0x1300;
rom[i] ^= x;
}
for (i = 0x25300/2; i < 0x25400/2; i++)
{
x = 0x1300;
rom[i] ^= x;
}
*/
for (i = 0x25400/2; i < 0x25500/2; i++)
{
x = 0x4200;
if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x;
}
for (i = 0x25500/2; i < 0x25600/2; i++)
{
x = 0x4200;
if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0080;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0040;
if ( !(i & 0x0002) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0010;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0001) ) x |= 0x0001;
if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0080;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0040;
if ( !(i & 0x0002) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0010;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x;
}
/*
for (i = 0x25700/2; i < 0x25800/2; i++)
{
x = 0x6800;
if ( !(i & 0x0001) ) x |= 0x8000;
for (i = 0x25700/2; i < 0x25800/2; i++)
{
x = 0x6800;
if ( !(i & 0x0001) ) x |= 0x8000;
if ( !(i & 0x0040) || ((i & 0x0001) || !(i & 0x0001)) ) x |= 0x0100;
if ( !(i & 0x0040) || ((i & 0x0001) || !(i & 0x0001)) ) x |= 0x0100;
rom[i] ^= x;
}
rom[i] ^= x;
}
*/
for (i = 0x25800/2; i < 0x25900/2; i++)
{
x = 0x8300;
if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x2000;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0001;
if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x2000;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0001;
rom[i] ^= x;
}
// for (i = 0x25900/2; i < 0x25a00/2; i++)
// for (i = 0x25900/2; i < 0x25a00/2; i++)
for (i = 0x25c00/2; i < 0x25d00/2; i++)
{
// changed from 25400
// x = 0x4200;
// x = 0x4200;
x = 0x4000;
// if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
// if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x;
}
/*
for (i = 0x25d00/2; i < 0x25e00/2; i++)
{
x = 0x4000;
if ( !(i & 0x0040) ) x |= 0x0800;
for (i = 0x25d00/2; i < 0x25e00/2; i++)
{
x = 0x4000;
if ( !(i & 0x0040) ) x |= 0x0800;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0100; // almost!!
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0100; // almost!!
if ( ((i & 0x0040)&&((i & 0x0020)||(i & 0x0010))) || !(i & 0x0001) ) x |= 0x0200; // almost!!
if ( (!(i & 0x0040) || !(i & 0x0008)) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0040) || !(i & 0x0020) || (i & 0x0001) ) x |= 0x0001; // almost!!
rom[i] ^= x;
}
if ( ((i & 0x0040)&&((i & 0x0020)||(i & 0x0010))) || !(i & 0x0001) ) x |= 0x0200; // almost!!
if ( (!(i & 0x0040) || !(i & 0x0008)) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0040) || !(i & 0x0020) || (i & 0x0001) ) x |= 0x0001; // almost!!
rom[i] ^= x;
}
*/
/*
for (i = 0x25e00/2; i < 0x25f00/2; i++)
{
x = 0xa600;
for (i = 0x25e00/2; i < 0x25f00/2; i++)
{
x = 0xa600;
if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x4000;
if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x0800;
if ( !(i & 0x0001) ) x |= 0x0100;
if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x4000;
if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x0800;
if ( !(i & 0x0001) ) x |= 0x0100;
if ( ( (i & 0x0040) && (i & 0x0008) && !(i & 0x0001)) ||
( !(i & 0x0040) && ((i & 0x0004) ^ (i & 0x0002)) && !(i & 0x0001) ) ) x |= 0x0002; // almost!!
if ( ( (i & 0x0040) && (i & 0x0008) && !(i & 0x0001)) ||
( !(i & 0x0040) && ((i & 0x0004) ^ (i & 0x0002)) && !(i & 0x0001) ) ) x |= 0x0002; // almost!!
if ( !(i & 0x0040) || !(i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x;
}
if ( !(i & 0x0040) || !(i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x;
}
*/
for (i = 0x26f00/2; i < 0x27000/2; i++)

2
src/mame/drivers/cabal.c
View File

@ -475,7 +475,7 @@ static MACHINE_CONFIG_START( cabal, cabal_state )
MCFG_CPU_ADD("audiocpu", Z80, XTAL_3_579545MHz) /* verified on pcb */
MCFG_CPU_PROGRAM_MAP(sound_map)
MCFG_MACHINE_START_OVERRIDE(cabal_state,cabal)
/* video hardware */

2
src/mame/drivers/capbowl.c
View File

@ -293,7 +293,7 @@ INPUT_PORTS_END
void capbowl_state::machine_start()
{
m_update_timer = timer_alloc(TIMER_UPDATE);
save_item(NAME(m_blitter_addr));
save_item(NAME(m_last_trackball_val));
}

10
src/mame/drivers/cocoloco.c
View File

@ -192,21 +192,21 @@ public:
required_device<cpu_device> m_maincpu;
required_device<palette_device> m_palette;
UINT8 *m_videoram;
UINT8 m_videobank;
DECLARE_READ8_MEMBER(vram_r);
DECLARE_WRITE8_MEMBER(vram_w);
DECLARE_WRITE8_MEMBER(vbank_w);
DECLARE_WRITE8_MEMBER(vram_clear_w);
DECLARE_WRITE8_MEMBER(coincounter_w);
DECLARE_INPUT_CHANGED_MEMBER(coin_inserted);
virtual void video_start();
DECLARE_PALETTE_INIT(cocoloco);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};

18
src/mame/drivers/dynax.c
View File

@ -1564,14 +1564,14 @@ static ADDRESS_MAP_START( cdracula_io_map, AS_IO, 8, dynax_state )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE( 0x01, 0x07 ) AM_WRITE(cdracula_blitter_rev2_w) // Blitter + Destination Layers
AM_RANGE( 0x10, 0x10 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
AM_RANGE( 0x11, 0x11 ) AM_NOP // unpopulated oki
AM_RANGE( 0x11, 0x11 ) AM_NOP // unpopulated oki
// AM_RANGE( 0x12, 0x12 ) AM_WRITENOP // CRT Controller
// AM_RANGE( 0x13, 0x13 ) AM_WRITENOP // CRT Controller
AM_RANGE( 0x20, 0x20 ) AM_READ_PORT("P1") // P1
AM_RANGE( 0x21, 0x21 ) AM_READ_PORT("P2") // P2
AM_RANGE( 0x22, 0x22 ) AM_READ_PORT("COINS") // Coins
AM_RANGE( 0x30, 0x30 ) AM_WRITE(dynax_layer_enable_w) // Layers Enable
// AM_RANGE( 0x31, 0x31 ) AM_WRITE(dynax_rombank_w) // BANK ROM Select
// AM_RANGE( 0x31, 0x31 ) AM_WRITE(dynax_rombank_w) // BANK ROM Select
AM_RANGE( 0x32, 0x32 ) AM_WRITE(dynax_blit_pen_w) // Destination Pen
AM_RANGE( 0x33, 0x33 ) AM_WRITE(dynax_blit_flags_w) // Flags + Do Blit
AM_RANGE( 0x34, 0x34 ) AM_WRITE(dynax_blit_palette01_w) // Layers Palettes (Low Bits)
@ -2042,7 +2042,7 @@ static INPUT_PORTS_START( cdracula )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("DSW1") // port $61 -> c217
PORT_START("DSW1") // port $61 -> c217
PORT_DIPNAME( 0x03, 0x02, DEF_STR( Difficulty ) ) PORT_DIPLOCATION( "SW1:1,2" )
PORT_DIPSETTING( 0x03, DEF_STR( Easy ) ) // 44
PORT_DIPSETTING( 0x02, DEF_STR( Normal ) ) // 47
@ -2062,9 +2062,9 @@ static INPUT_PORTS_START( cdracula )
PORT_DIPNAME( 0x40, 0x40, "Unknown 1-7" ) PORT_DIPLOCATION( "SW1:7" )
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION( "SW1:8" )
PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION( "SW1:8" )
PORT_START("DSW2") // port $60 -> c216
PORT_START("DSW2") // port $60 -> c216
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION( "SW2:1,2" )
PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
@ -3190,7 +3190,7 @@ static INPUT_PORTS_START( jantouki )
PORT_DIPSETTING( 0x00, "12:00" )
PORT_DIPNAME( 0x08, 0x00, "Nudity" )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x08, DEF_STR( No ) ) // Moles On Gal's Face
PORT_DIPSETTING( 0x08, DEF_STR( No ) ) // Moles On Gal's Face
PORT_DIPNAME( 0x10, 0x10, "Buy Screen Bonus Points" ) /* Sets your points to 100 every time you arrive at the screen for buying special items. */
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@ -3363,7 +3363,7 @@ static INPUT_PORTS_START( mjembase )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x00, "Nudity" )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
PORT_START("FAKE") /* IN10 - Fake DSW */
PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
@ -3500,7 +3500,7 @@ static INPUT_PORTS_START( mjelct3 )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x00, "Nudity" )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
PORT_START("FAKE") /* IN10 - Fake DSW */
PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
@ -4354,7 +4354,7 @@ static MACHINE_CONFIG_START( cdracula, dynax_state )
MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)
MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax)
// MCFG_NVRAM_ADD_0FILL("nvram") // no battery
// MCFG_NVRAM_ADD_0FILL("nvram") // no battery
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)

2
src/mame/drivers/fgoal.c
View File

@ -339,7 +339,7 @@ GFXDECODE_END
void fgoal_state::machine_start()
{
m_interrupt_timer = timer_alloc(TIMER_INTERRUPT);
save_item(NAME(m_xpos));
save_item(NAME(m_ypos));
save_item(NAME(m_current_color));

14
src/mame/drivers/flyball.c
View File

@ -61,10 +61,10 @@ public:
/* misc */
UINT8 m_potmask;
UINT8 m_potsense;
emu_timer *m_pot_clear_timer;
emu_timer *m_quarter_timer;
DECLARE_READ8_MEMBER(input_r);
DECLARE_READ8_MEMBER(scanline_r);
DECLARE_READ8_MEMBER(potsense_r);
@ -75,17 +75,17 @@ public:
DECLARE_WRITE8_MEMBER(pitcher_vert_w);
DECLARE_WRITE8_MEMBER(pitcher_horz_w);
DECLARE_WRITE8_MEMBER(misc_w);
TILEMAP_MAPPER_MEMBER(get_memory_offset);
TILE_GET_INFO_MEMBER(get_tile_info);
virtual void machine_start();
virtual void machine_reset();
virtual void video_start();
DECLARE_PALETTE_INIT(flyball);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(joystick_callback);
TIMER_CALLBACK_MEMBER(quarter_callback);
@ -428,7 +428,7 @@ void flyball_state::machine_start()
for (int i = 0; i < len; i++)
buf[i ^ 0x1ff] = ROM[i];
memcpy(ROM, buf, len);
m_pot_clear_timer = timer_alloc(TIMER_POT_CLEAR);
m_quarter_timer = timer_alloc(TIMER_QUARTER);

44
src/mame/drivers/goldstar.c
View File

@ -2993,8 +2993,8 @@ static INPUT_PORTS_START( ns8linew )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 1C_4C ) )
PORT_DIPSETTING( 0x18, DEF_STR( 1C_5C ) )
PORT_DIPSETTING( 0x20, DEF_STR( 1C_6C ) ) // manual says 1c/8c
PORT_DIPSETTING( 0x28, "1 Coin/10 Credits" )
PORT_DIPSETTING( 0x20, DEF_STR( 1C_6C ) ) // manual says 1c/8c
PORT_DIPSETTING( 0x28, "1 Coin/10 Credits" )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7") /* not checked */
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@ -3375,12 +3375,12 @@ static INPUT_PORTS_START( bingowng )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
/* On a W-4 PCB these are used as: "Special Odds-Prohibition Of Winning...(Odds B)" - see DSW2-7
PORT_DIPNAME( 0x80, 0x00, "Special Odds" ) PORT_DIPLOCATION("DSW1:7,8")
PORT_DIPSETTING( 0x00, "None" )
PORT_DIPSETTING( 0x40, "x300 (x1000)" )
PORT_DIPSETTING( 0x80, "x500 (x5000" )
PORT_DIPSETTING( 0xc0, "x1000 (x10000)
/* On a W-4 PCB these are used as: "Special Odds-Prohibition Of Winning...(Odds B)" - see DSW2-7
PORT_DIPNAME( 0x80, 0x00, "Special Odds" ) PORT_DIPLOCATION("DSW1:7,8")
PORT_DIPSETTING( 0x00, "None" )
PORT_DIPSETTING( 0x40, "x300 (x1000)" )
PORT_DIPSETTING( 0x80, "x500 (x5000" )
PORT_DIPSETTING( 0xc0, "x1000 (x10000)
*/
PORT_START("DSW2")
@ -3406,13 +3406,13 @@ static INPUT_PORTS_START( bingowng )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
/* On a W-4 PCB these are used as:
PORT_DIPNAME( 0x40, 0x40, "Odds" ) PORT_DIPLOCATION("DSW2:7")
PORT_DIPSETTING( 0x40, "Type A" )
PORT_DIPSETTING( 0x00, "Type B" )
PORT_DIPNAME( 0x80, 0x80, "Type Of W-Up Game" ) PORT_DIPLOCATION("DSW2:8")
PORT_DIPSETTING( 0x80, "Slots" )
PORT_DIPSETTING( 0x00, "Big/Small Card" )
/* On a W-4 PCB these are used as:
PORT_DIPNAME( 0x40, 0x40, "Odds" ) PORT_DIPLOCATION("DSW2:7")
PORT_DIPSETTING( 0x40, "Type A" )
PORT_DIPSETTING( 0x00, "Type B" )
PORT_DIPNAME( 0x80, 0x80, "Type Of W-Up Game" ) PORT_DIPLOCATION("DSW2:8")
PORT_DIPSETTING( 0x80, "Slots" )
PORT_DIPSETTING( 0x00, "Big/Small Card" )
*/
/* On a W-4 PCB DSW3 & DSW4 are reversed and all dips on DSW4 are set to off! */
@ -3672,7 +3672,7 @@ static INPUT_PORTS_START( schery97 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Key Out / Attendant")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats") // doesn't work in v352c4
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats") // doesn't work in v352c4
PORT_START("DSW1")
PORT_DIPNAME( 0x07, 0x03, "Game Level (Difficulty)" ) PORT_DIPLOCATION("DSW1:1,2,3") /* OK */
@ -4335,14 +4335,14 @@ static INPUT_PORTS_START( roypok96a )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x10, DEF_STR( On ) )
PORT_DIPNAME( 0x20, 0x00, "Unused - leave off" ) PORT_DIPLOCATION("DSW5:6")
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x20, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x00, "Reset Remaining Score To Zero" ) PORT_DIPLOCATION("DSW5:7")
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
PORT_DIPNAME( 0x80, 0x00, "Count Game To Issue Ticket" ) PORT_DIPLOCATION("DSW5:8")
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
INPUT_PORTS_END
@ -4472,7 +4472,7 @@ static INPUT_PORTS_START( pokonl97 )
PORT_DIPNAME( 0x10, 0x10, "Auto Ticket Dispense" ) PORT_DIPLOCATION("DSW4:5") /* not checked */
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
PORT_DIPNAME( 0xe0, 0xe0, "Ticket Dispense Mode" ) PORT_DIPLOCATION("DSW4:6,7,8")
PORT_DIPNAME( 0xe0, 0xe0, "Ticket Dispense Mode" ) PORT_DIPLOCATION("DSW4:6,7,8")
PORT_DIPSETTING( 0xe0, "Continuous" )
PORT_DIPSETTING( 0xc0, "Max 1 Ticket Per Game" )
PORT_DIPSETTING( 0xa0, "Max 2 Ticket Per Game" )

7
src/mame/drivers/hng64.c
View File

@ -918,7 +918,7 @@ WRITE32_MEMBER(hng64_state::hng64_sprite_clear_odd_w)
WRITE32_MEMBER(hng64_state::hng64_vregs_w)
{
// printf("hng64_vregs_w %02x, %08x %08x\n", offset * 4, data, mem_mask);
// printf("hng64_vregs_w %02x, %08x %08x\n", offset * 4, data, mem_mask);
COMBINE_DATA(&m_videoregs[offset]);
}
@ -1503,7 +1503,7 @@ void hng64_state::machine_start()
{
m_videoregs[i] = 0xdeadbeef;
}
}
@ -1569,8 +1569,7 @@ MACHINE_CONFIG_END
ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS */ \
ROM_LOAD ( "from1.bin", 0x000000, 0x080000, CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) ) \
ROM_REGION( 0x0100000, "fpga", 0 ) /* FPGA data */ \
ROM_LOAD ( "rom1.bin", 0x000000, 0x01ff32, CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) ) \
ROM_LOAD ( "rom1.bin", 0x000000, 0x01ff32, CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
ROM_START( hng64 )
/* BIOS */

8
src/mame/drivers/hotblock.c
View File

@ -57,7 +57,7 @@ public:
/* devices */
required_device<cpu_device> m_maincpu;
required_device<palette_device> m_palette;
/* memory pointers */
required_shared_ptr<UINT8> m_vram;
@ -67,15 +67,15 @@ public:
/* memory */
UINT8 m_pal[0x10000];
DECLARE_READ8_MEMBER(video_read);
DECLARE_READ8_MEMBER(port4_r);
DECLARE_WRITE8_MEMBER(port4_w);
DECLARE_WRITE8_MEMBER(port0_w);
DECLARE_WRITE8_MEMBER(video_write);
virtual void video_start();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};

12
src/mame/drivers/iteagle.c
View File

@ -105,9 +105,9 @@ class iteagle_state : public driver_device
public:
iteagle_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu")
m_maincpu(*this, "maincpu")
{}
required_device<mips3_device> m_maincpu;
virtual void machine_start();
@ -129,7 +129,7 @@ static MACHINE_CONFIG_START( gtfore, iteagle_state )
MCFG_CPU_ADD("maincpu", VR4310LE, 166666666)
MCFG_MIPS3_ICACHE_SIZE(16384)
MCFG_MIPS3_DCACHE_SIZE(16384)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
MCFG_ITEAGLE_FPGA_ADD( ":pci:06.0")
@ -144,7 +144,7 @@ static MACHINE_CONFIG_START( gtfore, iteagle_state )
MCFG_SCREEN_SIZE(640, 350)
MCFG_SCREEN_VISIBLE_AREA(0, 639, 0, 349)
MCFG_SCREEN_UPDATE_DEVICE(":pci:09.0", voodoo_pci_device, screen_update)
MACHINE_CONFIG_END
@ -167,7 +167,7 @@ static INPUT_PORTS_START( iteagle )
PORT_DIPNAME( 0x0F00, 0x0000, "GAME" )
PORT_DIPNAME( 0x00F0, 0x0000, "MAJOR" )
PORT_DIPNAME( 0x000F, 0x0000, "MINOR" )
INPUT_PORTS_END
static INPUT_PORTS_START( gtfore05 )
@ -263,7 +263,7 @@ ROM_START( gtfore02 )
DISK_REGION( ":pci:06.1:ide:0:hdd:image" )
DISK_IMAGE( "golf_fore_2002_v2.01.04_umv", 0, SHA1(e902b91bd739daee0b95b10e5cf33700dd63a76b) ) /* Labeled Golf Fore! V2.01.04 UMV */
//DISK_REGION( "ide:1:cdrom" ) // program CD-ROM
ROM_END
ROM_START( gtfore02o )

4
src/mame/drivers/jankenmn.c
View File

@ -153,11 +153,11 @@ public:
m_maincpu(*this, "maincpu") { }
required_device<cpu_device> m_maincpu;
DECLARE_WRITE8_MEMBER(lamps1_w);
DECLARE_WRITE8_MEMBER(lamps2_w);
DECLARE_WRITE8_MEMBER(lamps3_w);
DECLARE_CUSTOM_INPUT_MEMBER(hopper_status_r);
};

6
src/mame/drivers/jchan.c
View File

@ -228,9 +228,9 @@ public:
DECLARE_DRIVER_INIT(jchan);
virtual void video_start();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_DEVICE_CALLBACK_MEMBER(vblank);
};
@ -290,7 +290,7 @@ void jchan_state::video_start()
m_spritegen1->skns_sprite_kludge(0,0);
m_spritegen2->skns_sprite_kludge(0,0);
save_item(NAME(m_irq_sub_enable));
save_pointer(NAME(m_sprite_ram32_1), 0x4000/4);
save_pointer(NAME(m_sprite_ram32_2), 0x4000/4);

4
src/mame/drivers/junofrst.c
View File

@ -105,11 +105,11 @@ public:
required_device<filter_rc_device> m_filter_0_0;
required_device<filter_rc_device> m_filter_0_1;
required_device<filter_rc_device> m_filter_0_2;
UINT8 m_blitterdata[4];
int m_i8039_status;
int m_last_irq;
DECLARE_WRITE8_MEMBER(blitter_w);
DECLARE_WRITE8_MEMBER(bankselect_w);
DECLARE_WRITE8_MEMBER(sh_irqtrigger_w);

14
src/mame/drivers/m72.c
View File

@ -1785,7 +1785,7 @@ static MACHINE_CONFIG_START( m72_base, m72_state )
MCFG_CPU_ADD("soundcpu",Z80, SOUND_CLOCK)
MCFG_CPU_PROGRAM_MAP(sound_ram_map)
MCFG_CPU_IO_MAP(sound_portmap)
/* video hardware */
MCFG_GFXDECODE_ADD("gfxdecode", "palette", m72)
@ -1834,7 +1834,7 @@ static MACHINE_CONFIG_DERIVED( xmultiplm72, m72_8751 )
MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
MACHINE_CONFIG_END
@ -1852,7 +1852,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( dkgenm72, m72 ) // dervices from 'm72' because we use 'fake nmi' on the soundcpu
MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
MACHINE_CONFIG_END
@ -1871,7 +1871,7 @@ static MACHINE_CONFIG_DERIVED( xmultipl, m72 )
MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
MCFG_VIDEO_START_OVERRIDE(m72_state,xmultipl)
@ -1948,7 +1948,7 @@ static MACHINE_CONFIG_START( dbreed, m72_state )
MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
/* video hardware */
@ -1979,7 +1979,7 @@ static MACHINE_CONFIG_START( hharry, m72_state )
MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
/* video hardware */
@ -2011,7 +2011,7 @@ static MACHINE_CONFIG_START( hharryu, m72_state )
MCFG_CPU_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
MCFG_MACHINE_RESET_OVERRIDE(m72_state,xmultipl)
/* video hardware */

2
src/mame/drivers/madalien.c
View File

@ -437,7 +437,7 @@ ROM_START( madalienb )
ROM_LOAD( "mc-1.3k", 0x0000, 0x0400, BAD_DUMP CRC(2710c47e) SHA1(337e4f160c7db143ec3bfae3e08e8789b9e41cc5) ) // taken from chwy, see below, tile 2 is mismatched with the 2 roms from the actual PCB.
ROM_LOAD( "me-1.3l", 0x0400, 0x0400, CRC(7328a425) SHA1(327adc8b0e25d93f1ae98a44c26d0aaaac1b1a9c) )
ROM_LOAD( "md-1.3m", 0x0800, 0x0400, CRC(b5329929) SHA1(86890e1b7cc8cb31fc0dcbc2d3cff02e4cf95619) )
/* for reference, this is the data used by Highway Chase on the cassette system when extracted
ROM_REGION( 0x0400, "user1", 0 ) // background tile map
ROM_LOAD( "rom1", 0x0000, 0x0400, CRC(9b04c446) SHA1(918013f3c0244ab6a670b9d1b6b642298e2c5ab8) )

12
src/mame/drivers/mgolf.c
View File

@ -47,18 +47,18 @@ public:
DECLARE_READ8_MEMBER(dial_r);
DECLARE_READ8_MEMBER(misc_r);
DECLARE_WRITE8_MEMBER(wram_w);
TILE_GET_INFO_MEMBER(get_tile_info);
virtual void machine_start();
virtual void machine_reset();
virtual void video_start();
DECLARE_PALETTE_INIT(mgolf);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(interrupt_callback);
void update_plunger( );
double calc_plunger_pos();
@ -343,7 +343,7 @@ GFXDECODE_END
void mgolf_state::machine_start()
{
m_interrupt_timer = timer_alloc(TIMER_INTERRUPT);
save_item(NAME(m_prev));
save_item(NAME(m_mask));
save_item(NAME(m_time_pushed));

26
src/mame/drivers/neogeo.c
View File

@ -238,9 +238,9 @@
. NEO-AEG CHA42G-3
. NEO-AEG CHA42G-4
. NEO-AEG CHA256
. NEO-AEG CHA256 B
. NEO-AEG CHA256 B
. NEO-AEG CHA256[B]
. NEO-AEG CHA256BY
. NEO-AEG CHA256BY
. NEO-AEG CHA256RY
. NEO-AEG CHA512Y
. NEO-AEG CHAFIO (1999.8.10) - used with NEO-CMC 90G06C7042 or NEO-CMC 90G06C7050
@ -263,7 +263,7 @@
. NEO-AEG PROG4096 B
. NEO-AEG PROGGS
. NEO-AEG PROGTOP2
. NEO-AEG PROGTOP2Y
. NEO-AEG PROGTOP2Y
. NEO-AEG PROGEOP (1999.4.2)
. NEO-AEG PROGLBA (1999.7.6)
. NEO-AEG PROGRK
@ -310,16 +310,16 @@
GIGA PROG Board 1.0
GIGA PROG Board 1.5
Unofficial pcb's from NEOBITZ:
MVS CHA:
CHARBITZ1 2013.12.01
MVS PROG:
PROGBITZ1 2013.12.01
Unofficial pcb's from NEOBITZ:
MVS CHA:
CHARBITZ1 2013.12.01
MVS PROG:
PROGBITZ1 2013.12.01
Neo-Geo game PCB infos by Johnboy

28
src/mame/drivers/neogeo_noslot.c
View File

@ -1237,7 +1237,7 @@ ROM_END
ID-0023
. NGM-023
NEO-MVS PROG42G / NEO-MVS CHA42G
NEO-MVS PROGTOP / NEO-MVS CHA-256
NEO-MVS PROGTOP / NEO-MVS CHA-256
Boards used for the Korean release
. NGH-023
NEO-AEG PROG42G-1 / NEO-AEG CHA42G-1
@ -1915,7 +1915,7 @@ ROM_START( aof ) /* MVS AND AES VERSION */
ROM_REGION( 0x100000, "maincpu", 0 )
ROM_LOAD16_WORD_SWAP( "044-p1.p1", 0x000000, 0x080000, CRC(ca9f7a6d) SHA1(4d28ef86696f7e832510a66d3e8eb6c93b5b91a1) ) /* TC534200 */
/* also found sets with ep1 or p1 on eprom. */
NEO_SFIX_128K( "044-s1.s1", CRC(89903f39) SHA1(a04a0c244a5d5c7a595fcf649107969635a6a8b6) ) /* TC531000 */
NEO_BIOS_AUDIO_128K( "044-m1.m1", CRC(0987e4bb) SHA1(8fae4b7fac09d46d4727928e609ed9d3711dbded) ) /* TC531001 */
@ -1950,7 +1950,7 @@ ROM_START( samsho ) /* MVS VERSION */
ROM_LOAD16_WORD_SWAP( "045-p1.p1", 0x000000, 0x100000, CRC(dfe51bf0) SHA1(2243af3770a516ae698b69bcd9daf53632d9128d) ) /* TC538200 */
ROM_LOAD16_WORD_SWAP( "045-pg2.sp2", 0x100000, 0x100000, CRC(46745b94) SHA1(d9e959fd1f88c9402915c1d0dcdb4a9e3d49cdcb) ) /* TC538200 */
/* also found set with ep1 / ep2 on eprom and sp2 on maskrom; same rom data as samshoh is used. */
NEO_SFIX_128K( "045-s1.s1", CRC(9142a4d3) SHA1(54088e99fcfd75fd0f94852890a56350066a05a3) ) /* TC531000 */
NEO_BIOS_AUDIO_128K( "045-m1.m1", CRC(95170640) SHA1(125c502db0693e8d11cef619b090081c14a9a300) ) /* TC531001 */
@ -2271,7 +2271,7 @@ ROM_START( wh1h ) /* AES VERSION */
ROM_REGION( 0x100000, "maincpu", 0 )
ROM_LOAD16_WORD_SWAP( "053-p1.p1", 0x000000, 0x080000, CRC(95b574cb) SHA1(b7b7af6a04c3d902e7f8852897741ecaf0b1062c) ) /* TC534200 */
ROM_LOAD16_WORD_SWAP( "053-p2.p2", 0x080000, 0x080000, CRC(f198ed45) SHA1(24ccc091e97f63796562bb5b30df51f39bd504ef) ) /* TC534200 */
NEO_SFIX_128K( "053-s1.s1", CRC(8c2c2d6b) SHA1(87fa79611c6f8886dcc8766814829c669c65b40f) ) /* TC531000 */
NEO_BIOS_AUDIO_128K( "053-m1.m1", CRC(1bd9d04b) SHA1(65cd7b002123ed1a3111e3d942608d0082799ff3) ) /* TC531001 */
@ -2615,7 +2615,7 @@ ROM_START( ssideki2 ) /* MVS AND AES VERSION */
ROM_REGION( 0x100000, "maincpu", 0 )
ROM_LOAD16_WORD_SWAP( "061-p1.p1", 0x000000, 0x100000, CRC(5969e0dc) SHA1(78abea880c125ec5a85bef6404478512a34b5513) ) /* mask rom TC538200 */
/* also found MVS sets with ep1 / ep2 on eprom; correct chip label unknown. */
NEO_SFIX_128K( "061-s1.s1", CRC(226d1b68) SHA1(de010f6fda3ddadb181fe37daa6105f22e78b970) ) /* mask rom TC531000 */
NEO_BIOS_AUDIO_128K( "061-m1.m1", CRC(156f6951) SHA1(49686f615f109a02b4f23931f1c84fee13872ffd) ) /* mask rom TC531001 */
@ -2679,7 +2679,7 @@ ROM_START( samsho2 ) /* MVS AND AES VERSION */
ROM_LOAD16_WORD_SWAP( "063-p1.p1", 0x100000, 0x100000, CRC(22368892) SHA1(0997f8284aa0f57a333be8a0fdea777d0d01afd6) ) /* TC5316200 */
ROM_CONTINUE( 0x000000, 0x100000 )
/* also found MVS sets with ep1 / ep2 on eprom and p1 / sp2 on maskrom; correct chip label unknown */
NEO_SFIX_128K( "063-s1.s1", CRC(64a5cd66) SHA1(12cdfb27bf9ccd5a8df6ddd4628ef7cf2c6d4964) ) /* TC531000 */
NEO_BIOS_AUDIO_128K( "063-m1.m1", CRC(56675098) SHA1(90429fc40d056d480d0e2bbefbc691d9fa260fc4) ) /* TC531001 */
@ -2965,7 +2965,7 @@ ROM_END
BANK 3 NOT USED
****************************************/
ROM_START( b2b )
ROM_START( b2b )
ROM_REGION( 0x100000, "maincpu", 0 )
ROM_LOAD16_WORD_SWAP( "071.p1", 0x000000, 0x080000, CRC(7687197d) SHA1(4bb9cb7819807f7a7e1f85f1c4faac4a2f8761e8) )
@ -4252,7 +4252,7 @@ ROM_START( kof96 ) /* MVS VERSION */
ROM_LOAD16_WORD_SWAP( "214-p1.p1", 0x000000, 0x100000, CRC(52755d74) SHA1(4232d627f1d2e6ea9fc8cf01571d77d4d5b8a1bb) ) /* TC538200 */
ROM_LOAD16_WORD_SWAP( "214-p2.sp2", 0x100000, 0x200000, CRC(002ccb73) SHA1(3ae8df682c75027ca82db25491021eeba00a267e) ) /* TC5316200 */
/* also found sets with ep1 / ep2 / ep3 / ep4 on eprom and 214-P5 on TC5316200; correct chip labels for eproms is unknown */
NEO_SFIX_128K( "214-s1.s1", CRC(1254cbdb) SHA1(fce5cf42588298711a3633e9c9c1d4dcb723ac76) ) /* TC531000 */
NEO_BIOS_AUDIO_128K( "214-m1.m1", CRC(dabc427c) SHA1(b76722ed142ee7addceb4757424870dbd003e8b3) ) /* TC531001 */
@ -5013,9 +5013,9 @@ ROM_START( lastblad ) /* MVS VERSION */
ROM_REGION( 0x500000, "maincpu", 0 )
ROM_LOAD16_WORD_SWAP( "234-p1.p1", 0x000000, 0x100000, CRC(e123a5a3) SHA1(a3ddabc00feeb54272b145246612ad4632b0e413) ) /* TC538200 */
ROM_LOAD16_WORD_SWAP( "234-p2.sp2", 0x100000, 0x400000, CRC(0fdc289e) SHA1(1ff31c0b0f4f9ddbedaf4bcf927faaae81892ec7) ) /* TC5332205 */
/* also found sets with p1 / sp2 / ep1 / ep2 / m1 on eprom with sticker */
/* also found sets with p1 / sp2 / ep1 / ep2 / m1 on eprom with sticker */
/* chip label is 0234-P1, 0234-SP2, 0234-EP1, 0234-EP2 and 0234-M1 */
NEO_SFIX_128K( "234-s1.s1", CRC(95561412) SHA1(995de272f572fd08d909d3d0af4251b9957b3640) ) /* TC531000 */
NEO_BIOS_AUDIO_128K( "234-m1.m1", CRC(087628ea) SHA1(48dcf739bb16699af4ab8ed632b7dcb25e470e06) ) /* TC531001 */
@ -6193,7 +6193,7 @@ ROM_START( mslug3 ) /* Original Version - Encrypted Code & GFX */ /* revision 20
/* The SMA for this release has a green colour marking; the older revision has a white colour marking */
ROM_LOAD16_WORD_SWAP( "256-pg1.p1", 0x100000, 0x400000, CRC(b07edfd5) SHA1(dcbd9e500bfae98d754e55cdbbbbf9401013f8ee) ) /* TC5332202 */
ROM_LOAD16_WORD_SWAP( "256-pg2.p2", 0x500000, 0x400000, CRC(6097c26b) SHA1(248ec29d21216f29dc6f5f3f0e1ad1601b3501b6) ) /* TC5332202 */
ROM_Y_ZOOM
/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */
@ -6230,7 +6230,7 @@ ROM_START( mslug3h ) /* Original Version - Encrypted GFX */ /* revision 2000.3.1
ROM_LOAD16_WORD_SWAP( "256-ph2.sp2", 0x100000, 0x400000, CRC(1f3d8ce8) SHA1(08b05a8abfb86ec09a5e758d6273acf1489961f9) )
/* also found AES set with p1 / p2 on maskrom on NEO-AEG PROGLBA (NEO-SMA); chip labels is 256-PG1 and 256-PG2 */
/* The SMA for this release has a pink color marking */
ROM_Y_ZOOM
/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */
@ -6748,7 +6748,7 @@ ROM_START( pnyaa ) /* Encrypted Set */ /* MVS ONLY RELEASE */
ROM_REGION( 0x100000, "maincpu", 0 )
ROM_LOAD16_WORD_SWAP( "267-p1.p1", 0x000000, 0x100000, CRC(112fe2c0) SHA1(01420e051f0bdbd4f68ce306a3738161b96f8ba8) ) /* mask rom TC538200 */
/* also found set with p1 and m1 on eprom with sticker; chip labels is PN 2.02 and M1 */
ROM_Y_ZOOM
/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */
@ -6820,7 +6820,7 @@ ROM_START( mslug5h ) /* Encrypted Set */ /* AES release of the game but is also
ROM_LOAD32_WORD_SWAP( "268-p1c.p1", 0x000000, 0x400000, CRC(3636690a) SHA1(e0da714b4bdc6efffe1250ded02ebddb3ab6d7b3) )
ROM_LOAD32_WORD_SWAP( "268-p2c.p2", 0x000002, 0x400000, CRC(8dfc47a2) SHA1(27d618cfbd0107a4d2a836797e967b39d2eb4851) )
/* also found AES set with p1 / p2 on maskrom; chip labels is 268-P1CR2 and 268-P2CR2 */
ROM_Y_ZOOM
/* The Encrypted Boards do not have an s1 rom, data for it comes from the Cx ROMs */

2
src/mame/drivers/paradise.c
View File

@ -660,7 +660,7 @@ GFXDECODE_END
void paradise_state::machine_start()
{
int bank_n = memregion("maincpu")->bytes() / 0x4000;
membank("prgbank")->configure_entries(0, bank_n, memregion("maincpu")->base(), 0x4000);
save_item(NAME(m_palbank));

2
src/mame/drivers/peplus.c
View File

@ -9256,7 +9256,7 @@ Joker Poker P17A 95.50%
ROM_REGION( 0x10000, "maincpu", 0 )
ROM_LOAD( "xmp00025.u67", 0x00000, 0x10000, CRC(5d39ff71) SHA1(0a5f67e61ae0e8a08cc551ab4271ffc97c343ae3) ) /* International multi currency version - Auto Hold always on */
/* Also compatible with XMP00002, XMP00003, XMP00004, XMP00006 and XMP00024 programs */
ROM_REGION( 0x10000, "user1", 0 )
ROM_LOAD( "xm00013p.u66", 0x00000, 0x10000, CRC(4fde73f9) SHA1(f8eb6fb0585e8df9a7eb2ddc65bb20b120753d7a) )

6
src/mame/drivers/playmark.c
View File

@ -1375,7 +1375,7 @@ static MACHINE_CONFIG_START( hrdtimes, playmark_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold)
MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
@ -1416,7 +1416,7 @@ static MACHINE_CONFIG_START( hotmind, playmark_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold) // irq 2 and 6 point to the same location on hotmind
MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
@ -1462,7 +1462,7 @@ static MACHINE_CONFIG_START( luckboomh, playmark_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold)
MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))

8
src/mame/drivers/psychic5.c
View File

@ -318,14 +318,14 @@ The first sprite data is located at f20b,then f21b and so on.
MACHINE_START_MEMBER(psychic5_state, psychic5)
{
membank("mainbank")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x4000);
save_item(NAME(m_bank_latch));
}
MACHINE_START_MEMBER(psychic5_state, bombsa)
{
membank("mainbank")->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x4000);
save_item(NAME(m_bank_latch));
}
@ -707,7 +707,7 @@ static MACHINE_CONFIG_START( psychic5, psychic5_state )
MCFG_CPU_IO_MAP(psychic5_soundport_map)
MCFG_QUANTUM_TIME(attotime::from_hz(600)) /* Allow time for 2nd cpu to interleave */
MCFG_MACHINE_START_OVERRIDE(psychic5_state,psychic5)
/* video hardware */
@ -763,7 +763,7 @@ static MACHINE_CONFIG_START( bombsa, psychic5_state )
MCFG_CPU_IO_MAP(bombsa_soundport_map)
MCFG_QUANTUM_TIME(attotime::from_hz(600))
MCFG_MACHINE_START_OVERRIDE(psychic5_state,bombsa)
/* video hardware */

8
src/mame/drivers/pturn.c
View File

@ -123,14 +123,14 @@ public:
TILE_GET_INFO_MEMBER(get_tile_info);
TILE_GET_INFO_MEMBER(get_bg_tile_info);
DECLARE_DRIVER_INIT(pturn);
virtual void machine_start();
virtual void machine_reset();
virtual void video_start();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
INTERRUPT_GEN_MEMBER(sub_intgen);
INTERRUPT_GEN_MEMBER(main_intgen);
};
@ -174,7 +174,7 @@ void pturn_state::video_start()
m_fgmap->set_transparent_pen(0);
m_bgmap = &machine().tilemap().create(m_gfxdecode, tilemap_get_info_delegate(FUNC(pturn_state::get_bg_tile_info),this),TILEMAP_SCAN_ROWS,8, 8,32,32*8);
m_bgmap->set_transparent_pen(0);
save_item(NAME(m_bgbank));
save_item(NAME(m_fgbank));
save_item(NAME(m_bgpalette));

8
src/mame/drivers/re900.c
View File

@ -101,18 +101,18 @@ public:
UINT8 m_ledant;
UINT8 m_player;
UINT8 m_stat_a;
// common
DECLARE_READ8_MEMBER(rom_r);
DECLARE_WRITE8_MEMBER(cpu_port_0_w);
DECLARE_WRITE8_MEMBER(watchdog_reset_w);
// re900 specific
DECLARE_READ8_MEMBER(re_psg_portA_r);
DECLARE_READ8_MEMBER(re_psg_portB_r);
DECLARE_WRITE8_MEMBER(re_mux_port_A_w);
DECLARE_WRITE8_MEMBER(re_mux_port_B_w);
DECLARE_DRIVER_INIT(re900);
};
@ -432,7 +432,7 @@ DRIVER_INIT_MEMBER(re900_state,re900)
m_player = 1;
m_stat_a = 1;
m_psg_pa = m_psg_pb = m_mux_data = m_ledant = 0;
save_item(NAME(m_psg_pa));
save_item(NAME(m_psg_pb));
save_item(NAME(m_mux_data));

2
src/mame/drivers/rltennis.c
View File

@ -157,7 +157,7 @@ void rltennis_state::machine_start()
m_samples_2 = memregion("samples2")->base();
m_gfx = memregion("gfx1")->base();
m_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(rltennis_state::sample_player),this));
save_item(NAME(m_data760000));
save_item(NAME(m_data740000));
save_item(NAME(m_dac_counter));

10
src/mame/drivers/sandscrp.c
View File

@ -102,7 +102,7 @@ public:
UINT8 m_vblank_irq;
UINT8 m_latch1_full;
UINT8 m_latch2_full;
DECLARE_READ16_MEMBER(irq_cause_r);
DECLARE_WRITE16_MEMBER(irq_cause_w);
DECLARE_WRITE16_MEMBER(coincounter_w);
@ -114,12 +114,12 @@ public:
DECLARE_READ8_MEMBER(latchstatus_r);
DECLARE_READ8_MEMBER(soundlatch_r);
DECLARE_WRITE8_MEMBER(soundlatch_w);
virtual void machine_start();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
void screen_eof(screen_device &screen, bool state);
INTERRUPT_GEN_MEMBER(interrupt);
void update_irq_state();
};
@ -150,7 +150,7 @@ UINT32 sandscrp_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap
void sandscrp_state::machine_start()
{
membank("bank1")->configure_entries(0, 8, memregion("audiocpu")->base(), 0x4000);
save_item(NAME(m_sprite_irq));
save_item(NAME(m_unknown_irq));
save_item(NAME(m_vblank_irq));

1
src/mame/drivers/scobra.c
View File

@ -1253,4 +1253,3 @@ GAME( 1981, hustlerb4, hustler, hustlerb4, hustler, driver_device, 0,
GAME( 1982, mimonkey, 0, mimonkey, mimonkey, scramble_state, mimonkey, ROT90, "Universal Video Games", "Mighty Monkey", GAME_SUPPORTS_SAVE )
GAME( 1982, mimonsco, mimonkey, mimonkey, mimonsco, scramble_state, mimonsco, ROT90, "bootleg", "Mighty Monkey (bootleg on Super Cobra hardware)", GAME_SUPPORTS_SAVE )

56
src/mame/drivers/seta.c
View File

@ -7796,7 +7796,7 @@ static MACHINE_CONFIG_START( downtown, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on pcb */
@ -7857,7 +7857,7 @@ static MACHINE_CONFIG_START( usclssic, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -7912,7 +7912,7 @@ static MACHINE_CONFIG_START( calibr50, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on pcb */
@ -7956,7 +7956,7 @@ static MACHINE_CONFIG_START( metafox, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8040,7 +8040,7 @@ static MACHINE_CONFIG_START( blandia, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8078,7 +8078,7 @@ static MACHINE_CONFIG_START( blandiap, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8196,7 +8196,7 @@ static MACHINE_CONFIG_START( daioh, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on PCB */
@ -8235,7 +8235,7 @@ static MACHINE_CONFIG_START( daiohp, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(57.42) /* verified on PCB */
@ -8279,7 +8279,7 @@ static MACHINE_CONFIG_START( drgnunit, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8317,7 +8317,7 @@ static MACHINE_CONFIG_START( qzkklgy2, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8368,7 +8368,7 @@ static MACHINE_CONFIG_START( setaroul, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
MCFG_NVRAM_ADD_RANDOM_FILL("nvram")
/* video hardware */
@ -8412,7 +8412,7 @@ static MACHINE_CONFIG_START( eightfrc, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8456,7 +8456,7 @@ static MACHINE_CONFIG_START( extdwnhl, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8522,7 +8522,7 @@ static MACHINE_CONFIG_START( gundhara, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8568,7 +8568,7 @@ static MACHINE_CONFIG_START( jjsquawk, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8605,7 +8605,7 @@ static MACHINE_CONFIG_START( jjsquawb, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8651,7 +8651,7 @@ static MACHINE_CONFIG_START( kamenrid, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8820,7 +8820,7 @@ static MACHINE_CONFIG_START( madshark, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8866,7 +8866,7 @@ static MACHINE_CONFIG_START( magspeed, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8915,7 +8915,7 @@ static MACHINE_CONFIG_START( msgundam, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(56.66) /* between 56 and 57 to match a real PCB's game speed */
@ -8956,7 +8956,7 @@ static MACHINE_CONFIG_START( oisipuzl, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -8996,7 +8996,7 @@ static MACHINE_CONFIG_START( triplfun, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -9077,7 +9077,7 @@ static MACHINE_CONFIG_START( rezon, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -9313,7 +9313,7 @@ static MACHINE_CONFIG_START( utoukond, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -9365,7 +9365,7 @@ static MACHINE_CONFIG_START( wrofaero, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -9411,7 +9411,7 @@ static MACHINE_CONFIG_START( zingzip, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -9519,7 +9519,7 @@ static MACHINE_CONFIG_START( crazyfgt, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
@ -9585,7 +9585,7 @@ static MACHINE_CONFIG_START( inttoote, seta_state )
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
MCFG_SETA001_SPRITE_PALETTE("palette")
MCFG_SETA001_SPRITE_GFXBANK_CB(seta_state, setac_gfxbank_callback)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)

2
src/mame/drivers/seta2.c
View File

@ -585,7 +585,7 @@ void funcube_touchscreen_device::device_start()
emu_timer *tm = timer_alloc(0);
tm->adjust(attotime::from_ticks(1, clock()), 0, attotime::from_ticks(1, clock()));
m_tx_cb.resolve_safe();
save_item(NAME(m_button_state));
save_item(NAME(m_serial_pos));
save_item(NAME(m_serial));

8
src/mame/drivers/shougi.c
View File

@ -107,7 +107,7 @@ public:
int m_r;
//UINT8 *m_cpu_sharedram;
//UINT8 m_cpu_sharedram_control_val;
DECLARE_WRITE8_MEMBER(cpu_sharedram_sub_w);
DECLARE_WRITE8_MEMBER(cpu_sharedram_main_w);
DECLARE_READ8_MEMBER(cpu_sharedram_r);
@ -118,12 +118,12 @@ public:
DECLARE_WRITE8_MEMBER(nmi_disable_and_clear_line_w);
DECLARE_WRITE8_MEMBER(nmi_enable_w);
DECLARE_READ8_MEMBER(dummy_r);
DECLARE_PALETTE_INIT(shougi);
virtual void machine_start();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
INTERRUPT_GEN_MEMBER(vblank_nmi);
};

8
src/mame/drivers/sidearms.c
View File

@ -43,12 +43,12 @@ Notes:
void sidearms_state::machine_start()
{
membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x8000, 0x4000);
membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x8000, 0x4000);
}
WRITE8_MEMBER(sidearms_state::bankswitch_w)
{
membank("bank1")->set_entry(data & 0x07);
membank("bank1")->set_entry(data & 0x07);
}
@ -119,7 +119,7 @@ ADDRESS_MAP_END
WRITE8_MEMBER(sidearms_state::whizz_bankswitch_w)
{
int bank = 0;
int bank = 0;
switch (data & 0xC0)
{
case 0x00 : bank = 0; break;
@ -127,7 +127,7 @@ WRITE8_MEMBER(sidearms_state::whizz_bankswitch_w)
case 0x80 : bank = 1; break;
case 0xC0 : bank = 3; break;
}
membank("bank1")->set_entry(bank);
membank("bank1")->set_entry(bank);
}
static ADDRESS_MAP_START( whizz_map, AS_PROGRAM, 8, sidearms_state )

6
src/mame/drivers/simple_st0016.c
View File

@ -33,7 +33,7 @@ Dips verified for Neratte Chu (nratechu) from manual
void st0016_state::machine_start()
{
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
}
static ADDRESS_MAP_START( st0016_mem, AS_PROGRAM, 8, st0016_state )
@ -81,8 +81,8 @@ WRITE8_MEMBER(st0016_state::mux_select_w)
WRITE8_MEMBER(st0016_state::st0016_rom_bank_w)
{
membank("bank1")->set_entry(data);
// st0016_rom_bank = data;
membank("bank1")->set_entry(data);
// st0016_rom_bank = data;
}
static ADDRESS_MAP_START( st0016_io, AS_IO, 8, st0016_state )

6
src/mame/drivers/sothello.c
View File

@ -72,7 +72,7 @@ public:
DECLARE_READ8_MEMBER(subcpu_status_r);
DECLARE_WRITE8_MEMBER(msm_cfg_w);
virtual void machine_start();
virtual void machine_start();
virtual void machine_reset();
TIMER_CALLBACK_MEMBER(subcpu_suspend);
TIMER_CALLBACK_MEMBER(subcpu_resume);
@ -101,7 +101,7 @@ public:
void sothello_state::machine_start()
{
membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000);
membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000);
}
WRITE8_MEMBER(sothello_state::bank_w)
@ -114,7 +114,7 @@ WRITE8_MEMBER(sothello_state::bank_w)
case 4: bank=2; break;
case 8: bank=3; break;
}
membank("bank1")->set_entry(bank);
membank("bank1")->set_entry(bank);
}
TIMER_CALLBACK_MEMBER(sothello_state::subcpu_suspend)

6
src/mame/drivers/speglsht.c
View File

@ -134,7 +134,7 @@ public:
DECLARE_READ32_MEMBER(irq_ack_clear);
DECLARE_DRIVER_INIT(speglsht);
DECLARE_MACHINE_RESET(speglsht);
virtual void machine_start();
virtual void machine_start();
DECLARE_VIDEO_START(speglsht);
UINT32 screen_update_speglsht(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
required_device<palette_device> m_palette;
@ -160,13 +160,13 @@ ADDRESS_MAP_END
void speglsht_state::machine_start()
{
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
}
// common rombank? should go in machine/st0016 with larger address space exposed?
WRITE8_MEMBER(speglsht_state::st0016_rom_bank_w)
{
membank("bank1")->set_entry(data);
membank("bank1")->set_entry(data);
}

20
src/mame/drivers/srmp2.c
View File

@ -83,7 +83,7 @@ void srmp2_state::machine_start()
MACHINE_START_MEMBER(srmp2_state,srmp2)
{
machine_start();
m_iox.reset = 0x1f;
m_iox.ff_event = -1;
m_iox.ff_1 = 0x00;
@ -92,14 +92,14 @@ MACHINE_START_MEMBER(srmp2_state,srmp2)
m_iox.protcheck[1] = -1; m_iox.protlatch[1] = -1;
m_iox.protcheck[2] = -1; m_iox.protlatch[2] = -1;
m_iox.protcheck[3] = -1; m_iox.protlatch[3] = -1;
save_item(NAME(m_color_bank));
}
MACHINE_START_MEMBER(srmp2_state,srmp3)
{
machine_start();
m_iox.reset = 0xc8;
m_iox.ff_event = 0xef;
m_iox.ff_1 = -1;
@ -107,16 +107,16 @@ MACHINE_START_MEMBER(srmp2_state,srmp3)
m_iox.protcheck[1] = 0x4c; m_iox.protlatch[1] = 0x00;
m_iox.protcheck[2] = 0x1c; m_iox.protlatch[2] = 0x04;
m_iox.protcheck[3] = 0x45; m_iox.protlatch[3] = 0x00;
membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base(), 0x2000);
membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base(), 0x2000);
save_item(NAME(m_gfx_bank));
}
MACHINE_START_MEMBER(srmp2_state,rmgoldyh)
{
machine_start();
m_iox.reset = 0xc8;
m_iox.ff_event = 0xff;
m_iox.ff_1 = -1;
@ -125,15 +125,15 @@ MACHINE_START_MEMBER(srmp2_state,rmgoldyh)
m_iox.protcheck[2] = -1; m_iox.protlatch[2] = -1;
m_iox.protcheck[3] = -1; m_iox.protlatch[3] = -1;
membank("bank1")->configure_entries(0, 32, memregion("maincpu")->base(), 0x2000);
membank("bank1")->configure_entries(0, 32, memregion("maincpu")->base(), 0x2000);
save_item(NAME(m_gfx_bank));
}
MACHINE_START_MEMBER(srmp2_state,mjyuugi)
{
machine_start();
m_iox.reset = 0x1f;
m_iox.ff_event = -1;
m_iox.ff_1 = 0x00;

6
src/mame/drivers/srmp5.c
View File

@ -114,7 +114,7 @@ public:
DECLARE_READ8_MEMBER(cmd1_r);
DECLARE_READ8_MEMBER(cmd2_r);
DECLARE_READ8_MEMBER(cmd_stat8_r);
virtual void machine_start();
virtual void machine_start();
DECLARE_DRIVER_INIT(srmp5);
UINT32 screen_update_srmp5(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@ -240,7 +240,7 @@ UINT32 srmp5_state::screen_update_srmp5(screen_device &screen, bitmap_rgb32 &bit
void srmp5_state::machine_start()
{
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
}
WRITE32_MEMBER(srmp5_state::bank_w)
@ -400,7 +400,7 @@ READ8_MEMBER(srmp5_state::cmd_stat8_r)
// common rombank? should go in machine/st0016 with larger address space exposed?
WRITE8_MEMBER(srmp5_state::st0016_rom_bank_w)
{
membank("bank1")->set_entry(data);
membank("bank1")->set_entry(data);
}

8
src/mame/drivers/srmp6.c
View File

@ -107,7 +107,7 @@ public:
DECLARE_WRITE16_MEMBER(paletteram_w);
DECLARE_READ16_MEMBER(srmp6_irq_ack_r);
DECLARE_DRIVER_INIT(INIT);
virtual void machine_start();
virtual void machine_start();
virtual void video_start();
UINT32 screen_update_srmp6(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void update_palette();
@ -309,7 +309,7 @@ UINT32 srmp6_state::screen_update_srmp6(screen_device &screen, bitmap_rgb32 &bit
void srmp6_state::machine_start()
{
membank("bank1")->configure_entries(0, 16, memregion("nile")->base(), 0x200000);
membank("bank1")->configure_entries(0, 16, memregion("nile")->base(), 0x200000);
}
WRITE16_MEMBER(srmp6_state::srmp6_input_select_w)
@ -340,8 +340,8 @@ WRITE16_MEMBER(srmp6_state::video_regs_w)
{
case 0x5e/2: // bank switch, used by ROM check
{
LOG(("%x\n",data));
membank("bank1")->set_entry(data & 0x0f);
LOG(("%x\n",data));
membank("bank1")->set_entry(data & 0x0f);
break;
}

14
src/mame/drivers/srumbler.c
View File

@ -32,25 +32,25 @@ WRITE8_MEMBER(srumbler_state::bankswitch_w)
for (int i = 0x05;i < 0x10;i++)
{
/* bit 2 of prom1 selects ROM or RAM - not supported */
/* bit 2 of prom1 selects ROM or RAM - not supported */
int bank = ((prom1[i] & 0x03) << 4) | (prom2[i] & 0x0f);
char bankname[10];
char bankname[10];
sprintf(bankname, "%04x", i*0x1000);
membank(bankname)->set_entry(bank);
membank(bankname)->set_entry(bank);
}
}
void srumbler_state::machine_start()
{
for (int i = 0x05; i < 0x10; i++)
for (int i = 0x05; i < 0x10; i++)
{
char bankname[10];
char bankname[10];
sprintf(bankname, "%04x", i*0x1000);
membank(bankname)->configure_entries(0, 64, memregion("user1")->base(), 0x1000);
membank(bankname)->configure_entries(0, 64, memregion("user1")->base(), 0x1000);
}
/* initialize banked ROM pointers */
/* initialize banked ROM pointers */
bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0);
}

8
src/mame/drivers/sstrangr.c
View File

@ -24,13 +24,13 @@ public:
required_device<cpu_device> m_maincpu;
required_shared_ptr<UINT8> m_ram;
UINT8 m_flip_screen;
DECLARE_WRITE8_MEMBER(port_w);
virtual void video_start();
UINT32 screen_update_sstrangr(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
UINT32 screen_update_sstrngr2(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
};

2
src/mame/drivers/ssv.c
View File

@ -2491,7 +2491,7 @@ void ssv_state::init(int interrupt_ultrax)
( (i & 1) ? (8 << 16) : 0 ) ;
enable_video(1);
m_interrupt_ultrax = interrupt_ultrax;
save_item(NAME(m_requested_int));
save_item(NAME(m_irq_enable));
}

8
src/mame/drivers/sub.c
View File

@ -139,15 +139,15 @@ public:
required_shared_ptr<UINT8> m_spriteram;
required_shared_ptr<UINT8> m_spriteram2;
required_shared_ptr<UINT8> m_scrolly;
UINT8 m_nmi_en;
DECLARE_WRITE8_MEMBER(to_sound_w);
DECLARE_WRITE8_MEMBER(nmi_mask_w);
virtual void machine_start();
DECLARE_PALETTE_INIT(sub);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
INTERRUPT_GEN_MEMBER(sound_irq);
};

26
src/mame/drivers/suna16.c
View File

@ -215,7 +215,7 @@ ADDRESS_MAP_END
MACHINE_START_MEMBER(suna16_state,bestbest)
{
save_item(NAME(m_prot));
save_item(NAME(m_prot));
}
@ -294,8 +294,8 @@ ADDRESS_MAP_END
MACHINE_START_MEMBER(suna16_state, bssoccer)
{
membank("bank1")->configure_entries(0, 8, memregion("pcm1")->base() + 0x1000, 0x10000);
membank("bank2")->configure_entries(0, 8, memregion("pcm2")->base() + 0x1000, 0x10000);
membank("bank1")->configure_entries(0, 8, memregion("pcm1")->base() + 0x1000, 0x10000);
membank("bank2")->configure_entries(0, 8, memregion("pcm2")->base() + 0x1000, 0x10000);
}
/* Bank Switching */
@ -304,16 +304,16 @@ WRITE8_MEMBER(suna16_state::bssoccer_pcm_1_bankswitch_w)
{
const int bank = data & 7;
if (bank & ~7) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
printf("%d %d\n", 1, bank);
membank("bank1")->set_entry(bank);
printf("%d %d\n", 1, bank);
membank("bank1")->set_entry(bank);
}
WRITE8_MEMBER(suna16_state::bssoccer_pcm_2_bankswitch_w)
{
const int bank = data & 7;
if (bank & ~7) logerror("CPU#3 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
printf("%d %d\n", 2, bank);
membank("bank2")->set_entry(bank);
printf("%d %d\n", 2, bank);
membank("bank2")->set_entry(bank);
}
@ -378,7 +378,7 @@ WRITE8_MEMBER(suna16_state::uballoon_pcm_1_bankswitch_w)
{
const int bank = data & 1;
if (bank & ~1) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
membank("bank1")->set_entry(bank);
membank("bank1")->set_entry(bank);
}
/* Memory maps: Yes, *no* RAM */
@ -398,8 +398,8 @@ ADDRESS_MAP_END
MACHINE_START_MEMBER(suna16_state,uballoon)
{
membank("bank1")->configure_entries(0, 2, memregion("pcm1")->base() + 0x400, 0x10000);
membank("bank1")->configure_entries(0, 2, memregion("pcm1")->base() + 0x400, 0x10000);
save_item(NAME(m_prot));
}
@ -828,7 +828,7 @@ static MACHINE_CONFIG_START( bssoccer, suna16_state )
MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_MACHINE_START_OVERRIDE(suna16_state,bssoccer)
MCFG_MACHINE_START_OVERRIDE(suna16_state,bssoccer)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -887,7 +887,7 @@ static MACHINE_CONFIG_START( uballoon, suna16_state )
MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_MACHINE_START_OVERRIDE(suna16_state,uballoon)
MCFG_MACHINE_START_OVERRIDE(suna16_state,uballoon)
MCFG_MACHINE_RESET_OVERRIDE(suna16_state,uballoon)
/* video hardware */
@ -992,7 +992,7 @@ static MACHINE_CONFIG_START( bestbest, suna16_state )
/* 2nd PCM Z80 missing */
MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_MACHINE_START_OVERRIDE(suna16_state, bestbest)
/* video hardware */

22
src/mame/drivers/suna8.c
View File

@ -735,7 +735,7 @@ static ADDRESS_MAP_START( brickzn11_map, AS_PROGRAM, 8, suna8_state )
AM_RANGE(0xc060, 0xc060) AM_WRITE(brickzn_rombank_w ) // ROM Bank
AM_RANGE(0xc080, 0xc080) AM_WRITE(brickzn_leds_w ) // Leds
AM_RANGE(0xc0a0, 0xc0a0) AM_WRITE(brickzn_palbank_w ) // Palette RAM Bank
// AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_prot2_w ) // Protection 2
// AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_prot2_w ) // Protection 2
AM_RANGE(0xc100, 0xc100) AM_READ_PORT("P1") // P1 (Buttons)
AM_RANGE(0xc101, 0xc101) AM_READ_PORT("P2") // P2 (Buttons)
@ -771,13 +771,13 @@ WRITE8_MEMBER(suna8_state::brickzn_multi_w)
else if (protselect == 0x90)
{
/*
0d brick hit NO! 25?
2c side wall hit OK
3b paddle hit OK
44 death OK?
53 death OK?
56 coin in OK?
70 monster hit NO? 58?
0d brick hit NO! 25?
2c side wall hit OK
3b paddle hit OK
44 death OK?
53 death OK?
56 coin in OK?
70 monster hit NO? 58?
*/
UINT8 remap = (m_remap_sound ? BITSWAP8(data, 7,6,3,4,5,2,1,0) : data);
@ -1975,7 +1975,7 @@ MACHINE_CONFIG_END
MACHINE_RESET_MEMBER(suna8_state,brickzn)
{
m_protection_val = m_prot2 = m_prot2_prev = 0xff;
m_paletteram_enab = 1; // for brickzn11
m_paletteram_enab = 1; // for brickzn11
m_remap_sound = 0;
membank("bank1")->set_entry(0);
}
@ -2015,12 +2015,12 @@ static MACHINE_CONFIG_START( brickzn11, suna8_state )
/* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SOUND_ADD("ymsnd", YM3812, SUNA8_MASTER_CLOCK / 8) // 3MHz (measured)
MCFG_SOUND_ADD("ymsnd", YM3812, SUNA8_MASTER_CLOCK / 8) // 3MHz (measured)
MCFG_YM3812_IRQ_HANDLER(INPUTLINE("audiocpu", 0))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
MCFG_SOUND_ADD("aysnd", AY8910, SUNA8_MASTER_CLOCK / 16) // 1.5MHz (measured)
MCFG_SOUND_ADD("aysnd", AY8910, SUNA8_MASTER_CLOCK / 16) // 1.5MHz (measured)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.33)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.33)

10
src/mame/drivers/supdrapo.c
View File

@ -82,13 +82,13 @@ public:
required_device<cpu_device> m_maincpu;
required_device<gfxdecode_device> m_gfxdecode;
required_device<palette_device> m_palette;
required_shared_ptr<UINT8> m_col_line;
required_shared_ptr<UINT8> m_videoram;
required_shared_ptr<UINT8> m_char_bank;
UINT8 m_wdog;
DECLARE_READ8_MEMBER(rng_r);
DECLARE_WRITE8_MEMBER(wdog8000_w);
DECLARE_WRITE8_MEMBER(debug8004_w);
@ -97,12 +97,12 @@ public:
DECLARE_WRITE8_MEMBER(payout_w);
DECLARE_WRITE8_MEMBER(ay8910_outputa_w);
DECLARE_WRITE8_MEMBER(ay8910_outputb_w);
virtual void machine_start();
virtual void machine_reset();
virtual void video_start();
DECLARE_PALETTE_INIT(supdrapo);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};

8
src/mame/drivers/supertnk.c
View File

@ -124,7 +124,7 @@ public:
DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_0_w);
DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_1_w);
DECLARE_DRIVER_INIT(supertnk);
virtual void machine_start();
virtual void machine_start();
virtual void machine_reset();
virtual void video_start();
UINT32 screen_update_supertnk(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@ -135,7 +135,7 @@ public:
void supertnk_state::machine_start()
{
membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x1000);
membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x1000);
}
@ -148,14 +148,14 @@ void supertnk_state::machine_start()
WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_0_w)
{
m_rom_bank = (m_rom_bank & 0x02) | ((data << 0) & 0x01);
membank("bank1")->set_entry(m_rom_bank);
membank("bank1")->set_entry(m_rom_bank);
}
WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_1_w)
{
m_rom_bank = (m_rom_bank & 0x01) | ((data << 1) & 0x02);
membank("bank1")->set_entry(m_rom_bank);
membank("bank1")->set_entry(m_rom_bank);
}

6
src/mame/drivers/superwng.c
View File

@ -10,7 +10,7 @@ Hardware a bit (interrupts, sound) similar to mouser as well
TODO:
- unused rom 6.8s (located on the pcb near the gfx rom 7.8p, but contains
data (similar to the one in roms 4.5p and 5.5r)
The game currently crashes after the bonus round rather than moving on to
the next level, it writes 01 to 0xa187 which is probably ROM bank, however
banking the ROM in there results in the game crashing anyway, and looking
@ -101,7 +101,7 @@ WRITE8_MEMBER(superwng_state::superwng_unk_a187_w)
WRITE8_MEMBER(superwng_state::superwng_unk_a185_w)
{
// printf("superwng_unk_a185_w %02x\n", data);
// printf("superwng_unk_a185_w %02x\n", data);
}
TILE_GET_INFO_MEMBER(superwng_state::get_bg_tile_info)
@ -456,7 +456,7 @@ void superwng_state::machine_start()
save_item(NAME(m_tile_bank));
save_item(NAME(m_sound_byte));
save_item(NAME(m_nmi_enable));
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base()+0x4000, 0x4000);
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base()+0x4000, 0x4000);
}
void superwng_state::machine_reset()

30
src/mame/drivers/suprgolf.c
View File

@ -60,7 +60,7 @@ public:
UINT8 m_palette_switch;
UINT8 m_bg_vreg_test;
UINT8 m_toggle;
DECLARE_READ8_MEMBER(videoram_r);
DECLARE_WRITE8_MEMBER(videoram_w);
DECLARE_READ8_MEMBER(bg_vram_r);
@ -78,14 +78,14 @@ public:
DECLARE_WRITE8_MEMBER(writeA);
DECLARE_WRITE8_MEMBER(writeB);
DECLARE_WRITE_LINE_MEMBER(adpcm_int);
TILE_GET_INFO_MEMBER(get_tile_info);
DECLARE_DRIVER_INIT(suprgolf);
virtual void machine_start();
virtual void machine_start();
virtual void machine_reset();
virtual void video_start();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
};
@ -109,7 +109,7 @@ void suprgolf_state::video_start()
m_fg_fb = auto_alloc_array(machine(), UINT16, 0x2000*0x20);
m_tilemap->set_transparent_pen(15);
save_item(NAME(m_bg_bank));
save_item(NAME(m_vreg_bank));
save_item(NAME(m_vreg_pen));
@ -267,9 +267,9 @@ WRITE8_MEMBER(suprgolf_state::bg_vram_w)
void suprgolf_state::machine_start()
{
membank("bank1")->configure_entries(0, 16, memregion("user2")->base(), 0x4000);
membank("bank2")->configure_entries(0, 64, memregion("user1")->base(), 0x4000);
membank("bank1")->configure_entries(0, 16, memregion("user2")->base(), 0x4000);
membank("bank2")->configure_entries(0, 64, memregion("user1")->base(), 0x4000);
save_item(NAME(m_rom_bank));
save_item(NAME(m_msm5205next));
save_item(NAME(m_msm_nmi_mask));
@ -293,11 +293,11 @@ READ8_MEMBER(suprgolf_state::rom_bank_select_r)
WRITE8_MEMBER(suprgolf_state::rom_bank_select_w)
{
m_rom_bank = data;
m_rom_bank = data;
//popmessage("%08x %02x",((data & 0x3f) * 0x4000),data);
//osd_printf_debug("ROM_BANK 0x8000 - %X @%X\n",data,space.device().safe_pcbase());
membank("bank2")->set_entry(data & 0x3f);
//popmessage("%08x %02x",((data & 0x3f) * 0x4000),data);
//osd_printf_debug("ROM_BANK 0x8000 - %X @%X\n",data,space.device().safe_pcbase());
membank("bank2")->set_entry(data & 0x3f);
m_msm_nmi_mask = data & 0x40;
flip_screen_set(data & 0x80);
@ -305,9 +305,9 @@ WRITE8_MEMBER(suprgolf_state::rom_bank_select_w)
WRITE8_MEMBER(suprgolf_state::rom2_bank_select_w)
{
//osd_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,space.device().safe_pcbase());
membank("bank1")->set_entry(data & 0x0f);
//osd_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,space.device().safe_pcbase());
membank("bank1")->set_entry(data & 0x0f);
if(data & 0xf0)
printf("Rom bank select 2 with data %02x activated\n",data);
}

4
src/mame/drivers/suprslam.c
View File

@ -115,7 +115,7 @@ WRITE8_MEMBER(suprslam_state::pending_command_clear_w)
WRITE8_MEMBER(suprslam_state::suprslam_sh_bankswitch_w)
{
membank("bank1")->set_entry(data & 0x03);
membank("bank1")->set_entry(data & 0x03);
}
/*** MEMORY MAPS *************************************************************/
@ -285,7 +285,7 @@ void suprslam_state::machine_start()
save_item(NAME(m_bg_bank));
save_item(NAME(m_pending_command));
membank("bank1")->configure_entries(0, 4, memregion("audiocpu")->base() + 0x10000, 0x8000);
membank("bank1")->configure_entries(0, 4, memregion("audiocpu")->base() + 0x10000, 0x8000);
}
void suprslam_state::machine_reset()

8
src/mame/drivers/tankbust.c
View File

@ -24,9 +24,9 @@ To do:
void tankbust_state::machine_start()
{
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000);
membank("bank2")->configure_entries(0, 2, memregion("maincpu")->base() + 0x18000, 0x2000);
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000);
membank("bank2")->configure_entries(0, 2, memregion("maincpu")->base() + 0x18000, 0x2000);
save_item(NAME(m_latch));
save_item(NAME(m_timer1));
save_item(NAME(m_e0xx_data));
@ -107,7 +107,7 @@ WRITE8_MEMBER(tankbust_state::e0xx_w)
case 7: /* 0xe007 bankswitch */
/* bank 1 at 0x6000-9fff = from 0x10000 when bit0=0 else from 0x14000 */
membank("bank1")->set_entry(data & 1);
membank("bank1")->set_entry(data & 1);
/* bank 2 at 0xa000-bfff = from 0x18000 when bit0=0 else from 0x1a000 */
membank("bank2")->set_entry(data & 1); /* verified (the game will reset after the "game over" otherwise) */

2
src/mame/drivers/taotaido.c
View File

@ -76,7 +76,7 @@ zooming might be wrong
void taotaido_state::machine_start()
{
membank("soundbank")->configure_entries(0, 4, memregion("audiocpu")->base(), 0x8000);
save_item(NAME(m_pending_command));
}

2
src/mame/drivers/tbowl.c
View File

@ -418,7 +418,7 @@ void tbowl_state::machine_start()
{
membank("mainbank")->configure_entries(0, 32, memregion("maincpu")->base() + 0x10000, 0x800);
membank("subbank")->configure_entries(0, 32, memregion("sub")->base() + 0x10000, 0x800);
save_item(NAME(m_adpcm_pos));
save_item(NAME(m_adpcm_end));
save_item(NAME(m_adpcm_data));

10
src/mame/drivers/tgtpanic.c
View File

@ -24,15 +24,15 @@ public:
required_device<cpu_device> m_maincpu;
required_device<screen_device> m_screen;
required_shared_ptr<UINT8> m_ram;
UINT8 m_color;
DECLARE_WRITE8_MEMBER(color_w);
virtual void machine_start();
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
};

2
src/mame/drivers/thunderx.c
View File

@ -317,7 +317,7 @@ WRITE8_MEMBER(thunderx_state::thunderx_1f98_w)
WRITE8_MEMBER(thunderx_state::scontra_bankswitch_w)
{
// bits 0-3 select ROM bank at 6000-7fff
m_rombank->set_entry(data & 0x0f);
m_rombank->set_entry(data & 0x0f);
// bit 4 selects work RAM or palette RAM at 5800-5fff
m_bank5800->set_bank((data & 0x10) >> 4);

4
src/mame/drivers/tryout.c
View File

@ -45,12 +45,12 @@ WRITE8_MEMBER(tryout_state::sound_irq_ack_w)
void tryout_state::machine_start()
{
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x2000);
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x2000);
}
WRITE8_MEMBER(tryout_state::bankswitch_w)
{
membank("bank1")->set_entry(data & 0x01);
membank("bank1")->set_entry(data & 0x01);
}
static ADDRESS_MAP_START( main_cpu, AS_PROGRAM, 8, tryout_state )

6
src/mame/drivers/tsamurai.c
View File

@ -711,7 +711,7 @@ static MACHINE_CONFIG_START( tsamurai, tsamurai_state )
MCFG_CPU_ADD("audio2", Z80, XTAL_24MHz/8)
MCFG_CPU_PROGRAM_MAP(sound2_map)
MCFG_MACHINE_START_OVERRIDE(tsamurai_state,tsamurai)
/* video hardware */
@ -752,7 +752,7 @@ static MACHINE_CONFIG_START( vsgongf, tsamurai_state )
MCFG_CPU_PROGRAM_MAP(sound_vsgongf_map)
MCFG_CPU_IO_MAP(vsgongf_audio_io_map)
MCFG_CPU_PERIODIC_INT_DRIVER(tsamurai_state, vsgongf_sound_interrupt, 3*60)
MCFG_MACHINE_START_OVERRIDE(tsamurai_state,vsgongf)
/* video hardware */
@ -797,7 +797,7 @@ static MACHINE_CONFIG_START( m660, tsamurai_state )
MCFG_CPU_PROGRAM_MAP(sound3_m660_map)
MCFG_CPU_IO_MAP(sound3_m660_io_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", tsamurai_state, nmi_line_pulse)
MCFG_MACHINE_START_OVERRIDE(tsamurai_state,m660)
/* video hardware */

57
src/mame/drivers/ttchamp.c
View File

@ -51,7 +51,7 @@ Dumped by tirino73
- works in a very similar way to 'Spider' (twins.c)
- works in a very similar way to 'Spider' (twins.c)
including the blitter (seems to be doubled up hardware tho, twice as many layers?)
- need to work out how it selects between upper/lower
program roms as blitter source
@ -85,7 +85,7 @@ public:
DECLARE_WRITE16_MEMBER(port20_w);
DECLARE_WRITE16_MEMBER(port62_w);
DECLARE_READ16_MEMBER(port1e_r);
@ -100,7 +100,7 @@ public:
DECLARE_WRITE16_MEMBER(ttchamp_mem_w);
UINT16 m_videoram0[0x10000 / 2];
// UINT16 m_videoram1[0x10000 / 2];
// UINT16 m_videoram1[0x10000 / 2];
UINT16 m_videoram2[0x10000 / 2];
@ -130,7 +130,6 @@ void ttchamp_state::machine_start()
void ttchamp_state::video_start()
{
}
UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
@ -143,7 +142,7 @@ UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16
bitmap.fill(m_palette->black_pen());
UINT8 *videoramfg;
UINT8* videorambg;
count=0;
videorambg = (UINT8*)m_videoram0;
videoramfg = (UINT8*)m_videoram2;
@ -156,21 +155,21 @@ UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16
count++;
}
}
/*
count=0;
videoram = (UINT8*)m_videoram1;
for (y=0;y<yyy;y++)
{
for(x=0;x<xxx;x++)
{
UINT8 pix = videoram[BYTE_XOR_LE(count)];
if (pix) bitmap.pix16(y, x) = pix+0x200;
count++;
}
for(x=0;x<xxx;x++)
{
UINT8 pix = videoram[BYTE_XOR_LE(count)];
if (pix) bitmap.pix16(y, x) = pix+0x200;
count++;
}
}
*/
count=0;
for (y=0;y<yyy;y++)
{
@ -204,7 +203,7 @@ UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16
count++;
}
}
#if 0
for (int i = 0; i < 0x8000; i++)
{
@ -212,11 +211,11 @@ UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16
// I think it actually does more blit operations with
// different bits of m_port10 set to redraw the backgrounds using the video ram data as a source rather than ROM - notice the garbage you see behind 'sprites' right now
// this method also removes the text layer, which we don't want
// m_videoram1[i] = 0x0000;
// m_videoram2[i] = 0x0000;
// m_videoram1[i] = 0x0000;
// m_videoram2[i] = 0x0000;
}
#endif
return 0;
}
@ -289,18 +288,18 @@ WRITE16_MEMBER(ttchamp_state::ttchamp_mem_w)
if (m_spritesinit == 1)
{
// printf("%06x: spider_blitter_w %08x %04x %04x (init?) (base?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
// printf("%06x: spider_blitter_w %08x %04x %04x (init?) (base?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
m_spritesinit = 2;
m_spritesaddr = offset;
}
else if (m_spritesinit == 2)
{
// printf("%06x: spider_blitter_w %08x %04x %04x (init2) (width?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
// printf("%06x: spider_blitter_w %08x %04x %04x (init2) (width?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
m_spriteswidth = offset & 0xff;
//printf("%08x\n",(offset*2) & 0xfff00);
m_spritesinit = 3;
}
else
@ -320,7 +319,7 @@ WRITE16_MEMBER(ttchamp_state::ttchamp_mem_w)
printf("blitter bus write but blitter unselected? %08x %04x\n",offset*2,data);
return;
}
m_spritesinit = 0;
// 0x30000-0x3ffff used, on Spider it's 0x20000-0x2ffff
@ -331,7 +330,7 @@ WRITE16_MEMBER(ttchamp_state::ttchamp_mem_w)
if (m_rombank)
src += 0x100000;
// printf("%06x: spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", space.device().safe_pc(), offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
// printf("%06x: spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", space.device().safe_pc(), offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
offset &= 0x7fff;
for (int i = 0; i < m_spriteswidth; i++)
@ -347,7 +346,7 @@ WRITE16_MEMBER(ttchamp_state::ttchamp_mem_w)
data = (src[(m_spritesaddr * 2) + 1]);
//data |= vram[offset] >> 8;
/* bit 1 actually enables transparent pen */
if (data || (m_port10 & 2) == 0)
vram[offset] = (vram[offset] & 0x00ff) | data << 8;
@ -397,7 +396,7 @@ WRITE16_MEMBER(ttchamp_state::port10_w)
{
UINT8 res;
COMBINE_DATA(&m_port10);
res = m_port10 & 0xf0;
/* Assume that both bits clears layers. */
if(res == 0x30)
@ -444,7 +443,7 @@ static ADDRESS_MAP_START( ttchamp_io, AS_IO, 16, ttchamp_state )
AM_RANGE(0x0020, 0x0021) AM_WRITE(port20_w)
// AM_RANGE(0x0034, 0x0035) AM_READ(peno_rand) AM_WRITENOP // eeprom (PIC?) / settings?
// AM_RANGE(0x0034, 0x0035) AM_READ(peno_rand) AM_WRITENOP // eeprom (PIC?) / settings?
AM_RANGE(0x0062, 0x0063) AM_WRITE(port62_w)
@ -577,9 +576,9 @@ ROM_END
DRIVER_INIT_MEMBER(ttchamp_state,ttchamp)
{
// UINT8 *ROM1 = memregion("user1")->base();
// membank("bank1")->set_base(&ROM1[0x100000]);
// membank("bank2")->set_base(&ROM1[0x180000]);
// UINT8 *ROM1 = memregion("user1")->base();
// membank("bank1")->set_base(&ROM1[0x100000]);
// membank("bank2")->set_base(&ROM1[0x180000]);
}
GAME( 1995, ttchamp, 0, ttchamp, ttchamp, ttchamp_state, ttchamp, ROT0, "Gamart", "Table Tennis Champions", GAME_NOT_WORKING ) // this has various advertising boards, including 'Electronic Devices' and 'Deniam'

10
src/mame/drivers/tugboat.c
View File

@ -49,7 +49,7 @@ public:
required_device<gfxdecode_device> m_gfxdecode;
required_device<screen_device> m_screen;
required_device<palette_device> m_palette;
required_shared_ptr<UINT8> m_ram;
UINT8 m_hd46505_0_reg[18];
@ -58,18 +58,18 @@ public:
int m_reg1;
int m_ctrl;
emu_timer *m_interrupt_timer;
DECLARE_WRITE8_MEMBER(hd46505_0_w);
DECLARE_WRITE8_MEMBER(hd46505_1_w);
DECLARE_WRITE8_MEMBER(score_w);
DECLARE_READ8_MEMBER(input_r);
DECLARE_WRITE8_MEMBER(ctrl_w);
virtual void machine_start();
virtual void video_start();
virtual void machine_reset();
DECLARE_PALETTE_INIT(tugboat);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
void draw_tilemap(bitmap_ind16 &bitmap,const rectangle &cliprect,
int addr,int gfx0,int gfx1,int transparency);
@ -82,7 +82,7 @@ protected:
void tugboat_state::machine_start()
{
m_interrupt_timer = timer_alloc(TIMER_INTERRUPT);
save_item(NAME(m_hd46505_0_reg));
save_item(NAME(m_hd46505_1_reg));
save_item(NAME(m_reg0));

34
src/mame/drivers/twins.c
View File

@ -123,15 +123,15 @@ void twins_state::machine_start()
READ16_MEMBER(twins_state::twins_port4_r)
{
// doesn't work??
// printf("%08x: twins_port4_r %04x\n", space.device().safe_pc(), mem_mask);
// return m_i2cmem->read_sda();// | 0xfffe;
// printf("%08x: twins_port4_r %04x\n", space.device().safe_pc(), mem_mask);
// return m_i2cmem->read_sda();// | 0xfffe;
return 0x0001;
}
WRITE16_MEMBER(twins_state::twins_port4_w)
{
// printf("%08x: twins_port4_w %04x %04x\n", space.device().safe_pc(), data, mem_mask);
// printf("%08x: twins_port4_w %04x %04x\n", space.device().safe_pc(), data, mem_mask);
int i2c_clk = BIT(data, 1);
int i2c_mem = BIT(data, 0);
m_i2cmem->write_scl(i2c_clk);
@ -165,7 +165,7 @@ WRITE16_MEMBER(twins_state::twins_pal_w)
/* ??? weird ..*/
WRITE16_MEMBER(twins_state::porte_paloff0_w)
{
// printf("porte_paloff0_w %04x\n", data);
// printf("porte_paloff0_w %04x\n", data);
m_paloff = 0;
}
@ -205,14 +205,14 @@ WRITE16_MEMBER(twins_state::spider_blitter_w)
if (m_spritesinit == 1)
{
// printf("spider_blitter_w %08x %04x %04x (init?) (base?)\n", offset * 2, data, mem_mask);
// printf("spider_blitter_w %08x %04x %04x (init?) (base?)\n", offset * 2, data, mem_mask);
m_spritesinit = 2;
m_spritesaddr = offset;
}
else if (m_spritesinit == 2)
{
// printf("spider_blitter_w %08x %04x %04x (init2) (width?)\n", offset * 2, data, mem_mask);
// printf("spider_blitter_w %08x %04x %04x (init2) (width?)\n", offset * 2, data, mem_mask);
m_spriteswidth = offset & 0xff;
if (m_spriteswidth == 0)
m_spriteswidth = 80;
@ -234,26 +234,26 @@ WRITE16_MEMBER(twins_state::spider_blitter_w)
{
UINT8 *src = m_rom8;
// printf("spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
// printf("spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
offset &= 0x7fff;
for (int i = 0; i < m_spriteswidth; i++)
{
UINT8 data;
data = (src[(m_spritesaddr * 2) + 1]);
if (data)
vram[offset] = (vram[offset] & 0x00ff) | data << 8;
data = src[(m_spritesaddr*2)];
if (data)
vram[offset] = (vram[offset] & 0xff00) | data;
m_spritesaddr ++;
m_spritesaddr ++;
offset++;
offset &= 0x7fff;
@ -386,7 +386,7 @@ static MACHINE_CONFIG_START( twins, twins_state )
MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 200-1)
MCFG_SCREEN_UPDATE_DRIVER(twins_state, screen_update_twins)
MCFG_SCREEN_PALETTE("palette")
MCFG_24C02_ADD("i2cmem")
MCFG_PALETTE_ADD("palette", 0x100)
@ -447,7 +447,7 @@ static MACHINE_CONFIG_START( twinsa, twins_state )
MCFG_PALETTE_ADD("palette", 256)
MCFG_RAMDAC_ADD("ramdac", ramdac_map, "palette")
MCFG_RAMDAC_SPLIT_READ(0)
MCFG_24C02_ADD("i2cmem")
MCFG_VIDEO_START_OVERRIDE(twins_state,twinsa)
@ -477,9 +477,9 @@ WRITE16_MEMBER(twins_state::spider_pal_w)
}
else
{
// printf("first palette write %04x\n", data);
// printf("first palette write %04x\n", data);
}
m_paloff++;
if (m_paloff == 0x101)
@ -503,7 +503,7 @@ WRITE16_MEMBER(twins_state::spider_port_1c_w)
{
// done before the 'sprite' read / writes
// might clear a buffer?
// game is only animating sprites at 30fps, maybe there's some double buffering too?
UINT16* vram;
@ -575,7 +575,7 @@ static MACHINE_CONFIG_START( spider, twins_state )
MCFG_PALETTE_ADD("palette", 0x100)
MCFG_VIDEO_START_OVERRIDE(twins_state,twins)
MCFG_24C02_ADD("i2cmem")
/* sound hardware */

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