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Cleanups and version bump

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This commit is contained in:
Miodrag Milanovic 2015-03-25 08:16:51 +01:00
parent fda60d87eb
commit 0147bb4cc8
206 changed files with 1714 additions and 1733 deletions
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4
hash/nes.xml
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@ -57391,7 +57391,7 @@ preliminary proto for the PAL version, still running on NTSC systems) or the gfx
<publisher>Union Bond</publisher> <publisher>Union Bond</publisher>
<info name="serial" value="G-0005"/> <info name="serial" value="G-0005"/>
<part name="cart" interface="nes_cart"> <part name="cart" interface="nes_cart">
<feature name="slot" value="nanjing" /> <!-- header actually says 164... --> <feature name="slot" value="nanjing" /> <!-- header actually says 164... -->
<feature name="pcb" value="UNL-NANJING" /> <feature name="pcb" value="UNL-NANJING" />
<dataarea name="prg" size="524288"> <dataarea name="prg" size="524288">
<rom name="ying tao xiao wan zi (g-005) (ch).prg" size="524288" crc="8209ba79" sha1="fa56608d8dcf5a144dd1fc81282cd86fd51060fe" offset="00000" status="baddump" /> <rom name="ying tao xiao wan zi (g-005) (ch).prg" size="524288" crc="8209ba79" sha1="fa56608d8dcf5a144dd1fc81282cd86fd51060fe" offset="00000" status="baddump" />
@ -75420,7 +75420,7 @@ be better to redump them properly. -->
<year>19??</year> <year>19??</year>
<publisher>&lt;unknown&gt;</publisher> <publisher>&lt;unknown&gt;</publisher>
<part name="cart" interface="nes_cart"> <part name="cart" interface="nes_cart">
<feature name="slot" value="fk23ca" /> <!-- UNIF header pointed to FK23C, but the menu does not appear with that mapper... investigate! --> <feature name="slot" value="fk23ca" /> <!-- UNIF header pointed to FK23C, but the menu does not appear with that mapper... investigate! -->
<feature name="pcb" value="BMC-FK23C" /> <feature name="pcb" value="BMC-FK23C" />
<dataarea name="prg" size="8388608"> <dataarea name="prg" size="8388608">
<rom name="120-in-1 (unl)[u].prg" size="8388608" crc="678de5aa" sha1="01da22ddf1897b47d6b03ecb4ff0c093f9b39dfc" offset="00000" status="baddump" /> <rom name="120-in-1 (unl)[u].prg" size="8388608" crc="678de5aa" sha1="01da22ddf1897b47d6b03ecb4ff0c093f9b39dfc" offset="00000" status="baddump" />

5
src/emu/bus/a2bus/ezcgi.c
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@ -43,7 +43,7 @@ MACHINE_CONFIG_END
#define MSX2_VISIBLE_YBORDER_PIXELS 14 * 2 #define MSX2_VISIBLE_YBORDER_PIXELS 14 * 2
MACHINE_CONFIG_FRAGMENT( ezcgi9938 ) MACHINE_CONFIG_FRAGMENT( ezcgi9938 )
MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM MCFG_V9938_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9938_device, tms_irq_w)) MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9938_device, tms_irq_w))
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER) MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
@ -57,7 +57,7 @@ MACHINE_CONFIG_FRAGMENT( ezcgi9938 )
MACHINE_CONFIG_END MACHINE_CONFIG_END
MACHINE_CONFIG_FRAGMENT( ezcgi9958 ) MACHINE_CONFIG_FRAGMENT( ezcgi9958 )
MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM MCFG_V9958_ADD(TMS_TAG, SCREEN_TAG, 0x30000) // 192K of VRAM
MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9958_device, tms_irq_w)) MCFG_V99X8_INTERRUPT_CALLBACK(WRITELINE(a2bus_ezcgi_9958_device, tms_irq_w))
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER) MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
@ -311,4 +311,3 @@ WRITE_LINE_MEMBER( a2bus_ezcgi_9958_device::tms_irq_w )
lower_slot_irq(); lower_slot_irq();
} }
} }

4
src/emu/bus/scsi/omti5100.c
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@ -20,8 +20,8 @@ const rom_entry *omti5100_device::device_rom_region() const
omti5100_device::omti5100_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) omti5100_device::omti5100_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: scsihd_device(mconfig, OMTI5100, "OMTI 5100", tag, owner, clock, "omti5100", __FILE__), : scsihd_device(mconfig, OMTI5100, "OMTI 5100", tag, owner, clock, "omti5100", __FILE__),
m_image0(*this, "image0"), m_image0(*this, "image0"),
m_image1(*this, "image1") m_image1(*this, "image1")
{ {
} }

2
src/emu/cpu/i386/i386ops.h
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@ -333,7 +333,7 @@ const i386_device::X86_OPCODE i386_device::s_x86_opcode_table[] =
{ 0x3B, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false}, { 0x3B, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
{ 0x3C, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false}, { 0x3C, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
{ 0x3D, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false}, { 0x3D, OP_2BYTE|OP_CYRIX, &i386_device::i386_cyrix_special, &i386_device::i386_cyrix_special, false},
{ 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false}, { 0x40, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovo_r16_rm16, &i386_device::pentium_cmovo_r32_rm32, false},
{ 0x41, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovno_r16_rm16, &i386_device::pentium_cmovno_r32_rm32, false}, { 0x41, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovno_r16_rm16, &i386_device::pentium_cmovno_r32_rm32, false},
{ 0x42, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovb_r16_rm16, &i386_device::pentium_cmovb_r32_rm32, false}, { 0x42, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovb_r16_rm16, &i386_device::pentium_cmovb_r32_rm32, false},
{ 0x43, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovae_r16_rm16, &i386_device::pentium_cmovae_r32_rm32, false}, { 0x43, OP_2BYTE|OP_PENTIUM, &i386_device::pentium_cmovae_r16_rm16, &i386_device::pentium_cmovae_r32_rm32, false},

8
src/emu/cpu/i386/pentops.inc
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@ -1065,10 +1065,10 @@ void i386_device::pentium_movnti_m32_r32() // Opcode 0f c3
void i386_device::i386_cyrix_special() // Opcode 0x0f 3a-3d void i386_device::i386_cyrix_special() // Opcode 0x0f 3a-3d
{ {
/* /*
0f 3a BB0_RESET (set BB0 pointer = base) 0f 3a BB0_RESET (set BB0 pointer = base)
0f 3b BB1_RESET (set BB1 pointer = base) 0f 3b BB1_RESET (set BB1 pointer = base)
0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax) 0f 3c CPU_WRITE (write special CPU memory-mapped register, [ebx] = eax)
0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx]) 0f 3d CPU_READ (read special CPU memory-mapped register, eax, = [ebx])
*/ */
CYCLES(1); CYCLES(1);

33
src/emu/cpu/nec/v53.c
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@ -239,7 +239,6 @@ void v53_base_device::install_peripheral_io()
{ {
if (IOAG) // 8-bit if (IOAG) // 8-bit
{ {
} }
else else
{ {
@ -258,7 +257,6 @@ void v53_base_device::install_peripheral_io()
if (IOAG) // 8-bit if (IOAG) // 8-bit
{ {
} }
else else
{ {
@ -274,7 +272,6 @@ void v53_base_device::install_peripheral_io()
if (IOAG) // 8-bit if (IOAG) // 8-bit
{ {
} }
else else
{ {
@ -292,7 +289,6 @@ void v53_base_device::install_peripheral_io()
if (IOAG) // 8-bit if (IOAG) // 8-bit
{ {
} }
else else
{ {
@ -333,9 +329,9 @@ WRITE8_MEMBER(v53_base_device::tmu_tct2_w) { m_v53tcu->write(space, 2, data); }
WRITE8_MEMBER(v53_base_device::tmu_tmd_w) { m_v53tcu->write(space, 3, data); } WRITE8_MEMBER(v53_base_device::tmu_tmd_w) { m_v53tcu->write(space, 3, data); }
READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); } READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(space, 0); }
READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); } READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(space, 1); }
READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); } READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(space, 2); }
@ -409,20 +405,20 @@ WRITE_LINE_MEMBER(v53_base_device::hack_w)
static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device ) static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BSEL_w, 0x00ff) // 0xffe0 // uPD71037 DMA mode bank selection register
AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA) AM_RANGE(0xffe0, 0xffe1) AM_WRITE8( BADR_w, 0xff00) // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA)
// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2 // AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2
// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3 // AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3
// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4 // AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4
// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5 // AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5
// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6 // AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6
// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7 // AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7
// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8 // AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8
AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral) AM_RANGE(0xffe8, 0xffe9) AM_WRITE8( BRC_w , 0xff00) // 0xffe9 // baud rate counter (used for serial peripheral)
AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WMB0_w, 0x00ff) // 0xffea // waitstate control
AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control AM_RANGE(0xffea, 0xffeb) AM_WRITE8( WCY1_w, 0xff00) // 0xffeb // waitstate control
AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control AM_RANGE(0xffec, 0xffed) AM_WRITE8( WCY0_w, 0x00ff) // 0xffec // waitstate control
AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control AM_RANGE(0xffec, 0xffed) AM_WRITE8( WAC_w, 0xff00) // 0xffed // waitstate control
// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee // AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee
// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef // AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef
AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( TCKS_w, 0x00ff) // 0xfff0 // timer clocks
AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc. AM_RANGE(0xfff0, 0xfff1) AM_WRITE8( SBCR_w, 0xff00) // 0xfff1 // internal clock divider, halt behavior etc.
AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control AM_RANGE(0xfff2, 0xfff3) AM_WRITE8( REFC_w, 0x00ff) // 0xfff2 // ram refresh control
@ -430,7 +426,7 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY2_w, 0x00ff) // 0xfff4 // waitstate control
AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control AM_RANGE(0xfff4, 0xfff5) AM_WRITE8( WCY3_w, 0xff00) // 0xfff5 // waitstate control
AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control AM_RANGE(0xfff6, 0xfff7) AM_WRITE8( WCY4_w, 0x00ff) // 0xfff6 // waitstate control
// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7 // AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7
AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( SULA_w, 0x00ff) // 0xfff8 // peripheral mapping
AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping AM_RANGE(0xfff8, 0xfff9) AM_WRITE8( TULA_w, 0xff00) // 0xfff9 // peripheral mapping
AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping AM_RANGE(0xfffa, 0xfffb) AM_WRITE8( IULA_w, 0x00ff) // 0xfffa // peripheral mapping
@ -438,7 +434,7 @@ static ADDRESS_MAP_START( v53_internal_port_map, AS_IO, 16, v53_base_device )
AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common) AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPHA_w, 0x00ff) // 0xfffc // peripheral mapping (upper bits, common)
AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling AM_RANGE(0xfffc, 0xfffd) AM_WRITE8( OPSEL_w, 0xff00) // 0xfffd // peripheral enabling
AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping) AM_RANGE(0xfffe, 0xffff) AM_WRITE8( SCTL_w, 0x00ff) // 0xfffe // peripheral configuration (& byte / word mapping)
// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff // AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff
ADDRESS_MAP_END ADDRESS_MAP_END
@ -578,4 +574,3 @@ v53a_device::v53a_device(const machine_config &mconfig, const char *tag, device_
: v53_base_device(mconfig, V53A, "V53A", tag, owner, clock, "v53a", BYTE_XOR_LE(0), 6, 1, V33_TYPE) : v53_base_device(mconfig, V53A, "V53A", tag, owner, clock, "v53a", BYTE_XOR_LE(0), 6, 1, V33_TYPE)
{ {
} }

26
src/emu/cpu/nec/v53.h
View File

@ -151,10 +151,10 @@ public:
template<class _Object> static devcb_base &set_syndet_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_syndet_handler.set_callback(object); } template<class _Object> static devcb_base &set_syndet_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_syndet_handler.set_callback(object); }
DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */ DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */ DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); }
DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); } DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); }
// TCU // TCU
@ -165,9 +165,9 @@ public:
DECLARE_READ8_MEMBER(tmu_tst2_r); DECLARE_READ8_MEMBER(tmu_tst2_r);
DECLARE_WRITE8_MEMBER(tmu_tct2_w); DECLARE_WRITE8_MEMBER(tmu_tct2_w);
DECLARE_WRITE8_MEMBER(tmu_tmd_w); DECLARE_WRITE8_MEMBER(tmu_tmd_w);
// static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; } // static void set_clk0(device_t &device, double clk0) { downcast<v53_base_device &>(device).m_clk0 = clk0; }
// static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; } // static void set_clk1(device_t &device, double clk1) { downcast<v53_base_device &>(device).m_clk1 = clk1; }
// static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; } // static void set_clk2(device_t &device, double clk2) { downcast<v53_base_device &>(device).m_clk2 = clk2; }
template<class _Object> static devcb_base &set_out0_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out0_handler.set_callback(object); } template<class _Object> static devcb_base &set_out0_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out0_handler.set_callback(object); }
template<class _Object> static devcb_base &set_out1_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out1_handler.set_callback(object); } template<class _Object> static devcb_base &set_out1_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out1_handler.set_callback(object); }
template<class _Object> static devcb_base &set_out2_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out2_handler.set_callback(object); } template<class _Object> static devcb_base &set_out2_handler(device_t &device, _Object object) { return downcast<v53_base_device &>(device).m_out2_handler.set_callback(object); }
@ -195,7 +195,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(hreq_trampoline_cb) { m_out_hreq_cb(state); } DECLARE_WRITE_LINE_MEMBER(hreq_trampoline_cb) { m_out_hreq_cb(state); }
DECLARE_WRITE_LINE_MEMBER(eop_trampoline_cb) { m_out_eop_cb(state); } DECLARE_WRITE_LINE_MEMBER(eop_trampoline_cb) { m_out_eop_cb(state); }
DECLARE_READ8_MEMBER(dma_memr_trampoline_r) { return m_in_memr_cb(space, offset); } DECLARE_READ8_MEMBER(dma_memr_trampoline_r) { return m_in_memr_cb(space, offset); }
DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); } DECLARE_WRITE8_MEMBER(dma_memw_trampoline_w) { m_out_memw_cb(space, offset, data); }
DECLARE_READ8_MEMBER(dma_io_0_trampoline_r) { return m_in_ior_0_cb(space, offset); } DECLARE_READ8_MEMBER(dma_io_0_trampoline_r) { return m_in_ior_0_cb(space, offset); }
DECLARE_READ8_MEMBER(dma_io_1_trampoline_r) { return m_in_ior_1_cb(space, offset); } DECLARE_READ8_MEMBER(dma_io_1_trampoline_r) { return m_in_ior_1_cb(space, offset); }
DECLARE_READ8_MEMBER(dma_io_2_trampoline_r) { return m_in_ior_2_cb(space, offset); } DECLARE_READ8_MEMBER(dma_io_2_trampoline_r) { return m_in_ior_2_cb(space, offset); }
@ -204,10 +204,10 @@ public:
DECLARE_WRITE8_MEMBER(dma_io_1_trampoline_w) { m_out_iow_1_cb(space, offset, data); } DECLARE_WRITE8_MEMBER(dma_io_1_trampoline_w) { m_out_iow_1_cb(space, offset, data); }
DECLARE_WRITE8_MEMBER(dma_io_2_trampoline_w) { m_out_iow_2_cb(space, offset, data); } DECLARE_WRITE8_MEMBER(dma_io_2_trampoline_w) { m_out_iow_2_cb(space, offset, data); }
DECLARE_WRITE8_MEMBER(dma_io_3_trampoline_w) { m_out_iow_3_cb(space, offset, data); } DECLARE_WRITE8_MEMBER(dma_io_3_trampoline_w) { m_out_iow_3_cb(space, offset, data); }
DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); } DECLARE_WRITE_LINE_MEMBER(dma_dack0_trampoline_w) { m_out_dack_0_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); } DECLARE_WRITE_LINE_MEMBER(dma_dack1_trampoline_w) { m_out_dack_1_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); } DECLARE_WRITE_LINE_MEMBER(dma_dack2_trampoline_w) { m_out_dack_2_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); } DECLARE_WRITE_LINE_MEMBER(dma_dack3_trampoline_w) { m_out_dack_3_cb(state); }
DECLARE_WRITE_LINE_MEMBER(dreq0_w); DECLARE_WRITE_LINE_MEMBER(dreq0_w);
@ -260,9 +260,9 @@ protected:
devcb_write_line m_syndet_handler; devcb_write_line m_syndet_handler;
// TCU // TCU
// double m_clk0; // double m_clk0;
// double m_clk1; // double m_clk1;
// double m_clk2; // double m_clk2;
devcb_write_line m_out0_handler; devcb_write_line m_out0_handler;
devcb_write_line m_out1_handler; devcb_write_line m_out1_handler;
devcb_write_line m_out2_handler; devcb_write_line m_out2_handler;

12
src/emu/cpu/z80/kl5c80a12.c
View File

@ -1,13 +1,13 @@
/*************************************************************************** /***************************************************************************
Kawasaki LSI Kawasaki LSI
KL5C80A12 CPU (KL5C80A12CFP on hng64.c) KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
(is this different enough to need it's own core?) (is this different enough to need it's own core?)
(todo: everything, some code currently lives in machine/hng64_net.c but not much) (todo: everything, some code currently lives in machine/hng64_net.c but not much)
***************************************************************************/ ***************************************************************************/

12
src/emu/cpu/z80/kl5c80a12.h
View File

@ -1,13 +1,13 @@
/*************************************************************************** /***************************************************************************
Kawasaki LSI Kawasaki LSI
KL5C80A12 CPU (KL5C80A12CFP on hng64.c) KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller Timers / Counters, Parrallel / Serial ports/ MMU, Interrupt Controller
(is this different enough to need it's own core?) (is this different enough to need it's own core?)
(todo: everything, some code currently lives in machine/hng64_net.c but not much) (todo: everything, some code currently lives in machine/hng64_net.c but not much)
***************************************************************************/ ***************************************************************************/

32
src/emu/machine/am9517a.c
View File

@ -3,15 +3,15 @@
/*************************************************************************** /***************************************************************************
AMD AM9517A AMD AM9517A
Intel 8237A Intel 8237A
NEC uPD71037 NEC uPD71037
NEC uPD71071 (extended version of above) NEC uPD71071 (extended version of above)
a variant is used in the V53 CPU which offers subsets of both the a variant is used in the V53 CPU which offers subsets of both the
uPD71071 and uPD71037 functionality depending on a mode bit. uPD71071 and uPD71037 functionality depending on a mode bit.
Multimode DMA Controller emulation Multimode DMA Controller emulation
Copyright the MESS Team. Copyright the MESS Team.
Visit http://mamedev.org for licensing and usage restrictions. Visit http://mamedev.org for licensing and usage restrictions.
@ -28,17 +28,17 @@
/* /*
When the V53 operates in uPD71071 compatible mode there are the following When the V53 operates in uPD71071 compatible mode there are the following
differences from a real uPD71071 differences from a real uPD71071
V53 Real uPD71071 V53 Real uPD71071
Software Reqs No Yes Software Reqs No Yes
Memory-to-Memory DMA No Yes Memory-to-Memory DMA No Yes
DMARQ active level High programmable DMARQ active level High programmable
DMAAK active level Low programmable DMAAK active level Low programmable
Bus Cycle 4 4 or 3 Bus Cycle 4 4 or 3
we don't currently handle the differences we don't currently handle the differences
*/ */
@ -1194,7 +1194,7 @@ WRITE8_MEMBER(upd71071_v53_device::write)
// TODO: reset (bit 0) // TODO: reset (bit 0)
//m_buswidth = data & 0x02; //m_buswidth = data & 0x02;
//if (data & 0x01) //if (data & 0x01)
// soft_reset(); // soft_reset();
logerror("DMA: Initialise [%02x]\n", data); logerror("DMA: Initialise [%02x]\n", data);
break; break;
case 0x01: // Channel case 0x01: // Channel

2
src/emu/machine/am9517a.h
View File

@ -172,7 +172,7 @@ protected:
virtual void device_start(); virtual void device_start();
virtual void device_reset(); virtual void device_reset();
int m_selected_channel; int m_selected_channel;
int m_base; int m_base;
UINT8 m_command_high; UINT8 m_command_high;

132
src/emu/machine/i8251.c
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@ -3,10 +3,10 @@
i8251.c i8251.c
Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter code Intel 8251 Universal Synchronous/Asynchronous Receiver Transmitter code
NEC uPD71051 is a clone NEC uPD71051 is a clone
The V53/V53A use a customized version with only the Asynchronous mode The V53/V53A use a customized version with only the Asynchronous mode
and a split command / mode register and a split command / mode register
@ -428,29 +428,29 @@ WRITE8_MEMBER(i8251_device::command_w)
/* bit 7: /* bit 7:
0 = normal operation 0 = normal operation
1 = hunt mode 1 = hunt mode
bit 6: bit 6:
0 = normal operation 0 = normal operation
1 = internal reset 1 = internal reset
bit 5: bit 5:
0 = /RTS set to 1 0 = /RTS set to 1
1 = /RTS set to 0 1 = /RTS set to 0
bit 4: bit 4:
0 = normal operation 0 = normal operation
1 = reset error flag 1 = reset error flag
bit 3: bit 3:
0 = normal operation 0 = normal operation
1 = send break character 1 = send break character
bit 2: bit 2:
0 = receive disable 0 = receive disable
1 = receive enable 1 = receive enable
bit 1: bit 1:
0 = /DTR set to 1 0 = /DTR set to 1
1 = /DTR set to 0 1 = /DTR set to 0
bit 0: bit 0:
0 = transmit disable 0 = transmit disable
1 = transmit enable 1 = transmit enable
*/ */
m_rts_handler(!BIT(data, 5)); m_rts_handler(!BIT(data, 5));
@ -484,28 +484,28 @@ WRITE8_MEMBER(i8251_device::mode_w)
{ {
/* Asynchronous /* Asynchronous
bit 7,6: stop bit length bit 7,6: stop bit length
0 = inhibit 0 = inhibit
1 = 1 bit 1 = 1 bit
2 = 1.5 bits 2 = 1.5 bits
3 = 2 bits 3 = 2 bits
bit 5: parity type bit 5: parity type
0 = parity odd 0 = parity odd
1 = parity even 1 = parity even
bit 4: parity test enable bit 4: parity test enable
0 = disable 0 = disable
1 = enable 1 = enable
bit 3,2: character length bit 3,2: character length
0 = 5 bits 0 = 5 bits
1 = 6 bits 1 = 6 bits
2 = 7 bits 2 = 7 bits
3 = 8 bits 3 = 8 bits
bit 1,0: baud rate factor bit 1,0: baud rate factor
0 = defines command byte for synchronous or asynchronous 0 = defines command byte for synchronous or asynchronous
1 = x1 1 = x1
2 = x16 2 = x16
3 = x64 3 = x64
*/ */
LOG(("I8251: Asynchronous operation\n")); LOG(("I8251: Asynchronous operation\n"));
@ -597,24 +597,24 @@ WRITE8_MEMBER(i8251_device::mode_w)
else else
{ {
/* bit 7: Number of sync characters /* bit 7: Number of sync characters
0 = 1 character 0 = 1 character
1 = 2 character 1 = 2 character
bit 6: Synchronous mode bit 6: Synchronous mode
0 = Internal synchronisation 0 = Internal synchronisation
1 = External synchronisation 1 = External synchronisation
bit 5: parity type bit 5: parity type
0 = parity odd 0 = parity odd
1 = parity even 1 = parity even
bit 4: parity test enable bit 4: parity test enable
0 = disable 0 = disable
1 = enable 1 = enable
bit 3,2: character length bit 3,2: character length
0 = 5 bits 0 = 5 bits
1 = 6 bits 1 = 6 bits
2 = 7 bits 2 = 7 bits
3 = 8 bits 3 = 8 bits
bit 1,0 = 0 bit 1,0 = 0
*/ */
LOG(("I8251: Synchronous operation\n")); LOG(("I8251: Synchronous operation\n"));
/* setup for sync byte(s) */ /* setup for sync byte(s) */

2
src/emu/machine/i8257.c
View File

@ -79,7 +79,7 @@ inline void i8257_device::dma_request(int channel, int state)
} }
else else
{ {
m_request &= ~(1 << channel); m_request &= ~(1 << channel);
} }
trigger(1); trigger(1);
} }

8
src/emu/machine/upd71071.c
View File

@ -1,7 +1,7 @@
/* /*
am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it am9517a.c is a more complete implementation of this, the uPD71071 appears to be a clone of it
NEC uPD71071 DMA Controller NEC uPD71071 DMA Controller
Used on the Fujitsu FM-Towns Used on the Fujitsu FM-Towns
@ -31,8 +31,8 @@
Self-explanatory, I hope. :) Self-explanatory, I hope. :)
NOTE: Datasheet clearly shows this as 24-bit, with register 7 unused. NOTE: Datasheet clearly shows this as 24-bit, with register 7 unused.
But the FM-Towns definitely uses reg 7 as bits 24-31. But the FM-Towns definitely uses reg 7 as bits 24-31.
The documentation on the V53A manual doesn't show these bits either, maybe it's The documentation on the V53A manual doesn't show these bits either, maybe it's
an external connection on the FMT? might be worth checking overflow behavior etc. an external connection on the FMT? might be worth checking overflow behavior etc.
0x08: 0x08:
0x09: Device Control register (16-bit) 0x09: Device Control register (16-bit)
@ -78,7 +78,7 @@
bit 0-3: DMARQ mask bit 0-3: DMARQ mask
bits 1 and 0 only in MTM transfers bits 1 and 0 only in MTM transfers
Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways Note, the uPD71071 compatible mode of the V53 CPU differs from a real uPD71071 in the following ways

1
src/emu/machine/vrc4373.c
View File

@ -341,4 +341,3 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
} }
} }

10
src/emu/machine/vrc4373.h
View File

@ -12,11 +12,11 @@
#define VRC4373_PAGESHIFT 12 #define VRC4373_PAGESHIFT 12
/* NILE 3 registers 0x000-0x0ff */ /* NILE 3 registers 0x000-0x0ff */
#define NREG_BMCR (0x000/4) #define NREG_BMCR (0x000/4)
#define NREG_SIMM1 (0x004/4) #define NREG_SIMM1 (0x004/4)
#define NREG_SIMM2 (0x008/4) #define NREG_SIMM2 (0x008/4)
#define NREG_SIMM3 (0x00C/4) #define NREG_SIMM3 (0x00C/4)
#define NREG_SIMM4 (0x010/4) #define NREG_SIMM4 (0x010/4)
#define NREG_PCIMW1 (0x014/4) #define NREG_PCIMW1 (0x014/4)
#define NREG_PCIMW2 (0x018/4) #define NREG_PCIMW2 (0x018/4)
#define NREG_PCITW1 (0x01C/4) #define NREG_PCITW1 (0x01C/4)

6
src/emu/render.c
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@ -2494,13 +2494,13 @@ float render_manager::ui_aspect(render_container *rc)
orient = orientation_add(m_ui_target->orientation(), m_ui_container->orientation()); orient = orientation_add(m_ui_target->orientation(), m_ui_container->orientation());
// based on the orientation of the target, compute height/width or width/height // based on the orientation of the target, compute height/width or width/height
if (!(orient & ORIENTATION_SWAP_XY)) if (!(orient & ORIENTATION_SWAP_XY))
aspect = (float)m_ui_target->height() / (float)m_ui_target->width(); aspect = (float)m_ui_target->height() / (float)m_ui_target->width();
else else
aspect = (float)m_ui_target->width() / (float)m_ui_target->height(); aspect = (float)m_ui_target->width() / (float)m_ui_target->height();
// if we have a valid pixel aspect, apply that and return // if we have a valid pixel aspect, apply that and return
if (m_ui_target->pixel_aspect() != 0.0f) if (m_ui_target->pixel_aspect() != 0.0f)
return (aspect / m_ui_target->pixel_aspect()); return (aspect / m_ui_target->pixel_aspect());
} else { } else {
// single screen container // single screen container

40
src/emu/sound/es1373.h
View File

@ -9,26 +9,26 @@
MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371) MCFG_PCI_DEVICE_ADD(_tag, ES1373, 0x12741371, 0x04, 0x040100, 0x12741371)
/* Ensonic ES1373 registers 0x00-0x3f */ /* Ensonic ES1373 registers 0x00-0x3f */
#define ES_INT_CS_CTRL (0x00/4) #define ES_INT_CS_CTRL (0x00/4)
#define ES_INT_CS_STATUS (0x04/4) #define ES_INT_CS_STATUS (0x04/4)
#define ES_UART_DATA (0x08/4) #define ES_UART_DATA (0x08/4)
#define ES_UART_STATUS (0x09/4) #define ES_UART_STATUS (0x09/4)
#define ES_UART_CTRL (0x09/4) #define ES_UART_CTRL (0x09/4)
#define ES_UART_RSVD (0x0A/4) #define ES_UART_RSVD (0x0A/4)
#define ES_MEM_PAGE (0x0C/4) #define ES_MEM_PAGE (0x0C/4)
#define ES_SRC_IF (0x10/4) #define ES_SRC_IF (0x10/4)
#define ES_CODEC (0x14/4) #define ES_CODEC (0x14/4)
#define ES_LEGACY (0x18/4) #define ES_LEGACY (0x18/4)
#define ES_CHAN_CTRL (0x1C/4) #define ES_CHAN_CTRL (0x1C/4)
#define ES_SERIAL_CTRL (0x20/4) #define ES_SERIAL_CTRL (0x20/4)
#define ES_DAC1_CNT (0x24/4) #define ES_DAC1_CNT (0x24/4)
#define ES_DAC2_CNT (0x28/4) #define ES_DAC2_CNT (0x28/4)
#define ES_ADC_CNT (0x2C/4) #define ES_ADC_CNT (0x2C/4)
#define ES_ADC_CNT (0x2C/4) #define ES_ADC_CNT (0x2C/4)
#define ES_HOST_IF0 (0x30/4) #define ES_HOST_IF0 (0x30/4)
#define ES_HOST_IF1 (0x34/4) #define ES_HOST_IF1 (0x34/4)
#define ES_HOST_IF2 (0x38/4) #define ES_HOST_IF2 (0x38/4)
#define ES_HOST_IF3 (0x3C/4) #define ES_HOST_IF3 (0x3C/4)
struct frame_reg { struct frame_reg {
UINT32 pci_addr; UINT32 pci_addr;

2
src/emu/video.h
View File

@ -178,7 +178,7 @@ private:
UINT32 m_avi_frame; // current movie frame number UINT32 m_avi_frame; // current movie frame number
// movie recording - dummy // movie recording - dummy
bool m_dummy_recording; // indicates if snapshot should be created of every frame bool m_dummy_recording; // indicates if snapshot should be created of every frame
static const UINT8 s_skiptable[FRAMESKIP_LEVELS][FRAMESKIP_LEVELS]; static const UINT8 s_skiptable[FRAMESKIP_LEVELS][FRAMESKIP_LEVELS];

2
src/lib/formats/d88_dsk.c
View File

@ -27,7 +27,7 @@
* *
*/ */
#include <assert.h> #include <assert.h>
#include "flopimg.h" #include "flopimg.h"
#include "imageutl.h" #include "imageutl.h"

2
src/lib/formats/flex_dsk.c
View File

@ -4,7 +4,7 @@
* Created on: 24/06/2014 * Created on: 24/06/2014
*/ */
#include "emu.h" // logerror #include "emu.h" // logerror
#include "flex_dsk.h" #include "flex_dsk.h"
flex_format::flex_format() flex_format::flex_format()

2
src/lib/formats/fmtowns_dsk.c
View File

@ -6,7 +6,7 @@
* Created on: 23/03/2014 * Created on: 23/03/2014
*/ */
#include <assert.h> #include <assert.h>
#include "formats/fmtowns_dsk.h" #include "formats/fmtowns_dsk.h"

2
src/lib/formats/nfd_dsk.c
View File

@ -77,7 +77,7 @@
*********************************************************************/ *********************************************************************/
#include <assert.h> #include <assert.h>
#include "nfd_dsk.h" #include "nfd_dsk.h"

22
src/mame/audio/hng64.c
View File

@ -191,12 +191,12 @@ ADDRESS_MAP_END
WRITE16_MEMBER(hng64_state::hng64_sound_port_0008_w) WRITE16_MEMBER(hng64_state::hng64_sound_port_0008_w)
{ {
// logerror("hng64_sound_port_0008_w %04x %04x\n", data, mem_mask); // logerror("hng64_sound_port_0008_w %04x %04x\n", data, mem_mask);
// seems to one or more of the DMARQ on the V53, writes here when it expects DMA channel 3 to transfer ~0x20 bytes just after startup // seems to one or more of the DMARQ on the V53, writes here when it expects DMA channel 3 to transfer ~0x20 bytes just after startup
m_audiocpu->dreq3_w(data&1); m_audiocpu->dreq3_w(data&1);
// m_audiocpu->hack_w(1); // m_audiocpu->hack_w(1);
} }
@ -262,23 +262,23 @@ WRITE16_MEMBER(hng64_state::hng64_sound_data_02_w)
{ {
m_audiodat[m_audiochannel].dat[2] = data; m_audiodat[m_audiochannel].dat[2] = data;
// if ((m_audiochannel & 0xff00) == 0x0a00) // if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0002 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]); // printf("write port 0x0002 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
} }
WRITE16_MEMBER(hng64_state::hng64_sound_data_04_w) WRITE16_MEMBER(hng64_state::hng64_sound_data_04_w)
{ {
m_audiodat[m_audiochannel].dat[1] = data; m_audiodat[m_audiochannel].dat[1] = data;
// if ((m_audiochannel & 0xff00) == 0x0a00) // if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0004 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]); // printf("write port 0x0004 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
} }
WRITE16_MEMBER(hng64_state::hng64_sound_data_06_w) WRITE16_MEMBER(hng64_state::hng64_sound_data_06_w)
{ {
m_audiodat[m_audiochannel].dat[0] = data; m_audiodat[m_audiochannel].dat[0] = data;
// if ((m_audiochannel & 0xff00) == 0x0a00) // if ((m_audiochannel & 0xff00) == 0x0a00)
// printf("write port 0x0006 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]); // printf("write port 0x0006 chansel %04x data %04x (%04x%04x%04x)\n", m_audiochannel, data, m_audiodat[m_audiochannel].dat[0], m_audiodat[m_audiochannel].dat[1], m_audiodat[m_audiochannel].dat[2]);
} }
// but why not just use the V33/V53 XA mode?? // but why not just use the V33/V53 XA mode??
@ -414,14 +414,14 @@ WRITE_LINE_MEMBER(hng64_state::tcu_tm0_cb)
WRITE_LINE_MEMBER(hng64_state::tcu_tm1_cb) WRITE_LINE_MEMBER(hng64_state::tcu_tm1_cb)
{ {
// these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1 // these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1
// logerror("tcu_tm1_cb %02x\n", state); // logerror("tcu_tm1_cb %02x\n", state);
m_audiocpu->set_input_line(5, state? ASSERT_LINE:CLEAR_LINE); // not accurate, just so we have a trigger m_audiocpu->set_input_line(5, state? ASSERT_LINE:CLEAR_LINE); // not accurate, just so we have a trigger
} }
WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb) WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb)
{ {
// these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1 // these are very active, maybe they feed back into the v53 via one of the IRQ pins? TM2 toggles more rapidly than TM1
// logerror("tcu_tm2_cb %02x\n", state); // logerror("tcu_tm2_cb %02x\n", state);
// NOT ACCURATE, just so that all the interrupts get triggered for now. // NOT ACCURATE, just so that all the interrupts get triggered for now.
static int i = 0; static int i = 0;
@ -445,5 +445,3 @@ MACHINE_CONFIG_FRAGMENT( hng64_audio )
MCFG_V53_TCU_OUT2_HANDLER(WRITELINE(hng64_state, tcu_tm2_cb)) MCFG_V53_TCU_OUT2_HANDLER(WRITELINE(hng64_state, tcu_tm2_cb))
MACHINE_CONFIG_END MACHINE_CONFIG_END

156
src/mame/drivers/astrcorp.c
View File

@ -1159,130 +1159,130 @@ DRIVER_INIT_MEMBER(astrocorp_state,astoneag)
for (i = 0x25100/2; i < 0x25200/2; i++) for (i = 0x25100/2; i < 0x25200/2; i++)
{ {
x = 0x0000; x = 0x0000;
if ( (i & 0x0001) ) x |= 0x0200; if ( (i & 0x0001) ) x |= 0x0200;
if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0080; if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0080;
if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x0040; if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0020; if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0020) || (i & 0x0001) ) x |= 0x0010; if ( !(i & 0x0020) || (i & 0x0001) ) x |= 0x0010;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0008; if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0004; if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0004;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0002; if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0001; if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0001;
rom[i] ^= x; rom[i] ^= x;
} }
/* /*
for (i = 0x25300/2; i < 0x25400/2; i++) for (i = 0x25300/2; i < 0x25400/2; i++)
{ {
x = 0x1300; x = 0x1300;
rom[i] ^= x; rom[i] ^= x;
} }
*/ */
for (i = 0x25400/2; i < 0x25500/2; i++) for (i = 0x25400/2; i < 0x25500/2; i++)
{ {
x = 0x4200; x = 0x4200;
if ( (i & 0x0001) ) x |= 0x0400; if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080; if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040; if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020; if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010; if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004; if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002; if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001; if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x; rom[i] ^= x;
} }
for (i = 0x25500/2; i < 0x25600/2; i++) for (i = 0x25500/2; i < 0x25600/2; i++)
{ {
x = 0x4200; x = 0x4200;
if ( (i & 0x0001) ) x |= 0x0400; if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0080; if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0080;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0040; if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0040;
if ( !(i & 0x0002) && !(i & 0x0001) ) x |= 0x0020; if ( !(i & 0x0002) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0010; if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0010;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0008; if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0004; if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0002; if ( (i & 0x0004) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0001) ) x |= 0x0001; if ( (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x; rom[i] ^= x;
} }
/* /*
for (i = 0x25700/2; i < 0x25800/2; i++) for (i = 0x25700/2; i < 0x25800/2; i++)
{ {
x = 0x6800; x = 0x6800;
if ( !(i & 0x0001) ) x |= 0x8000; if ( !(i & 0x0001) ) x |= 0x8000;
if ( !(i & 0x0040) || ((i & 0x0001) || !(i & 0x0001)) ) x |= 0x0100; if ( !(i & 0x0040) || ((i & 0x0001) || !(i & 0x0001)) ) x |= 0x0100;
rom[i] ^= x; rom[i] ^= x;
} }
*/ */
for (i = 0x25800/2; i < 0x25900/2; i++) for (i = 0x25800/2; i < 0x25900/2; i++)
{ {
x = 0x8300; x = 0x8300;
if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x2000; if ( (i & 0x0040) || (i & 0x0001) ) x |= 0x2000;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0080; if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0040; if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0020; if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010; if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0008; if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0004; if ( (i & 0x0010) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002; if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0001; if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0001;
rom[i] ^= x; rom[i] ^= x;
} }
// for (i = 0x25900/2; i < 0x25a00/2; i++) // for (i = 0x25900/2; i < 0x25a00/2; i++)
for (i = 0x25c00/2; i < 0x25d00/2; i++) for (i = 0x25c00/2; i < 0x25d00/2; i++)
{ {
// changed from 25400 // changed from 25400
// x = 0x4200; // x = 0x4200;
x = 0x4000; x = 0x4000;
// if ( (i & 0x0001) ) x |= 0x0400; // if ( (i & 0x0001) ) x |= 0x0400;
if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080; if ( (i & 0x0020) && !(i & 0x0001) ) x |= 0x0080;
if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040; if ( !(i & 0x0010) || (i & 0x0001) ) x |= 0x0040;
if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020; if ( (i & 0x0040) && !(i & 0x0001) ) x |= 0x0020;
if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010; if ( !(i & 0x0004) || (i & 0x0001) ) x |= 0x0010;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004; if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0004;
if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002; if ( (i & 0x0008) && !(i & 0x0001) ) x |= 0x0002;
if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001; if ( (i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x; rom[i] ^= x;
} }
/* /*
for (i = 0x25d00/2; i < 0x25e00/2; i++) for (i = 0x25d00/2; i < 0x25e00/2; i++)
{ {
x = 0x4000; x = 0x4000;
if ( !(i & 0x0040) ) x |= 0x0800; if ( !(i & 0x0040) ) x |= 0x0800;
if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0100; // almost!! if ( !(i & 0x0040) && !(i & 0x0001) ) x |= 0x0100; // almost!!
if ( ((i & 0x0040)&&((i & 0x0020)||(i & 0x0010))) || !(i & 0x0001) ) x |= 0x0200; // almost!! if ( ((i & 0x0040)&&((i & 0x0020)||(i & 0x0010))) || !(i & 0x0001) ) x |= 0x0200; // almost!!
if ( (!(i & 0x0040) || !(i & 0x0008)) && !(i & 0x0001) ) x |= 0x0008; if ( (!(i & 0x0040) || !(i & 0x0008)) && !(i & 0x0001) ) x |= 0x0008;
if ( (i & 0x0040) || !(i & 0x0020) || (i & 0x0001) ) x |= 0x0001; // almost!! if ( (i & 0x0040) || !(i & 0x0020) || (i & 0x0001) ) x |= 0x0001; // almost!!
rom[i] ^= x; rom[i] ^= x;
} }
*/ */
/* /*
for (i = 0x25e00/2; i < 0x25f00/2; i++) for (i = 0x25e00/2; i < 0x25f00/2; i++)
{ {
x = 0xa600; x = 0xa600;
if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x4000; if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x4000;
if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x0800; if ( (i & 0x0040) && (i & 0x0001) ) x |= 0x0800;
if ( !(i & 0x0001) ) x |= 0x0100; if ( !(i & 0x0001) ) x |= 0x0100;
if ( ( (i & 0x0040) && (i & 0x0008) && !(i & 0x0001)) || if ( ( (i & 0x0040) && (i & 0x0008) && !(i & 0x0001)) ||
( !(i & 0x0040) && ((i & 0x0004) ^ (i & 0x0002)) && !(i & 0x0001) ) ) x |= 0x0002; // almost!! ( !(i & 0x0040) && ((i & 0x0004) ^ (i & 0x0002)) && !(i & 0x0001) ) ) x |= 0x0002; // almost!!
if ( !(i & 0x0040) || !(i & 0x0002) || (i & 0x0001) ) x |= 0x0001; if ( !(i & 0x0040) || !(i & 0x0002) || (i & 0x0001) ) x |= 0x0001;
rom[i] ^= x; rom[i] ^= x;
} }
*/ */
for (i = 0x26f00/2; i < 0x27000/2; i++) for (i = 0x26f00/2; i < 0x27000/2; i++)

16
src/mame/drivers/dynax.c
View File

@ -1564,14 +1564,14 @@ static ADDRESS_MAP_START( cdracula_io_map, AS_IO, 8, dynax_state )
ADDRESS_MAP_GLOBAL_MASK(0xff) ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE( 0x01, 0x07 ) AM_WRITE(cdracula_blitter_rev2_w) // Blitter + Destination Layers AM_RANGE( 0x01, 0x07 ) AM_WRITE(cdracula_blitter_rev2_w) // Blitter + Destination Layers
AM_RANGE( 0x10, 0x10 ) AM_DEVREADWRITE("oki", okim6295_device, read, write) AM_RANGE( 0x10, 0x10 ) AM_DEVREADWRITE("oki", okim6295_device, read, write)
AM_RANGE( 0x11, 0x11 ) AM_NOP // unpopulated oki AM_RANGE( 0x11, 0x11 ) AM_NOP // unpopulated oki
// AM_RANGE( 0x12, 0x12 ) AM_WRITENOP // CRT Controller // AM_RANGE( 0x12, 0x12 ) AM_WRITENOP // CRT Controller
// AM_RANGE( 0x13, 0x13 ) AM_WRITENOP // CRT Controller // AM_RANGE( 0x13, 0x13 ) AM_WRITENOP // CRT Controller
AM_RANGE( 0x20, 0x20 ) AM_READ_PORT("P1") // P1 AM_RANGE( 0x20, 0x20 ) AM_READ_PORT("P1") // P1
AM_RANGE( 0x21, 0x21 ) AM_READ_PORT("P2") // P2 AM_RANGE( 0x21, 0x21 ) AM_READ_PORT("P2") // P2
AM_RANGE( 0x22, 0x22 ) AM_READ_PORT("COINS") // Coins AM_RANGE( 0x22, 0x22 ) AM_READ_PORT("COINS") // Coins
AM_RANGE( 0x30, 0x30 ) AM_WRITE(dynax_layer_enable_w) // Layers Enable AM_RANGE( 0x30, 0x30 ) AM_WRITE(dynax_layer_enable_w) // Layers Enable
// AM_RANGE( 0x31, 0x31 ) AM_WRITE(dynax_rombank_w) // BANK ROM Select // AM_RANGE( 0x31, 0x31 ) AM_WRITE(dynax_rombank_w) // BANK ROM Select
AM_RANGE( 0x32, 0x32 ) AM_WRITE(dynax_blit_pen_w) // Destination Pen AM_RANGE( 0x32, 0x32 ) AM_WRITE(dynax_blit_pen_w) // Destination Pen
AM_RANGE( 0x33, 0x33 ) AM_WRITE(dynax_blit_flags_w) // Flags + Do Blit AM_RANGE( 0x33, 0x33 ) AM_WRITE(dynax_blit_flags_w) // Flags + Do Blit
AM_RANGE( 0x34, 0x34 ) AM_WRITE(dynax_blit_palette01_w) // Layers Palettes (Low Bits) AM_RANGE( 0x34, 0x34 ) AM_WRITE(dynax_blit_palette01_w) // Layers Palettes (Low Bits)
@ -2042,7 +2042,7 @@ static INPUT_PORTS_START( cdracula )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("DSW1") // port $61 -> c217 PORT_START("DSW1") // port $61 -> c217
PORT_DIPNAME( 0x03, 0x02, DEF_STR( Difficulty ) ) PORT_DIPLOCATION( "SW1:1,2" ) PORT_DIPNAME( 0x03, 0x02, DEF_STR( Difficulty ) ) PORT_DIPLOCATION( "SW1:1,2" )
PORT_DIPSETTING( 0x03, DEF_STR( Easy ) ) // 44 PORT_DIPSETTING( 0x03, DEF_STR( Easy ) ) // 44
PORT_DIPSETTING( 0x02, DEF_STR( Normal ) ) // 47 PORT_DIPSETTING( 0x02, DEF_STR( Normal ) ) // 47
@ -2064,7 +2064,7 @@ static INPUT_PORTS_START( cdracula )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION( "SW1:8" ) PORT_SERVICE( 0x80, IP_ACTIVE_LOW ) PORT_DIPLOCATION( "SW1:8" )
PORT_START("DSW2") // port $60 -> c216 PORT_START("DSW2") // port $60 -> c216
PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION( "SW2:1,2" ) PORT_DIPNAME( 0x03, 0x03, DEF_STR( Coinage ) ) PORT_DIPLOCATION( "SW2:1,2" )
PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) ) PORT_DIPSETTING( 0x00, DEF_STR( 3C_1C ) )
PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) ) PORT_DIPSETTING( 0x01, DEF_STR( 2C_1C ) )
@ -3190,7 +3190,7 @@ static INPUT_PORTS_START( jantouki )
PORT_DIPSETTING( 0x00, "12:00" ) PORT_DIPSETTING( 0x00, "12:00" )
PORT_DIPNAME( 0x08, 0x00, "Nudity" ) PORT_DIPNAME( 0x08, 0x00, "Nudity" )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x08, DEF_STR( No ) ) // Moles On Gal's Face PORT_DIPSETTING( 0x08, DEF_STR( No ) ) // Moles On Gal's Face
PORT_DIPNAME( 0x10, 0x10, "Buy Screen Bonus Points" ) /* Sets your points to 100 every time you arrive at the screen for buying special items. */ PORT_DIPNAME( 0x10, 0x10, "Buy Screen Bonus Points" ) /* Sets your points to 100 every time you arrive at the screen for buying special items. */
PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
@ -3363,7 +3363,7 @@ static INPUT_PORTS_START( mjembase )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x00, "Nudity" ) PORT_DIPNAME( 0x80, 0x00, "Nudity" )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
PORT_START("FAKE") /* IN10 - Fake DSW */ PORT_START("FAKE") /* IN10 - Fake DSW */
PORT_DIPNAME( 0xff, 0xff, "Allow Bets" ) PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
@ -3500,7 +3500,7 @@ static INPUT_PORTS_START( mjelct3 )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
PORT_DIPNAME( 0x80, 0x00, "Nudity" ) PORT_DIPNAME( 0x80, 0x00, "Nudity" )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face PORT_DIPSETTING( 0x80, DEF_STR( No ) ) // Moles On Gal's Face
PORT_START("FAKE") /* IN10 - Fake DSW */ PORT_START("FAKE") /* IN10 - Fake DSW */
PORT_DIPNAME( 0xff, 0xff, "Allow Bets" ) PORT_DIPNAME( 0xff, 0xff, "Allow Bets" )
@ -4354,7 +4354,7 @@ static MACHINE_CONFIG_START( cdracula, dynax_state )
MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax) MCFG_MACHINE_START_OVERRIDE(dynax_state,dynax)
MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax) MCFG_MACHINE_RESET_OVERRIDE(dynax_state,dynax)
// MCFG_NVRAM_ADD_0FILL("nvram") // no battery // MCFG_NVRAM_ADD_0FILL("nvram") // no battery
/* video hardware */ /* video hardware */
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)

40
src/mame/drivers/goldstar.c
View File

@ -2993,7 +2993,7 @@ static INPUT_PORTS_START( ns8linew )
PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) ) PORT_DIPSETTING( 0x08, DEF_STR( 1C_2C ) )
PORT_DIPSETTING( 0x10, DEF_STR( 1C_4C ) ) PORT_DIPSETTING( 0x10, DEF_STR( 1C_4C ) )
PORT_DIPSETTING( 0x18, DEF_STR( 1C_5C ) ) PORT_DIPSETTING( 0x18, DEF_STR( 1C_5C ) )
PORT_DIPSETTING( 0x20, DEF_STR( 1C_6C ) ) // manual says 1c/8c PORT_DIPSETTING( 0x20, DEF_STR( 1C_6C ) ) // manual says 1c/8c
PORT_DIPSETTING( 0x28, "1 Coin/10 Credits" ) PORT_DIPSETTING( 0x28, "1 Coin/10 Credits" )
PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7") /* not checked */ PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW4:7") /* not checked */
PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
@ -3375,12 +3375,12 @@ static INPUT_PORTS_START( bingowng )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8") PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW1:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
/* On a W-4 PCB these are used as: "Special Odds-Prohibition Of Winning...(Odds B)" - see DSW2-7 /* On a W-4 PCB these are used as: "Special Odds-Prohibition Of Winning...(Odds B)" - see DSW2-7
PORT_DIPNAME( 0x80, 0x00, "Special Odds" ) PORT_DIPLOCATION("DSW1:7,8") PORT_DIPNAME( 0x80, 0x00, "Special Odds" ) PORT_DIPLOCATION("DSW1:7,8")
PORT_DIPSETTING( 0x00, "None" ) PORT_DIPSETTING( 0x00, "None" )
PORT_DIPSETTING( 0x40, "x300 (x1000)" ) PORT_DIPSETTING( 0x40, "x300 (x1000)" )
PORT_DIPSETTING( 0x80, "x500 (x5000" ) PORT_DIPSETTING( 0x80, "x500 (x5000" )
PORT_DIPSETTING( 0xc0, "x1000 (x10000) PORT_DIPSETTING( 0xc0, "x1000 (x10000)
*/ */
PORT_START("DSW2") PORT_START("DSW2")
@ -3406,13 +3406,13 @@ static INPUT_PORTS_START( bingowng )
PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8") PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) PORT_DIPLOCATION("DSW2:8")
PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) )
/* On a W-4 PCB these are used as: /* On a W-4 PCB these are used as:
PORT_DIPNAME( 0x40, 0x40, "Odds" ) PORT_DIPLOCATION("DSW2:7") PORT_DIPNAME( 0x40, 0x40, "Odds" ) PORT_DIPLOCATION("DSW2:7")
PORT_DIPSETTING( 0x40, "Type A" ) PORT_DIPSETTING( 0x40, "Type A" )
PORT_DIPSETTING( 0x00, "Type B" ) PORT_DIPSETTING( 0x00, "Type B" )
PORT_DIPNAME( 0x80, 0x80, "Type Of W-Up Game" ) PORT_DIPLOCATION("DSW2:8") PORT_DIPNAME( 0x80, 0x80, "Type Of W-Up Game" ) PORT_DIPLOCATION("DSW2:8")
PORT_DIPSETTING( 0x80, "Slots" ) PORT_DIPSETTING( 0x80, "Slots" )
PORT_DIPSETTING( 0x00, "Big/Small Card" ) PORT_DIPSETTING( 0x00, "Big/Small Card" )
*/ */
/* On a W-4 PCB DSW3 & DSW4 are reversed and all dips on DSW4 are set to off! */ /* On a W-4 PCB DSW3 & DSW4 are reversed and all dips on DSW4 are set to off! */
@ -3672,7 +3672,7 @@ static INPUT_PORTS_START( schery97 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Key Out / Attendant") PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT ) PORT_NAME("Key Out / Attendant")
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings") PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_GAMBLE_SERVICE ) PORT_NAME("Settings")
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats") // doesn't work in v352c4 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_BOOK ) PORT_NAME("Stats") // doesn't work in v352c4
PORT_START("DSW1") PORT_START("DSW1")
PORT_DIPNAME( 0x07, 0x03, "Game Level (Difficulty)" ) PORT_DIPLOCATION("DSW1:1,2,3") /* OK */ PORT_DIPNAME( 0x07, 0x03, "Game Level (Difficulty)" ) PORT_DIPLOCATION("DSW1:1,2,3") /* OK */
@ -4338,11 +4338,11 @@ static INPUT_PORTS_START( roypok96a )
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
PORT_DIPSETTING( 0x20, DEF_STR( On ) ) PORT_DIPSETTING( 0x20, DEF_STR( On ) )
PORT_DIPNAME( 0x40, 0x00, "Reset Remaining Score To Zero" ) PORT_DIPLOCATION("DSW5:7") PORT_DIPNAME( 0x40, 0x00, "Reset Remaining Score To Zero" ) PORT_DIPLOCATION("DSW5:7")
PORT_DIPSETTING( 0x00, DEF_STR( No ) ) PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x40, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
PORT_DIPNAME( 0x80, 0x00, "Count Game To Issue Ticket" ) PORT_DIPLOCATION("DSW5:8") PORT_DIPNAME( 0x80, 0x00, "Count Game To Issue Ticket" ) PORT_DIPLOCATION("DSW5:8")
PORT_DIPSETTING( 0x00, DEF_STR( No ) ) PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x80, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x80, DEF_STR( Yes ) )
INPUT_PORTS_END INPUT_PORTS_END
@ -4472,7 +4472,7 @@ static INPUT_PORTS_START( pokonl97 )
PORT_DIPNAME( 0x10, 0x10, "Auto Ticket Dispense" ) PORT_DIPLOCATION("DSW4:5") /* not checked */ PORT_DIPNAME( 0x10, 0x10, "Auto Ticket Dispense" ) PORT_DIPLOCATION("DSW4:5") /* not checked */
PORT_DIPSETTING( 0x00, DEF_STR( No ) ) PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x10, DEF_STR( Yes ) ) PORT_DIPSETTING( 0x10, DEF_STR( Yes ) )
PORT_DIPNAME( 0xe0, 0xe0, "Ticket Dispense Mode" ) PORT_DIPLOCATION("DSW4:6,7,8") PORT_DIPNAME( 0xe0, 0xe0, "Ticket Dispense Mode" ) PORT_DIPLOCATION("DSW4:6,7,8")
PORT_DIPSETTING( 0xe0, "Continuous" ) PORT_DIPSETTING( 0xe0, "Continuous" )
PORT_DIPSETTING( 0xc0, "Max 1 Ticket Per Game" ) PORT_DIPSETTING( 0xc0, "Max 1 Ticket Per Game" )
PORT_DIPSETTING( 0xa0, "Max 2 Ticket Per Game" ) PORT_DIPSETTING( 0xa0, "Max 2 Ticket Per Game" )

5
src/mame/drivers/hng64.c
View File

@ -918,7 +918,7 @@ WRITE32_MEMBER(hng64_state::hng64_sprite_clear_odd_w)
WRITE32_MEMBER(hng64_state::hng64_vregs_w) WRITE32_MEMBER(hng64_state::hng64_vregs_w)
{ {
// printf("hng64_vregs_w %02x, %08x %08x\n", offset * 4, data, mem_mask); // printf("hng64_vregs_w %02x, %08x %08x\n", offset * 4, data, mem_mask);
COMBINE_DATA(&m_videoregs[offset]); COMBINE_DATA(&m_videoregs[offset]);
} }
@ -1569,8 +1569,7 @@ MACHINE_CONFIG_END
ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS */ \ ROM_REGION( 0x0100000, "user2", 0 ) /* KL5C80 BIOS */ \
ROM_LOAD ( "from1.bin", 0x000000, 0x080000, CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) ) \ ROM_LOAD ( "from1.bin", 0x000000, 0x080000, CRC(6b933005) SHA1(e992747f46c48b66e5509fe0adf19c91250b00c7) ) \
ROM_REGION( 0x0100000, "fpga", 0 ) /* FPGA data */ \ ROM_REGION( 0x0100000, "fpga", 0 ) /* FPGA data */ \
ROM_LOAD ( "rom1.bin", 0x000000, 0x01ff32, CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) ) \ ROM_LOAD ( "rom1.bin", 0x000000, 0x01ff32, CRC(4a6832dc) SHA1(ae504f7733c2f40450157cd1d3b85bc83fac8569) )
ROM_START( hng64 ) ROM_START( hng64 )
/* BIOS */ /* BIOS */

16
src/mame/drivers/neogeo.c
View File

@ -238,9 +238,9 @@
. NEO-AEG CHA42G-3 . NEO-AEG CHA42G-3
. NEO-AEG CHA42G-4 . NEO-AEG CHA42G-4
. NEO-AEG CHA256 . NEO-AEG CHA256
. NEO-AEG CHA256 B . NEO-AEG CHA256 B
. NEO-AEG CHA256[B] . NEO-AEG CHA256[B]
. NEO-AEG CHA256BY . NEO-AEG CHA256BY
. NEO-AEG CHA256RY . NEO-AEG CHA256RY
. NEO-AEG CHA512Y . NEO-AEG CHA512Y
. NEO-AEG CHAFIO (1999.8.10) - used with NEO-CMC 90G06C7042 or NEO-CMC 90G06C7050 . NEO-AEG CHAFIO (1999.8.10) - used with NEO-CMC 90G06C7042 or NEO-CMC 90G06C7050
@ -263,7 +263,7 @@
. NEO-AEG PROG4096 B . NEO-AEG PROG4096 B
. NEO-AEG PROGGS . NEO-AEG PROGGS
. NEO-AEG PROGTOP2 . NEO-AEG PROGTOP2
. NEO-AEG PROGTOP2Y . NEO-AEG PROGTOP2Y
. NEO-AEG PROGEOP (1999.4.2) . NEO-AEG PROGEOP (1999.4.2)
. NEO-AEG PROGLBA (1999.7.6) . NEO-AEG PROGLBA (1999.7.6)
. NEO-AEG PROGRK . NEO-AEG PROGRK
@ -311,13 +311,13 @@
GIGA PROG Board 1.5 GIGA PROG Board 1.5
Unofficial pcb's from NEOBITZ: Unofficial pcb's from NEOBITZ:
MVS CHA: MVS CHA:
CHARBITZ1 2013.12.01 CHARBITZ1 2013.12.01
MVS PROG: MVS PROG:
PROGBITZ1 2013.12.01 PROGBITZ1 2013.12.01
Neo-Geo game PCB infos by Johnboy Neo-Geo game PCB infos by Johnboy

2
src/mame/drivers/neogeo_noslot.c
View File

@ -2965,7 +2965,7 @@ ROM_END
BANK 3 NOT USED BANK 3 NOT USED
****************************************/ ****************************************/
ROM_START( b2b ) ROM_START( b2b )
ROM_REGION( 0x100000, "maincpu", 0 ) ROM_REGION( 0x100000, "maincpu", 0 )
ROM_LOAD16_WORD_SWAP( "071.p1", 0x000000, 0x080000, CRC(7687197d) SHA1(4bb9cb7819807f7a7e1f85f1c4faac4a2f8761e8) ) ROM_LOAD16_WORD_SWAP( "071.p1", 0x000000, 0x080000, CRC(7687197d) SHA1(4bb9cb7819807f7a7e1f85f1c4faac4a2f8761e8) )

6
src/mame/drivers/playmark.c
View File

@ -1375,7 +1375,7 @@ static MACHINE_CONFIG_START( hrdtimes, playmark_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold) MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold)
MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */ MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead // MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r)) MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w)) MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r)) MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
@ -1416,7 +1416,7 @@ static MACHINE_CONFIG_START( hotmind, playmark_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold) // irq 2 and 6 point to the same location on hotmind MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold) // irq 2 and 6 point to the same location on hotmind
MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */ MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead // MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r)) MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w)) MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r)) MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))
@ -1462,7 +1462,7 @@ static MACHINE_CONFIG_START( luckboomh, playmark_state )
MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold) MCFG_CPU_VBLANK_INT_DRIVER("screen", playmark_state, irq6_line_hold)
MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */ MCFG_CPU_ADD("audiocpu", PIC16C57, XTAL_24MHz/2) /* verified on pcb */
// MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead // MCFG_PIC16C5x_WRITE_A_CB(WRITE8(playmark_state, playmark_oki_banking_w)) // Banking data output but not wired. Port C is wired to the OKI banking instead
MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r)) MCFG_PIC16C5x_READ_B_CB(READ8(playmark_state, playmark_snd_command_r))
MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w)) MCFG_PIC16C5x_WRITE_B_CB(WRITE8(playmark_state, playmark_oki_w))
MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r)) MCFG_PIC16C5x_READ_C_CB(READ8(playmark_state, playmark_snd_flag_r))

1
src/mame/drivers/scobra.c
View File

@ -1253,4 +1253,3 @@ GAME( 1981, hustlerb4, hustler, hustlerb4, hustler, driver_device, 0,
GAME( 1982, mimonkey, 0, mimonkey, mimonkey, scramble_state, mimonkey, ROT90, "Universal Video Games", "Mighty Monkey", GAME_SUPPORTS_SAVE ) GAME( 1982, mimonkey, 0, mimonkey, mimonkey, scramble_state, mimonkey, ROT90, "Universal Video Games", "Mighty Monkey", GAME_SUPPORTS_SAVE )
GAME( 1982, mimonsco, mimonkey, mimonkey, mimonsco, scramble_state, mimonsco, ROT90, "bootleg", "Mighty Monkey (bootleg on Super Cobra hardware)", GAME_SUPPORTS_SAVE ) GAME( 1982, mimonsco, mimonkey, mimonkey, mimonsco, scramble_state, mimonsco, ROT90, "bootleg", "Mighty Monkey (bootleg on Super Cobra hardware)", GAME_SUPPORTS_SAVE )

8
src/mame/drivers/sidearms.c
View File

@ -43,12 +43,12 @@ Notes:
void sidearms_state::machine_start() void sidearms_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x8000, 0x4000); membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x8000, 0x4000);
} }
WRITE8_MEMBER(sidearms_state::bankswitch_w) WRITE8_MEMBER(sidearms_state::bankswitch_w)
{ {
membank("bank1")->set_entry(data & 0x07); membank("bank1")->set_entry(data & 0x07);
} }
@ -119,7 +119,7 @@ ADDRESS_MAP_END
WRITE8_MEMBER(sidearms_state::whizz_bankswitch_w) WRITE8_MEMBER(sidearms_state::whizz_bankswitch_w)
{ {
int bank = 0; int bank = 0;
switch (data & 0xC0) switch (data & 0xC0)
{ {
case 0x00 : bank = 0; break; case 0x00 : bank = 0; break;
@ -127,7 +127,7 @@ WRITE8_MEMBER(sidearms_state::whizz_bankswitch_w)
case 0x80 : bank = 1; break; case 0x80 : bank = 1; break;
case 0xC0 : bank = 3; break; case 0xC0 : bank = 3; break;
} }
membank("bank1")->set_entry(bank); membank("bank1")->set_entry(bank);
} }
static ADDRESS_MAP_START( whizz_map, AS_PROGRAM, 8, sidearms_state ) static ADDRESS_MAP_START( whizz_map, AS_PROGRAM, 8, sidearms_state )

6
src/mame/drivers/simple_st0016.c
View File

@ -33,7 +33,7 @@ Dips verified for Neratte Chu (nratechu) from manual
void st0016_state::machine_start() void st0016_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000); membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
} }
static ADDRESS_MAP_START( st0016_mem, AS_PROGRAM, 8, st0016_state ) static ADDRESS_MAP_START( st0016_mem, AS_PROGRAM, 8, st0016_state )
@ -81,8 +81,8 @@ WRITE8_MEMBER(st0016_state::mux_select_w)
WRITE8_MEMBER(st0016_state::st0016_rom_bank_w) WRITE8_MEMBER(st0016_state::st0016_rom_bank_w)
{ {
membank("bank1")->set_entry(data); membank("bank1")->set_entry(data);
// st0016_rom_bank = data; // st0016_rom_bank = data;
} }
static ADDRESS_MAP_START( st0016_io, AS_IO, 8, st0016_state ) static ADDRESS_MAP_START( st0016_io, AS_IO, 8, st0016_state )

6
src/mame/drivers/sothello.c
View File

@ -72,7 +72,7 @@ public:
DECLARE_READ8_MEMBER(subcpu_status_r); DECLARE_READ8_MEMBER(subcpu_status_r);
DECLARE_WRITE8_MEMBER(msm_cfg_w); DECLARE_WRITE8_MEMBER(msm_cfg_w);
virtual void machine_start(); virtual void machine_start();
virtual void machine_reset(); virtual void machine_reset();
TIMER_CALLBACK_MEMBER(subcpu_suspend); TIMER_CALLBACK_MEMBER(subcpu_suspend);
TIMER_CALLBACK_MEMBER(subcpu_resume); TIMER_CALLBACK_MEMBER(subcpu_resume);
@ -101,7 +101,7 @@ public:
void sothello_state::machine_start() void sothello_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000); membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000);
} }
WRITE8_MEMBER(sothello_state::bank_w) WRITE8_MEMBER(sothello_state::bank_w)
@ -114,7 +114,7 @@ WRITE8_MEMBER(sothello_state::bank_w)
case 4: bank=2; break; case 4: bank=2; break;
case 8: bank=3; break; case 8: bank=3; break;
} }
membank("bank1")->set_entry(bank); membank("bank1")->set_entry(bank);
} }
TIMER_CALLBACK_MEMBER(sothello_state::subcpu_suspend) TIMER_CALLBACK_MEMBER(sothello_state::subcpu_suspend)

6
src/mame/drivers/speglsht.c
View File

@ -134,7 +134,7 @@ public:
DECLARE_READ32_MEMBER(irq_ack_clear); DECLARE_READ32_MEMBER(irq_ack_clear);
DECLARE_DRIVER_INIT(speglsht); DECLARE_DRIVER_INIT(speglsht);
DECLARE_MACHINE_RESET(speglsht); DECLARE_MACHINE_RESET(speglsht);
virtual void machine_start(); virtual void machine_start();
DECLARE_VIDEO_START(speglsht); DECLARE_VIDEO_START(speglsht);
UINT32 screen_update_speglsht(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); UINT32 screen_update_speglsht(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
required_device<palette_device> m_palette; required_device<palette_device> m_palette;
@ -160,13 +160,13 @@ ADDRESS_MAP_END
void speglsht_state::machine_start() void speglsht_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000); membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
} }
// common rombank? should go in machine/st0016 with larger address space exposed? // common rombank? should go in machine/st0016 with larger address space exposed?
WRITE8_MEMBER(speglsht_state::st0016_rom_bank_w) WRITE8_MEMBER(speglsht_state::st0016_rom_bank_w)
{ {
membank("bank1")->set_entry(data); membank("bank1")->set_entry(data);
} }

4
src/mame/drivers/srmp2.c
View File

@ -108,7 +108,7 @@ MACHINE_START_MEMBER(srmp2_state,srmp3)
m_iox.protcheck[2] = 0x1c; m_iox.protlatch[2] = 0x04; m_iox.protcheck[2] = 0x1c; m_iox.protlatch[2] = 0x04;
m_iox.protcheck[3] = 0x45; m_iox.protlatch[3] = 0x00; m_iox.protcheck[3] = 0x45; m_iox.protlatch[3] = 0x00;
membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base(), 0x2000); membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base(), 0x2000);
save_item(NAME(m_gfx_bank)); save_item(NAME(m_gfx_bank));
} }
@ -125,7 +125,7 @@ MACHINE_START_MEMBER(srmp2_state,rmgoldyh)
m_iox.protcheck[2] = -1; m_iox.protlatch[2] = -1; m_iox.protcheck[2] = -1; m_iox.protlatch[2] = -1;
m_iox.protcheck[3] = -1; m_iox.protlatch[3] = -1; m_iox.protcheck[3] = -1; m_iox.protlatch[3] = -1;
membank("bank1")->configure_entries(0, 32, memregion("maincpu")->base(), 0x2000); membank("bank1")->configure_entries(0, 32, memregion("maincpu")->base(), 0x2000);
save_item(NAME(m_gfx_bank)); save_item(NAME(m_gfx_bank));
} }

6
src/mame/drivers/srmp5.c
View File

@ -114,7 +114,7 @@ public:
DECLARE_READ8_MEMBER(cmd1_r); DECLARE_READ8_MEMBER(cmd1_r);
DECLARE_READ8_MEMBER(cmd2_r); DECLARE_READ8_MEMBER(cmd2_r);
DECLARE_READ8_MEMBER(cmd_stat8_r); DECLARE_READ8_MEMBER(cmd_stat8_r);
virtual void machine_start(); virtual void machine_start();
DECLARE_DRIVER_INIT(srmp5); DECLARE_DRIVER_INIT(srmp5);
UINT32 screen_update_srmp5(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); UINT32 screen_update_srmp5(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@ -240,7 +240,7 @@ UINT32 srmp5_state::screen_update_srmp5(screen_device &screen, bitmap_rgb32 &bit
void srmp5_state::machine_start() void srmp5_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000); membank("bank1")->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
} }
WRITE32_MEMBER(srmp5_state::bank_w) WRITE32_MEMBER(srmp5_state::bank_w)
@ -400,7 +400,7 @@ READ8_MEMBER(srmp5_state::cmd_stat8_r)
// common rombank? should go in machine/st0016 with larger address space exposed? // common rombank? should go in machine/st0016 with larger address space exposed?
WRITE8_MEMBER(srmp5_state::st0016_rom_bank_w) WRITE8_MEMBER(srmp5_state::st0016_rom_bank_w)
{ {
membank("bank1")->set_entry(data); membank("bank1")->set_entry(data);
} }

8
src/mame/drivers/srmp6.c
View File

@ -107,7 +107,7 @@ public:
DECLARE_WRITE16_MEMBER(paletteram_w); DECLARE_WRITE16_MEMBER(paletteram_w);
DECLARE_READ16_MEMBER(srmp6_irq_ack_r); DECLARE_READ16_MEMBER(srmp6_irq_ack_r);
DECLARE_DRIVER_INIT(INIT); DECLARE_DRIVER_INIT(INIT);
virtual void machine_start(); virtual void machine_start();
virtual void video_start(); virtual void video_start();
UINT32 screen_update_srmp6(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); UINT32 screen_update_srmp6(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
void update_palette(); void update_palette();
@ -309,7 +309,7 @@ UINT32 srmp6_state::screen_update_srmp6(screen_device &screen, bitmap_rgb32 &bit
void srmp6_state::machine_start() void srmp6_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 16, memregion("nile")->base(), 0x200000); membank("bank1")->configure_entries(0, 16, memregion("nile")->base(), 0x200000);
} }
WRITE16_MEMBER(srmp6_state::srmp6_input_select_w) WRITE16_MEMBER(srmp6_state::srmp6_input_select_w)
@ -340,8 +340,8 @@ WRITE16_MEMBER(srmp6_state::video_regs_w)
{ {
case 0x5e/2: // bank switch, used by ROM check case 0x5e/2: // bank switch, used by ROM check
{ {
LOG(("%x\n",data)); LOG(("%x\n",data));
membank("bank1")->set_entry(data & 0x0f); membank("bank1")->set_entry(data & 0x0f);
break; break;
} }

14
src/mame/drivers/srumbler.c
View File

@ -32,25 +32,25 @@ WRITE8_MEMBER(srumbler_state::bankswitch_w)
for (int i = 0x05;i < 0x10;i++) for (int i = 0x05;i < 0x10;i++)
{ {
/* bit 2 of prom1 selects ROM or RAM - not supported */ /* bit 2 of prom1 selects ROM or RAM - not supported */
int bank = ((prom1[i] & 0x03) << 4) | (prom2[i] & 0x0f); int bank = ((prom1[i] & 0x03) << 4) | (prom2[i] & 0x0f);
char bankname[10]; char bankname[10];
sprintf(bankname, "%04x", i*0x1000); sprintf(bankname, "%04x", i*0x1000);
membank(bankname)->set_entry(bank); membank(bankname)->set_entry(bank);
} }
} }
void srumbler_state::machine_start() void srumbler_state::machine_start()
{ {
for (int i = 0x05; i < 0x10; i++) for (int i = 0x05; i < 0x10; i++)
{ {
char bankname[10]; char bankname[10];
sprintf(bankname, "%04x", i*0x1000); sprintf(bankname, "%04x", i*0x1000);
membank(bankname)->configure_entries(0, 64, memregion("user1")->base(), 0x1000); membank(bankname)->configure_entries(0, 64, memregion("user1")->base(), 0x1000);
} }
/* initialize banked ROM pointers */ /* initialize banked ROM pointers */
bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0); bankswitch_w(m_maincpu->space(AS_PROGRAM), 0, 0);
} }

22
src/mame/drivers/suna16.c
View File

@ -215,7 +215,7 @@ ADDRESS_MAP_END
MACHINE_START_MEMBER(suna16_state,bestbest) MACHINE_START_MEMBER(suna16_state,bestbest)
{ {
save_item(NAME(m_prot)); save_item(NAME(m_prot));
} }
@ -294,8 +294,8 @@ ADDRESS_MAP_END
MACHINE_START_MEMBER(suna16_state, bssoccer) MACHINE_START_MEMBER(suna16_state, bssoccer)
{ {
membank("bank1")->configure_entries(0, 8, memregion("pcm1")->base() + 0x1000, 0x10000); membank("bank1")->configure_entries(0, 8, memregion("pcm1")->base() + 0x1000, 0x10000);
membank("bank2")->configure_entries(0, 8, memregion("pcm2")->base() + 0x1000, 0x10000); membank("bank2")->configure_entries(0, 8, memregion("pcm2")->base() + 0x1000, 0x10000);
} }
/* Bank Switching */ /* Bank Switching */
@ -304,16 +304,16 @@ WRITE8_MEMBER(suna16_state::bssoccer_pcm_1_bankswitch_w)
{ {
const int bank = data & 7; const int bank = data & 7;
if (bank & ~7) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data); if (bank & ~7) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
printf("%d %d\n", 1, bank); printf("%d %d\n", 1, bank);
membank("bank1")->set_entry(bank); membank("bank1")->set_entry(bank);
} }
WRITE8_MEMBER(suna16_state::bssoccer_pcm_2_bankswitch_w) WRITE8_MEMBER(suna16_state::bssoccer_pcm_2_bankswitch_w)
{ {
const int bank = data & 7; const int bank = data & 7;
if (bank & ~7) logerror("CPU#3 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data); if (bank & ~7) logerror("CPU#3 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
printf("%d %d\n", 2, bank); printf("%d %d\n", 2, bank);
membank("bank2")->set_entry(bank); membank("bank2")->set_entry(bank);
} }
@ -378,7 +378,7 @@ WRITE8_MEMBER(suna16_state::uballoon_pcm_1_bankswitch_w)
{ {
const int bank = data & 1; const int bank = data & 1;
if (bank & ~1) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data); if (bank & ~1) logerror("CPU#2 PC %06X - ROM bank unknown bits: %02X\n", space.device().safe_pc(), data);
membank("bank1")->set_entry(bank); membank("bank1")->set_entry(bank);
} }
/* Memory maps: Yes, *no* RAM */ /* Memory maps: Yes, *no* RAM */
@ -398,7 +398,7 @@ ADDRESS_MAP_END
MACHINE_START_MEMBER(suna16_state,uballoon) MACHINE_START_MEMBER(suna16_state,uballoon)
{ {
membank("bank1")->configure_entries(0, 2, memregion("pcm1")->base() + 0x400, 0x10000); membank("bank1")->configure_entries(0, 2, memregion("pcm1")->base() + 0x400, 0x10000);
save_item(NAME(m_prot)); save_item(NAME(m_prot));
} }
@ -828,7 +828,7 @@ static MACHINE_CONFIG_START( bssoccer, suna16_state )
MCFG_QUANTUM_TIME(attotime::from_hz(6000)) MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_MACHINE_START_OVERRIDE(suna16_state,bssoccer) MCFG_MACHINE_START_OVERRIDE(suna16_state,bssoccer)
/* video hardware */ /* video hardware */
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)
@ -887,7 +887,7 @@ static MACHINE_CONFIG_START( uballoon, suna16_state )
MCFG_QUANTUM_TIME(attotime::from_hz(6000)) MCFG_QUANTUM_TIME(attotime::from_hz(6000))
MCFG_MACHINE_START_OVERRIDE(suna16_state,uballoon) MCFG_MACHINE_START_OVERRIDE(suna16_state,uballoon)
MCFG_MACHINE_RESET_OVERRIDE(suna16_state,uballoon) MCFG_MACHINE_RESET_OVERRIDE(suna16_state,uballoon)
/* video hardware */ /* video hardware */

22
src/mame/drivers/suna8.c
View File

@ -735,7 +735,7 @@ static ADDRESS_MAP_START( brickzn11_map, AS_PROGRAM, 8, suna8_state )
AM_RANGE(0xc060, 0xc060) AM_WRITE(brickzn_rombank_w ) // ROM Bank AM_RANGE(0xc060, 0xc060) AM_WRITE(brickzn_rombank_w ) // ROM Bank
AM_RANGE(0xc080, 0xc080) AM_WRITE(brickzn_leds_w ) // Leds AM_RANGE(0xc080, 0xc080) AM_WRITE(brickzn_leds_w ) // Leds
AM_RANGE(0xc0a0, 0xc0a0) AM_WRITE(brickzn_palbank_w ) // Palette RAM Bank AM_RANGE(0xc0a0, 0xc0a0) AM_WRITE(brickzn_palbank_w ) // Palette RAM Bank
// AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_prot2_w ) // Protection 2 // AM_RANGE(0xc0c0, 0xc0c0) AM_WRITE(brickzn_prot2_w ) // Protection 2
AM_RANGE(0xc100, 0xc100) AM_READ_PORT("P1") // P1 (Buttons) AM_RANGE(0xc100, 0xc100) AM_READ_PORT("P1") // P1 (Buttons)
AM_RANGE(0xc101, 0xc101) AM_READ_PORT("P2") // P2 (Buttons) AM_RANGE(0xc101, 0xc101) AM_READ_PORT("P2") // P2 (Buttons)
@ -771,13 +771,13 @@ WRITE8_MEMBER(suna8_state::brickzn_multi_w)
else if (protselect == 0x90) else if (protselect == 0x90)
{ {
/* /*
0d brick hit NO! 25? 0d brick hit NO! 25?
2c side wall hit OK 2c side wall hit OK
3b paddle hit OK 3b paddle hit OK
44 death OK? 44 death OK?
53 death OK? 53 death OK?
56 coin in OK? 56 coin in OK?
70 monster hit NO? 58? 70 monster hit NO? 58?
*/ */
UINT8 remap = (m_remap_sound ? BITSWAP8(data, 7,6,3,4,5,2,1,0) : data); UINT8 remap = (m_remap_sound ? BITSWAP8(data, 7,6,3,4,5,2,1,0) : data);
@ -1975,7 +1975,7 @@ MACHINE_CONFIG_END
MACHINE_RESET_MEMBER(suna8_state,brickzn) MACHINE_RESET_MEMBER(suna8_state,brickzn)
{ {
m_protection_val = m_prot2 = m_prot2_prev = 0xff; m_protection_val = m_prot2 = m_prot2_prev = 0xff;
m_paletteram_enab = 1; // for brickzn11 m_paletteram_enab = 1; // for brickzn11
m_remap_sound = 0; m_remap_sound = 0;
membank("bank1")->set_entry(0); membank("bank1")->set_entry(0);
} }
@ -2015,12 +2015,12 @@ static MACHINE_CONFIG_START( brickzn11, suna8_state )
/* sound hardware */ /* sound hardware */
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
MCFG_SOUND_ADD("ymsnd", YM3812, SUNA8_MASTER_CLOCK / 8) // 3MHz (measured) MCFG_SOUND_ADD("ymsnd", YM3812, SUNA8_MASTER_CLOCK / 8) // 3MHz (measured)
MCFG_YM3812_IRQ_HANDLER(INPUTLINE("audiocpu", 0)) MCFG_YM3812_IRQ_HANDLER(INPUTLINE("audiocpu", 0))
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 1.0)
MCFG_SOUND_ADD("aysnd", AY8910, SUNA8_MASTER_CLOCK / 16) // 1.5MHz (measured) MCFG_SOUND_ADD("aysnd", AY8910, SUNA8_MASTER_CLOCK / 16) // 1.5MHz (measured)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.33) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.33)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.33) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.33)

8
src/mame/drivers/supertnk.c
View File

@ -124,7 +124,7 @@ public:
DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_0_w); DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_0_w);
DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_1_w); DECLARE_WRITE8_MEMBER(supertnk_bitplane_select_1_w);
DECLARE_DRIVER_INIT(supertnk); DECLARE_DRIVER_INIT(supertnk);
virtual void machine_start(); virtual void machine_start();
virtual void machine_reset(); virtual void machine_reset();
virtual void video_start(); virtual void video_start();
UINT32 screen_update_supertnk(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); UINT32 screen_update_supertnk(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
@ -135,7 +135,7 @@ public:
void supertnk_state::machine_start() void supertnk_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x1000); membank("bank1")->configure_entries(0, 4, memregion("maincpu")->base() + 0x10000, 0x1000);
} }
@ -148,14 +148,14 @@ void supertnk_state::machine_start()
WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_0_w) WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_0_w)
{ {
m_rom_bank = (m_rom_bank & 0x02) | ((data << 0) & 0x01); m_rom_bank = (m_rom_bank & 0x02) | ((data << 0) & 0x01);
membank("bank1")->set_entry(m_rom_bank); membank("bank1")->set_entry(m_rom_bank);
} }
WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_1_w) WRITE8_MEMBER(supertnk_state::supertnk_bankswitch_1_w)
{ {
m_rom_bank = (m_rom_bank & 0x01) | ((data << 1) & 0x02); m_rom_bank = (m_rom_bank & 0x01) | ((data << 1) & 0x02);
membank("bank1")->set_entry(m_rom_bank); membank("bank1")->set_entry(m_rom_bank);
} }

4
src/mame/drivers/superwng.c
View File

@ -101,7 +101,7 @@ WRITE8_MEMBER(superwng_state::superwng_unk_a187_w)
WRITE8_MEMBER(superwng_state::superwng_unk_a185_w) WRITE8_MEMBER(superwng_state::superwng_unk_a185_w)
{ {
// printf("superwng_unk_a185_w %02x\n", data); // printf("superwng_unk_a185_w %02x\n", data);
} }
TILE_GET_INFO_MEMBER(superwng_state::get_bg_tile_info) TILE_GET_INFO_MEMBER(superwng_state::get_bg_tile_info)
@ -456,7 +456,7 @@ void superwng_state::machine_start()
save_item(NAME(m_tile_bank)); save_item(NAME(m_tile_bank));
save_item(NAME(m_sound_byte)); save_item(NAME(m_sound_byte));
save_item(NAME(m_nmi_enable)); save_item(NAME(m_nmi_enable));
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base()+0x4000, 0x4000); membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base()+0x4000, 0x4000);
} }
void superwng_state::machine_reset() void superwng_state::machine_reset()

18
src/mame/drivers/suprgolf.c
View File

@ -82,7 +82,7 @@ public:
TILE_GET_INFO_MEMBER(get_tile_info); TILE_GET_INFO_MEMBER(get_tile_info);
DECLARE_DRIVER_INIT(suprgolf); DECLARE_DRIVER_INIT(suprgolf);
virtual void machine_start(); virtual void machine_start();
virtual void machine_reset(); virtual void machine_reset();
virtual void video_start(); virtual void video_start();
@ -267,8 +267,8 @@ WRITE8_MEMBER(suprgolf_state::bg_vram_w)
void suprgolf_state::machine_start() void suprgolf_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 16, memregion("user2")->base(), 0x4000); membank("bank1")->configure_entries(0, 16, memregion("user2")->base(), 0x4000);
membank("bank2")->configure_entries(0, 64, memregion("user1")->base(), 0x4000); membank("bank2")->configure_entries(0, 64, memregion("user1")->base(), 0x4000);
save_item(NAME(m_rom_bank)); save_item(NAME(m_rom_bank));
save_item(NAME(m_msm5205next)); save_item(NAME(m_msm5205next));
@ -293,11 +293,11 @@ READ8_MEMBER(suprgolf_state::rom_bank_select_r)
WRITE8_MEMBER(suprgolf_state::rom_bank_select_w) WRITE8_MEMBER(suprgolf_state::rom_bank_select_w)
{ {
m_rom_bank = data; m_rom_bank = data;
//popmessage("%08x %02x",((data & 0x3f) * 0x4000),data); //popmessage("%08x %02x",((data & 0x3f) * 0x4000),data);
//osd_printf_debug("ROM_BANK 0x8000 - %X @%X\n",data,space.device().safe_pcbase()); //osd_printf_debug("ROM_BANK 0x8000 - %X @%X\n",data,space.device().safe_pcbase());
membank("bank2")->set_entry(data & 0x3f); membank("bank2")->set_entry(data & 0x3f);
m_msm_nmi_mask = data & 0x40; m_msm_nmi_mask = data & 0x40;
flip_screen_set(data & 0x80); flip_screen_set(data & 0x80);
@ -305,8 +305,8 @@ WRITE8_MEMBER(suprgolf_state::rom_bank_select_w)
WRITE8_MEMBER(suprgolf_state::rom2_bank_select_w) WRITE8_MEMBER(suprgolf_state::rom2_bank_select_w)
{ {
//osd_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,space.device().safe_pcbase()); //osd_printf_debug("ROM_BANK 0x4000 - %X @%X\n",data,space.device().safe_pcbase());
membank("bank1")->set_entry(data & 0x0f); membank("bank1")->set_entry(data & 0x0f);
if(data & 0xf0) if(data & 0xf0)
printf("Rom bank select 2 with data %02x activated\n",data); printf("Rom bank select 2 with data %02x activated\n",data);

4
src/mame/drivers/suprslam.c
View File

@ -115,7 +115,7 @@ WRITE8_MEMBER(suprslam_state::pending_command_clear_w)
WRITE8_MEMBER(suprslam_state::suprslam_sh_bankswitch_w) WRITE8_MEMBER(suprslam_state::suprslam_sh_bankswitch_w)
{ {
membank("bank1")->set_entry(data & 0x03); membank("bank1")->set_entry(data & 0x03);
} }
/*** MEMORY MAPS *************************************************************/ /*** MEMORY MAPS *************************************************************/
@ -285,7 +285,7 @@ void suprslam_state::machine_start()
save_item(NAME(m_bg_bank)); save_item(NAME(m_bg_bank));
save_item(NAME(m_pending_command)); save_item(NAME(m_pending_command));
membank("bank1")->configure_entries(0, 4, memregion("audiocpu")->base() + 0x10000, 0x8000); membank("bank1")->configure_entries(0, 4, memregion("audiocpu")->base() + 0x10000, 0x8000);
} }
void suprslam_state::machine_reset() void suprslam_state::machine_reset()

6
src/mame/drivers/tankbust.c
View File

@ -24,8 +24,8 @@ To do:
void tankbust_state::machine_start() void tankbust_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000); membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000);
membank("bank2")->configure_entries(0, 2, memregion("maincpu")->base() + 0x18000, 0x2000); membank("bank2")->configure_entries(0, 2, memregion("maincpu")->base() + 0x18000, 0x2000);
save_item(NAME(m_latch)); save_item(NAME(m_latch));
save_item(NAME(m_timer1)); save_item(NAME(m_timer1));
@ -107,7 +107,7 @@ WRITE8_MEMBER(tankbust_state::e0xx_w)
case 7: /* 0xe007 bankswitch */ case 7: /* 0xe007 bankswitch */
/* bank 1 at 0x6000-9fff = from 0x10000 when bit0=0 else from 0x14000 */ /* bank 1 at 0x6000-9fff = from 0x10000 when bit0=0 else from 0x14000 */
membank("bank1")->set_entry(data & 1); membank("bank1")->set_entry(data & 1);
/* bank 2 at 0xa000-bfff = from 0x18000 when bit0=0 else from 0x1a000 */ /* bank 2 at 0xa000-bfff = from 0x18000 when bit0=0 else from 0x1a000 */
membank("bank2")->set_entry(data & 1); /* verified (the game will reset after the "game over" otherwise) */ membank("bank2")->set_entry(data & 1); /* verified (the game will reset after the "game over" otherwise) */

2
src/mame/drivers/thunderx.c
View File

@ -317,7 +317,7 @@ WRITE8_MEMBER(thunderx_state::thunderx_1f98_w)
WRITE8_MEMBER(thunderx_state::scontra_bankswitch_w) WRITE8_MEMBER(thunderx_state::scontra_bankswitch_w)
{ {
// bits 0-3 select ROM bank at 6000-7fff // bits 0-3 select ROM bank at 6000-7fff
m_rombank->set_entry(data & 0x0f); m_rombank->set_entry(data & 0x0f);
// bit 4 selects work RAM or palette RAM at 5800-5fff // bit 4 selects work RAM or palette RAM at 5800-5fff
m_bank5800->set_bank((data & 0x10) >> 4); m_bank5800->set_bank((data & 0x10) >> 4);

4
src/mame/drivers/tryout.c
View File

@ -45,12 +45,12 @@ WRITE8_MEMBER(tryout_state::sound_irq_ack_w)
void tryout_state::machine_start() void tryout_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x2000); membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x2000);
} }
WRITE8_MEMBER(tryout_state::bankswitch_w) WRITE8_MEMBER(tryout_state::bankswitch_w)
{ {
membank("bank1")->set_entry(data & 0x01); membank("bank1")->set_entry(data & 0x01);
} }
static ADDRESS_MAP_START( main_cpu, AS_PROGRAM, 8, tryout_state ) static ADDRESS_MAP_START( main_cpu, AS_PROGRAM, 8, tryout_state )

33
src/mame/drivers/ttchamp.c
View File

@ -100,7 +100,7 @@ public:
DECLARE_WRITE16_MEMBER(ttchamp_mem_w); DECLARE_WRITE16_MEMBER(ttchamp_mem_w);
UINT16 m_videoram0[0x10000 / 2]; UINT16 m_videoram0[0x10000 / 2];
// UINT16 m_videoram1[0x10000 / 2]; // UINT16 m_videoram1[0x10000 / 2];
UINT16 m_videoram2[0x10000 / 2]; UINT16 m_videoram2[0x10000 / 2];
@ -130,7 +130,6 @@ void ttchamp_state::machine_start()
void ttchamp_state::video_start() void ttchamp_state::video_start()
{ {
} }
UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect) UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
@ -162,12 +161,12 @@ UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16
videoram = (UINT8*)m_videoram1; videoram = (UINT8*)m_videoram1;
for (y=0;y<yyy;y++) for (y=0;y<yyy;y++)
{ {
for(x=0;x<xxx;x++) for(x=0;x<xxx;x++)
{ {
UINT8 pix = videoram[BYTE_XOR_LE(count)]; UINT8 pix = videoram[BYTE_XOR_LE(count)];
if (pix) bitmap.pix16(y, x) = pix+0x200; if (pix) bitmap.pix16(y, x) = pix+0x200;
count++; count++;
} }
} }
*/ */
@ -212,8 +211,8 @@ UINT32 ttchamp_state::screen_update_ttchamp(screen_device &screen, bitmap_ind16
// I think it actually does more blit operations with // I think it actually does more blit operations with
// different bits of m_port10 set to redraw the backgrounds using the video ram data as a source rather than ROM - notice the garbage you see behind 'sprites' right now // different bits of m_port10 set to redraw the backgrounds using the video ram data as a source rather than ROM - notice the garbage you see behind 'sprites' right now
// this method also removes the text layer, which we don't want // this method also removes the text layer, which we don't want
// m_videoram1[i] = 0x0000; // m_videoram1[i] = 0x0000;
// m_videoram2[i] = 0x0000; // m_videoram2[i] = 0x0000;
} }
#endif #endif
@ -289,7 +288,7 @@ WRITE16_MEMBER(ttchamp_state::ttchamp_mem_w)
if (m_spritesinit == 1) if (m_spritesinit == 1)
{ {
// printf("%06x: spider_blitter_w %08x %04x %04x (init?) (base?)\n", space.device().safe_pc(), offset * 2, data, mem_mask); // printf("%06x: spider_blitter_w %08x %04x %04x (init?) (base?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
m_spritesinit = 2; m_spritesinit = 2;
m_spritesaddr = offset; m_spritesaddr = offset;
@ -297,7 +296,7 @@ WRITE16_MEMBER(ttchamp_state::ttchamp_mem_w)
} }
else if (m_spritesinit == 2) else if (m_spritesinit == 2)
{ {
// printf("%06x: spider_blitter_w %08x %04x %04x (init2) (width?)\n", space.device().safe_pc(), offset * 2, data, mem_mask); // printf("%06x: spider_blitter_w %08x %04x %04x (init2) (width?)\n", space.device().safe_pc(), offset * 2, data, mem_mask);
m_spriteswidth = offset & 0xff; m_spriteswidth = offset & 0xff;
//printf("%08x\n",(offset*2) & 0xfff00); //printf("%08x\n",(offset*2) & 0xfff00);
@ -331,7 +330,7 @@ WRITE16_MEMBER(ttchamp_state::ttchamp_mem_w)
if (m_rombank) if (m_rombank)
src += 0x100000; src += 0x100000;
// printf("%06x: spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", space.device().safe_pc(), offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr); // printf("%06x: spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", space.device().safe_pc(), offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
offset &= 0x7fff; offset &= 0x7fff;
for (int i = 0; i < m_spriteswidth; i++) for (int i = 0; i < m_spriteswidth; i++)
@ -444,7 +443,7 @@ static ADDRESS_MAP_START( ttchamp_io, AS_IO, 16, ttchamp_state )
AM_RANGE(0x0020, 0x0021) AM_WRITE(port20_w) AM_RANGE(0x0020, 0x0021) AM_WRITE(port20_w)
// AM_RANGE(0x0034, 0x0035) AM_READ(peno_rand) AM_WRITENOP // eeprom (PIC?) / settings? // AM_RANGE(0x0034, 0x0035) AM_READ(peno_rand) AM_WRITENOP // eeprom (PIC?) / settings?
AM_RANGE(0x0062, 0x0063) AM_WRITE(port62_w) AM_RANGE(0x0062, 0x0063) AM_WRITE(port62_w)
@ -577,9 +576,9 @@ ROM_END
DRIVER_INIT_MEMBER(ttchamp_state,ttchamp) DRIVER_INIT_MEMBER(ttchamp_state,ttchamp)
{ {
// UINT8 *ROM1 = memregion("user1")->base(); // UINT8 *ROM1 = memregion("user1")->base();
// membank("bank1")->set_base(&ROM1[0x100000]); // membank("bank1")->set_base(&ROM1[0x100000]);
// membank("bank2")->set_base(&ROM1[0x180000]); // membank("bank2")->set_base(&ROM1[0x180000]);
} }
GAME( 1995, ttchamp, 0, ttchamp, ttchamp, ttchamp_state, ttchamp, ROT0, "Gamart", "Table Tennis Champions", GAME_NOT_WORKING ) // this has various advertising boards, including 'Electronic Devices' and 'Deniam' GAME( 1995, ttchamp, 0, ttchamp, ttchamp, ttchamp_state, ttchamp, ROT0, "Gamart", "Table Tennis Champions", GAME_NOT_WORKING ) // this has various advertising boards, including 'Electronic Devices' and 'Deniam'

16
src/mame/drivers/twins.c
View File

@ -123,15 +123,15 @@ void twins_state::machine_start()
READ16_MEMBER(twins_state::twins_port4_r) READ16_MEMBER(twins_state::twins_port4_r)
{ {
// doesn't work?? // doesn't work??
// printf("%08x: twins_port4_r %04x\n", space.device().safe_pc(), mem_mask); // printf("%08x: twins_port4_r %04x\n", space.device().safe_pc(), mem_mask);
// return m_i2cmem->read_sda();// | 0xfffe; // return m_i2cmem->read_sda();// | 0xfffe;
return 0x0001; return 0x0001;
} }
WRITE16_MEMBER(twins_state::twins_port4_w) WRITE16_MEMBER(twins_state::twins_port4_w)
{ {
// printf("%08x: twins_port4_w %04x %04x\n", space.device().safe_pc(), data, mem_mask); // printf("%08x: twins_port4_w %04x %04x\n", space.device().safe_pc(), data, mem_mask);
int i2c_clk = BIT(data, 1); int i2c_clk = BIT(data, 1);
int i2c_mem = BIT(data, 0); int i2c_mem = BIT(data, 0);
m_i2cmem->write_scl(i2c_clk); m_i2cmem->write_scl(i2c_clk);
@ -165,7 +165,7 @@ WRITE16_MEMBER(twins_state::twins_pal_w)
/* ??? weird ..*/ /* ??? weird ..*/
WRITE16_MEMBER(twins_state::porte_paloff0_w) WRITE16_MEMBER(twins_state::porte_paloff0_w)
{ {
// printf("porte_paloff0_w %04x\n", data); // printf("porte_paloff0_w %04x\n", data);
m_paloff = 0; m_paloff = 0;
} }
@ -205,14 +205,14 @@ WRITE16_MEMBER(twins_state::spider_blitter_w)
if (m_spritesinit == 1) if (m_spritesinit == 1)
{ {
// printf("spider_blitter_w %08x %04x %04x (init?) (base?)\n", offset * 2, data, mem_mask); // printf("spider_blitter_w %08x %04x %04x (init?) (base?)\n", offset * 2, data, mem_mask);
m_spritesinit = 2; m_spritesinit = 2;
m_spritesaddr = offset; m_spritesaddr = offset;
} }
else if (m_spritesinit == 2) else if (m_spritesinit == 2)
{ {
// printf("spider_blitter_w %08x %04x %04x (init2) (width?)\n", offset * 2, data, mem_mask); // printf("spider_blitter_w %08x %04x %04x (init2) (width?)\n", offset * 2, data, mem_mask);
m_spriteswidth = offset & 0xff; m_spriteswidth = offset & 0xff;
if (m_spriteswidth == 0) if (m_spriteswidth == 0)
m_spriteswidth = 80; m_spriteswidth = 80;
@ -234,7 +234,7 @@ WRITE16_MEMBER(twins_state::spider_blitter_w)
{ {
UINT8 *src = m_rom8; UINT8 *src = m_rom8;
// printf("spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr); // printf("spider_blitter_w %08x %04x %04x (previous data width %d address %08x)\n", offset * 2, data, mem_mask, m_spriteswidth, m_spritesaddr);
offset &= 0x7fff; offset &= 0x7fff;
for (int i = 0; i < m_spriteswidth; i++) for (int i = 0; i < m_spriteswidth; i++)
@ -477,7 +477,7 @@ WRITE16_MEMBER(twins_state::spider_pal_w)
} }
else else
{ {
// printf("first palette write %04x\n", data); // printf("first palette write %04x\n", data);
} }
m_paloff++; m_paloff++;

4
src/mame/drivers/usgames.c
View File

@ -32,12 +32,12 @@ Sound: AY-3-8912
void usgames_state::machine_start() void usgames_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x4000); membank("bank1")->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x4000);
} }
WRITE8_MEMBER(usgames_state::usgames_rombank_w) WRITE8_MEMBER(usgames_state::usgames_rombank_w)
{ {
membank("bank1")->set_entry(data); membank("bank1")->set_entry(data);
} }
WRITE8_MEMBER(usgames_state::lamps1_w) WRITE8_MEMBER(usgames_state::lamps1_w)

6
src/mame/drivers/vamphalf.c
View File

@ -2754,10 +2754,10 @@ DRIVER_INIT_MEMBER(vamphalf_state,yorijori)
m_semicom_prot_data[0] = 2; m_semicom_prot_data[0] = 2;
m_semicom_prot_data[1] = 1; m_semicom_prot_data[1] = 1;
// UINT8 *romx = (UINT8 *)memregion("user1")->base(); // UINT8 *romx = (UINT8 *)memregion("user1")->base();
// prevent code dying after a trap 33 by patching it out, why? // prevent code dying after a trap 33 by patching it out, why?
// romx[BYTE4_XOR_BE(0x8ff0)] = 3; // romx[BYTE4_XOR_BE(0x8ff0)] = 3;
// romx[BYTE4_XOR_BE(0x8ff1)] = 0; // romx[BYTE4_XOR_BE(0x8ff1)] = 0;
// Configure the QS1000 ROM banking. Care must be taken not to overlap the 256b internal RAM // Configure the QS1000 ROM banking. Care must be taken not to overlap the 256b internal RAM
machine().device("qs1000:cpu")->memory().space(AS_IO).install_read_bank(0x0100, 0xffff, "data"); machine().device("qs1000:cpu")->memory().space(AS_IO).install_read_bank(0x0100, 0xffff, "data");

4
src/mame/drivers/vigilant.c
View File

@ -24,12 +24,12 @@ Buccaneers has a 5.6888 Mhz and a 18.432 Mhz OSC
void vigilant_state::machine_start() void vigilant_state::machine_start()
{ {
membank("bank1")->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x4000); membank("bank1")->configure_entries(0, 8, memregion("maincpu")->base() + 0x10000, 0x4000);
} }
WRITE8_MEMBER(vigilant_state::vigilant_bank_select_w) WRITE8_MEMBER(vigilant_state::vigilant_bank_select_w)
{ {
membank("bank1")->set_entry(data & 0x07); membank("bank1")->set_entry(data & 0x07);
} }
/*************************************************************************** /***************************************************************************

2
src/mame/includes/fgoal.h
View File

@ -15,7 +15,7 @@ public:
m_gfxdecode(*this, "gfxdecode"), m_gfxdecode(*this, "gfxdecode"),
m_screen(*this, "screen"), m_screen(*this, "screen"),
m_palette(*this, "palette"), m_palette(*this, "palette"),
m_video_ram(*this, "video_ram") { } m_video_ram(*this, "video_ram") { }
/* devices */ /* devices */
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;

1
src/mame/includes/hng64.h
View File

@ -395,4 +395,3 @@ public:
DECLARE_WRITE16_MEMBER(hng64_sound_bank_w); DECLARE_WRITE16_MEMBER(hng64_sound_bank_w);
}; };

2
src/mame/includes/sidearms.h
View File

@ -64,7 +64,7 @@ public:
DECLARE_DRIVER_INIT(whizz); DECLARE_DRIVER_INIT(whizz);
DECLARE_DRIVER_INIT(turtship); DECLARE_DRIVER_INIT(turtship);
virtual void machine_start(); virtual void machine_start();
virtual void video_start(); virtual void video_start();
TILE_GET_INFO_MEMBER(get_sidearms_bg_tile_info); TILE_GET_INFO_MEMBER(get_sidearms_bg_tile_info);
TILE_GET_INFO_MEMBER(get_philko_bg_tile_info); TILE_GET_INFO_MEMBER(get_philko_bg_tile_info);

4
src/mame/includes/simple_st0016.h
View File

@ -12,7 +12,7 @@ public:
{ } { }
int mux_port; int mux_port;
// UINT32 m_st0016_rom_bank; // UINT32 m_st0016_rom_bank;
optional_device<st0016_cpu_device> m_maincpu; optional_device<st0016_cpu_device> m_maincpu;
DECLARE_READ8_MEMBER(mux_r); DECLARE_READ8_MEMBER(mux_r);
@ -27,7 +27,7 @@ public:
DECLARE_DRIVER_INIT(mayjinsn); DECLARE_DRIVER_INIT(mayjinsn);
DECLARE_DRIVER_INIT(mayjisn2); DECLARE_DRIVER_INIT(mayjisn2);
DECLARE_DRIVER_INIT(renju); DECLARE_DRIVER_INIT(renju);
virtual void machine_start(); virtual void machine_start();
DECLARE_VIDEO_START(st0016); DECLARE_VIDEO_START(st0016);
void st0016_draw_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); void st0016_draw_screen(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
UINT32 screen_update_st0016(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 screen_update_st0016(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

2
src/mame/includes/suna16.h
View File

@ -67,7 +67,7 @@ public:
virtual void video_start(); virtual void video_start();
DECLARE_MACHINE_START(bestbest); DECLARE_MACHINE_START(bestbest);
DECLARE_MACHINE_START(bssoccer); DECLARE_MACHINE_START(bssoccer);
DECLARE_MACHINE_START(uballoon); DECLARE_MACHINE_START(uballoon);
DECLARE_MACHINE_RESET(uballoon); DECLARE_MACHINE_RESET(uballoon);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

4
src/mame/includes/tankbust.h
View File

@ -48,8 +48,8 @@ public:
TILE_GET_INFO_MEMBER(get_bg_tile_info); TILE_GET_INFO_MEMBER(get_bg_tile_info);
TILE_GET_INFO_MEMBER(get_txt_tile_info); TILE_GET_INFO_MEMBER(get_txt_tile_info);
virtual void machine_start(); virtual void machine_start();
virtual void machine_reset(); virtual void machine_reset();
virtual void video_start(); virtual void video_start();
DECLARE_PALETTE_INIT(tankbust); DECLARE_PALETTE_INIT(tankbust);

2
src/mame/includes/thunderx.h
View File

@ -62,7 +62,7 @@ public:
virtual void machine_start(); virtual void machine_start();
virtual void machine_reset(); virtual void machine_reset();
virtual void video_start(); virtual void video_start();
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
INTERRUPT_GEN_MEMBER(vblank_interrupt); INTERRUPT_GEN_MEMBER(vblank_interrupt);

4
src/mame/includes/tryout.h
View File

@ -45,8 +45,8 @@ public:
TILEMAP_MAPPER_MEMBER(get_fg_memory_offset); TILEMAP_MAPPER_MEMBER(get_fg_memory_offset);
TILEMAP_MAPPER_MEMBER(get_bg_memory_offset); TILEMAP_MAPPER_MEMBER(get_bg_memory_offset);
virtual void machine_start(); virtual void machine_start();
virtual void video_start(); virtual void video_start();
DECLARE_PALETTE_INIT(tryout); DECLARE_PALETTE_INIT(tryout);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

4
src/mame/includes/usgames.h
View File

@ -17,8 +17,8 @@ public:
DECLARE_WRITE8_MEMBER(usgames_videoram_w); DECLARE_WRITE8_MEMBER(usgames_videoram_w);
DECLARE_WRITE8_MEMBER(usgames_charram_w); DECLARE_WRITE8_MEMBER(usgames_charram_w);
TILE_GET_INFO_MEMBER(get_usgames_tile_info); TILE_GET_INFO_MEMBER(get_usgames_tile_info);
virtual void machine_start(); virtual void machine_start();
virtual void video_start(); virtual void video_start();
DECLARE_PALETTE_INIT(usgames); DECLARE_PALETTE_INIT(usgames);
UINT32 screen_update_usgames(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 screen_update_usgames(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;

4
src/mame/includes/vigilant.h
View File

@ -38,8 +38,8 @@ public:
DECLARE_WRITE8_MEMBER(vigilant_horiz_scroll_w); DECLARE_WRITE8_MEMBER(vigilant_horiz_scroll_w);
DECLARE_WRITE8_MEMBER(vigilant_rear_horiz_scroll_w); DECLARE_WRITE8_MEMBER(vigilant_rear_horiz_scroll_w);
DECLARE_WRITE8_MEMBER(vigilant_rear_color_w); DECLARE_WRITE8_MEMBER(vigilant_rear_color_w);
virtual void machine_start(); virtual void machine_start();
virtual void video_start(); virtual void video_start();
virtual void video_reset(); virtual void video_reset();
UINT32 screen_update_vigilant(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 screen_update_vigilant(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
UINT32 screen_update_kikcubic(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect); UINT32 screen_update_kikcubic(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

4
src/mame/machine/iteagle_fpga.c
View File

@ -257,7 +257,7 @@ READ32_MEMBER( iteagle_eeprom_device::eeprom_r )
case 0xC/4: // I2C Handler case 0xC/4: // I2C Handler
if (ACCESSING_BITS_16_23) { if (ACCESSING_BITS_16_23) {
result = m_eeprom->do_read()<<(16+3); result = m_eeprom->do_read()<<(16+3);
} else { } else {
if (LOG_EEPROM) if (LOG_EEPROM)
logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask); logerror("%s:eeprom read from offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
} }
@ -278,7 +278,7 @@ WRITE32_MEMBER( iteagle_eeprom_device::eeprom_w )
m_eeprom->di_write((data & 0x040000) >> (16+2)); m_eeprom->di_write((data & 0x040000) >> (16+2));
m_eeprom->cs_write((data & 0x020000) ? ASSERT_LINE : CLEAR_LINE); m_eeprom->cs_write((data & 0x020000) ? ASSERT_LINE : CLEAR_LINE);
m_eeprom->clk_write((data & 0x010000) ? ASSERT_LINE : CLEAR_LINE); m_eeprom->clk_write((data & 0x010000) ? ASSERT_LINE : CLEAR_LINE);
} else { } else {
if (LOG_EEPROM) if (LOG_EEPROM)
logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask); logerror("%s:eeprom write to offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
} }

12
src/mame/mame.lst
View File

@ -336,7 +336,7 @@ froggers // bootleg
frogf // bootleg frogf // bootleg
quaak // bootleg quaak // bootleg
froggeram // bootleg froggeram // bootleg
froggerv // bootleg froggerv // bootleg
amidars // GX337 (c) 1982 Konami amidars // GX337 (c) 1982 Konami
triplep // (c) 1982 KKI / made by Sanritsu? triplep // (c) 1982 KKI / made by Sanritsu?
triplepa // (c) 1982 KKI / made by Sanritsu? triplepa // (c) 1982 KKI / made by Sanritsu?
@ -6350,7 +6350,7 @@ combatsc // GX611 (c) 1988
combatsct // GX611 (c) 1987 combatsct // GX611 (c) 1987
combatscj // GX611 (c) 1987 (Japan) combatscj // GX611 (c) 1987 (Japan)
bootcamp // GX611 (c) 1987 bootcamp // GX611 (c) 1987
bootcampa // GX611 (c) 1987 bootcampa // GX611 (c) 1987
combatscb // bootleg combatscb // bootleg
rockrage // GX620 (c) 1986 (World?) rockrage // GX620 (c) 1986 (World?)
rockragea // GX620 (c) 1986 (Prototype?) rockragea // GX620 (c) 1986 (Prototype?)
@ -7713,7 +7713,7 @@ kof2000 // 0257 (c) 2000 SNK
kof2000n // 0257 (c) 2000 SNK kof2000n // 0257 (c) 2000 SNK
// 0258 SNK vs. Capcom? // 0258 SNK vs. Capcom?
bangbead // 0259 (c) 2000 Visco bangbead // 0259 (c) 2000 Visco
b2b // 0071 (c) 2000 Visco (released by NCI in 2010) b2b // 0071 (c) 2000 Visco (released by NCI in 2010)
nitd // 0260 (c) 2000 Eleven / Gavaking nitd // 0260 (c) 2000 Eleven / Gavaking
nitdbl // bootleg nitdbl // bootleg
sengoku3 // 0261 (c) 2001 Noise Factory / SNK sengoku3 // 0261 (c) 2001 Noise Factory / SNK
@ -7910,7 +7910,7 @@ tstrike // East Coast Coin Company (Melbourne)
tstrikea // Game Room tstrikea // Game Room
ctribe // TA-0028 (c) 1990 (US) ctribe // TA-0028 (c) 1990 (US)
ctribe1 // TA-0028 (c) 1990 (US) ctribe1 // TA-0028 (c) 1990 (US)
ctribeo // TA-0028 (c) 1990 (US) ctribeo // TA-0028 (c) 1990 (US)
ctribej // TA-0028 (c) 1990 (Japan) ctribej // TA-0028 (c) 1990 (Japan)
ctribeb // bootleg ctribeb // bootleg
ctribeb2 // bootleg ctribeb2 // bootleg
@ -8453,7 +8453,7 @@ raiden2ea // (c) 1993 Seibu Kaihatsu
raiden2eu // (c) 1993 Seibu Kaihatsu + Fabtek license raiden2eu // (c) 1993 Seibu Kaihatsu + Fabtek license
raiden2eua // (c) 1993 Seibu Kaihatsu + Fabtek license raiden2eua // (c) 1993 Seibu Kaihatsu + Fabtek license
raiden2nl // (c) 1993 Seibu Kaihatsu raiden2nl // (c) 1993 Seibu Kaihatsu
raiden2f // (c) 1993 Seibu Kaihatsu raiden2f // (c) 1993 Seibu Kaihatsu
raiden2g // (c) 1993 Seibu Kaihatsu + Tuning license raiden2g // (c) 1993 Seibu Kaihatsu + Tuning license
raiden2dx // (c) 1993 Seibu Kaihatsu raiden2dx // (c) 1993 Seibu Kaihatsu
@ -8777,7 +8777,7 @@ gunbird // (c) 1994
gunbirdk // (c) 1994 gunbirdk // (c) 1994
gunbirdj // (c) 1994 gunbirdj // (c) 1994
btlkroad // (c) 1994 btlkroad // (c) 1994
btlkroadk // (c) 1994 btlkroadk // (c) 1994
s1945 // (c) 1995 s1945 // (c) 1995
s1945a // (c) 1995 s1945a // (c) 1995
s1945j // (c) 1995 s1945j // (c) 1995

10
src/mame/video/dynax.c
View File

@ -122,8 +122,8 @@ WRITE8_MEMBER(dynax_state::tenkai_blit_dest_w)
} }
/* /*
mjelctrn: 7 d e -> 1 - 4 8 mjelctrn: 7 d e -> 1 - 4 8
mjembase: b d e -> - 2 4 8 mjembase: b d e -> - 2 4 8
*/ */
WRITE8_MEMBER(dynax_state::mjembase_blit_dest_w) WRITE8_MEMBER(dynax_state::mjembase_blit_dest_w)
{ {
@ -381,7 +381,7 @@ void dynax_state::blitter_plot_pixel( int layer, int mask, int x, int y, int pen
} }
/* /*
Flags: Flags:
7654 ---- - 7654 ---- -
---- 3--- Rotation = SWAPXY + FLIPY ---- 3--- Rotation = SWAPXY + FLIPY
@ -1223,9 +1223,9 @@ WRITE8_MEMBER(dynax_state::tenkai_priority_w)
} }
/* /*
mjembase: priority: 00 08 10 18 20 28; enable: 1,2,4 mjembase: priority: 00 08 10 18 20 28; enable: 1,2,4
Convert to: Convert to:
mjelctrn: priority: 00 20 10 40 30 50; enable: 1,2,8 mjelctrn: priority: 00 20 10 40 30 50; enable: 1,2,8
*/ */
WRITE8_MEMBER(dynax_state::mjembase_priority_w) WRITE8_MEMBER(dynax_state::mjembase_priority_w)
{ {

3
src/mame/video/hng64.c
View File

@ -660,7 +660,7 @@ void hng64_state::hng64_drawtilemap(screen_device &screen, bitmap_rgb32 &bitmap,
// xrally's pink tilemaps make me think this is a tilemap enable bit. // xrally's pink tilemaps make me think this is a tilemap enable bit.
// fatfurwa makes me think otherwise. // fatfurwa makes me think otherwise.
// if (!(tileregs & 0x0040)) return; // if (!(tileregs & 0x0040)) return;
// set the transmask so our manual copy is correct // set the transmask so our manual copy is correct
if (tileregs & 0x0400) if (tileregs & 0x0400)
@ -1251,4 +1251,3 @@ void hng64_state::video_start()
m_vertsrom = (UINT16*)memregion("verts")->base(); m_vertsrom = (UINT16*)memregion("verts")->base();
m_vertsrom_size = memregion("verts")->bytes(); m_vertsrom_size = memregion("verts")->bytes();
} }

6
src/mame/video/hng64_3d.c
View File

@ -68,7 +68,7 @@ TIMER_CALLBACK_MEMBER(hng64_state::hng64_3dfifo_processed )
/* Note: Samurai Shodown games never calls bit 1, so it can't be framebuffer clear. It also calls bit 3 at start-up, meaning unknown */ /* Note: Samurai Shodown games never calls bit 1, so it can't be framebuffer clear. It also calls bit 3 at start-up, meaning unknown */
WRITE32_MEMBER(hng64_state::dl_control_w) // This handles framebuffers WRITE32_MEMBER(hng64_state::dl_control_w) // This handles framebuffers
{ {
// printf("dl_control_w %08x %08x\n", data, mem_mask); // printf("dl_control_w %08x %08x\n", data, mem_mask);
//if(data & 2) // swap buffers //if(data & 2) // swap buffers
//{ //{
@ -540,7 +540,7 @@ void hng64_state::recoverPolygonBlock(const UINT16* packet, struct polygon* poly
#if 0 #if 0
if (((chunkOffset[2] & 0xc000) == 0x4000) && (m_screen->frame_number() & 1)) if (((chunkOffset[2] & 0xc000) == 0x4000) && (m_screen->frame_number() & 1))
{ {
// if (chunkOffset[2] == 0xd870) // if (chunkOffset[2] == 0xd870)
{ {
polys[*numPolys].debugColor = 0xffff0000; polys[*numPolys].debugColor = 0xffff0000;
printf("%d (%08x) : %04x %04x %04x\n", k, address[k] * 3 * 2, chunkOffset[0], chunkOffset[1], chunkOffset[2]); printf("%d (%08x) : %04x %04x %04x\n", k, address[k] * 3 * 2, chunkOffset[0], chunkOffset[1], chunkOffset[2]);
@ -863,7 +863,6 @@ void hng64_state::recoverPolygonBlock(const UINT16* packet, struct polygon* poly
void hng64_state::hng64_command3d(const UINT16* packet) void hng64_state::hng64_command3d(const UINT16* packet)
{ {
/* A temporary place to put some polygons. This will optimize away if the compiler's any good. */ /* A temporary place to put some polygons. This will optimize away if the compiler's any good. */
int numPolys = 0; int numPolys = 0;
dynamic_array<polygon> polys(1024*5); dynamic_array<polygon> polys(1024*5);
@ -1702,4 +1701,3 @@ void hng64_state::drawShaded( struct polygon *p)
prOptions); prOptions);
} }
} }

1
src/mame/video/hng64_sprite.c
View File

@ -222,4 +222,3 @@ void hng64_state::draw_sprites(screen_device &screen, bitmap_rgb32 &bitmap, cons
if (!chaini) source +=8; if (!chaini) source +=8;
} }
} }

1
src/mame/video/thedeep.c
View File

@ -134,4 +134,3 @@ UINT32 thedeep_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap,
m_tilemap_1->draw(screen, bitmap, cliprect, 0,0); m_tilemap_1->draw(screen, bitmap, cliprect, 0,0);
return 0; return 0;
} }

2
src/mess/audio/gamate.c
View File

@ -38,7 +38,7 @@ gamate_sound_device::gamate_sound_device(const machine_config &mconfig, const ch
void gamate_sound_device::device_start() void gamate_sound_device::device_start()
{ {
// bind callbacks // bind callbacks
// m_irq_cb.bind_relative_to(*owner()); // m_irq_cb.bind_relative_to(*owner());
memset(m_channels, 0, sizeof(m_channels)); memset(m_channels, 0, sizeof(m_channels));
memset(reg, 0, sizeof(reg)); memset(reg, 0, sizeof(reg));

10
src/mess/drivers/a7800.c
View File

@ -286,11 +286,11 @@ static ADDRESS_MAP_START( a7800_mem, AS_PROGRAM, 8, a7800_state )
AM_RANGE(0x0480, 0x04ff) AM_RAM AM_SHARE("riot_ram") AM_MIRROR(0x100) AM_RANGE(0x0480, 0x04ff) AM_RAM AM_SHARE("riot_ram") AM_MIRROR(0x100)
AM_RANGE(0x1800, 0x1fff) AM_RAM AM_SHARE("6116_1") AM_RANGE(0x1800, 0x1fff) AM_RAM AM_SHARE("6116_1")
AM_RANGE(0x2000, 0x27ff) AM_RAM AM_SHARE("6116_2") AM_MIRROR(0x0800) AM_RANGE(0x2000, 0x27ff) AM_RAM AM_SHARE("6116_2") AM_MIRROR(0x0800)
// According to the official Software Guide, the RAM at 0x2000 is // According to the official Software Guide, the RAM at 0x2000 is
// repeatedly mirrored up to 0x3fff, but this is evidently incorrect // repeatedly mirrored up to 0x3fff, but this is evidently incorrect
// because the High Score Cartridge maps ROM at 0x3000-0x3fff // because the High Score Cartridge maps ROM at 0x3000-0x3fff
// Hardware tests show that only the mirror at 0x2800-0x2fff actually // Hardware tests show that only the mirror at 0x2800-0x2fff actually
// exists, and only on some hardware (MARIA? motherboard?) revisions // exists, and only on some hardware (MARIA? motherboard?) revisions
AM_RANGE(0x4000, 0xffff) AM_DEVWRITE("cartslot", a78_cart_slot_device, write_40xx) AM_RANGE(0x4000, 0xffff) AM_DEVWRITE("cartslot", a78_cart_slot_device, write_40xx)
AM_RANGE(0x4000, 0xbfff) AM_DEVREAD("cartslot", a78_cart_slot_device, read_40xx) AM_RANGE(0x4000, 0xbfff) AM_DEVREAD("cartslot", a78_cart_slot_device, read_40xx)
AM_RANGE(0xc000, 0xffff) AM_READ(bios_or_cart_r) // here also the BIOS can be accessed AM_RANGE(0xc000, 0xffff) AM_READ(bios_or_cart_r) // here also the BIOS can be accessed

6
src/mess/drivers/apple2.c
View File

@ -1229,9 +1229,9 @@ static SLOT_INTERFACE_START(apple2_cards)
SLOT_INTERFACE("dx1", A2BUS_DX1) /* Decillonix DX-1 sampler card */ SLOT_INTERFACE("dx1", A2BUS_DX1) /* Decillonix DX-1 sampler card */
SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */ SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */
SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */ SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */ SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */
SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */ SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */
SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */ SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */
// SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */ // SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */
SLOT_INTERFACE_END SLOT_INTERFACE_END

6
src/mess/drivers/apple2e.c
View File

@ -3036,9 +3036,9 @@ static SLOT_INTERFACE_START(apple2_cards)
SLOT_INTERFACE("dx1", A2BUS_DX1) /* Decillonix DX-1 sampler card */ SLOT_INTERFACE("dx1", A2BUS_DX1) /* Decillonix DX-1 sampler card */
SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */ SLOT_INTERFACE("tm2ho", A2BUS_TIMEMASTERHO) /* Applied Engineering TimeMaster II H.O. */
SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */ SLOT_INTERFACE("mouse", A2BUS_MOUSE) /* Apple II Mouse Card */
SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */ SLOT_INTERFACE("ezcgi", A2BUS_EZCGI) /* E-Z Color Graphics Interface */
SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */ SLOT_INTERFACE("ezcgi9938", A2BUS_EZCGI_9938) /* E-Z Color Graphics Interface (TMS9938) */
SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */ SLOT_INTERFACE("ezcgi9958", A2BUS_EZCGI_9958) /* E-Z Color Graphics Interface (TMS9958) */
// SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */ // SLOT_INTERFACE("magicmusician", A2BUS_MAGICMUSICIAN) /* Magic Musician Card */
SLOT_INTERFACE_END SLOT_INTERFACE_END

7
src/mess/drivers/gamate.c
View File

@ -118,7 +118,7 @@ READ8_MEMBER( gamate_state::gamate_cart_protection_r )
ret=(card_protection.cartridge_byte&0x80) ? 2 : 0; ret=(card_protection.cartridge_byte&0x80) ? 2 : 0;
if (card_protection.bit_shifter==7 && !card_protection.failed) if (card_protection.bit_shifter==7 && !card_protection.failed)
{ // now protection chip on cartridge activates cartridge chip select on cpu accesses { // now protection chip on cartridge activates cartridge chip select on cpu accesses
// m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r)); // next time I will try to get this working // m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r)); // next time I will try to get this working
} }
card_protection.cartridge_byte<<=1; card_protection.cartridge_byte<<=1;
} }
@ -318,12 +318,12 @@ void gamate_state::machine_start()
m_cart_ptr = memregion("maincpu")->base() + 0x6000; m_cart_ptr = memregion("maincpu")->base() + 0x6000;
if (m_cart->exists()) if (m_cart->exists())
{ {
// m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r)); // m_maincpu->space(AS_PROGRAM).install_read_handler(0x6000, 0x6000, READ8_DELEGATE(gamate_state, gamate_cart_protection_r));
m_cart_ptr = m_cart->get_rom_base(); m_cart_ptr = m_cart->get_rom_base();
membank("bankmulti")->set_base(m_cart->get_rom_base()+1); membank("bankmulti")->set_base(m_cart->get_rom_base()+1);
membank("bank")->set_base(m_cart->get_rom_base()+0x4000); // bankswitched games in reality no offset membank("bank")->set_base(m_cart->get_rom_base()+0x4000); // bankswitched games in reality no offset
} }
// m_bios[0xdf1]=0xea; m_bios[0xdf2]=0xea; // default bios: $47 protection readback // m_bios[0xdf1]=0xea; m_bios[0xdf2]=0xea; // default bios: $47 protection readback
card_protection.set=false; card_protection.set=false;
bank_multi=0; bank_multi=0;
card_protection.unprotected=false; card_protection.unprotected=false;
@ -400,4 +400,3 @@ ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */ /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */
CONS( 19??, gamate, 0, 0, gamate, gamate, gamate_state, gamate, "Bit Corp", "Gamate", 0) CONS( 19??, gamate, 0, 0, gamate, gamate, gamate_state, gamate, "Bit Corp", "Gamate", 0)

22
src/mess/drivers/hh_hmcs40.c
View File

@ -82,7 +82,7 @@ public:
UINT32 m_grid; // VFD current row data UINT32 m_grid; // VFD current row data
UINT64 m_plate; // VFD current column data UINT64 m_plate; // VFD current column data
UINT64 m_display_state[0x20]; // display matrix rows data UINT64 m_display_state[0x20]; // display matrix rows data
UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
UINT64 m_display_cache[0x20]; // (internal use) UINT64 m_display_cache[0x20]; // (internal use)
UINT8 m_display_decay[0x20][0x40]; // (internal use) UINT8 m_display_decay[0x20][0x40]; // (internal use)
@ -249,7 +249,7 @@ static MACHINE_CONFIG_START( bambball, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38750, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38750, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -284,7 +284,7 @@ static MACHINE_CONFIG_START( packmon, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -318,7 +318,7 @@ static MACHINE_CONFIG_START( zackman, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -449,7 +449,7 @@ static MACHINE_CONFIG_START( cdkong, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -484,7 +484,7 @@ static MACHINE_CONFIG_START( cgalaxn, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -519,7 +519,7 @@ static MACHINE_CONFIG_START( cpacman, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -554,7 +554,7 @@ static MACHINE_CONFIG_START( cmspacmn, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -766,7 +766,7 @@ static MACHINE_CONFIG_START( pbqbert, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38820, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -801,7 +801,7 @@ static MACHINE_CONFIG_START( kingman, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */
@ -836,7 +836,7 @@ static MACHINE_CONFIG_START( tmtron, hh_hmcs40_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc. MCFG_CPU_ADD("maincpu", HD38800, 400000) // approximation - RC osc.
// MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1)) // MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_hmcs40_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test) MCFG_DEFAULT_LAYOUT(layout_hh_hmcs40_test)
/* no video! */ /* no video! */

2
src/mess/drivers/hh_pic16.c
View File

@ -58,7 +58,7 @@ public:
int m_display_maxy; // display matrix number of rows int m_display_maxy; // display matrix number of rows
int m_display_maxx; // display matrix number of columns int m_display_maxx; // display matrix number of columns
UINT32 m_display_state[0x20]; // display matrix rows data UINT32 m_display_state[0x20]; // display matrix rows data
UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
UINT32 m_display_cache[0x20]; // (internal use) UINT32 m_display_cache[0x20]; // (internal use)
UINT8 m_display_decay[0x20][0x20]; // (internal use) UINT8 m_display_decay[0x20][0x20]; // (internal use)

2
src/mess/drivers/hh_ucom4.c
View File

@ -69,7 +69,7 @@ public:
UINT32 m_grid; // VFD current row data UINT32 m_grid; // VFD current row data
UINT32 m_plate; // VFD current column data UINT32 m_plate; // VFD current column data
UINT32 m_display_state[0x20]; // display matrix rows data UINT32 m_display_state[0x20]; // display matrix rows data
UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
UINT32 m_display_cache[0x20]; // (internal use) UINT32 m_display_cache[0x20]; // (internal use)
UINT8 m_display_decay[0x20][0x20]; // (internal use) UINT8 m_display_decay[0x20][0x20]; // (internal use)

834
src/mess/drivers/imds2.c
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File diff suppressed because it is too large Load Diff

4
src/mess/drivers/snes.c
View File

@ -1005,9 +1005,9 @@ WRITE8_MEMBER( snes_console_state::pfest94_lo_w )
*************************************/ *************************************/
static ADDRESS_MAP_START( snes_map, AS_PROGRAM, 8, snes_console_state ) static ADDRESS_MAP_START( snes_map, AS_PROGRAM, 8, snes_console_state )
// AM_RANGE(0x000000, 0x7dffff) AM_READWRITE(snes20_lo_r, snes20_lo_w) // AM_RANGE(0x000000, 0x7dffff) AM_READWRITE(snes20_lo_r, snes20_lo_w)
AM_RANGE(0x7e0000, 0x7fffff) AM_RAM /* 8KB Low RAM, 24KB High RAM, 96KB Expanded RAM */ AM_RANGE(0x7e0000, 0x7fffff) AM_RAM /* 8KB Low RAM, 24KB High RAM, 96KB Expanded RAM */
// AM_RANGE(0x800000, 0xffffff) AM_READWRITE(snes20_hi_r, snes20_hi_w) // AM_RANGE(0x800000, 0xffffff) AM_READWRITE(snes20_hi_r, snes20_hi_w)
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( spc_map, AS_PROGRAM, 8, snes_console_state ) static ADDRESS_MAP_START( spc_map, AS_PROGRAM, 8, snes_console_state )

2
src/mess/drivers/ticalc1x.c
View File

@ -60,7 +60,7 @@ public:
int m_display_maxy; // display matrix number of rows int m_display_maxy; // display matrix number of rows
int m_display_maxx; // display matrix number of columns int m_display_maxx; // display matrix number of columns
UINT32 m_display_state[0x20]; // display matrix rows data UINT32 m_display_state[0x20]; // display matrix rows data
UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
UINT32 m_display_cache[0x20]; // (internal use) UINT32 m_display_cache[0x20]; // (internal use)
UINT8 m_display_decay[0x20][0x20]; // (internal use) UINT8 m_display_decay[0x20][0x20]; // (internal use)

2
src/mess/drivers/tispeak.c
View File

@ -327,7 +327,7 @@ public:
int m_display_maxy; // display matrix number of rows int m_display_maxy; // display matrix number of rows
int m_display_maxx; // display matrix number of columns int m_display_maxx; // display matrix number of columns
UINT32 m_display_state[0x20]; // display matrix rows data UINT32 m_display_state[0x20]; // display matrix rows data
UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
UINT32 m_display_cache[0x20]; // (internal use) UINT32 m_display_cache[0x20]; // (internal use)
UINT8 m_display_decay[0x20][0x20]; // (internal use) UINT8 m_display_decay[0x20][0x20]; // (internal use)

2
src/mess/includes/hh_tms1k.h
View File

@ -48,7 +48,7 @@ public:
int m_display_maxy; // display matrix number of rows int m_display_maxy; // display matrix number of rows
int m_display_maxx; // display matrix number of columns int m_display_maxx; // display matrix number of columns
UINT32 m_display_state[0x20]; // display matrix rows data UINT32 m_display_state[0x20]; // display matrix rows data
UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments UINT16 m_display_segmask[0x20]; // if not 0, display matrix row is a digit, mask indicates connected segments
UINT32 m_display_cache[0x20]; // (internal use) UINT32 m_display_cache[0x20]; // (internal use)
UINT8 m_display_decay[0x20][0x20]; // (internal use) UINT8 m_display_decay[0x20][0x20]; // (internal use)

162
src/mess/includes/imds2.h
View File

@ -18,105 +18,105 @@
class imds2_state : public driver_device class imds2_state : public driver_device
{ {
public: public:
imds2_state(const machine_config &mconfig, device_type type, const char *tag); imds2_state(const machine_config &mconfig, device_type type, const char *tag);
DECLARE_READ8_MEMBER(ipc_mem_read); DECLARE_READ8_MEMBER(ipc_mem_read);
DECLARE_WRITE8_MEMBER(ipc_mem_write); DECLARE_WRITE8_MEMBER(ipc_mem_write);
DECLARE_WRITE8_MEMBER(imds2_ipc_control_w); DECLARE_WRITE8_MEMBER(imds2_ipc_control_w);
DECLARE_WRITE_LINE_MEMBER(imds2_ipc_intr); DECLARE_WRITE_LINE_MEMBER(imds2_ipc_intr);
DECLARE_READ8_MEMBER(imds2_ipcsyspic_r); DECLARE_READ8_MEMBER(imds2_ipcsyspic_r);
DECLARE_READ8_MEMBER(imds2_ipclocpic_r); DECLARE_READ8_MEMBER(imds2_ipclocpic_r);
DECLARE_WRITE8_MEMBER(imds2_ipcsyspic_w); DECLARE_WRITE8_MEMBER(imds2_ipcsyspic_w);
DECLARE_WRITE8_MEMBER(imds2_ipclocpic_w); DECLARE_WRITE8_MEMBER(imds2_ipclocpic_w);
DECLARE_WRITE8_MEMBER(imds2_miscout_w); DECLARE_WRITE8_MEMBER(imds2_miscout_w);
DECLARE_READ8_MEMBER(imds2_miscin_r); DECLARE_READ8_MEMBER(imds2_miscin_r);
DECLARE_WRITE_LINE_MEMBER(imds2_beep_timer_w); DECLARE_WRITE_LINE_MEMBER(imds2_beep_timer_w);
DECLARE_WRITE8_MEMBER(imds2_start_timer_w); DECLARE_WRITE8_MEMBER(imds2_start_timer_w);
DECLARE_READ8_MEMBER(imds2_kb_read); DECLARE_READ8_MEMBER(imds2_kb_read);
DECLARE_READ8_MEMBER(imds2_kb_port_p2_r); DECLARE_READ8_MEMBER(imds2_kb_port_p2_r);
DECLARE_WRITE8_MEMBER(imds2_kb_port_p1_w); DECLARE_WRITE8_MEMBER(imds2_kb_port_p1_w);
DECLARE_READ8_MEMBER(imds2_kb_port_t0_r); DECLARE_READ8_MEMBER(imds2_kb_port_t0_r);
DECLARE_READ8_MEMBER(imds2_kb_port_t1_r); DECLARE_READ8_MEMBER(imds2_kb_port_t1_r);
DECLARE_WRITE8_MEMBER(imds2_ioc_dbbout_w); DECLARE_WRITE8_MEMBER(imds2_ioc_dbbout_w);
DECLARE_WRITE8_MEMBER(imds2_ioc_f0_w); DECLARE_WRITE8_MEMBER(imds2_ioc_f0_w);
DECLARE_WRITE8_MEMBER(imds2_ioc_set_f1_w); DECLARE_WRITE8_MEMBER(imds2_ioc_set_f1_w);
DECLARE_WRITE8_MEMBER(imds2_ioc_reset_f1_w); DECLARE_WRITE8_MEMBER(imds2_ioc_reset_f1_w);
DECLARE_READ8_MEMBER(imds2_ioc_status_r); DECLARE_READ8_MEMBER(imds2_ioc_status_r);
DECLARE_READ8_MEMBER(imds2_ioc_dbbin_r); DECLARE_READ8_MEMBER(imds2_ioc_dbbin_r);
DECLARE_READ8_MEMBER(imds2_ipc_dbbout_r); DECLARE_READ8_MEMBER(imds2_ipc_dbbout_r);
DECLARE_READ8_MEMBER(imds2_ipc_status_r); DECLARE_READ8_MEMBER(imds2_ipc_status_r);
DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_data_w); DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_data_w);
DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_cmd_w); DECLARE_WRITE8_MEMBER(imds2_ipc_dbbin_cmd_w);
DECLARE_WRITE_LINE_MEMBER(imds2_hrq_w); DECLARE_WRITE_LINE_MEMBER(imds2_hrq_w);
DECLARE_READ8_MEMBER(imds2_ioc_mem_r); DECLARE_READ8_MEMBER(imds2_ioc_mem_r);
DECLARE_WRITE8_MEMBER(imds2_ioc_mem_w); DECLARE_WRITE8_MEMBER(imds2_ioc_mem_w);
I8275_DRAW_CHARACTER_MEMBER(crtc_display_pixels); I8275_DRAW_CHARACTER_MEMBER(crtc_display_pixels);
virtual void driver_start(); virtual void driver_start();
virtual void machine_start(); virtual void machine_start();
virtual void video_start(); virtual void video_start();
virtual void machine_reset(); virtual void machine_reset();
private: private:
required_device<i8085a_cpu_device> m_ipccpu; required_device<i8085a_cpu_device> m_ipccpu;
required_device<pic8259_device> m_ipcsyspic; required_device<pic8259_device> m_ipcsyspic;
required_device<pic8259_device> m_ipclocpic; required_device<pic8259_device> m_ipclocpic;
required_device<i8080a_cpu_device> m_ioccpu; required_device<i8080a_cpu_device> m_ioccpu;
required_device<i8257_device> m_iocdma; required_device<i8257_device> m_iocdma;
required_device<i8275_device> m_ioccrtc; required_device<i8275_device> m_ioccrtc;
required_device<beep_device> m_iocbeep; required_device<beep_device> m_iocbeep;
required_device<pit8253_device> m_ioctimer; required_device<pit8253_device> m_ioctimer;
required_device<i8271_device> m_iocfdc; required_device<i8271_device> m_iocfdc;
required_device<i8741_device> m_kbcpu; required_device<i8741_device> m_kbcpu;
required_device<palette_device> m_palette; required_device<palette_device> m_palette;
required_device<gfxdecode_device> m_gfxdecode; required_device<gfxdecode_device> m_gfxdecode;
required_device<legacy_floppy_image_device> m_floppy0; required_device<legacy_floppy_image_device> m_floppy0;
required_ioport m_io_key0; required_ioport m_io_key0;
required_ioport m_io_key1; required_ioport m_io_key1;
required_ioport m_io_key2; required_ioport m_io_key2;
required_ioport m_io_key3; required_ioport m_io_key3;
required_ioport m_io_key4; required_ioport m_io_key4;
required_ioport m_io_key5; required_ioport m_io_key5;
required_ioport m_io_key6; required_ioport m_io_key6;
required_ioport m_io_key7; required_ioport m_io_key7;
required_ioport m_ioc_options; required_ioport m_ioc_options;
dynamic_array<UINT8> m_ipc_ram; dynamic_array<UINT8> m_ipc_ram;
bool imds2_in_ipc_rom(offs_t offset) const; bool imds2_in_ipc_rom(offs_t offset) const;
void imds2_update_beeper(void); void imds2_update_beeper(void);
// IPC control port // IPC control port
UINT8 m_ipc_control; UINT8 m_ipc_control;
// IPC ROM content // IPC ROM content
const UINT8 *m_ipc_rom; const UINT8 *m_ipc_rom;
// Character generator // Character generator
const UINT8 *m_chargen; const UINT8 *m_chargen;
// MISCOUT state // MISCOUT state
UINT8 m_miscout; UINT8 m_miscout;
// Beeper timer line // Beeper timer line
int m_beeper_timer; int m_beeper_timer;
// Keyboard state // Keyboard state
UINT8 m_kb_p1; UINT8 m_kb_p1;
// IPC to IOC buffer // IPC to IOC buffer
UINT8 m_ioc_ibf; UINT8 m_ioc_ibf;
// IOC to IPC buffer // IOC to IPC buffer
UINT8 m_ioc_obf; UINT8 m_ioc_obf;
// IPC/IOC status // IPC/IOC status
UINT8 m_ipc_ioc_status; UINT8 m_ipc_ioc_status;
}; };
#endif /* _IMDS2_H_ */ #endif /* _IMDS2_H_ */

34
src/mess/mess.mak
View File

@ -1335,7 +1335,7 @@ $(MESSOBJ)/intel.a: \
$(MESS_DRIVERS)/rex6000.o \ $(MESS_DRIVERS)/rex6000.o \
$(MESS_DRIVERS)/sdk85.o \ $(MESS_DRIVERS)/sdk85.o \
$(MESS_DRIVERS)/sdk86.o \ $(MESS_DRIVERS)/sdk86.o \
$(MESS_DRIVERS)/imds2.o \ $(MESS_DRIVERS)/imds2.o \
$(MESSOBJ)/imp.a: \ $(MESSOBJ)/imp.a: \
$(MESS_DRIVERS)/tim011.o \ $(MESS_DRIVERS)/tim011.o \
@ -2137,22 +2137,22 @@ $(MESS_DRIVERS)/h8.o: $(MESS_LAYOUT)/h8.lh
$(MESS_DRIVERS)/hh_hmcs40.o:$(MESS_LAYOUT)/hh_hmcs40_test.lh $(MESS_DRIVERS)/hh_hmcs40.o:$(MESS_LAYOUT)/hh_hmcs40_test.lh
$(MESS_DRIVERS)/hh_pic16.o: $(MESS_LAYOUT)/maniac.lh $(MESS_DRIVERS)/hh_pic16.o: $(MESS_LAYOUT)/maniac.lh
$(MESS_DRIVERS)/hh_tms1k.o: $(MESS_LAYOUT)/amaztron.lh \ $(MESS_DRIVERS)/hh_tms1k.o: $(MESS_LAYOUT)/amaztron.lh \
$(MESS_LAYOUT)/bankshot.lh \ $(MESS_LAYOUT)/bankshot.lh \
$(MESS_LAYOUT)/cnsector.lh \ $(MESS_LAYOUT)/cnsector.lh \
$(MESS_LAYOUT)/comp4.lh \ $(MESS_LAYOUT)/comp4.lh \
$(MESS_LAYOUT)/ebball.lh \ $(MESS_LAYOUT)/ebball.lh \
$(MESS_LAYOUT)/ebball2.lh \ $(MESS_LAYOUT)/ebball2.lh \
$(MESS_LAYOUT)/ebball3.lh \ $(MESS_LAYOUT)/ebball3.lh \
$(MESS_LAYOUT)/elecdet.lh \ $(MESS_LAYOUT)/elecdet.lh \
$(MESS_LAYOUT)/mathmagi.lh \ $(MESS_LAYOUT)/mathmagi.lh \
$(MESS_LAYOUT)/merlin.lh \ $(MESS_LAYOUT)/merlin.lh \
$(MESS_LAYOUT)/simon.lh \ $(MESS_LAYOUT)/simon.lh \
$(MESS_LAYOUT)/ssimon.lh \ $(MESS_LAYOUT)/ssimon.lh \
$(MESS_LAYOUT)/splitsec.lh \ $(MESS_LAYOUT)/splitsec.lh \
$(MESS_LAYOUT)/starwbc.lh \ $(MESS_LAYOUT)/starwbc.lh \
$(MESS_LAYOUT)/stopthie.lh \ $(MESS_LAYOUT)/stopthie.lh \
$(MESS_LAYOUT)/tandy12.lh \ $(MESS_LAYOUT)/tandy12.lh \
$(MESS_LAYOUT)/tc4.lh $(MESS_LAYOUT)/tc4.lh
$(MESS_DRIVERS)/hh_ucom4.o: $(MESS_LAYOUT)/hh_ucom4_test.lh $(MESS_DRIVERS)/hh_ucom4.o: $(MESS_LAYOUT)/hh_ucom4_test.lh
$(MESS_DRIVERS)/ie15.o: $(MESS_LAYOUT)/ie15.lh $(MESS_DRIVERS)/ie15.o: $(MESS_LAYOUT)/ie15.lh
$(MESS_DRIVERS)/instruct.o: $(MESS_LAYOUT)/instruct.lh $(MESS_DRIVERS)/instruct.o: $(MESS_LAYOUT)/instruct.lh

10
src/osd/modules/opengl/osd_opengl.h
View File

@ -61,11 +61,11 @@
virtual const char *LastErrorMsg() = 0; virtual const char *LastErrorMsg() = 0;
virtual void *getProcAddress(const char *proc) = 0; virtual void *getProcAddress(const char *proc) = 0;
/* /*
* 0 for immediate updates, * 0 for immediate updates,
* 1 for updates synchronized with the vertical retrace, * 1 for updates synchronized with the vertical retrace,
* -1 for late swap tearing * -1 for late swap tearing
* *
* returns -1 if swap interval is not supported * returns -1 if swap interval is not supported
* *
*/ */
virtual int SetSwapInterval(const int swap) = 0; virtual int SetSwapInterval(const int swap) = 0;
@ -99,7 +99,7 @@
#undef GET_GLFUNC #undef GET_GLFUNC
}; };
#ifdef _MSC_VER #ifdef _MSC_VER
} }
#endif #endif
#undef OSD_GL #undef OSD_GL

6
src/osd/modules/osdwindow.h
View File

@ -78,9 +78,9 @@ public:
#endif #endif
render_primitive_list *m_primlist; render_primitive_list *m_primlist;
osd_window_config m_win_config; osd_window_config m_win_config;
protected: protected:
int m_prescale; int m_prescale;
}; };
class osd_renderer class osd_renderer
@ -131,7 +131,7 @@ protected:
private: private:
osd_window *m_window; osd_window *m_window;
int m_flags; int m_flags;
}; };

2
src/osd/modules/render/draw13.c
View File

@ -118,7 +118,7 @@ public:
private: private:
Uint32 m_sdl_access; Uint32 m_sdl_access;
sdl_info13 * m_renderer; sdl_info13 * m_renderer;
render_texinfo m_texinfo; // copy of the texture info render_texinfo m_texinfo; // copy of the texture info
HashT m_hash; // hash value for the texture (must be >= pointer size) HashT m_hash; // hash value for the texture (must be >= pointer size)
UINT32 m_flags; // rendering flags UINT32 m_flags; // rendering flags

76
src/osd/modules/render/drawogl.c
View File

@ -281,50 +281,50 @@ private:
int setupPixelFormat(HDC hDC) int setupPixelFormat(HDC hDC)
{ {
PIXELFORMATDESCRIPTOR pfd = { PIXELFORMATDESCRIPTOR pfd = {
sizeof(PIXELFORMATDESCRIPTOR), /* size */ sizeof(PIXELFORMATDESCRIPTOR), /* size */
1, /* version */ 1, /* version */
PFD_SUPPORT_OPENGL | PFD_SUPPORT_OPENGL |
PFD_DRAW_TO_WINDOW | PFD_DRAW_TO_WINDOW |
PFD_DOUBLEBUFFER, /* support double-buffering */ PFD_DOUBLEBUFFER, /* support double-buffering */
PFD_TYPE_RGBA, /* color type */ PFD_TYPE_RGBA, /* color type */
32, /* prefered color depth */ 32, /* prefered color depth */
0, 0, 0, 0, 0, 0, /* color bits (ignored) */ 0, 0, 0, 0, 0, 0, /* color bits (ignored) */
0, /* no alpha buffer */ 0, /* no alpha buffer */
0, /* alpha bits (ignored) */ 0, /* alpha bits (ignored) */
0, /* no accumulation buffer */ 0, /* no accumulation buffer */
0, 0, 0, 0, /* accum bits (ignored) */ 0, 0, 0, 0, /* accum bits (ignored) */
16, /* depth buffer */ 16, /* depth buffer */
0, /* no stencil buffer */ 0, /* no stencil buffer */
0, /* no auxiliary buffers */ 0, /* no auxiliary buffers */
PFD_MAIN_PLANE, /* main layer */ PFD_MAIN_PLANE, /* main layer */
0, /* reserved */ 0, /* reserved */
0, 0, 0, /* no layer, visible, damage masks */ 0, 0, 0, /* no layer, visible, damage masks */
}; };
int pixelFormat; int pixelFormat;
pixelFormat = ChoosePixelFormat(hDC, &pfd); pixelFormat = ChoosePixelFormat(hDC, &pfd);
if (pixelFormat == 0) { if (pixelFormat == 0) {
strcpy(m_error, "ChoosePixelFormat failed"); strcpy(m_error, "ChoosePixelFormat failed");
return 1; return 1;
} }
if (SetPixelFormat(hDC, pixelFormat, &pfd) != TRUE) { if (SetPixelFormat(hDC, pixelFormat, &pfd) != TRUE) {
strcpy(m_error, "SetPixelFormat failed."); strcpy(m_error, "SetPixelFormat failed.");
return 1; return 1;
} }
return 0; return 0;
} }
bool WGLExtensionSupported(const char *extension_name) bool WGLExtensionSupported(const char *extension_name)
{ {
//if (pfn_wglGetExtensionsStringEXT != NULL) //if (pfn_wglGetExtensionsStringEXT != NULL)
// printf("%s\n", this->pfn_wglGetExtensionsStringEXT()); // printf("%s\n", this->pfn_wglGetExtensionsStringEXT());
if (pfn_wglGetExtensionsStringEXT != NULL && strstr(pfn_wglGetExtensionsStringEXT(), extension_name) != NULL) if (pfn_wglGetExtensionsStringEXT != NULL && strstr(pfn_wglGetExtensionsStringEXT(), extension_name) != NULL)
return true; return true;
else else
return false; return false;
} }
HGLRC m_context; HGLRC m_context;
@ -589,7 +589,7 @@ private:
int m_height; int m_height;
osd_dim m_blit_dim; osd_dim m_blit_dim;
osd_gl_context *m_gl_context; osd_gl_context *m_gl_context;
int m_initialized; // is everything well initialized, i.e. all GL stuff etc. int m_initialized; // is everything well initialized, i.e. all GL stuff etc.
// 3D info (GL mode only) // 3D info (GL mode only)

8
src/osd/sdl/video.h
View File

@ -131,9 +131,9 @@ public:
osd_monitor_info *m_next; // pointer to next monitor in list osd_monitor_info *m_next; // pointer to next monitor in list
protected: protected:
virtual void refresh() = 0; virtual void refresh() = 0;
osd_rect m_pos_size; osd_rect m_pos_size;
osd_rect m_usuable_pos_size; osd_rect m_usuable_pos_size;
bool m_is_primary; bool m_is_primary;
char m_name[64]; char m_name[64];
private: private:
@ -185,7 +185,7 @@ struct osd_video_config
int syncrefresh; // sync only to refresh rate int syncrefresh; // sync only to refresh rate
int switchres; // switch resolutions int switchres; // switch resolutions
int fullstretch; // FXIME: implement in windows! int fullstretch; // FXIME: implement in windows!
// ddraw options // ddraw options
int hwstretch; // stretch using the hardware int hwstretch; // stretch using the hardware

4
src/osd/sdl/window.c
View File

@ -1153,8 +1153,8 @@ OSDWORK_CALLBACK( sdl_window_info::complete_create_wt )
#ifdef SDLMAME_MACOSX #ifdef SDLMAME_MACOSX
/* FIMXE: On OSX, SDL_WINDOW_FULLSCREEN_DESKTOP seems to be more reliable. /* FIMXE: On OSX, SDL_WINDOW_FULLSCREEN_DESKTOP seems to be more reliable.
* It however creates issues with white borders, i.e. the screen clear * It however creates issues with white borders, i.e. the screen clear
* does not work. This happens both with opengl and accel. * does not work. This happens both with opengl and accel.
*/ */
#endif #endif

8
src/osd/windows/video.h
View File

@ -131,9 +131,9 @@ public:
osd_monitor_info *m_next; // pointer to next monitor in list osd_monitor_info *m_next; // pointer to next monitor in list
protected: protected:
virtual void refresh() = 0; virtual void refresh() = 0;
osd_rect m_pos_size; osd_rect m_pos_size;
osd_rect m_usuable_pos_size; osd_rect m_usuable_pos_size;
bool m_is_primary; bool m_is_primary;
char m_name[64]; char m_name[64];
private: private:
@ -175,7 +175,7 @@ struct osd_video_config
int syncrefresh; // sync only to refresh rate int syncrefresh; // sync only to refresh rate
int switchres; // switch resolutions int switchres; // switch resolutions
int fullstretch; // FXIME: implement in windows! int fullstretch; // FXIME: implement in windows!
// ddraw options // ddraw options
int hwstretch; // stretch using the hardware int hwstretch; // stretch using the hardware

2
src/version.c
View File

@ -8,7 +8,7 @@
***************************************************************************/ ***************************************************************************/
#define BARE_BUILD_VERSION "0.159" #define BARE_BUILD_VERSION "0.160"
extern const char bare_build_version[]; extern const char bare_build_version[];
extern const char build_version[]; extern const char build_version[];