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srcclean and fix up some bits

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This commit is contained in:
Vas Crabb 2023-07-23 05:14:08 +10:00
parent 871503d040
commit 01745bc035
31 changed files with 142 additions and 142 deletions
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2
hash/spectrum_cass.xml
View File

@ -10135,7 +10135,7 @@ Expects you to press a key after the title screen appears, or it will miss the n
<info name="region" value="Germany" />
<part name="cass" interface="spectrum_cass">
<dataarea name="cass" size="7673">
<rom name="Golf - Profisoft.tzx" size="7673" crc="bfcac21e " sha1="52a34b240166267c28bf7adb69cd618a7d84a3ee"/>
<rom name="Golf - Profisoft.tzx" size="7673" crc="bfcac21e" sha1="52a34b240166267c28bf7adb69cd618a7d84a3ee"/>
</dataarea>
</part>
</software>

2
src/devices/bus/a2bus/noisemaker.cpp
View File

@ -8,7 +8,7 @@
Programmable Sound Generator through two I/O addresses, and has
a dedicated audio amplifier and speaker connector for the combined
output of its three channels. The manual gives the option of using
8T26 inverting buffers instead of 8T28 noninverting buffers, which
8T26 inverting buffers instead of 8T28 noninverting buffers, which
changes the programming interface somewhat, though both schematics
and actual boards have 8T28s.

6
src/devices/bus/isa/svga_paradise.cpp
View File

@ -384,8 +384,8 @@ isa16_wd90c31_lr_device::isa16_wd90c31_lr_device(const machine_config &mconfig,
ROM_START( wd90c31_lr )
ROM_REGION(0x8000,"vga_rom", ROMREGION_ERASE00)
ROM_SYSTEM_BIOS(0, "wdxlr831", "Western Digital WD90C31-LR")
ROMX_LOAD( "62-003259-800.bin", 0x000001, 0x004000, CRC(e71090bd) SHA1(f784ebc14801a0944271aab9ba4746dd9d0e001d), ROM_SKIP(1) | ROM_BIOS(0) )
ROMX_LOAD( "62-003260-800.bin", 0x000000, 0x004000, CRC(1e66af70) SHA1(7f236d6acb34d07480584d51f6bb57836ff262c4), ROM_SKIP(1) |ROM_BIOS(0) )
ROMX_LOAD( "62-003259-800.bin", 0x000001, 0x004000, CRC(e71090bd) SHA1(f784ebc14801a0944271aab9ba4746dd9d0e001d), ROM_SKIP(1) | ROM_BIOS(0) )
ROMX_LOAD( "62-003260-800.bin", 0x000000, 0x004000, CRC(1e66af70) SHA1(7f236d6acb34d07480584d51f6bb57836ff262c4), ROM_SKIP(1) | ROM_BIOS(0) )
ROM_END
const tiny_rom_entry *isa16_wd90c31_lr_device::device_rom_region() const
@ -439,7 +439,7 @@ ROM_START( wd90c31a_lr )
ROM_REGION(0x8000,"vga_rom", ROMREGION_ERASE00)
ROM_SYSTEM_BIOS(0, "speed24x", "Diamond Speedstar 24x (Vers. 1.04)")
ROMX_LOAD( "wd90c31alrdiamondspeedstar24x2.bin", 0x000000, 0x008000, CRC(578cb3c3) SHA1(ca7d871f9589eb06ace8075dd2d87a59bd191744), ROM_BIOS(0) )
// "wd90c31alrdiamondspeedstar24x1.bin" identical to above
// "wd90c31alrdiamondspeedstar24x1.bin" identical to above
ROM_SYSTEM_BIOS(1, "wd90c31a_lr", "Western Digital WD90C31A-LR")
ROMX_LOAD( "bios.bin", 0x000000, 0x008000, CRC(cdc4c32e) SHA1(52ed7b8301ec5ebab0d87bab8cddd9cc8612e2ab), ROM_BIOS(1) )
ROM_IGNORE( 0x8000 )

2
src/devices/bus/isa/vga_ati.cpp
View File

@ -319,7 +319,7 @@ void isa16_vga_mach64_device::device_start()
m_isa->install_device(0x1ce, 0x1cf, read8sm_delegate(*m_vga, FUNC(mach64_device::ati_port_ext_r)), write8sm_delegate(*m_vga, FUNC(mach64_device::ati_port_ext_w)));
m_isa->install_device(0x2e8, 0x2ef, read8sm_delegate(*m_vga, FUNC(mach64_device::mach32_status_r)), write8sm_delegate(*m_vga, FUNC(mach64_device::ibm8514_htotal_w)));
m_isa->install_device(0x03b0, 0x03df, *this, &isa16_vga_mach64_device::io_isa_map);
m_isa->install16_device(0x12e8, 0x12eb, read16smo_delegate(*m_vga, FUNC(mach64_device::ibm8514_vtotal_r)), write16smo_delegate(*m_vga, FUNC(mach64_device::ibm8514_vtotal_w)));

2
src/devices/bus/spectrum/smuc.cpp
View File

@ -23,7 +23,7 @@ public:
, m_rtc(*this, "rtc")
, m_eeprom(*this, "eeprom")
, m_ata(*this, "ata")
{ }
{ }
protected:
virtual void device_add_mconfig(machine_config &config) override;

2
src/devices/bus/vidbrain/info_manager.cpp
View File

@ -6,7 +6,7 @@
6KB EPROM (3*B2716), 1KB RAM (2*2114)
It has the same PCB layout as comp_language, with wire mods to put
the ROM/RAM at fixed addresses. There's a big orange label saying
the ROM/RAM at fixed addresses. There's a big orange label saying
"TEST UNIT NO. 14", and a handwritten one with "INFO. MGR SPECIAL".
**********************************************************************/

4
src/devices/video/clgd546x_laguna.h
View File

@ -37,8 +37,8 @@ private:
u8 vram_r(offs_t offset);
void vram_w(offs_t offset, uint8_t data);
// u32 unmap_log_r(offs_t offset, u32 mem_mask = ~0);
// void unmap_log_w(offs_t offset, u32 data, u32 mem_mask = ~0);
// u32 unmap_log_r(offs_t offset, u32 mem_mask = ~0);
// void unmap_log_w(offs_t offset, u32 data, u32 mem_mask = ~0);
bool m_vga_legacy_enable = false;
};

2
src/devices/video/geforce.cpp
View File

@ -100,7 +100,7 @@ quadro_device::quadro_device(const machine_config &mconfig, const char *tag, dev
ROM_START( quadro )
ROM_REGION32_LE( 0x10000, "vga_rom", ROMREGION_ERASEFF )
// NB: difference between these two is type of RAM used (SDR vs. DDR) and
// NB: difference between these two is type of RAM used (SDR vs. DDR) and
// interface type (AGP x4 vs. Pro)
ROM_SYSTEM_BIOS( 0, "elsa", "Elsa GLoria II (Ver 7.02.02)" )
ROMX_LOAD( "elsagloriaii.bin", 0x000000, 0x00ac00, CRC(78a6fbad) SHA1(5517fefc314bd34de7839fb8077aeb252689595d), ROM_BIOS(0) )

44
src/devices/video/pc_vga.cpp
View File

@ -302,9 +302,9 @@ void vga_device::device_reset()
void vga_device::io_map(address_map &map)
{
map.unmap_value_high();
// map(0x00, 0x0b).view(m_ioas_3bx_view);
// m_ioas_3bx_view[0](0x00, 0x0b).m(FUNC(vga_device::io_3bx_3dx_map));
// m_ioas_3bx_view[1](0x00, 0x0b).unmaprw();
// map(0x00, 0x0b).view(m_ioas_3bx_view);
// m_ioas_3bx_view[0](0x00, 0x0b).m(FUNC(vga_device::io_3bx_3dx_map));
// m_ioas_3bx_view[1](0x00, 0x0b).unmaprw();
map(0x00, 0x0b).lrw8(
NAME([this] (offs_t offset) {
if (m_ioas == false)
@ -321,9 +321,9 @@ void vga_device::io_map(address_map &map)
map(0x10, 0x1f).m(FUNC(vga_device::io_3cx_map));
// map(0x20, 0x2f).view(m_ioas_3dx_view);
// m_ioas_3dx_view[0](0x20, 0x2f).unmaprw();
// m_ioas_3dx_view[1](0x20, 0x2f).m(FUNC(vga_device::io_3bx_3dx_map));
// map(0x20, 0x2f).view(m_ioas_3dx_view);
// m_ioas_3dx_view[0](0x20, 0x2f).unmaprw();
// m_ioas_3dx_view[1](0x20, 0x2f).m(FUNC(vga_device::io_3bx_3dx_map));
map(0x20, 0x2f).lrw8(
NAME([this] (offs_t offset) {
if (m_ioas == true)
@ -443,7 +443,7 @@ u8 vga_device::input_status_1_r(offs_t offset)
case 0x20:
if (vga.attribute.data[0x11]&2)
res |= 0x10;
if (vga.attribute.data[0x11]&8)
if (vga.attribute.data[0x11]&8)
res |= 0x20;
break;
case 0x30:
@ -975,25 +975,25 @@ void vga_device::gc_map(address_map &map)
map.unmap_value_high();
map(0x00, 0x00).lrw8(
NAME([this](offs_t offset) {
return vga.gc.set_reset & 0xf;
return vga.gc.set_reset & 0xf;
}),
NAME([this](offs_t offset, u8 data) {
vga.gc.set_reset = data & 0xf;
NAME([this](offs_t offset, u8 data) {
vga.gc.set_reset = data & 0xf;
})
);
map(0x01, 0x01).lrw8(
NAME([this](offs_t offset) {
NAME([this](offs_t offset) {
return vga.gc.enable_set_reset & 0xf;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
vga.gc.enable_set_reset = data & 0xf;
})
);
map(0x02, 0x02).lrw8(
NAME([this](offs_t offset) {
NAME([this](offs_t offset) {
return vga.gc.color_compare & 0xf;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
vga.gc.color_compare = data & 0xf;
})
);
@ -1001,7 +1001,7 @@ void vga_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return ((vga.gc.logical_op & 3) << 3) | (vga.gc.rotate_count & 7);
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
vga.gc.logical_op = (data & 0x18) >> 3;
vga.gc.rotate_count = data & 7;
})
@ -1010,7 +1010,7 @@ void vga_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return vga.gc.read_map_sel & 3;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
vga.gc.read_map_sel = data & 3;
})
);
@ -1023,7 +1023,7 @@ void vga_device::gc_map(address_map &map)
res |= (vga.gc.write_mode & 3);
return res;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
vga.gc.shift256 = BIT(data, 6);
vga.gc.shift_reg = BIT(data, 5);
vga.gc.host_oe = BIT(data, 4);
@ -1034,7 +1034,7 @@ void vga_device::gc_map(address_map &map)
})
);
map(0x06, 0x06).lrw8(
NAME([this](offs_t offset) {
NAME([this](offs_t offset) {
u8 res = (vga.gc.memory_map_sel & 3) << 2;
res |= (vga.gc.chain_oe & 1) << 1;
res |= (vga.gc.alpha_dis & 1);
@ -1083,8 +1083,8 @@ void vga_device::sequencer_map(address_map &map)
return res;
})
);
// map(0x00, 0x00) Reset Register
// map(0x01, 0x01) Clocking Mode Register
// map(0x00, 0x00) Reset Register
// map(0x01, 0x01) Clocking Mode Register
map(0x02, 0x02).lw8(
NAME([this] (offs_t offset, u8 data) {
vga.sequencer.map_mask = data & 0xf;
@ -1101,10 +1101,10 @@ void vga_device::sequencer_map(address_map &map)
})
);
// Sequencer Memory Mode Register
// map(0x04, 0x04)
// map(0x04, 0x04)
// (undocumented) Sequencer Horizontal Character Counter Reset
// Any write strobe to this register will lock the character generator until another write to other regs happens.
// map(0x07, 0x07)
// map(0x07, 0x07)
}
/**************************************

6
src/devices/video/pc_vga.h
View File

@ -21,9 +21,9 @@
// ======================> vga_device
class vga_device : public device_t
, public device_video_interface
, public device_palette_interface
, public device_memory_interface
, public device_video_interface
, public device_palette_interface
, public device_memory_interface
{
friend class ibm8514a_device;

48
src/devices/video/pc_vga_cirrus.cpp
View File

@ -249,7 +249,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return vga.gc.set_reset & ((gc_mode_ext & 0x04) ? 0xff : 0x0f);
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
// if extended writes are enabled (bit 2 of index 0bh), then index 0 and 1 are extended to 8 bits,
// however XFree86 does not appear to do this...
vga.gc.set_reset = data & 0xff;
@ -259,7 +259,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return vga.gc.enable_set_reset & ((gc_mode_ext & 0x04) ? 0xff : 0x0f);
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
vga.gc.enable_set_reset = data & 0xff;
})
);
@ -275,7 +275,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
res |= (vga.gc.write_mode & 3);
return res;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
vga.gc.shift256 = (data & 0x40) >> 6;
vga.gc.shift_reg = (data & 0x20) >> 5;
vga.gc.host_oe = (data & 0x10) >> 4;
@ -291,7 +291,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return gc_bank_0;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
gc_bank_0 = data;
LOG("CL: Offset register 0 set to %i\n", data);
})
@ -301,7 +301,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return gc_bank_1;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
gc_bank_1 = data;
LOG("CL: Offset register 1 set to %i\n", data);
})
@ -311,7 +311,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return gc_mode_ext;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
gc_mode_ext = data;
if(!(data & 0x04))
{
@ -333,7 +333,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_gr10;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_gr10 = data;
})
);
@ -342,7 +342,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_gr11;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_gr11 = data;
})
);
@ -351,7 +351,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_width & 0x00ff;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_width = (m_blt_width & 0xff00) | data;
})
);
@ -360,7 +360,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_width >> 8;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_width = (m_blt_width & 0x00ff) | (data << 8);
})
);
@ -369,7 +369,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_height & 0x00ff;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_height = (m_blt_height & 0xff00) | data;
})
);
@ -378,7 +378,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_height >> 8;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_height = (m_blt_height & 0x00ff) | (data << 8);
})
);
@ -387,7 +387,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_dest_pitch & 0x00ff;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_dest_pitch = (m_blt_dest_pitch & 0xff00) | data;
})
);
@ -396,7 +396,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_dest_pitch >> 8;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_dest_pitch = (m_blt_dest_pitch & 0x00ff) | (data << 8);
})
);
@ -405,7 +405,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_source_pitch & 0x00ff;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_source_pitch = (m_blt_source_pitch & 0xff00) | data;
})
);
@ -414,7 +414,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_source_pitch >> 8;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_source_pitch = (m_blt_source_pitch & 0x00ff) | (data << 8);
})
);
@ -434,7 +434,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return (m_blt_source >> (8 * (offset & 3))) & 0xff;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
const u8 byte_access = (8 * (offset & 3));
const u32 old_mask = ~(0xff << byte_access);
m_blt_source = (m_blt_source & old_mask) | (data << byte_access);
@ -447,7 +447,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_mode;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_mode = data;
})
);
@ -456,7 +456,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_status;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_status = data & ~0xf2;
if(data & 0x02)
{
@ -472,7 +472,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_rop;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_rop = data;
})
);
@ -490,7 +490,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_trans_colour >> 8;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_trans_colour = (m_blt_trans_colour & 0x00ff) | (data << 8);
})
);
@ -499,7 +499,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_trans_colour_mask & 0xff;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_trans_colour_mask = (m_blt_trans_colour_mask & 0xff00) | data;
})
);
@ -508,7 +508,7 @@ void cirrus_gd5428_device::gc_map(address_map &map)
NAME([this](offs_t offset) {
return m_blt_trans_colour_mask >> 8;
}),
NAME([this](offs_t offset, u8 data) {
NAME([this](offs_t offset, u8 data) {
m_blt_trans_colour_mask = (m_blt_trans_colour_mask & 0x00ff) | (data << 8);
})
);
@ -518,7 +518,7 @@ void cirrus_gd5428_device::sequencer_map(address_map &map)
{
svga_device::sequencer_map(map);
map(0x02, 0x02).lrw8(
NAME([this] (offs_t offset) {
NAME([this] (offs_t offset) {
return vga.sequencer.map_mask & ((gc_mode_ext & 0x08) ? 0xff : 0x0f);
}),
NAME([this] (offs_t offset, u8 data) {

2
src/devices/video/pc_vga_nvidia.cpp
View File

@ -316,5 +316,5 @@ void nvidia_nv3_vga_device::crtc_map(address_map &map)
* ---x ---- SCL
* ---- x--- SDA
*/
// map(0x3f, 0x3f)
// map(0x3f, 0x3f)
}

50
src/devices/video/pc_vga_paradise.cpp
View File

@ -341,9 +341,9 @@ void wd90c00_vga_device::crtc_map(address_map &map)
m_ext_crtc_view[1](0x2b, 0x2b).ram(); // PR12 scratch pad
m_ext_crtc_view[1](0x2c, 0x2d).rw(FUNC(wd90c00_vga_device::interlace_r), FUNC(wd90c00_vga_device::interlace_w));
m_ext_crtc_view[1](0x2e, 0x2e).rw(FUNC(wd90c00_vga_device::misc_control_1_r), FUNC(wd90c00_vga_device::misc_control_1_w));
// m_ext_crtc_view[1](0x2f, 0x2f) PR16 Misc Control 2
// m_ext_crtc_view[1](0x30, 0x30) PR17 Misc Control 3
// m_ext_crtc_view[1](0x31, 0x3f) <reserved>
// m_ext_crtc_view[1](0x2f, 0x2f) PR16 Misc Control 2
// m_ext_crtc_view[1](0x30, 0x30) PR17 Misc Control 3
// m_ext_crtc_view[1](0x31, 0x3f) <reserved>
}
void wd90c00_vga_device::recompute_params()
@ -364,7 +364,7 @@ void wd90c00_vga_device::recompute_params()
case 1: xtal = XTAL(28'636'363).value() * multiplier; break;
// VCLK2, selected in 800x600 modes
case 2:
// TODO: wd90c30 selects this for 1024x768 interlace mode
// TODO: wd90c30 selects this for 1024x768 interlace mode
// (~40 Hz, should be 43 according to defined video clocks in WD9710 driver .inf)
default:
xtal = XTAL(42'000'000).value();
@ -530,12 +530,12 @@ void wd90c11a_vga_device::sequencer_map(address_map &map)
return 0xff;
})
);
// m_ext_seq_view[1](0x07, 0x07) PR21 Display Configuration and Scratch Pad
// m_ext_seq_view[1](0x07, 0x07) PR21 Display Configuration and Scratch Pad
m_ext_seq_view[1](0x08, 0x08).ram(); // PR22 'C11A only Scratch Pad
m_ext_seq_view[1](0x09, 0x09).ram(); // PR23 'C11A only Scratch Pad
// m_ext_seq_view[1](0x10, 0x10) PR30 Memory Interface and FIFO Control
// m_ext_seq_view[1](0x10, 0x10) PR30 Memory Interface and FIFO Control
m_ext_seq_view[1](0x11, 0x11).rw(FUNC(wd90c11a_vga_device::sys_if_control_r), FUNC(wd90c11a_vga_device::sys_if_control_w));
// m_ext_seq_view[1](0x12, 0x12) PR32 Miscellaneous Control 4
// m_ext_seq_view[1](0x12, 0x12) PR32 Miscellaneous Control 4
}
// unlock also dictates index mask
@ -625,17 +625,17 @@ void wd90c30_vga_device::crtc_map(address_map &map)
{
wd90c11a_vga_device::crtc_map(map);
// m_ext_crtc_view[1](0x20, 0x21) Signature read data
// m_ext_crtc_view[1](0x3d, 0x3d) PR1A CRTC Shadow Register Control
// m_ext_crtc_view[1](0x3d, 0x3d) PR1A CRTC Shadow Register Control
m_ext_crtc_view[1](0x3e, 0x3e).rw(FUNC(wd90c30_vga_device::vert_timing_overflow_r), FUNC(wd90c30_vga_device::vert_timing_overflow_w));
// m_ext_crtc_view[1](0x3f, 0x3f) PR19 Signature Analyzer Control
// m_ext_crtc_view[1](0x3f, 0x3f) PR19 Signature Analyzer Control
}
void wd90c30_vga_device::sequencer_map(address_map &map)
{
wd90c11a_vga_device::sequencer_map(map);
// m_ext_seq_view[1](0x13, 0x13) PR33 DRAM Timing and zero Wait State Control
// m_ext_seq_view[1](0x14, 0x14) PR34 Video Memory Mapping
// m_ext_seq_view[1](0x15, 0x15) PR35 USR0, USR1 Output Select, <reserved> on 'C31A
// m_ext_seq_view[1](0x13, 0x13) PR33 DRAM Timing and zero Wait State Control
// m_ext_seq_view[1](0x14, 0x14) PR34 Video Memory Mapping
// m_ext_seq_view[1](0x15, 0x15) PR35 USR0, USR1 Output Select, <reserved> on 'C31A
}
/*
@ -698,10 +698,10 @@ wd90c31_vga_device::wd90c31_vga_device(const machine_config &mconfig, const char
// maps at $23c0 in normal conditions, 16-bit
void wd90c31_vga_device::ext_io_map(address_map &map)
{
// map(0x00, 0x01) Index Control register
// map(0x02, 0x03) Register Access port
// map(0x04, 0x05) BITBLT I/O Port
// map(0x06, 0x07) <reserved>
// map(0x00, 0x01) Index Control register
// map(0x02, 0x03) Register Access port
// map(0x04, 0x05) BITBLT I/O Port
// map(0x06, 0x07) <reserved>
}
/*
@ -761,18 +761,18 @@ wd90c33_vga_device::wd90c33_vga_device(const machine_config &mconfig, const char
void wd90c33_vga_device::ext_io_map(address_map &map)
{
wd90c31_vga_device::ext_io_map(map);
// map(0x04, 0x07) Host Bit Block Transfer (HBLT), same as above but 32-bit?
// map(0x08, 0x09) K1 Line Draw Constant 1
// map(0x0a, 0x0b) K2 Line Draw Constant 2
// map(0x0c, 0x0d) ET Line Draw Error Term
// map(0x0e, 0x0f) Command Buffer and Interrupt
// map(0x04, 0x07) Host Bit Block Transfer (HBLT), same as above but 32-bit?
// map(0x08, 0x09) K1 Line Draw Constant 1
// map(0x0a, 0x0b) K2 Line Draw Constant 2
// map(0x0c, 0x0d) ET Line Draw Error Term
// map(0x0e, 0x0f) Command Buffer and Interrupt
}
// maps at $23d0 in normal conditions, 8-bit
void wd90c33_vga_device::localbus_if_map(address_map &map)
{
// map(0x00, 0x00) configuration
// map(0x01, 0x01) wait state
// map(0x02, 0x02) Video Memory Mapping Register (MMIO)
// map(0x03, 0x03) (r/o) Status Register
// map(0x00, 0x00) configuration
// map(0x01, 0x01) wait state
// map(0x02, 0x02) Video Memory Mapping Register (MMIO)
// map(0x03, 0x03) (r/o) Status Register
}

6
src/devices/video/pc_vga_sis.cpp
View File

@ -63,7 +63,7 @@ void sis630_svga_device::io_3cx_map(address_map &map)
return svga.bank_r;
}),
NAME([this] (offs_t offset, u8 data) {
svga.bank_r = data;
svga.bank_r = data;
})
);
map(0x0d, 0x0d).lrw8(
@ -92,8 +92,8 @@ void sis630_svga_device::crtc_map(address_map &map)
);
// TODO: very preliminary, undocumented stuff
map(0x30, 0xff).lrw8(
NAME([this] (offs_t offset) {
return vga.crtc.data[offset];
NAME([this] (offs_t offset) {
return vga.crtc.data[offset];
}),
NAME([this] (offs_t offset, u8 data) {
// TODO: if one of these is 0xff then it enables a single port transfer to $b8000

6
src/devices/video/pc_vga_trident.cpp
View File

@ -437,7 +437,7 @@ void trident_vga_device::gc_map(address_map &map)
svga_device::gc_map(map);
// New Source Address Register (bit 1 is inverted here, also)
map(0x0e, 0x0e).lrw8(
NAME([this] (offs_t offset) {
NAME([this] (offs_t offset) {
return tri.gc0e;
}),
NAME([this] (offs_t offset, u8 data) {
@ -450,7 +450,7 @@ void trident_vga_device::gc_map(address_map &map)
})
);
map(0x0f, 0x0f).lrw8(
NAME([this] (offs_t offset) {
NAME([this] (offs_t offset) {
return tri.gc0f;
}),
NAME([this] (offs_t offset, u8 data) {
@ -460,7 +460,7 @@ void trident_vga_device::gc_map(address_map &map)
);
// XFree86 refers to this register as "MiscIntContReg", setting bit 2, but gives no indication as to what it does
map(0x2f, 0x2f).lrw8(
NAME([this] (offs_t offset) {
NAME([this] (offs_t offset) {
return tri.gc2f;
}),
NAME([this] (offs_t offset, u8 data) {

4
src/devices/video/pc_vga_tseng.cpp
View File

@ -162,7 +162,7 @@ void tseng_vga_device::attribute_map(address_map &map)
// TODO: implement KEY protection
map(0x16, 0x16).mirror(0x20).lrw8(
NAME([this] (offs_t offset) { return et4k.misc1; }),
NAME([this] (offs_t offset, u8 data) {
NAME([this] (offs_t offset, u8 data) {
et4k.misc1 = data;
// TODO: this should be taken into account for recompute_params
#if 0
@ -190,7 +190,7 @@ void tseng_vga_device::attribute_map(address_map &map)
// TODO: not on stock et4k?
map(0x17, 0x17).mirror(0x20).lrw8(
NAME([this] (offs_t offset) { return et4k.misc2; }),
NAME([this] (offs_t offset, u8 data) {
NAME([this] (offs_t offset, u8 data) {
et4k.misc2 = data;
})
);

2
src/devices/video/pc_xga.cpp
View File

@ -830,7 +830,7 @@ void oak_oti111_vga_device::device_start()
void oak_oti111_vga_device::ramdac_mmio_map(address_map &map)
{
map.unmap_value_high();
// TODO: 0x04, 0x05 alt accesses for CRTC?
// TODO: 0x04, 0x05 alt accesses for CRTC?
map(0x06, 0x06).rw(FUNC(oak_oti111_vga_device::ramdac_mask_r), FUNC(oak_oti111_vga_device::ramdac_mask_w));
map(0x07, 0x07).rw(FUNC(oak_oti111_vga_device::ramdac_state_r), FUNC(oak_oti111_vga_device::ramdac_read_index_w));
map(0x08, 0x08).rw(FUNC(oak_oti111_vga_device::ramdac_write_index_r), FUNC(oak_oti111_vga_device::ramdac_write_index_w));

6
src/devices/video/rivatnt.cpp
View File

@ -219,10 +219,10 @@ ROM_START( rivatnt2_m64 )
// following is just an alias of "inno3dpci_125-125mhz.bin" with empty data in the 0x10000-0x1ffff bank (likely inaccessible too)
// rivatnt2m64inno3d.BIN 1xxxxxxxxxxxxxxxx = 0x00
// inno3dpci_125-125mhz.bin rivatnt2m64inno3d.BIN [1/2] IDENTICAL
// ROMX_LOAD( "rivatnt2m64inno3d.bin", 0x000000, 0x020000, CRC(7241c671) SHA1(24f6f1fbcd3d42ec354185697f8e856d876e2a50), ROM_BIOS(0) )
// ROMX_LOAD( "rivatnt2m64inno3d.bin", 0x000000, 0x020000, CRC(7241c671) SHA1(24f6f1fbcd3d42ec354185697f8e856d876e2a50), ROM_BIOS(0) )
// "rivatnt2m64.bin" is another alias
// inno3dpci_125-125mhz.bin rivatnt2m64.BIN IDENTICAL
// "rivatnt2m64.bin" is another alias
// inno3dpci_125-125mhz.bin rivatnt2m64.BIN IDENTICAL
ROM_END
const tiny_rom_entry *rivatnt2_model64_device::device_rom_region() const

2
src/devices/video/s3virge.cpp
View File

@ -205,7 +205,7 @@ void s3virge_vga_device::crtc_map(address_map &map)
map(0x40, 0x40).lw8(
NAME([this] (offs_t offset, u8 data) {
// enable S3D registers
s3.enable_s3d = data & 0x01;
s3.enable_s3d = data & 0x01;
})
);
map(0x43, 0x43).lw8(

38
src/devices/video/wd90c26.cpp
View File

@ -28,26 +28,26 @@ wd90c26_vga_device::wd90c26_vga_device(const machine_config &mconfig, const char
void wd90c26_vga_device::crtc_map(address_map &map)
{
wd90c11a_vga_device::crtc_map(map);
// m_ext_crtc_view[1](0x31, 0x31) PR18 Flat Panel Status
// m_ext_crtc_view[1](0x32, 0x33) PR19/PR1A Flat Panel Control
// m_ext_crtc_view[1](0x34, 0x34) PR1B Flat Panel Unlock
// m_ext_crtc_view[1](0x35, 0x35) PR30 Mapping RAM Unlock
// m_ext_crtc_view[1](0x37, 0x37) PR41 Vertical Expansion Initial Value
// m_ext_crtc_view[1](0x38, 0x38) PR33 Mapping RAM Address Counter
// m_ext_crtc_view[1](0x39, 0x39) PR34 Mapping RAM Data
// m_ext_crtc_view[1](0x3a, 0x3a) PR35 Mapping RAM Control and Power-Down
// m_ext_crtc_view[1](0x3b, 0x3b) PR36 LCD Panel Height Select
// m_ext_crtc_view[1](0x3c, 0x3c) PR37 Flat Panel Blinking Control
// m_ext_crtc_view[1](0x3e, 0x3e) PR39 Color LCD Control
// m_ext_crtc_view[1](0x3f, 0x3f) PR44 Power-Down Memory Refresh Control
// m_ext_crtc_view[1](0x31, 0x31) PR18 Flat Panel Status
// m_ext_crtc_view[1](0x32, 0x33) PR19/PR1A Flat Panel Control
// m_ext_crtc_view[1](0x34, 0x34) PR1B Flat Panel Unlock
// m_ext_crtc_view[1](0x35, 0x35) PR30 Mapping RAM Unlock
// m_ext_crtc_view[1](0x37, 0x37) PR41 Vertical Expansion Initial Value
// m_ext_crtc_view[1](0x38, 0x38) PR33 Mapping RAM Address Counter
// m_ext_crtc_view[1](0x39, 0x39) PR34 Mapping RAM Data
// m_ext_crtc_view[1](0x3a, 0x3a) PR35 Mapping RAM Control and Power-Down
// m_ext_crtc_view[1](0x3b, 0x3b) PR36 LCD Panel Height Select
// m_ext_crtc_view[1](0x3c, 0x3c) PR37 Flat Panel Blinking Control
// m_ext_crtc_view[1](0x3e, 0x3e) PR39 Color LCD Control
// m_ext_crtc_view[1](0x3f, 0x3f) PR44 Power-Down Memory Refresh Control
}
void wd90c26_vga_device::gc_map(address_map &map)
{
wd90c11a_vga_device::gc_map(map);
// map(0x10, 0x11) PR57/PR58 WD90C26 Feature Register I/II
// map(0x12, 0x12) PR59 Memory Arbitration Cycle Setup
// map(0x15, 0x15) PR62 FR Timing
// map(0x10, 0x11) PR57/PR58 WD90C26 Feature Register I/II
// map(0x12, 0x12) PR59 Memory Arbitration Cycle Setup
// map(0x15, 0x15) PR62 FR Timing
}
void wd90c26_vga_device::sequencer_map(address_map &map)
@ -55,8 +55,8 @@ void wd90c26_vga_device::sequencer_map(address_map &map)
wd90c11a_vga_device::sequencer_map(map);
m_ext_seq_view[1](0x08, 0x08).unmaprw(); // undefined, assume unmapped
m_ext_seq_view[1](0x09, 0x09).unmaprw(); // ^
// m_ext_seq_view[1](0x10, 0x10) PR30A Memory Interface Write Buffer & FIFO Control
// m_ext_seq_view[1](0x14, 0x14) PR34A Video Memory Virtual Page
// m_ext_seq_view[1](0x16, 0x16) PR45 Video Signature Control
// m_ext_seq_view[1](0x17, 0x18) PR45A/PR45B Signature Analyzer
// m_ext_seq_view[1](0x10, 0x10) PR30A Memory Interface Write Buffer & FIFO Control
// m_ext_seq_view[1](0x14, 0x14) PR34A Video Memory Virtual Page
// m_ext_seq_view[1](0x16, 0x16) PR45 Video Signature Control
// m_ext_seq_view[1](0x17, 0x18) PR45A/PR45B Signature Analyzer
}

2
src/mame/apple/macpwrbk030.cpp
View File

@ -732,7 +732,7 @@ void macpb030_state::macpb165c_map(address_map &map)
// on-board color video on 165c/180c
map(0xfc000000, 0xfc07ffff).rw(m_vga, FUNC(wd90c26_vga_device::mem_linear_r), FUNC(wd90c26_vga_device::mem_linear_w)).mirror(0x00380000); // 512k of VRAM
// map(0xfc400000, 0xfc7fffff).rw(FUNC(macpb030_state::macwd_r), FUNC(macpb030_state::macwd_w));
// map(0xfc400000, 0xfc7fffff).rw(FUNC(macpb030_state::macwd_r), FUNC(macpb030_state::macwd_w));
map(0xfc4003b0, 0xfc4003df).m(m_vga, FUNC(wd90c26_vga_device::io_map));
// something else video related? is at fc800000
map(0xfcff8000, 0xfcffffff).rom().region("vrom", 0x0000);

8
src/mame/misc/bingor.cpp
View File

@ -1057,7 +1057,7 @@ ROM_START( bellstr2 ) // Strings: C1992, AWR. Copyright (c) 1995-1997 Paloma El
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "bell-star+_vip2_25.02.02_l.bin", 0x00000, 0x08000, CRC(82ff28c5) SHA1(b0f7c47f32457ebb7783acb94a2ee7d60dbf000f) )
ROM_LOAD16_BYTE( "bell-star+_vip2_25.02.02_h.bin", 0x00001, 0x08000, CRC(b6243a72) SHA1(2d0f5222a1908076658614035c96a69a579ee3a2) )
// ROM_LOAD16_BYTE( "bell-star+_vip2_v_25.2.02_h.bin", 0x00001, 0x08000, CRC(c9ab19a0) SHA1(e65a4923a8efb0847b5156b68dbf9f2e5aedfecb) )
// ROM_LOAD16_BYTE( "bell-star+_vip2_v_25.2.02_h.bin", 0x00001, 0x08000, CRC(c9ab19a0) SHA1(e65a4923a8efb0847b5156b68dbf9f2e5aedfecb) )
ROM_REGION16_LE( 0x10000, "alt_h", 0 ) // from identical set, but different high program (to check).
ROM_LOAD16_BYTE( "bell-star+_vip2_v_25.2.02_h.bin", 0x00001, 0x08000, CRC(c9ab19a0) SHA1(e65a4923a8efb0847b5156b68dbf9f2e5aedfecb) )
@ -1099,14 +1099,14 @@ ROM_START( bellstr3 ) // Strings: Copyright (c) 1995-1997 Paloma Elektronik.
ROM_REGION( 0x20000, "eeprom", 0 ) // eeprom
ROM_LOAD( "24c04a.bin", 0x000000, 0x200, CRC(26ca6607) SHA1(e6f162481bf2e7196f06239e09ed81bb14e99f1e) )
ROM_END
/* Bell Star Plus
1998 Paloma Elektronik.
Play Star Austria 0316/821193.
CBA-Design, Lyon France.
Same PCB layout than bingor2, 3, 4
Serial: 9837
@ -1221,7 +1221,7 @@ ROM_END
Serial: 9813
*/
ROM_START( roljokr1 ) // Strings:
ROM_START( roljokr1 ) // Strings:
ROM_REGION16_LE( 0x10000, "boot_prg", ROMREGION_ERASE00 ) // i186 code
ROM_LOAD16_BYTE( "rol_l.bin", 0x00000, 0x08000, CRC(df4b5758) SHA1(88dfc7a623e4f200d4c90e6118e1a101242cb8ab) )
ROM_LOAD16_BYTE( "rol_h.bin", 0x00001, 0x08000, CRC(02bf6d89) SHA1(57f0bfeb6ad579b7bb0a022b2c1acd217ccae995) )

10
src/mame/misc/corona.cpp
View File

@ -47,7 +47,7 @@
Four players 6-horses racing game, similar to Winner Circle
(note that this one has 6 horses instead of 7).
It has four independent coin slots of 10-francs each.
It has four independent coin slots of 10-francs each.
**************************************************************************
@ -462,10 +462,10 @@ void corona_state::blitter_aux_w(uint8_t data)
uint8_t corona_state::blitter_status_r()
{
// Code checks bit 6 and/or bit 7
// Code checks bit 6 and/or bit 7
//
// x--- ---- blitter busy
// -x-- ---- vblank
// x--- ---- blitter busy
// -x-- ---- vblank
return 0x80 | ((m_screen->vblank() & 1) << 6);
// return machine().rand() & 0xc0;
@ -1641,7 +1641,7 @@ ROM_END
Isermatic France S.A.
Four players 6-horses racing game.
It has four independent coin slots of 10-francs each.
It has four independent coin slots of 10-francs each.
*/
ROM_START(legrandc)

2
src/mame/misc/gammagic.cpp
View File

@ -93,7 +93,7 @@ void gammagic_state::gammagic_io(address_map &map)
map(0x00e8, 0x00ef).noprw();
// map(0x00f0, 0x01ef).noprw();
// map(0x01f8, 0x03af).noprw();
// map(0x03b0, 0x03df).m("vga", FUNC(vga_device::io_map));
// map(0x03b0, 0x03df).m("vga", FUNC(vga_device::io_map));
// map(0x03e0, 0x03ef).noprw();
// map(0x0cf8, 0x0cff).rw("pcibus", FUNC(pci_bus_device::read), FUNC(pci_bus_device::write));
// map(0x0400, 0xffff).noprw();

2
src/mame/misc/jackpot.cpp
View File

@ -259,7 +259,7 @@ void jackpot_state::jackpot(machine_config &config) // clocks not verified
m_crtc->set_screen("screen");
m_crtc->set_show_border_area(false);
m_crtc->set_char_width(8);
// m_crtc->out_vsync_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
// m_crtc->out_vsync_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
SPEAKER(config, "mono").front_center();

6
src/mame/misc/mpu12wbk.cpp
View File

@ -1104,7 +1104,7 @@ ROM_END
Program flash ROM is inside a CPU epoxy block
with M6809 CPU and one PLD.
STK => Steiermark, Austria.
*/
@ -1140,7 +1140,7 @@ ROM_END
Program flash ROM is inside a CPU epoxy block
with M6809 CPU and one PLD.
BGL => Burgenland, Austria.
*/
@ -1174,7 +1174,7 @@ ROM_END
Program flash ROM is inside a CPU epoxy block
with M6809 CPU and one PLD.
BGL => Burgenland, Austria.
Program has 4 bytes different to the other set.

2
src/mame/misc/unkgolf.cpp
View File

@ -74,7 +74,7 @@ void unkgolf_state::io_map(address_map &map)
map(0x40, 0x43).rw("ppi2", FUNC(i8255_device::read), FUNC(i8255_device::write));
map(0x50, 0x53).rw("ppi3", FUNC(i8255_device::read), FUNC(i8255_device::write));
map(0x60, 0x63).rw("ppi4", FUNC(i8255_device::read), FUNC(i8255_device::write)); // indirect input/output through 61h. no sense at all since was set to output.
// map(0x70, 0x73).rw("ppi5", FUNC(i8255_device::read), FUNC(i8255_device::write)); // initialized, but not used.
// map(0x70, 0x73).rw("ppi5", FUNC(i8255_device::read), FUNC(i8255_device::write)); // initialized, but not used.
/*
.-----.-----------.---------.---------.---------.-------.-------.-------.------.

2
src/mame/pc/paokaipc.cpp
View File

@ -64,7 +64,7 @@ void paokaipc_state::main_io(address_map &map)
{
pcat32_io_common(map);
map(0x01f0, 0x01f7).rw("ide", FUNC(ide_controller_device::cs0_r), FUNC(ide_controller_device::cs0_w));
// map(0x03b0, 0x03df).m("vga", FUNC(vga_device::io_map));
// map(0x03b0, 0x03df).m("vga", FUNC(vga_device::io_map));
map(0x03f0, 0x03f7).rw("ide", FUNC(ide_controller_device::cs1_r), FUNC(ide_controller_device::cs1_w));
// map(0x0880, 0x0880) extensively accessed at POST, hangs if returns wrong values
// map(0x0cf8, 0x0cff).rw(m_pcibus, FUNC(pci_bus_device::read), FUNC(pci_bus_device::write));

10
src/mame/pc/pcipc_sis.cpp
View File

@ -404,13 +404,13 @@ COMP( 199?, aoap43, 0, 0, sis496, 0, sis496_state, empty_init, "AOpen", "AP43
COMP( 1994, a486sp3, 0, 0, sis496, 0, sis496_state, empty_init, "Asus", "PVI-486SP3 (SiS 85C496/85C497)", MACHINE_NOT_WORKING ) // hangs during irq check
COMP( 1995, aa486s, 0, 0, sis496, 0, sis496_state, empty_init, "Asus", "PCI/I-A486S (SiS 85C496/85C497)", MACHINE_NOT_WORKING ) // -bios 0 crashes on boot, -bios 1 hardlocks MAME
COMP( 199?, ch486spm, 0, 0, sis496, 0, sis496_state, empty_init, "Chaintech", "486SPM", MACHINE_NOT_WORKING ) // both versions used to show Award BootBlock, now show a black screen
COMP( 199?, ch4spi, 0, 0, sis496, 0, sis496_state, empty_init, "Chaintech", "4SPI", MACHINE_NOT_WORKING ) // used to come up, now black screen
COMP( 199?, ch486spm, 0, 0, sis496, 0, sis496_state, empty_init, "Chaintech", "486SPM", MACHINE_NOT_WORKING ) // both versions used to show Award BootBlock, now show a black screen
COMP( 199?, ch4spi, 0, 0, sis496, 0, sis496_state, empty_init, "Chaintech", "4SPI", MACHINE_NOT_WORKING ) // used to come up, now black screen
COMP( 1995, ft486f55, 0, 0, sis496, 0, sis496_state, empty_init, "Freetech", "486FT55", MACHINE_NOT_WORKING ) // used to show Award BootBlow, now black screen
COMP( 1995, ft486f55, 0, 0, sis496, 0, sis496_state, empty_init, "Freetech", "486FT55", MACHINE_NOT_WORKING ) // used to show Award BootBlow, now black screen
COMP( 199?, jakms41, 0, 0, sis496, 0, sis496_state, empty_init, "Jamicon", "KM-S4-1 VER 1.1", MACHINE_NOT_WORKING )
COMP( 199?, jwj446a, 0, 0, sis496, 0, sis496_state, empty_init, "Jetway", "J-446A", MACHINE_NOT_WORKING ) // BIOS 0 shows BootBlock, but hangs on beep, BIOS 1 hangs, used to show BootBlock
COMP( 199?, jakms41, 0, 0, sis496, 0, sis496_state, empty_init, "Jamicon", "KM-S4-1 VER 1.1", MACHINE_NOT_WORKING )
COMP( 199?, jwj446a, 0, 0, sis496, 0, sis496_state, empty_init, "Jetway", "J-446A", MACHINE_NOT_WORKING ) // BIOS 0 shows BootBlock, but hangs on beep, BIOS 1 hangs, used to show BootBlock
COMP( 199?, ls486e, 0, 0, sis496, 0, sis496_state, empty_init, "LuckyStar", "LS-486E Rev:C", MACHINE_NOT_WORKING ) // All versions POST, except LH5 (BootBlock)

2
src/mame/pc/queen.cpp
View File

@ -263,7 +263,7 @@ void queen_state::queen_io(address_map &map)
map(0x0170, 0x0177).rw("ide2", FUNC(ide_controller_32_device::cs0_r), FUNC(ide_controller_32_device::cs0_w));
map(0x01f0, 0x01f7).rw("ide", FUNC(ide_controller_device::cs0_r), FUNC(ide_controller_device::cs0_w));
map(0x0370, 0x0377).rw("ide2", FUNC(ide_controller_32_device::cs1_r), FUNC(ide_controller_32_device::cs1_w));
// map(0x03b0, 0x03df).m("vga", FUNC(vga_device::io_map));
// map(0x03b0, 0x03df).m("vga", FUNC(vga_device::io_map));
map(0x03f0, 0x03f7).rw("ide", FUNC(ide_controller_device::cs1_r), FUNC(ide_controller_device::cs1_w));
map(0x0cf8, 0x0cff).rw("pcibus", FUNC(pci_bus_legacy_device::read), FUNC(pci_bus_legacy_device::write));

2
src/mame/taito/changela.cpp
View File

@ -671,7 +671,7 @@ void changela_state::draw_tree(bitmap_ind16 &bitmap, int sy, int tree_num)
h_count = ((math_train[9] & 0x0f) >> 1) | ((math_train[8] & 0x0f) << 3) | 0x80;
tile_h = (tile_h + 1) & 0xfff;
// Skip one count if LSB is high
// Skip one count if LSB is high
if (((math_train[9] & 0x01) && (tile_h & 0x01)))
h_count--;
}