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heathkit/h89.cpp: Added DIP switch settings for Ultimeth ROM. (#11839)

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Mark Garlanger 2023-12-15 08:00:37 -06:00 committed by GitHub
parent e4c71c67aa
commit 01db8a7d10
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 44 additions and 11 deletions
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src/mame/heathkit/h89.cpp
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@ -333,7 +333,7 @@ static INPUT_PORTS_START( h89 )
PORT_DIPSETTING( 0x00, DEF_STR( Normal ) )
PORT_DIPSETTING( 0x80, "Auto" )
// MMS 84-B
// MMS 444-84B (and possibly 444-84A)
PORT_DIPNAME( 0x03, 0x00, "Disk I/O #2" ) PORT_DIPLOCATION("SW501:1,2") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x10)
PORT_DIPSETTING( 0x00, "H-88-1" )
PORT_DIPSETTING( 0x01, "H/Z-47 (Not yet implemented)" )
@ -375,19 +375,51 @@ static INPUT_PORTS_START( h89 )
PORT_DIPSETTING( 0x0d, "Reserved" )
PORT_DIPSETTING( 0x0e, "Reserved" )
PORT_DIPSETTING( 0x0f, "Magnolia 128K pseudo disk, banks 0-1" )
PORT_DIPNAME( 0x10, 0x00, "Map ROM into RAM" ) PORT_DIPLOCATION("SW501:5") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x14)
PORT_DIPSETTING( 0x00, "Map to RAM" )
PORT_DIPSETTING( 0x10, "ROM" )
PORT_DIPNAME( 0x10, 0x00, "Map ROM into RAM on boot" ) PORT_DIPLOCATION("SW501:5") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x14)
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPSETTING( 0x10, DEF_STR( No ) )
PORT_DIPNAME( 0x20, 0x20, "Perform memory test at start" ) PORT_DIPLOCATION("SW501:6") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x14)
PORT_DIPSETTING( 0x20, DEF_STR( No ) )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPNAME( 0x40, 0x00, "LLL controller" ) PORT_DIPLOCATION("SW501:7") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x14)
PORT_DIPSETTING( 0x00, "No LLL controller" )
PORT_DIPSETTING( 0x40, "LLL controller" )
PORT_DIPNAME( 0x40, 0x00, "Have a LLL controller installed" ) PORT_DIPLOCATION("SW501:7") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x14)
PORT_DIPSETTING( 0x00, DEF_STR( No ) )
PORT_DIPSETTING( 0x40, DEF_STR( Yes ) )
PORT_DIPNAME( 0x80, 0x00, "Boot mode" ) PORT_DIPLOCATION("SW501:8") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x14)
PORT_DIPSETTING( 0x00, DEF_STR( Normal ) )
PORT_DIPSETTING( 0x80, "Auto" )
// Ultimeth MTRHEX-4k
// (values based on testing and comparison with the Kres KMR-100 ROM which was also written by Ultimeth)
PORT_DIPNAME( 0x0f, 0x00, "Default Boot Device" ) PORT_DIPLOCATION("SW501:1,2,3,4") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x18)
PORT_DIPSETTING( 0x00, "H-17 hard-sectored 5\" floppy" )
PORT_DIPSETTING( 0x01, "H-37 soft-sectored 5\" floppy" )
PORT_DIPSETTING( 0x02, "? Corvus hard disk/Magnolia interface" )
PORT_DIPSETTING( 0x03, "? CDR 5\"/8\" double density floppy" )
PORT_DIPSETTING( 0x04, "? H-47 8\" floppy at port 0x78/0170" )
PORT_DIPSETTING( 0x05, "? H-47 8\" floppy at port 0x7c/0174" )
PORT_DIPSETTING( 0x06, "? Reserved" )
PORT_DIPSETTING( 0x07, "? Reserved" )
PORT_DIPSETTING( 0x08, "? Reserved" )
PORT_DIPSETTING( 0x09, "? SASI controller or Z-67 at port 0x78/0170" )
PORT_DIPSETTING( 0x0a, "? SASI controller or Z-67 at port 0x7c/0174" )
PORT_DIPSETTING( 0x0b, "? Livingston 8\" single density floppy" )
PORT_DIPSETTING( 0x0c, "? Magnolia 5\"/8\" double density floppy" )
PORT_DIPSETTING( 0x0d, "? Reserved" )
PORT_DIPSETTING( 0x0e, "? Reserved" )
PORT_DIPSETTING( 0x0f, "? Magnolia 128K pseudo disk" )
PORT_DIPNAME( 0x10, 0x00, "? Map ROM into RAM on boot" ) PORT_DIPLOCATION("SW501:5") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x18)
PORT_DIPSETTING( 0x00, "? Yes" )
PORT_DIPSETTING( 0x10, "? No" )
PORT_DIPNAME( 0x20, 0x20, "Perform memory test at start" ) PORT_DIPLOCATION("SW501:6") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x18)
PORT_DIPSETTING( 0x20, DEF_STR( No ) )
PORT_DIPSETTING( 0x00, DEF_STR( Yes ) )
PORT_DIPNAME( 0x40, 0x00, "? Have a LLL controller installed" ) PORT_DIPLOCATION("SW501:7") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x18)
PORT_DIPSETTING( 0x00, "? No" )
PORT_DIPSETTING( 0x40, "? Yes" )
PORT_DIPNAME( 0x80, 0x00, "Boot mode" ) PORT_DIPLOCATION("SW501:8") PORT_CONDITION("CONFIG", 0x3c, EQUALS, 0x18)
PORT_DIPSETTING( 0x00, DEF_STR( Normal ) )
PORT_DIPSETTING( 0x80, "Auto" )
PORT_START("CONFIG")
PORT_CONFNAME(0x03, 0x00, "CPU Clock Speed Upgrade")
@ -399,8 +431,9 @@ static INPUT_PORTS_START( h89 )
PORT_CONFSETTING(0x04, "Heath MTR-90")
PORT_CONFSETTING(0x08, "Heath MTR-88")
PORT_CONFSETTING(0x0c, "Heath MTR-89")
PORT_CONFSETTING(0x10, "MMS 84B")
PORT_CONFSETTING(0x10, "MMS 444-84B/444-84A")
PORT_CONFSETTING(0x14, "Kres KMR-100")
PORT_CONFSETTING(0x18, "Ultimeth MTRHEX-4k")
INPUT_PORTS_END
@ -644,10 +677,10 @@ ROM_START( h89 )
ROM_SYSTEM_BIOS(2, "mtr89", "MTR-89 (444-62)")
ROMX_LOAD("2716_444-62_mtr89.u518", 0x0000, 0x0800, CRC(8f507972) SHA1(ac6c6c1344ee4e09fb60d53c85c9b761217fe9dc), ROM_BIOS(2))
ROM_SYSTEM_BIOS(3, "mms84b", "MMS 84B")
ROM_SYSTEM_BIOS(3, "mms84b", "MMS 444-84B")
ROMX_LOAD("2732_444_84b_mms.u518", 0x0000, 0x1000, CRC(7e75d6f4) SHA1(baf34e036388d1a191197e31f8a93209f04fc58b), ROM_BIOS(3))
ROM_SYSTEM_BIOS(4, "kmr-100_v3.a.02", "Kres KMR-100")
ROM_SYSTEM_BIOS(4, "kmr-100", "Kres KMR-100 V3.a.02")
ROMX_LOAD("2732_kmr100_v3_a_02.u518", 0x0000, 0x1000, CRC(fd491592) SHA1(3d5803f95c38b237b07cd230353cd9ddc9858c13), ROM_BIOS(4))
ROM_SYSTEM_BIOS(5, "mtrhex_4k", "Ultimeth ROM")
@ -656,7 +689,7 @@ ROM_START( h89 )
ROM_SYSTEM_BIOS(6, "mtr90-84", "Heath's MTR-90 (444-84 - Superseded by 444-142)")
ROMX_LOAD("2732_444-84_mtr90.u518", 0x0000, 0x1000, CRC(f10fca03) SHA1(c4a978153af0f2dfcc9ba05be4c1033d33fee30b), ROM_BIOS(6))
ROM_SYSTEM_BIOS(7, "mms84a", "MMS 84A (Superseded by MMS 84B)")
ROM_SYSTEM_BIOS(7, "mms84a", "MMS 444-84A (Superseded by MMS 444-84B)")
ROMX_LOAD("2732_444_84a_mms.u518", 0x0000, 0x1000, CRC(0e541a7e) SHA1(b1deb620fc89c1068e2e663e14be69d1f337a4b9), ROM_BIOS(7))
ROM_END