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synced 2025-05-30 17:41:47 +03:00
wrong cast, reg a/b are 8bit
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@ -2542,7 +2542,7 @@ static void HC11OP(rola)(hc11_state *cpustate)
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UINT16 r = ((REG_A & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0);
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (c & 0x80) ? CC_C : 0;
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REG_A = (UINT16)(r);
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REG_A = (UINT8)(r);
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SET_N8(REG_A);
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SET_Z8(REG_A);
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@ -2562,7 +2562,7 @@ static void HC11OP(rolb)(hc11_state *cpustate)
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UINT16 r = ((REG_B & 0x7f) << 1) | (cpustate->ccr & CC_C ? 1 : 0);
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (c & 0x80) ? CC_C : 0;
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REG_B = (UINT16)(r);
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REG_B = (UINT8)(r);
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SET_N8(REG_B);
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SET_Z8(REG_B);
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@ -2649,7 +2649,7 @@ static void HC11OP(rora)(hc11_state *cpustate)
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UINT16 r = ((REG_A & 0x7f) >> 1) | (cpustate->ccr & CC_C ? 0x80 : 0);
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (c & 1) ? CC_C : 0;
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REG_A = (UINT16)(r);
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REG_A = (UINT8)(r);
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SET_N8(REG_A);
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SET_Z8(REG_A);
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@ -2669,7 +2669,7 @@ static void HC11OP(rorb)(hc11_state *cpustate)
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UINT16 r = ((REG_B & 0x7f) >> 1) | (cpustate->ccr & CC_C ? 0x80 : 0);
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (c & 1) ? CC_C : 0;
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REG_B = (UINT16)(r);
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REG_B = (UINT8)(r);
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SET_N8(REG_B);
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SET_Z8(REG_B);
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