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m6502/om65ce02.lst: fix dew_zpg, phw_aba, phw_iw2 [smf]

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* allows commodore/c65 BASIC to be workable
This commit is contained in:
angelosa 2024-08-08 11:54:54 +02:00
parent 3c000d5387
commit 02595ddf2e
2 changed files with 5 additions and 6 deletions
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8
src/devices/cpu/m6502/om65ce02.lst
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@ -672,12 +672,12 @@ dew_zpg
TMP2++;
TMP = set_h(TMP, read(B|TMP2));
P &= ~(F_N|F_Z);
TMP++;
TMP--;
if(!TMP)
P |= F_Z;
else if(TMP & 0x8000)
P |= F_N;
TMP2++;
TMP2--;
write(B|TMP2, TMP);
TMP2++;
write(B|TMP2, TMP >> 8);
@ -1198,10 +1198,10 @@ phw_aba
PC++;
TMP3 = read(TMP);
TMP3 = set_h(TMP3, read(TMP+1));
dec_SP_ce();
write(SP, TMP3);
dec_SP_ce();
write(SP, TMP3 >> 8);
dec_SP_ce();
prefetch();
phw_iw2
@ -1209,10 +1209,10 @@ phw_iw2
PC++;
TMP = set_h(TMP, read_pc());
PC++;
dec_SP_ce();
write(SP, TMP);
dec_SP_ce();
write(SP, TMP >> 8);
dec_SP_ce();
prefetch();
phx_ce_imp

3
src/mame/commodore/c65.cpp
View File

@ -5,10 +5,9 @@
C=65 / C=64DX (c) 1991 Commodore
TODO:
- Fails interpreting BASIC commands, CPU core bug?
- DDR/port support from M4510;
- Complete memory model;
\- rom8 / roma and rome all causes issues if hooked up (needs the CPU DDR port?)
\- rom8 / roma / rome all causes bootstrap issues if hooked up (needs the CPU DDR port?)
\- Work RAM should really use a memory_share_creator, VIC-III can potentially access the full range.
\- CRAM is really just RAM that bitplane mode can access as-is;
- Complete interrupts;